Electrical and Computer Engineering

Computer Organization and Architecture

CSE 332
Credits – 3

Prerequisites : CSE 231 Digital Logic Design

1
 LESSON 6

ISA – MIPS Coding

2
 Example 1 - Hardware Design specification 1

You have been asked to design a small computing system with a customized ISA. The system can
only perform the following operations:
 Get data from data memory (by lw instruction),
 Perform addition / subtraction on two register operands (by add / sub instruction),
 Store the result into memory (by sw instruction).

The system has only 4 registers t0, t1, t2, t3. The formats of the instruction are as follows:
R-type
op (2 bit) rd (2 bit) rs (2 bit) rt (2 bit) func (2 bit)
I-type
op (2 bit) rd (2 bit) rt (2 bit) immediate (4 bit)

3
 Example 1 - MIPS codes
Consider the following set of compiled instructions of a C- code A = A - B. Assume there are some
values already stored in the registers at the beginning.
lw $t1, 0 ($t0) (1)
lw $t2, 4 ($t0) (2)
sub $t2,$t1,$t2 (3)
sw $t2, 0($t0) (4)

Consider the following set of compiled instructions of a C- code A = A + B. Assume there are some
values already stored in the registers at the beginning.
lw $t1, 0 ($t0) (1)
lw $t2, 0 ($t0) (2)
add $t2,$t1,$t2 (3)
sw $t2, 0($t0) (4)

4
 Problems to try before Mid

a. Find the MIPS codes for the

following C – codes:

•(A-B) . (A+B)

•(A-B) / (A+B)

•A . 2N

5
 Example 2- Design specification 2
Consider following types of loop program.
for (i=0, i<x , i++)
Sum = Sum + 2i
One solution to the problem is elaborated as below:

The formats of the instruction are as follows:

R-type
op (2 bit) rd (2 bit) rs (2 bit) rt (2 bit)
I-type
op (2 bit) rd (2 bit) rt (2 bit) immediate (2 bit)

There need one R-type instruction (add), two I-type (beq,addi) and one J-type (J) and four registers
$zero, t0, t1, t2to translate the program. t0, t1 and t2have been used to hold the value of x, i and Sum
respectively.
6
 Example 2 - MIPS code
Consider following types of loop program.
for (i=0, i<x , i++)
Sum = Sum + 2i
One solution to the problem is elaborated as below:
The above loop program can be translated into assembly code like this:

lw $t0, 0($zero) % load x from Memory

add $t1, $zero, $zero
add $t2, $zero, $zero
L1: beq $t1, $t0, L2% compare i& x
add $t2,$t2, $t1
add $t2,$t2, $t1
addi$t1,$t1, 1
beq$zero, $zero, L1% go back to the loop
L2:sw $t2, 4($zero) % store result to Memory

7
 Problem to try after Mid

b. Consider a new instruction loop r1, r2, offset.

This has the same effect as the following two instructions

addi r1, r1, 1

bne r1, r2, offset

I. What modification would you do to accommodate this instruction into the above code
II. What modification would you do to accommodate this instruction into the existing
datapath?

8
 END OF LESSON 6

Quiz 2 is on 12th December 2020