Laboratory Report Cover Sheet

UET ABBOTABAD CAMPUS

Faculty of Department of Electronics Engineering

ELE-408
FPGA BASED SYSTEM DESIGN
7th Semester fall 2018

Name: Zulfiqar Ali.

Register No./C.NO: 17ABELT0736.
Venue: Computer Laboratory # 1
Lab No. : 5
Lab Tile : Simulation and Implementation different types of Flip-flops and registers
using Spartan 3.
Date of Conduction:

Date of Submission:

Particulars Maximum Marks Marks Obtained

Pre –lab 20

Post lab Codes/simulation 30

Data analysis 30

Punctuality 20
Total 100

REPORT VERIFICATION
Date:

Instructor Name: Engr. Mehmoona Gul

Signature:
LAB #5
IMPLEMENT DIFFERENT TYPES OF FLIP-FLOPS USING SPARTAN
3.

1.1 AIM
Sequential circuits are digital circuits in which the output depends not only on the present input (like
combinatorial circuits), but also on the past sequence of inputs. In effect, these circuits must be able to
remember something about the past history of the inputs. The synchronous design methodology is the
most commonly used practice in designing a sequential circuit. In this methodology, all storage
elements are controlled (i.e., synchronized) by a global clock signal and the data is sampled and stored
at the rising or falling edge of the clock signal. It allows designers to separate the storage components
from the circuit and greatly simplifies the development process. This methodology is the most
important principle in developing a large, complex digital system and is the foundation of most
synthesis, verification, and testing algorithms. The basic aim, of the lab is to introduce the student with
timing concept and about the clock signal, how it provides the timing essence to the sequential circuits.

1.2 OBJECTIVE
After completing this lab, you will be able to:

 Model various types of latches.

 Model flip-flops with control signals.

1.3 THEORY
1.3.1 INTRODUCTION
A sequential circuit is a logical circuit, where the output depends on the present value of the input signal
as well as the sequence of past inputs. While a combinational circuit is a function of present input only.
A sequential circuit is a combination of combinational circuit and a storage element. The sequential
circuit use current input variables and previous input variables which are stored and provides the data
to the circuit on the next clock cycle.
 1.3.2 TYPES OF SEQUENTIAL CIRCUITS
The sequential circuits are classified into two types
 Synchronous Circuit
 Asynchronous Circuit
In synchronous sequential circuits, the state of device changes at discrete times in response to a clock
signal. In asynchronous circuits, the state of the device changes in response to changing inputs .

1.3.3 SYNCHRONOUS CIRCUITS

In synchronous circuits, the inputs are pulses with certain restrictions on pulse width and propagation
delay. Thus synchronous circuits can be divided into clocked and un-clocked or pulsed sequential
circuits.

1.3.4 FLIP-FLOPS:
Flip-flops and latches are used as data storage elements. Such data storage can be used for storage
of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the
output and next state depend not only on its current input, but also on its current state (and hence,
previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input
signals to some reference timing signal.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the
simple ones are commonly called latches. The word latch is mainly used for storage elements, while
clocked devices are described as flip-flops.
TABLE 5.1.

1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
PRE-LAB:
1. Draw a circuit diagram for 4-bit serial shift register.

RTL SCHEMATICS:
1 .5 SOFTWARE TOOLS REQUIREMENT
Equipment:
Computer with ISE Software
Specifications:
 HP Computer i5 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
 Software: ISE

1.6 VERILOG CODE FOR DIFFERENT TYPES OF FLIPFLOP

1.6.1 VERILOG CODE FOR S-R FLIP-FLOP

TEST FIXTURE:
ISIM RESULTS:
1.6.2 VERILOG CODE FOR D- FLIP-FLOP:

TEST FIXTURE:
ISIM RESULT:

1.6.3 VERILOG CODE FOR SERIAL-SHIFT REGISTER:

VERILOG TEST FIXTURE:

ISIM RESULTS:
A. Reset=0 for 1ns and then 1 till 2ns. After that reset remains 0 for the whole time. For that time
the values of A,E and clk are shown:
B. Since E(input) was zero for reset = 0 and reset =1 for 2ns. It will be zero till 22ns. This
E=0 will be available at A at 70ns till 90ns(at the rising edge of clk).A delay of 60ns is
added because of previous three registers with an additional 10ns delay caused by
path and other parameters.

C. E=1(From 22ns to 42ns). This E=1 will be available at A at 90ns till 110ns.
 D. E=0 (42ns to 62ns) will be available at output as A=0(110ns to 130ns).

In a similar manner the values of E will appear at output A with a delay of 70ns(at the rising
edge of clk).

1.8 IN LAB-TASK
JK-FLIPFLOP:
VERILOG MODULE:
VERILOG TEST FIXTURE:

ISIM RESULT:
T(TOGGLE) FLIP FLOP:

TEST FIXTURE:
ISIM RESULT:

1.9 POST-LAB TASK

Model N-bt shift register on target device/by simualtion.

VERILOG CODE:

TEST FIXTURE:
RESULT: