intel” M2114A 1024 x 4 BIT STATIC RAM Miltary M2114AL-3 M2114AL-4 M2114A-4 M2114AL-5 Max. Access Time (ns) 150 200 200 250 Max. Current (mA) 50 50, 70 70 HMOS Technology 1 Directly TTL Compatible: All Inputs and Low Power, High Speed Outputs Identical Cycle and Access Times = Common Data Input and Output Using 4 Three-State Outputs Sinle +5 Supply = 10% meriascaas igh Density 18-Pin Package Military Temperature Range Completely Static Memory—No Clock 55°C to + 125°C (To) or Timid suobe neneee Not Recommended for New Designs ‘The Intel M2114A is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits usi HMOS, a high performance MOS technology. It uses fully DC stable (static) circuitry throughout, in both ihe array and the decoding, therefore it requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The data is read out nondestructively and has the same Polarity as the input data. Common input/output pins are provided. ‘The M211144 is designed for memory applications where the high performance and high reliability of HMOS, low cost, large Bit storage, and simple interfacing are important design objectives. The M2114A is placed in an ‘48-pin package for the highest possible density. Itis directly TTL compatibie in all respects: inputs, outputs, and a signal +5V supply. A separate Chip Select (C8) lead allows easy selection of an individual packge when outputs are or-tied. Pin Configuration Logie Symbol Block Diagram rio PinNames 771%"? Ao-Aa Address Inputs We Write Enable cs Chip Select WO1-VOg Data Input/Output | Veo Power (+5V) | zri001-3 GND Ground December 1969 at ‘Order Number 271001-003,intel M2114A FAMILY ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias. Storage Temperature Voltage on any Pin 65°C to + 135°C Cito +150°C NOTICE: This is a production data sheet. The speci. cations are subject to change without notice, S WARNING: Stressing the device beyond the “Absolute ‘Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the With Respect to Ground -3.5Vto +7V Acer ocean I reeeawe ce and ex. Power Dissipation. .... “1.0W — may-atfect device retail. Conetions D.C. Output Current SMA Operating Conditions ‘Symbol Parameter Min Max Units To Case Temperature (Instant On) —55 +125 “c Voc. Digital Supply Voltage 4.50 5.50 Vv D.C. AND OPERATING CHARACTERISTICS (Over Specitied Operating Conditions) ‘Symbol Parameter Lal = Units Comments Min | Typ@)|Max| Min | Typ(2)| Max Iu Input Load Current 10 10 | pA [Viv = Oto5.5V (All Input Pins) Ito ]VO Leakage Current 10 10 | pA [OS = Vw Vo = GND to Voc lec Power Supply Current 25 | 50 50 | 70 | mA [Voc = max, lo = OMA, To = —55°C Vin. Input Low Voltage -3.0 0.8 | -3.0) os| Vv Vie Input High Voltage 2.0 6.0 | 20 6.0 lou Output Low Current 24 9.0 a1 9.0 lon Output High Current | — 1.0) -2.5 7-10} -25 los) _ | Output Short Circuit 40 40 Nores: 1. Typical values are for To = 25°C and Voc = 6.0V. 2. Duration not to excoed 30 seconds. a2intel M2114A FAMILY CAPACITANCE Tc = 25°C, f = 1.0 MHz A.C. CONDITIONS OF TEST Symbol[ Test [Max Units [Conditions| input Pulse Levels ......... o.8vt020v Gyo | Input/ourput] 5 | pF {Vso = OV] — Input Rise and Fall Times vee tOns Capacitance Input and Output Timing Levels 1.8V Cin | Input 5 | pF [Vin=ov Output Load . 1 TTL Gate and Cy = 100 pF Capacitance Load for Toro and Torw ov ov ~ g1aK 10% Dot out * 100 pt so zr1001-4 arv001-s Figure 1 Figure 2 83intel M2114A FAMILY TYPICAL D.C. AND A.C. CHARACTERISTICS normed Output Load Capacitance rN Normalized Access Time Vs. Supply Voltage Yee Normalized Access Time Vs. cor Output Source Current _. Ve. Output Voltage You tame Normalized Access Time Vs. 1,Gase Temperature ure SS Es ou — Output Sink Current Vo. Output Voltage 2r1001-8intel M2114A FAMILY A.C. CHARACTERISTICS (Over Specified Operating Conditions) READ CYCLE() M2114AL-3 | M2it4A-4/L-4 | M2114A5 Symbol Parameter win | Max [Min | Max Teun] Max] Units tac | Read Cycle Time 160 200 250 ns ta ‘Access Time 150 200 250 | ns ‘co __| Chip Selection to Output Valid 70 70 5 | ne ‘tox®__| Chip Selection to Output Active | 10 10 10 ns toro® | Output 3-State trom Deselection 40 50 60 | ns toa | Output Hold trom Address Change [15 15 15 | [ns WRITE CYCLE® M21t4AL-3 | M2114A4/L-4 W2114A-5 Symbol coemete Min [Max | Min Max__| Min | Max | Units two | Write Cycle Time 150 200 250 ns tw | Write Time 90 120 195. ns twa __| White Release Time 0 0 0 ns torw® | Output 3-State from Write 40 50 60 | ns tow Data to Write Time Overiap | 90 120 136 ns ton Data Hold from write Time | 0 0 o ns WAVEFORMS READ CYCLE) WRITE CYCLE ® B aod ars001-7 zr001-8 NOTES: 1. A Reed occurs during the overtop of a iow GS and a high WE. 2| Measured at +500 mV with 1 TFL Gate and C, = 5 pt. Using Figue 2 8. A Write occurs during the overlap of a low CS and a low WE. ty is measured trom the latter of TS or WE going iow tothe ‘earir of CS or WE going high. 4° WE is high for a Read Oyo. 5.1 the CS low transiton occurs simultaneously with the WE low transition, the output butlers remain in a high impedance sate 6. WE must be high during ll address trensiions. 85