ELECTRICAL AND ELECTRONIC ENGINEERING

INTERRUPT SEQUENCES

Interrupt is breaking the sequence of operation. It provides a facility to change program environment. The
transfer of program control is initiated by interrupt or external event (external hardware)
An interrupt signals the microprocessor (P) that an external event has occurred that requires attention.
The external event may be associated with transfer of input / output (I/O) data to and from the
microcomputer timing function, abnormal or catastrophic external conditions. Fig. 1(a) shows a flow
diagram of an interrupt sequence to a normal program. Fig. 1 (b) shows the similarities of subroutines and
interrupts.

Transfer of Data

Suppose a device is to send a string of 80 characters to the P. Two methods can be used to handle the
situation:
(i) A program could be written which accepts the characters one after the other each time waiting for
a READY signal. This method is referred to as programmed I/O.
Example
Suppose a peripheral data reader has a speed of 500bytes/second. To read a byte takes
2mSec. If an Input instruction requires 2.75 S, then for the P to get new data, it will
continually query the reader by means of another Input instruction and checking whether
READY status is active. The P time wasted is 1997.25S. For 500bytes, 998625S
would be wasted.

(ii) Device controller could interrupt the CPU when a character is ready to be input, forcing a branch
from the executing program to a special interrupt service routine.

Interrupts allow the CPU to make use of idle time associated with I/O activity. With proper use of
interrupts, the CPU may execute another portion of the program while the I/O idle time occurs, and be
informed of the availability of next data byte by interrupting action. Multiple I/O activities coming from
various I/O devices can operate in the interrupt fashion signaling the CPU by vectored interrupts.

Interrupts can be used to provide CPU timing functions. A time interval is provided via interrupt, with a
programmable counter timer interface that interrupt CPU every 10 seconds or so. This enables the CPU to
maintain the real time clock for system time–out functions or time of the day indications.

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Interrupts may be used for signaling to the CPU abnormal or catastrophic system conditions like power
failure or failure of a redundant portion of the system. Non-maskable interrupt is used for these functions
since it is recognized immediately and not deferred until current processing is completed. If the interrupt is
NOT a catastrophic one, the system should be operative. Flags and all P registers must be stored exactly
as they were at the time of interrupt. The non-maskable routine must save the environment by performing
exchange instructions.

Intel interrupts
From the combined efforts of the bus interface, pre-fetch queue and the execution unit, the processor
can be seen to carry out instructions endlessly. To interrupt the processor from its ever ending
executions, a so-called interrupt is issued. For the 80x86, 256 different interrupts are available with
the first 32 interrupts for exclusive use by the processor.
Depending on the source of interrupt, one can distinguish three categories:
(a) Software interrupts
(b) Hardware interrupts
(c) Exception

Hardware, software and internal interrupts can be served on priority basis.

(a) Software Interrupt

 Are initiated with an INT instruction

 In real mode address space for i386, 1024 bytes are reserved for interrupt vector table (refer fig.
2). This table contains an interrupt for each of the 256 possible interrupts. The position for this
table with an i8086 is preset by hardware.
 The i386 has an interrupt descriptor table register, which stores the base address and the limit of
the table (00000000(segment-offset) and the maximum offset limit 03ffh).
 * It is possible to change, move interrupt table in real mode but care has to be taken in overwriting
of interrupt vector table with incorrect values since this has a catastrophic effect on i386.
 Software interrupts are synchronized with program execution; this means that every time the
program gets to the point where there is an INT instruction, an interrupt is issued.

(b) Hardware Interrupt

 Assigned to devices such as keyboard, printer and timer to mention a few.

 Set by hardware components or by peripheral devices.
 There are two basic types: Non-maskable (NMI) and maskable (IRQ)
 I8259A controller manages iRQs.
 Examples for NMI are (i) memory parity error and (ii) erroneous bus arbitration.
 Masked interrupts require enabling the interrupt flag (IE) which is always cleared whenever
software interrupt is executed by issuing CLI. Set the flag (STI) any time you wish to use
maskable interrupt.

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 Given a vector, where is the ISR address stored in memory?
Offset  Type  4 . Example INT 36H
Offset    3  16   6   4  00 D8 H

Fig. 3 Interrupting system

Sequence of events for a maskable interrupt routine

Whenever the interrupt controller receives a request from a device, the interrupt controller sends the
interrupt request signal (IRQ) to the INTR input pin of the i386. If the processor can handle the
interrupt (IE set) a confirmation signal INTA (Int. Ack) is sent by setting the control signals M/ I / O
, D/ C and W/ R low. Other controls and data transfers are shown on table 1

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 M / IO D/ C W/R Comment
0 0 0 Interrupt Acknowledge sequence
0 0 1 Stop/special bus cycle
0 1 0 Read data from I/O port
0 1 1 Write data to I/O port
1 0 0 Read an instruction from memory (pre-fetch)
1 0 1 Reserved
1 1 0 Read data from memory
1 1 1 Write data to memory

Table 1
Where M is memory, IO- input output, D- data, C- control, W- write and R- read.

(c) Exception

 Originates in the processor itself.

 Occurs due to an internal processor error caused by system software that canno longer be handled
by the processor alone.

There are three categories:

Faults Exception is prior to completing the instruction. IP points to the instruction that led to the
exception
Traps Issues exception after completing an instruction execution
Aborts Does not always indicate the address of the error

(i) Fault: Fault issues an exception prior to completing the instruction. The (E)IP value is
saved such that the processor is able to re-execute the instruction, hopefully without an
exception again. Ex. Segment not present

(ii) Trap: Issues an exception after completing an instruction execution. The saved (E)IP
value points to the immediate instruction following the instruction that gave the
exception. Trap has applications such as breakpoints.

(iii) Abort: Does not always indicate the address of the error. It is therefore not always
possible to recover program execution after an abort. Aborts are used to indicate serious
failures such as hardware failures or invalid system tables.

Note: Most exceptions used in i386 operate in protected mode.

The 8259A Programmable Interrupt Controller (PIC)

Introduction
The original 8088/8086 PCs used an Intel 8259A PIC (Programmable Interrupt Controller) to manage its
eight hardware interrupts (also called IRQs, which is short for Interrupt Requests). This separate chip
communicates with the processor and tells it when an interrupt needs to be serviced and which ISR
(Interrupt Service Routine) to call. Therefore, any device that generates interrupts is connected to one the
interrupt pins on the PIC, not to the CPU. The interrupt (or IRQ) pins on the PIC are numbered 0 to 7
where IRQ 0 is the highest priority interrupt and IRQ 7 is the lowest priority. The PIC connects to the
processor's single maskable interrupt pin. If an interrupt occurs, the PIC lets the processor know by
asserting this interrupt pin.

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The Interrupt Flag
One of the flags in the 8086 processor is the interrupt flag, usually referred to as IF. This flag can be set or
cleared with the STI and CLI instructions respectively. When set (1), the processor monitors its interrupt
pin. When it is cleared (0), the processor ignores the signals on its interrupt pin. Therefore, interrupts can
be enabled or disabled by setting and resetting the IF flag. However, this essentially disables
communication between the PIC and the processor, disabling all external interrupts. To disable individual
interrupts, a mask value can be written to the PIC instead. However, this will not be necessary for this class.

The 8259A's Registers

The 8259A has three 8-bit registers that determine its behavior: the IMR (Interrupt Mask Register), the ISR
(In-Service Register), and the IRR (Interrupt Request Register). The bits of these registers are numbered 0
through 7, where 0 is the least significant and 7 is the most significant bit. Each bit of each of these
registers corresponds to the respective interrupt pin on the PIC. That is, bit 7 corresponds to IRQ 7, bit 6
corresponds to IRQ 6, and so on.

The IMR. This register allows the programmer to disable or "mask" individual interrupts so that the PIC
doesn't interrupt the processor when the corresponding interrupt is signaled. For an interrupt to be disabled,
its corresponding bit in the IMR must be 1. To be enabled, its bit must be 0. Interrupts can be enabled or
disabled by the programmer by reading the IMR, setting or clearing the appropriate bits, then writing the
new value back to the IMR.

The IRR. This register indicates when an interrupt has been signaled by a device. As soon as a device
signals an interrupt, the corresponding bit in the IRR is set to a 1. This register can only be modified by the
PIC and its contents are usually not important to the programmer. However, it can be used to tell which
interrupts are waiting for service.

The ISR. This register indicates which interrupts are currently being serviced (i.e., which ISRs have begun
execution and have not yet finished). A 1 bit indicates that the corresponding ISR is currently in-service.
Several interrupts can be in-service at the same time because of interrupt nesting. The PIC uses this register
to determine the highest priority of the interrupts currently being serviced. With this information, the PIC
will only interrupt the processor if the highest priority set bit in the IRR has a higher priority than the
highest priority set bit in the ISR. In other words, the PIC will never interrupt an in-service interrupt in
order to service another interrupt of the same or lower priority. Before an ISR finishes executing, it must
send to the PIC the end of interrupt command (EOI) so that the PIC knows that it can safely clear the
highest priority bit in the ISR and signal any other pending interrupts. Be careful not to confuse "In-Service
Register" with "Interrupt Service Routine", both of which use the "ISR" acronym.

Processor/PIC Actions
When an interrupt occurs, if the interrupt is enabled in the IMR (i.e., it's IMR bit is 0) and if the processor's
IF flag is set (IF=1), then hardware does the following:

1. The PIC informs the processor that an interrupt has occurred by asserting the processor's interrupt
pin.

2. The processor finishes the currently executing instruction.

3. The processor sends an acknowledgement signal to the PIC.

Interrupt Acknowledge cycle (added information)
Upon receipt of an interrupt (INTR), the 80x86 executes a two special cycles called interrupt
acknowledge cycle whose purpose is to fetch the interrupt vector number from the interrupting
device through data bus lines D0 – D7.
1st INTA cycle (2 clks) asserts the INTA number line and alerts the interrupting device thet it must
be ready to provide the vector number.
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 2nd INTA cycle (2 clks) asserts the INTA number line and the interrupting device must provide the
vector number via the lower data lines.

Interrupt processing.

4. The processor uses this vector number to determine the address where the ISR (interrupt service
routine) is stored. The vector number is used as an index into the interrupt vector table (or
interrupt descriptor table), which starts at address 0:0. The corresponding entry in the interrupt
vector table contains the address (segment and offset) for the ISR.

5. The processor pushes the flags, CS, and IP onto the stack (in that order).

6. The processor clears IF, disabling interrupts.

7. The processor then sets CS and IP to the segment and offset of the ISR that was read from the
vector table and begins execution.

The vector number that is passed to the CPU by the PIC corresponds to the interrupt that occurs. IRQ 0
corresponds to vector number 8, IRQ 1 corresponds to vector number 9, and so on.

ISR Actions
Once execution begins in the ISR, your code that makes up the ISR should do the following (in the order
given):

1. Save the context of whatever was running by pushing all registers onto the stack, except SP, SS,
CS, IP, and the flags.

2. Enable interrupts to allow higher priority IRQs to interrupt.

3. Run the interrupt handler, which is usually a C function that does the work for this interrupt.

4. Disable interrupts.

5. Send the EOI command to the PIC, informing it that the handler is finished.

6. Restore the context of what was running before the interrupt occurred by popping the registers
saved in step 1 off the stack.

7. Execute the iret instruction. This restores in one atomic operation the values for IP, CS, and the
flags, which were automatically saved on the stack by the processor when the interrupt occurred.
This effectively restores execution to the point where the interrupt occurred.

Important note: When using an RTOS (Real-Time Operating System) it is also usually necessary to call
an OS function after step 1 to inform the OS that an ISR has begun execution. Then another OS function
must be called after step 5 to inform the RTOS that the ISR is finished. In the RTOS you will build, these
functions correspond to YKEnterISR() and YKExitISR(). This will allow the RTOS to know when
execution is supposed to return to task code and allows the RTOS to return control to the highest prority
ready task rather than the interrupted task.

Remember that the handling of the IRR and ISR registers in the PIC is done for you automatically as
interrupts occur. Additionally, you do not need to read or set the IMR since the PIC will automatically
ignore interrupts of the same or lower priority while an interrupt is being serviced. For the labs in this class,
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if you do not wish to use an interrupt, you should simply create an ISR that does not call an interrupt
handler.

Do not push or pop the registers SP or SS when saving and restoring context! This is not necessary since
SS and SP must already be correct before executing "pop ss" or "pop sp". Also, the "push sp" instruction
behaves differently on some 8086 clones. In an RTOS it will be necessary to save and restore SS and SP as
part of a task's context, but this should be handled in a different way (e.g., the mov instruction).

The EOI Command:

In order for interrupts to work correctly, the PIC must be told when the end of an interrupt has occurred. To
tell the PIC that the end of an interrupt has occurred we send it what is called a nonspecific EOI command
(or unspecific EOI). To do this we simply write the value 0x20 to port 0x20, which is one of the PIC's
ports.
mov al, 0x20 ; Load nonspecific EOI value (0x20) into register al
out 0x20, al ; Write EOI to PIC (port 0x20)

This code should be executed by every ISR right before it restores the context and executes the iret
instruction.

Figs 5 and 6 illustrates assignments of vectors and interrupt requests of a computer.