TOPIC 6 MEMORY AND I/O INTERFACING MEMORY INTERFACING i. External ROM (program memory) Interfacing —Je a oe FIGURE 1 INTERFACING OF ROM/EPROM TO uC 9051. above figure shows how to access or interface ROM to HObI. port 0 is used as multiplexed data & address lines. it gives lower order (Ay-As) 8 bit address.in initial T cycle & higher order (Asis) used as data bus. 8 bit address is latched using external latch & ALE signal from 8051. port 2 provides higher order (As-Ay) 8 bit address. PSEN is used to activate the output enab ROM/EPROM. signal of external ii, Bxternal RAM (data memory). Taterfacing an Re Iplines Dy LT RAM 8051 LavcH AS ALE |——slock?| 7 |! Ayp address Tines | —S> _—— 7 3 mole: ps WR WR cE FIGURE 2 INTERFACING OF RAM(DATA MEMORY) TO pC 8051 above figure shows how to connect or interface external RAM(data memory) to 8051. port 0 is used as multiplexed data @ address lines. address lines are decoded using external latch & ALE signal from 8051 to provide lower order (A7-A0) address lines. port 2 gives higher order address lines. RD & WR signals from 8051 selects the memory read & memory write operations respectively. BD & WR signals: generally 73.6 & P3.7 pins of port 3 are used fo generate meanory read and memory write signals, remaining pins of port 3 i.e. P3.0-P3.5 can be used for other functions. 6 MEMORY AND I/O INTERFACING Chapter:LINEAR AND ABSOLUTE DECODING i. Absolute Decoding all h ss lines : decode sele specific logic levels. for other logic levels memory chip is disabled. generally used in large memory systems. figure below shows memory interfacing using absolute decoding. 7418373 Arve 8051 FIGURE 3 MEMORY (RAM) IVTERFACING USING ABSOLUTE DECODING: ii. Linear Decoding (Par for small systems ial Decoding) individual higher order address lines used to.select menory ch replacing the hardvare by decoding logic. reducing the cost of decoding, drawback is~ multiple addresses. as shown in Figure ow, Ay line is directly connected to chip select line, Ars\]inesnot anywhere, kep so, status Of Ais- not considered for generation of chip select signal. i= P0.7 148373 Ay-Bo ALE, alc oe FA 16 x 8 FIGURE 4 MEMORY (RAM) INTERFACING USING LINEAR DECODING. NG FACT B r/o 0 AND MEMORYAddress Mapping (Memory Map) i. Absolute Decoding Address Ais Aus Ais Auz Au Aus Ag Ac Ar Ac As Ay As Ar Ay Ay HEX adrs. starting 0 0 00 0 0 00 0000 0 0 0 0 0000H end oo 2 2 2122 221212 111 1 35FFH ii. Linear Decoding Address Ass Ar: Ars Arp Au Aap As As Ay Ac As Ax Bs Ap Ar Ay HEX adrs. starting 0 0 0 0 09 0 00 0000 6 0 0 0 s000H end x O12 2211 21221 1111 3FFFH Comparison between Full address (Absolute) § Partial address (Linear) Decoding. Full Adress (Absolute) Hl Partial Address (Linear Decoding Decoding i. all higher address lines are |i. few or individual address Jines decoded to select memory or | are decoded to select memory or I/O device. | 1/0 device, ii. more hardware : decoding lid. less hardware 2 deccding logic. logic. i (sometimes none») iii. decoding circuit : higher |iii. decoding circuit : less cost. cost. | iv. No multiple addresses. liveemultiple addresses possible. v. used in large systems. lv. used in small systems. Solved Examples: Example 1: Design a wController system using 9051,Interface the external RAM of size 16k x 8. Solution: Given, Memory size: 16k Vee that means we require 216k :: n address lines here n=14 t: Ay to Aw address lines are required. Aus and Ais are connected through OR gate to CS pin of external RAM. when Ay and Ai: both arc low (logic ‘0’), external data memory (RAM) is selected. Address Decoding (Memory Map) for 16k x 8 RAM. Address Ais Aw Ais Az Au Aso Ay As Ar Ae Ay Ag Ay Az By Ay HEX adrs. starting O/ 0-00 0 0 00 0000 6 0 0 © o000n end oc 2? Litt ttiadiiii 2 3eFFH _ EO.T D7-D0 FA 1 0.0 7418373 ALE >) 6 oc 8051 p20 Po 1 Ag-AL3 2.5 P2.6 2.7 SEN P3.6 3.7 w FIGURE 5 16K X 8 MEMORY (RAM) INTERFACING TO pe GOST 6 MEMORY AND I/O INTERFACING hapter:Example 2: Design a pController syste: size 4k x 8. using 8051. Interface the external ROM of Solution: Given, Memory size: 4k that means we require 2'=4k :: n address lines here n=12 :: Ay to An address lines are required. remaining lines As, As, As, Ay & PSEN are connected though OR gate to CS & RD of external ROM. when Ay to Ay are low (logic ‘0'), only then external ROM is selected. Address Decoding (Memory Map) for 4k x @ RAM, swing 0 00 0000 00000000 bum Vss oa irr _—_, T4L8373 Ar-Aa 8051 ROM ke - 22.7 WR PSEN >) oS 1 P3.7 —*> Bb FIGURE TG «x De Vaqeons! (ROM) INTERFACING 10 pC BST Example 3: Design a uController system using 8051, 16k bytes of ROM & 32k bytes of RAM. Interface the memory such that starting address for ROM is Q000H & RAM is BO0OH. Solution: Given, Memory size= ROM : 16k that means we require 2"=16k :: n address lines here n=1¢ :2 Ay to Ay address lines are required. AL4,A15, PSEN —> ORed —» TS when low ~ ROM is selected Memory size- RAM :32k that means we require 2"=32k :: n address lines here .n=15 to As address lines are required. ALS ——> inverted(NoT Gate) ———> Cs when high- RAM is selected. (BEN is used as chip select pin ROM. RD is used as read control signal pin. WR is used as write control signal pin. 6 MEMORY AND I/O INTERFACING Chapter:Address Decoding (Memory Map) for 16k x @ ROM. Address Ais Au Ais Ala All Ais As Ac Ay Ae As Ac As As Al Ap HEX adzs. starting 0 0 0 0 0 000 0000 0 00 0 0000K end 00 11 241 11 2211 1 11 1 35FFH Address Decoding (Memory Map) for 32k x 8 RAM. Address Ass Ais Bsa Biz Bn Aso Aa Ae Ay Ac As Ac Aa Az Ax Ay HEX adzs. starting 1 0 0 0 09 000 0000 000 0 8000H end aiid oda. a2 2222 2211 FRRFR Vee Vee Vas I 1 _ PO.7 I-00 FY 7-00 Ei UNG PO.0 7428373 RI-RO AT-AO mel Jo oe 16k x 8 32k x 8 8051 ROM RAM peo i ne-A13 —) AB-A13 P2.5 P26 _ = 2.7 | 3 E4 Bes) TEEN eee] ata P3.6 >) RD =z BD WR FIGURE 7 16K x p ROE 2m GaNy e BAM INTERFACING 70 pC 8052 Example 4:Design a pController system using 8051, 8k bytes of program ROM & 8k bytes of data RAM. Interface the memory such that starting address for ROM is OOOOH & RAM is EOOOR. Solution: Given, Memory size=-ROM : 8k that means we require 2"=8k :: n address lines here n=13 :2 Ay to Ay address lines are required. Al3,Al4,A15,PSEN——» ORed —» CS Memory size- RAM :8k that means we require 2"=8k i: n address lines here n=13 to Ay address lines are required. Al3,A14,A15 ———> NANDed ——* CS when high data RAM 4 (BEEN is used as chip select pin ROM. RD is used as read control signal pin. WR is used as write control signal pin. 6 MEMORY AND I/O INTERFACING Chapter:Address Decoding (Memory Map) for 8k x 8 ROM. Address Au Ais Aiz Au Ais As As Ar Ac As As starting 0000 0 000 0000 end 09001 2111 11 Address Decoding(Memory Map)for 8k x 8 RAM. Address As Avs Ars Aiz An Ais Ay Ag Ay Ac As Ac As Ae Ai As HEX starting 1 1 © 9 0 00 OOOH end .aidid tai FEFFH PO.7 DD: I P0.0 AiR ALE F oh} exe ek x 8 8051 1 ROM RAM P2.0 [> AeA? Ae-Acz cs wR RD FIGURE @ 8K Xp ROE sm Gy Mo RAM INTERFACING TO pC 8051 NG FACT B r/o 0 AND MEMORY