Low-voltage Low-power CMOS IF Programmable

Gain Amplifier

B. Calvo, S. Celma and M. T. Sanz

Group of Electronic Design

University of Zaragoza
E-50009 Zaragoza, Spain
{becalvo, materesa, scelma}(unizar.es

Abstract-This paper presents a low-voltage low-power

differential programmable gain amplifier (PGA) for wideband
applications. To achieve low-voltage low-power and wideband
operation while preserving linearity, the proposed cell is based
on a gm-boosted source-degenerated differential pair.
Programmability is achieved combining two techniques, a
switchable array of source degenerating hybrid polysilicon-
MOS resistors and a programmable output current mirror.
Designed in a 0.35 gm CMOS technology, the proposed PGA is
very compact in terms of silicon area and consumes 0.5 mW
from a single 1.8 V supply. The programmable gain varies
linearly in-dB from 0 to 21 dB in 3 dB steps through a 4-bit
word. Simulation results show an almost constant bandwidth
of 100 MHz and total harmonic distortion figures are below -70
dB over the whole gain range at 10 MHz for a 0.2 Vp-p
differential output.
I. INTRODUCTION
Programmable gain amplifiers (PGA) are basic building
blocks employed in many applications in order to optimize
the dynamic range of the overall system. Hard-disk-drive
(HDD) read/write channels [1, 2] and virtually all wireless
communication systems [3, 4, 5] are paradigmatic examples
where amplitude equalization is an essential part of the linear
signal processing. Fig. 1 shows a typical arrangement for a
PGA in an analog front-end. The amplifier is embedded in a
digital automatic gain control (AGC) loop that adjusts the
output signal to the optimal level for different input signal
strengths. Gain control computation is accurately performed
in the digital domain by using a digital signal processor
(DSP). To achieve a constant settling time of the AGC loop a
linear-in-dB gain control for the PGA is required [6].
The PGA design is clearly demanding in terms of
bandwidth and distortion so as to not limit the performance
of the succeeding circuits. In addition, the market has pushed
the industry to the implementation of monolithic CMOS
circuits to improve reliability and trim time-to-market.
Therefore, low voltage design techniques are mandatory.
Low power and area consumption architectures are also
becoming necessary, especially in the portable equipment
market. In CMOS technology, designing a low voltage PGA
with wide bandwidth, high linearity and acceptable power
consumption is a real challenge, and the focus of this work.
Fig. 1: Block diagram of an analog front-end
There are mainly two approaches for the implementation
of variable gain circuits: negative feedback closed-loop
configurations and open-loop amplifiers. A closed-loop
architecture exhibits better linearity and may allow a better
control of gain and accuracy. However, a large amount of
power consumption is usually required for an acceptable
amplifier performance, particularly in terms of bandwidth.
This architectural choice thus involves a trade-off between
gain range, bandwidth, linearity and power dissipation. On
the other hand, open-loop amplifiers are suitable for low
power and broadband applications, but the open-loop nature
of the circuit makes the linearity depend heavily on the
inherent linearity of the input stage. Therefore, the use of
linearization schemes is often required. The most widespread
open-loop variable gain amplifiers are based on simple
differential or pseudo-differential pairs [7], source
degeneration techniques [8, 9], analog multipliers [10, 11]
and differential pairs with diode connected loads [4].
This paper describes a differential programmable gain
amplifier with a single supply voltage of 1.8 V in a standard
3.3 V - 0.35 tm CMOS technology. It is based on a very
simple widely tunable differential pair degenerated with a
MOS-polysilicon resistor network and programmable output
current mirrors. In this way, a good trade-off between power
dissipation, gain programmability range, linearity, bandwidth
and area consumption will be achieved. Both the circuit
principle and the gain programmability scheme are discussed
in Section II. The PGA main performances are summarized
in Section III. Finally, in section IV some preliminary
conclusions are presented.

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Vot 2 Vj+ t M 1 || M 1 2 Vn
M3 >V VcasH
M2 M
M 2
Fig. 2: PGA conceptual scheme
II. PGA ARCHITECTURE
A. Differential Amplifier Architecture
The proposed differential programmable gain amplifier is
based on the conceptual scheme shown in Fig. 2. It is a
negative feedback gm-boosted source degenerated differential
pair with resistive loads.
Focusing on the transconductor core, it is a source
follower where the current through transistor Ml is held
constant [12, 13]. Transistors MI-M2 form a two-pole
negative-feedback loop that reduces the equivalent source
resistance of the input voltage buffer Ml down to 50 Q, value
approximately given by 1/(g9m1r1gm2), where all parameters
have their usual meaning. Consequently, for a source-
degenerated pair exploiting this approach, the differential
transconductance can be expressed as a/R, where oc denotes
the Ml gate-to-source DC voltage gain, which is somewhat
less than unity due to the body effect and R denotes one-half
the degeneration resistance. The simplicity of this modified
differential pair makes it very attractive for high-frequency
and low-voltage operation, conditions we are interested in.
The linearized differential signal current, copied out by
loading each M2 gate terminal with a matched NMOS device
and using cascode transistors M3 to provide a high output
resistance, is converted to voltage through load resistors RL.
Thereby, the differential gain of this stage is given by
Gain = ao RL
R
The amplifier gain can be selected either by using a
variable degeneration or load resistor. However, it is
preferably implemented using a variable degeneration
resistor while maintaining a constant load resistor. This
choice, adopted in this work, results in a fixed dominant
pole at the PGA output nodes, and thus a constant
bandwidth is maintained throughout all the gain stages [9].
For high-frequency applications, noise specifications limit
the value of the load and degeneration resistors to the kQ
range. Further, polysilicon resistive loads RL will be
implemented so as not to degrade the linearity performance.
B. Programmability
The simplest variable degeneration resistor is based
on the parallel connection of a switched array of MOS
transistors biased in the triode region. The resulting
topology is very compact in terms of silicon area. However,
o out the linearity performance and tuning capability of this
approach is limited by the modern supply voltages.
M3
For low-voltage operation, the common solution is the
M2 use of programmable arrays of passive resistors. High
linearity and dynamic range have been achieved with this
approach. Unfortunately, extensive area is needed to
guarantee accuracy and the operating frequency can be
limited by the presence of switches in the signal path.
To preserve good linearity and moderate area
consumption we have adopted an approach combining linear
polysilicon resistors and MOS transistors biased in the triode
region, which act simultaneously as resistors and switches.
Following this strategy, the proposed degeneration scheme is
shown in Fig. 3. The minimum gain setting is imposed by a
fixed high resistivity polysilicon (HRP) resistor R,. The gain
is then digitally controlled by adding in parallel a new linear
resistor in series with two Msi NMOS switches biased in the
triode region, whose on-resistance is one half of the total
conversion impedance.
An additional gain programmability degree of freedom
can be provided at the output current mirrors implemented
through M2-M3 by adding identical output stages in parallel,
as shown also in Fig. 3. The M3 cascode transistors act as
the switching elements. Their gate are controlled through aj
bits that fix the cascade gate voltage to Veas (branch ON) or
to ground (branch OFF), thus allowing to set the output
current mirror gain K to the desired value. Note that MI-M2-
M3 form a wide swing cascode current mirror topology.
Therefore, to improve the current copy transistors M3 will
be equally sized to Ml, and Veas equal to the input DC
common mode voltage VCM. When switching the output
stages, parallel DC current sources must be activated so as
to maintain the same output DC bias current value and
common mode voltage.
o-1 mi R Ml [ -o M
SiR /2 s
* ~~~R*/4 Ri /4
K..~~~~~~~~~~~~~~~~~~~~~~~~....
.R..... M3 M3
M2 M2 HM22 M2
Fig. 3: Digital gain programmability implementation
277
 Ro

a, I
~~~C;;h~--L
(W/L) (W/~~L)

2(W/L) 2(W/~L)
a2E
4/0.5
4(W/L) 4(W/L)
(a) (b)
Figure 4: PGA detailed schematic: (a) core and (b) programmable degeneration impedance

dB-scale from 0 to 21 dB in 3 dB steps, as shown in Fig. 5,

C. PGA implementation which reproduces the frequency responses for the main gain
The complete PGA scheme, specifying transistor sizes, settings. The bandwidth is kept constant around 100 MHz
is shown in Fig. 4. The cell, designed in a 0.35 tm CMOS assuming at the two outputs capacitive loads of 150 fF. The
process, is supplied at a single voltage of 1.8 V and the bias total harmonic distortion (THD) behaviour for a signal
current value has been fixed to 40 pA. Biasing currents have frequency of 10 MHz is depicted in Fig. 6 considering
been implemented through cascode configurations.
The programmable degeneration impedance consists of a TABLE I
3-bit array [a2 a, ao] of hybrid HRP-NMOS resistors in SUMMARY OF PGA PERFORMANCES
parallel, binary weighted to obtain a logarithmic gain Parameter Value
distribution ranging from 0 to 18 dB in 6 dB steps through a
thermometer code control. An additional a3 four bit allows Technology 0.35 urm CMOS
the output current mirror gain to be set either at K=1 or 1.5. Supply voltage 1.8 V
This enables to equally scale each 6 dB step, so that the Gain range, 4 bits 0 to 21 dB, 3 dB step
scheme covers an overall 0 to 21 dB gain programmability Bandwidth 100 MHz
range, in 3 dB steps, by a 4-bit discrete coarse tuning. Fine THDg 10MHz, 0.2 V. out < -70 dB
gain tuning can be performed if necessary through slight In-band noise @ 0 dB 51 nV/NHz
gate voltage variations for the switching transistors in order Quiescent power 0.5 mW
to improve the accuracy. Estimated Area 0.004 mm2
One important design parameter is the common-mode
voltage (VCM). The proposed cell has a limitation in the
input voltage signal swing, imposed by maintaining
transistors MI, M2 in saturation. Therefore, the input VCM
has been set to 1.3 V so as to obtain a maximum voltage
swing of 0.6 Vp-p on each input, or equivalently, a maximum
differential 1.2 Vp-p input voltage swing. Higher voltage
swings can be reached by including a DC level shifter in the
feedback path as in [9], but at the cost of a higher power
consumption. Hence, this option will not be considered, as a
our design goal is to maintain low power dissipation.
.)
A load resistor RL=8.3 kQ has been chosen. Therefore,
when the current mirror gain K=1, an additional current
source controlled through the complementary of a3 switches
on to generate a suitable common-mode output voltage.

III. PGA PERFORMANCES

The main performances of the proposed PGA, obtained
06
1 108 109
frequency (Hz)
by using Spectre with a BSIM3v3.2 level 53 transistor
Fig. 5: PGA frequency response
model, are summarized in Table 1. It consumes 0.5 mW (solid line, K=1; dashed line, K=1.5)
from a single 1.8 V supply. The gain increases linearly in a

278

-50 18 dB
-55
12 dB
6 dB
j//
m 0 dB
2 -60
N
I
2 -65
0 figures below -72 dB. This cell can be the basis for high-
O -70
-75
-80
0 0,2 0,4 0,6
Vout (Vpp)
Fig. 6: THD levels at 10 MHz for all gain settings
constant differential output levels. Figures are below -70 dB
over all the gain setting range with a differential output
signal level of 0.2 Vp p, value that increases to -60 dB for 0.4
Vp-p.
Finally, the main performances of the proposed design
are compared in Table 2 with those of several previous
realisations: references [8], [14] and [15], all using switched
banks of linear polysilicon resistors to obtain a similar gain
range. The presented circuit has a bandwidth just as large as
other published PGAs for similar technologies at a lower
supply voltage of 1.8 V and with significantly lower power
consumption and area. On the other hand, with our design-
as well as with [8], also based on a gm-boosted degenerated
differential pair- linearity is limited by the open loop nature
of the amplifier structure. The configurations described in
[14] and [15] use amplifiers operating in closed loop with a
resistor network feedback, thus obtaining better distortion
levels, at the cost of higher power consumption.
IV. CONCLUSIONS
A low-voltage 3-bit programmable gain amplifier has
successfully been implemented in a 0.35 tm CMOS process
showing a good trade off between power consumption,
maximum operating frequency and linearity. Measurement
results for a simple general purpose PGA show a wide
constant bandwidth over the 100 MHz range with distortion
gain multiple-stage PGAs fitting the specifications of many
applications, such as disk drivers, communication receivers,
subscriber lines, etc. In this case, the first gain stage can be
implemented as a low noise common-gate structure based
on the proposed topology, with the input resistance valued
so as to match the input network. Furthermore, the design
0,8 can be easily migrated to a 0.18 ptm 1.8-V CMOS process.
ACKNOWLEDGMENT
This work has been partially supported by DGA-FSE
(PIP/187-2005) and MCYT-FEDER (TIC2005-00285
/MIC).
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TABLE II
COMPARISON OF SEVERAL PGAs PERFORMANCES

Design [8], 1996 [14], 2003 [15], 2001 This work

CMOS process (rim) 0.5 0.35 0.25 0.35
Supply voltage (V) 5 3.3 2.5 1.8
Total current (mA) 5 6.4 2.7 0.28
Gain range (dB) -2 to 12 0 to 19 5.6 to 17 0 to 21
-3 dB BW (MHz) 15 125 100 100
Linearity at 10 MHz
Vpp ouJVs pply 0.2 0.6 0.56 0.2
THD (dB) -60 -74 -67 -60
Area (mm2) 0.175 0.18 0.038 0.004

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