library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity principal is
Port ( clk : in STD_LOGIC;
reset: in STD_LOGIC;
numero : out STD_LOGIC_VECTOR (2 downto 0));
end principal;

architecture Behavioral of principal is

COMPONENT ff_jk
PORT(
j : IN std_logic;
k : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
q : OUT std_logic
);
END COMPONENT;

signal q0, q1, q2: STD_LOGIC;

signal jk0, jk2: STD_LOGIC;

begin

jk0 <= '1';

jk2 <= q1 and q0;

Inst_ff_jk_0: ff_jk PORT MAP(

j => jk0,
k => jk0,
clk => clk,
reset => reset,
q => q0
);

Inst_ff_jk_1: ff_jk PORT MAP(

j => q0,
k => q0,
clk => clk,
reset => reset,
q => q1
);

Inst_ff_jk_2: ff_jk PORT MAP(

j => jk2,
k => jk2,
clk => clk,
reset => reset,
q => q2
);

numero(0) <= q0;

numero(1) <= q1;
numero(2) <= q2;
end Behavioral;