Digital IC Design - VL710

COURSE PLAN AND EVALUATION PLAN

0.1. Course Code: VL710 2. Course Title: Digital IC Design

3. L – T – P: 3-0-2 4. Credits: 4
5. Pre-requisite: Nil 6. Teaching Department: E & C Engineering
7. Course Instructor: Kalpana G. Bhat
8. Objectives of the Course:
At the end of the program the student must be able to
 Appreciate the usefulness of CMOS technology
 Design and optimize digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability
 Evaluate the circuit performance in different logic families
 Design CMOS circuits at schematic and layout levels for a given technology node
 Simulate the CMOS circuits using SPICE netlist obtained by extracting schematic and layout designs
9. Course Coverage (42 – Lecture Schedule):
Module Contents Lecture Evaluation
L1
Introduction to digital IC design
MOS device Device operation - Introduction of basic device equations, Introduction of
L2-L5 Comprehension
models for manual analysis, spice models, DSM effects, parasitic capacitances
Assignment I
Manufacturing Comprehension,
Fabrication process, Design rules L6-L8
technology Analysis
CMOS inverter – VI Characteristics, inverter delay, delay with load, buffer L9-L12 Application,
The Inverter design, power dissipation, principles of power reduction, technology scaling Analysis
Assignment II
The Comprehension,
Interconnect parameters, electrical wire models, wire delay L13-L15
Interconnect Analysis
Comprehension,
Static CMOS, Gate delay, logical effort, power consumption, Ratioed logic,
Combinational L16-L25 Application,
Pass-transistor logic, Dynamic logic
logic design Analysis
Assignment III
 Comprehension,
Sequential
Introduction, static and dynamic latches and registers L26-L30 Application,
logic design
Analysis
Set-up time, hold time, clock skew, clock jitter, timing requirements in Comprehension,
Timing Issues L31-L33
sequential circuits Analysis
Application,
Analysis,
Subsystem Adders, multipliers, shifters L34-L39
Design,
Design Evaluation
Term project
Application,
Memory
SRAM and DRAM, 6T-SRAM design considerations L40-L42 Analysis,
Design
Design,

10. Reference Books :

a) Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital Integrated Circuits – A design perspective”, Pearson, 2003
b) S. M. Kang & Y. Leblebici, “CMOS Digital Integrated Circuits”, McGraw Hill, 1999.
c) N. Weste and K. Eshraghian, “Principles of CMOS VLSI Design: A systems perspective”, 2 nd edition, Addison Wesley, 1993.
d) David A Hodges, Horace G. Jackson and Resve Saleh, “Analysis and Design of Digital Integrated Circuits”, 3 rd edition, Mc Graw
Hill, 2003
11. Evaluation Plan :

Mid semester exam - 25%

Quiz - 20%
Mini-project - 15%
End semester exam - 40%

12. Minimum passing mark - 30%

Kalpana G. Bhat Prof. Muralidhar Kulkarni

Asst. Professor, Dept. of E&C Engg. Prof. & Head, Dept. of E&C Engg.