FREQUENCY SYNTHESIS

WITH THE PLL

modules
basic: UTILITIES, VCO
advanced: DIGITAL UTILITIES, ERROR COUNTING UTILITIES

preparation
The Lab Sheet entitled Carrier acquisition – PLL examined an application of the phase
locked loop (PLL) in an analog environment. This Lab Sheet examines the same functional
arrangement, but in a digital environment. In the analog version the signals involved are
sinusoidal. In the digital version to be examined they are ‘digital’ – in TTL format.
Instead of an analog MULTIPLIER being used as a PHASE COMPARATOR, an EXCLUSIVE-OR
gate is used to compare the input TTL signal with a TTL output from a VCO.
The use of TTL signals enables a very simple - but significant - modification to be made.
This is the addition of a DIGITAL DIVIDER in the feedback loop.
A little thought will show that for lock to occur (signals of similar frequency at the inputs to
the exclusive-OR gate) it is necessary that the VCO frequency be ‘n’ times greater than the
input frequency, where ‘n’ is the digital division ratio.
This introduces a multiplication factor between the input and output signal frequency.
A second digital divider (of division factor ‘m’, say) can be inserted in the input path. Then
between the input to this divider and the VCO output there is a frequency multiplication
factor of n/m, or a division of m/n. This then is an implementation of a fractional frequency
divider. It finds application as a frequency synthesiser, which generates signals related to a
stable, reference source.
What ever name it is given, the arrangement can be modelled with TIMS, and some of its
capabilities demonstrated. However, its analysis is not a trivial matter, and is not attempted
here. Likewise, measurement of many of its properties (see below) presents practical
difficulties.

TTL input clock

X - OR TIMS allows one to make a model
at f bits/sec LOOP VCO
and to confirm that, in principle, the
FILTER
TTL output
arrangement exhibits useful
at nf bits/sec properties.
DIGITAL
DIVIDE by
‘n’ A block diagram is shown in Figure 1
opposite, and a model in Figure 2
Figure 1: block diagram below.

www.emona-tims.com 1/2
Emona-TIMS frequency synthesis with the PLL L-77 rev 1.0

experiment
The model shows the DIGITAL DIVIDER set to a division ratio of n = 9. Other ratios should
be examined. These, of course, must lie within the tuning range of the VCO.
A suggested input is the 8.333 kHz TTL SAMPLE CLOCK from MASTER SIGNALS.
For initial set-up, tune the VCO to
TTL out
TTL in
approximately ‘n’ times the input
signal before closing the negative
feedback loop.
Note that the TTL output from the
VCO is shown as the output of the
arrangement, but a sinusoidal
output is also available.
Figure 2: the TIMS model
When the loop is closed lock may be achieved. But this depends upon the setting of the
GAIN control of the VCO, which governs the loop gain of the negative feedback
arrangement. There will obviously (?) be no lock if there is insufficient gain, and probably
none if ‘too much’ gain is available. What might be the reason for this latter behaviour ?
Calculating the optimum amount of loop gain, as in most other calculations involving the
arrangement, is non-trivial. It may be necessary to further adjust the tuning of the VCO,
after closing the loop, to obtain a lock.
Since the DIGITAL DIVIDERS in the DIGITAL UTILITIES are independent, those not already
incorporated as the ‘n’ divider can be inserted in the input to implement the ‘m’ division,
referred to earlier. This demonstrates the fractional multiplication capabilities of the
arrangement.
The ‘new’ frequency component could have been obtained from the VCO alone, without the
negative feedback arrangement. But its frequency stability would have been dependent on
that of the VCO alone. The PLL-configuration ensures that the stability of the output signal
is intimately related to that of the input, or reference, clock. Herein lies one of the important
characteristics of the arrangement. Using a multitude of such phase locked loops many
different frequency components can be derived from a single, stable, reference source.
It finds wide application in many areas of communications systems, but perhaps is most
commonly found in frequency synthesisers. In combination with programmable dividers,
and commonly two reference frequency sources, it forms the basis of many channel
selecting systems in both receivers and transmitters.

measurements
Note that this Lab Sheet describes an ‘experiment’. Merriam-Webster defines this as “an
operation carried out under controlled conditions in order to discover an unknown effect or
law, to test or establish a hypothesis, or to illustrate a known law.” This is the approach
you can use in your investigation.
Have a look at the control voltage to the VCO. Is it pure DC ? If not, would this effect the
purity of the VCO output ? Measure the characteristics of the X-OR gate – for feedback to
cause lock, what should be the output when both inputs are the same ? Observe what
happens if an INVERTER (available in the DIGITAL UTILITIES module) is included in the
feed back path.

TIMS Lab Sheet copyright  tim hooper 2002, amberley holdings pty ltd ABN 61 001-080-093 2/2