CMOS Technologies in The 100 NM Range CMOS Technologies in The 100 NM Range For Rad-Hard Front-End Electronics in Future Collider Experiments P

CMOS technologies in the 100 nm range
for rad-hard front-end electronics in

future collider experiments
p
V. Rea,c, L. Gaionib,c, M. Manghisonia,c,

L Rattib,c
L. b c, V.
V Spezialib,c
b c, G.
G Traversia,c
ac
bUniversità degli Studi di Pavia

Dipartimento di Elettronica
aUniversità degli Studi di Bergamo

Di
Dipartimento
ti t di IIngegneria
i IIndustriale
d t i l
cINFN
S i
Sezione di P
Pavia
i
Motivation
Future generation of HEP experiments (LHC upgrade, ILC, Super B-Factory):
mixed signal integrated circuits for the readout of silicon pixel and microstrip
detectors designed
g in 130 nm ((90 nm)) CMOS p processes
Industrial technology development is driven by digital circuits; the critical
aspects for detector readout chips are noise performance, power dissipation
and radiation damageg
Inner SLHC detectors: ultra-deep submicron systems exposed to ionizing

radiation doses of 100 Mrad and beyond
While the scaling of the gate oxide thickness to about 2 nm gives a high
degree of radiation tolerance, issues such as the gate tunneling current and
the sidewall leakage associated to lateral isolation oxides must be investigated.
With special focus on the design of analog front-end circuits for silicon pixel
and strip detectors, the impact of ionizing radiation on the noise performance
is evaluated and the underlying
y g physical
p y degradation
g mechanisms are pointed
p
out to provide criteria for improving radiation hardness properties.
Sensitivity to Single Event Effects (SEE) can be a major problem for digital
systems in 100
100-nm
nm scale CMOS. The discussion of SEE and of circuit design for
SEE immunity is beyond the scope of this talk.
8th International Conference on Large Scale Applications, Florence, June 29th 2007 2
Investigated technologies and devices
Standard open layout PMOS and NMOS transistors from HCMOS9 130 nm and
CMOS090 90 nm triple well, epitaxial CMOS technologies by STMicroelectronics
HCMOS9 (Lmin=130 nm) CMOS090 (Lmin=90 nm)
Technology features: Technology features:
– VDD = 1.2
12V – VDD = 1 V
– Physical oxide thickness tOX= 2 nm – Physical oxide thickness tOX= 1.6 nm
– COX=15 fF/μm2 – COX=18 fF/μm2
Enclosed layout NMOS transistors (and standard PMOS) from 2nd 130 nm
CMOS vendor (CERN) Leakage path
G G
S D D S
Standard Enclosed
Irradiation tests
Front-end integrated circuits for inner detectors at SLHC must feature a high
radiation resistance, up to several hundred Mrad total dose of ionizing radiation.
Outer SLHC detector layers and less demanding (in terms of rad-hard
requirements) collider experiments set radiation tolerance specifications of
several Mrad on front-end electronics
10 Mrad irradiation 100 Mrad irradiation

60Co γ-rays 10 keV X-rays
– 90 nm and 130 nm open layout – 90 nm open layout devices from
devices from STMicroelectronics STMicroelectronics
10 keV X-rays – PMOS and enclosed NMOS from 2nd

– PMOS and enclosed NMOS from 2nd 130 nm vendor
130 nm vendor
d
The MOSFETs were biased during irradiation in the worst-case condition (all
terminals grounded, except gate of NMOS kept at VDD)
Ionizing radiation effects and scaling of
th gate
the t oxide
id thickness
thi k in
i ultra
lt deep
d
submicron CMOS
In very thin gate oxides (2 nm), radiation induced positive trapped charge is
removed by tunneling processes
Effects on threshold voltage and static drain current characteristics are very
small;
ll threshold
h h ld voltage
l shift
hif at 100 Mrad
M d isi off the
h order
d off 1 mV,
V if any
-1
10
-2
10
In PMOSFETs and in enclosed 130 -3

10 before irradiation
nm NMOSFETs, Id vs Vgs curves -4
100 Mrad
are unaffected by irradiation. 10
A]
130 nm vendor
Id [A
-5
10
Enclosed NMOS
-6 Vds = 0.6 V
10
W=1000 μm
-7 L=0.12 μm
10
-8
10
-9
10
0 0,5 1
Vgs [V]
Radiation effects in open layout NMOS
Radiation induced increase of the drain current is apparent in the constant
leakage
g current zone and in the subthreshold region.g This effect is larger
g in the
130 nm devices, whereas the impact is minor in 90 nm transistors. This behavior
is associated to the lateral parasitic transistors at the edge of the device.
-1
10 10
-1
-2
10
10
-2 pre-rad
-3 Prerad
10
-3 100Mrad
10
10
-4
10 Mrad
-4
10
I [A]
I [A]
10
-5 V =0.6 V
DS
D
d
-5
10
-6
10
-6
-7 10
10 90 nm STMicroelectronics
NMOS 130 nm NMOS, W/L = 200/0.13
W=1000 μm
-7
7
10
-8 10 Vds=0.6V
-9
L=0.13 μm -8
10 10
0 0,5 1 -0,2 0 0,2 0,4 0,6 0,8 1
V [V] V [V]
gs
GS
Radiation effects in lateral
isolation structures
In deep submicron bulk CMOS devices exposed to ionizing radiation, the main
degradation effects are associated to the thick (~ 300 nm) lateral isolation
oxides (STI = Shallow Trench Isolation).
Radiation-induced positive charge trapped in isolation oxides may invert a

P-type region in the well/substrate of NMOSFETs creating a leakage path
between source and drain.
Lateral parasitic transistors turn N+

Drain
on because of charge build up in
STI oxides. Source-
Poly Gate drain
leakage
The parasitic devices add a Source paths
contribution to the total drain N+
STI
current and noise of NMOSFETs.
NMOSFETs
We developed a model to account

for the white and 1/f noise
degradation due to the effect of
lateral parasitic transistors.
V. Re et al, “Impact of lateral isolation Main

oxides on radiation-induced noise Lateral transistor
degradation in CMOS technologies in parasitic finger
the 100 nm regime”,
regime” NSREC ‘07 devices
-1
10
For devices with a large W/L ratio
(no narrow channel effect) the 10
-2
total contribution from lateral

devices can be disentangled from 10
-3 Prerad
e ad
the drain current of the main 10 Mrad
transistor controlled by the gate 10
-4
lateral device
oxide.
A]
I [A
10
-5
5 V =0.6
=0 6 V
DS
D
-6
10
The impact of lateral parasitic
d i
devices iis llarger at small
ll current 10
-7
densities ID L/W
. NMOS 130 nm
10
-8 W=1000 μm
L=0.13 μm
-9
10
0 0,5 1
V [V]
GS
i l ti
t t
-3
10
The drain current is more -4

10
severely affected by sidewall
l k
leakage iin th
the 130 nm technology
t h l 130 nm technology
as compared to the 90 nm one. 10
-5
This could be explained by a
[[A]
higher doping concentration in -6
6
10
the p-type body for the 90 nm
D,lat
90 nm technology
I
process, which mitigates the
inversion of the surface along the
-7
10
STI sidewalls.
id ll Leakage current
-8
10 in lateral parasitic transistors
Main device irradiated at 10 Mrad:
NMOS, W/L = 600/0.13
-9
10
-0,2 -0,1 0 0,1 0,2 0,3
V [V]
GS
Radiation effects on noise
Signal-to-noise ratio is a critical issue for the design of silicon tracking and
vertexing detectors.
Noise vs power performance and radiation effects on noise are crucial

parameters for the choice of the technology for integrated front-end electronics,
especially in view of operating with thin and/or heavily irradiated silicon
detectors, where the collected charge will be considerably smaller than for
standard 300 μm sensors.
In 100-nm scale open layout CMOS devices, 1/f noise at small drain current
density is among the few parameters which are sensitive to ionizing radiation.
Radiation effects on noise
Noise in the drain current of a MOSFET can be represented through an
equivalent noise voltage source in series with the device gate
S 2V (f) = S 2W + S1/f
2
(f)
SW - white noise S1/f - 1/f noise

• channel thermal noise (main • technology dependent contribution
contribution in the considered
operating conditions)
2 Kf • kf 1/f noise parameter
• kB Boltzmann’s constant S1/f ((f)) =
4k B T Γ
C OX WLf α f
• αf 1/f noise slope-
slope
2
S ch = , • T absolute temperature related coefficient
gm • αw excess noise coefficient
Γ = α W nγ • γ channel thermal noise

coefficient • both kf and αf depend on the polarity of
the DUT
• other contributions from parasitic
resistances
Radiation effects on noise: NMOS 90 nm
In 90 nm open layout NMOSFETs, at 10 Mrad total dose the main radiation effect
is a 1/f noise increase at low current density, due to the contribution of lateral
parasitic devices. No increase in the white noise region is detected.
1000 1000
V/Hz ]
V/Hz ]
1/2
1/2
before irradiation before irradiation
10 Mrad 10 Mrad
oise Voltage Spectrum [nV
oise Voltage Spectrum [nV

100 90 nm process 100 90 nm process
NMOS W/L=200/0.20 NMOS W/L=200/0.20
Id=20 μA @ Vds=0.6 V Id=250 μA @ Vds=0.6 V
10 10
No
No
1 3 4 5 6 7 8
1 3 4 5 6 7 8
10 10 10 10 10 10 10 10 10 10 10 10
Frequency [Hz] Frequency [Hz]
Radiation effects on noise: NMOS 90 nm
At 100 Mrad, there is no sizable difference in radiation effects with respect to 10

Mrad. A further increase of 1/f noise is detected.
1000 1000
age Spectrum [nV/Hz ]
ge Spectrum [nV/Hz ]
1/2
1/2
before irradiation before irradiation
100 Mrad 100 Mrad
100
00 90 nm pprocess 100 90 nm process
NMOS W/L=200/0.20 NMOS W/L=200/0.20
Id=20 μA @ Vds=0.6 V Id=250 μA @ Vds=0.6 V
Noise Voltag
Noise Volta
10 10
1 3 4 5 6 7 8 1 3
10 10 10 10 10 10 10
4
10 10
5
10
6
10
7 8
10
Radiation effects on noise: NMOS
130 nm open layout
l t
In 130 nm open layout NMOSFETs, at 10 Mrad total dose the main radiation effect is
again a 1/f noise increase at low current density, due to the contribution of lateral
parasitic devices. Since the impact of lateral devices is larger for this process, a
noise increase in the white spectral region is also detected at low currents.
STM 130 nm process

STM 130 nm process
Noisse Voltage Spectrum [nV//Hz ]
open layout
pectrum [nV/Hz ]
1/2
1/2
open layout
100 NMOS W/L=1000/0.20
NMOS W/L
W/L=1000/0
1000/0.20
20 100
Id 1 mA
Id=1 A
Id=100 μA Vds=0.6 V
Vds=0.6 V
Noisse Voltage Sp
10 10
before irradiation
10 Mrad before
b f iirradiation
di ti
10 Mrad
1 1
3 4 5 6 7 8 3 4 5 6 7 8
10 10 10 10 10 10 10 10 10 10 10 10
Radiation effects on noise: NMOS
130 nm enclosed
In 130 nm enclosed NMOSFETs, at 100 Mrad total dose, noise degradation is
negligible. This provides evidence for a model where the basic mechanism
underlying noise increase in irradiated devices is associated to lateral parasitic
transistors.
100
100
nd
2 130 nm vendor nd
2 130 nm vendor
V/Hz ]
1/2
NMOS enclosed
Noise Voltage Spectrum [nV//Hz ]

1/2
NMOS enclosed
W/L=1000/0.24 W/L=1000/0.24
Spectrum [nV
Id=100 μA @ Vds=0.6 V Id=1 mA @ Vds=0.6 V

10 10
Noise Voltage S
1 1
before
b f iirradiation
di ti before irradiation
100 MRad 100 MRad
0,1 3 4 5 6 7 8
0,1 3 4 5 6 7 8
10 10 10 10 10 10 10 10 10 10 10 10
Radiation effects on noise: PMOS
In 130 nm and 90 nm PMOS (open layout), even at 100 Mrad total dose, noise
degradation is negligible. This is in agreement with the absence of sidewall leakage
currentt contributions.
t ib ti
100 100
nd
130 nm 2 vendor STM 90 nm process
V/Hz ]
V/Hz ]
1/2
1/2
PMOS W/L=1000/0.12 PMOS W/L=1000/0.35
Id=100 μA I =100 μ
μA
Spectrum [nV
Spectrum [nV
|Vd | 0 6 V
|Vds|=0.6 D
10 10 |V |=0.6 V
DS
Noise Voltage S
Noiise Voltage S
1 1
before
b f irradiation
i di ti pre-rad
d
100 MRad 100 Mrad
0,1 2 3 4 5 6 7 8
0,1 2 3 4 5 6 7 8
10 10 10 10 10 10 10 10 10 10 10 10 10 10
1/f noise coefficient Kf
At 100 Mrad total dose, Kf is very close to preirradiation values for enclosed NMOS
and for PMOS. Instead, Kf sizably increases at low drain current density for open
l
layout NMOS
NMOS.
8
7 90 nm NMOS 200/0
200/0.20
20
90 nm NMOS 200/0.35
90 nm PMOS 1000/35
6 130 nm NMOS enclosed
f,pre-rrad
5
NMOS
open layout
/K
4
NMOS enclosed,
f,100 Mrad
3 PMOS
K
0
0 200 400 600 800 1000
Drain Current [μA]

Ionizing radiation effects on the
gate leakage current
The absorption of a 100 Mrad total dose marginally affects the gate leakage current
(mostly due to direct tunneling through the thin gate oxide).
oxide) However,
However there may be
reliability problems (hard oxide breakdown) to be investigated.
-6
10
before irradiation
-7
10 100 Mrad
|I | (A)
G
-8
8
10
90 nm process
NMOS, W/L = 200/0.2
-9
9
10 V = 0.8 V
DS
-0,4
, -0,2
, 0 0,2
, 0,4
, 0,6
, 0,8
, 1 1,2
,
VGS (V)
Thick oxide I/O devices
In 90 nm CMOS, the gate current due to tunneling effects may play a sizable role
affecting the signal
signal-to-noise
to noise ratio of a front-end
front end system
system, especially at peaking times
above 100 ns. To avoid this problem, we could use devices with thicker gate oxide
and higher VDD available in advanced CMOS technologies.
However, a thicker gate oxide may give worse noise performances and is more
sensitive to ionizing radiation.
Preliminary tests on the STM 90 nm process show that I/O 2.5 V NMOSFETs have a
1/f noise parameter Kf 20 times bigger than standard core transistors with thin
oxide.
Low noise charge preamplifier design
Circuit designers can take advantage of single device characterization to predict

noise behavior of charge sensitive amplifiers
Equivalent noise charge is the figure of merit to be minimized:
4k B T Γ 1
ENC = (C D + C g ) A 1
kf 1 • CD detector capacitance
+ (2π ) f A 2 (α f )
α
• CG preamplifier input
gm t p C OX WL t 1p−α f capacitance
• tp peaking time
Channel thermal Flicker noise
noise contribution contribution • A1 A2 shaping coefficients
Data extracted
D d from
f single
i l transistor
i characterization
h i i can bbe used
d to plot
l
minimum ENC as a function of the main design parameters (peaking time, power
dissipation, polarity and dimensions of the preamplifier input device)
It is interesting to assess the impact of ionizing radiation effects on the S/N

achievable with front-end electronics in 100 nm – scale CMOS
Ionizing radiation effects on signal-to-noise ratio:
strip
t i readout
d t with
ith 90 nm electronics,
l t i NMOS input
i t
At 10 Mrad, at the low current density dictated by power dissipation constraints,
the 1/f noise increase affects ENC also in 25 – 50 ns peaking time region.
region
3
10
90 nm process
C =5 pF
D
NMOS W/L=380/0.20
@ Pd=100 μW
The device width W is
ENC [e rms]
optimized as a function of
the detector capacitance
for the peaking time region
around 50 ns under typical
power dissipation
di i i before irradiation
constraints @ 10 Mrad TID
2
10
10 100
Peaking Time [ns]
ENC estimates based on measured noise parameters show that ENC increases by
about 20% at tp = 25 ns (430 e → 520 e) and by about 30 % at tp = 50 ns (325 e
→ 430 e) (the noise contribution from the gate leakage current can be neglected in this range)
pixel
i l readout
d t with
l t i
standard input NMOS
Even at 10 Mrad, the white and 1/f noise degradation increase ENC by 60 – 80 %
in the 25 – 50 ns peaking time region.
3 STM 130 nm process C =0.5 pF

10 D
NMOS W/L=59/0.20
@ Pd=12 μW
OPEN LAYOUT
C [e rms]
-
2
ENC
10
before irradiation
@ 10 Mrad TID
1
10
-9 -8 -7 -6 -5
10 10 10 10 10
Peaking Time [s]
pixel
i l readout
d t with
l t i
enclosed input NMOS
Since there are no lateral parasitic devices turning on and contributing to noise
noise,
on the basis of irradiation tests we can predict that ENC is not affected by the
absorption of high ionizing radiation doses (100 Mrad).
3 2nd 130 nm vendor

10
C =0.5 pF
D
NMOS W/L=46/0.20
@ Pd=12 μW
C [e rms]
ENC = 150 e rms at tP=25 ns ENCLOSED LAYOUT
2
ENC
10
ENC = 120 e rms at tP = 50 ns
before irradiation
@ 100 Mrad TID
1
10
-9 -8 -7 -6 -5
10 10 10 10 10
Peaking Time [s]
Conclusions
Irradiation tests have been performed on devices belonging to the 130 nm
and 90 nm CMOS technology nodes, likely candidates for the design of
readout electronics in future high luminosity collider experiments.
As a general conclusion, test results confirm that CMOS technologies in the 100
nm regime
g exhibit a high
g degree
g of radiation tolerance and that they
y are suitable
for the design of rad-hard readout electronics (with a few caveats) even for very
harsh radiation environments such as the SLHC.
Experimental results show that in NMOS devices exposed to ionizing radiation 1/f
noise increases because of the contribution from the lateral parasitic transistors
along the STI sidewalls. White noise may also increase after irradiation if the
impact of these parasitic devices on the drain current is large.
Since the noise increase is mostly evident at low current density, this suggests to
carefully evaluate the use of NMOSFETs for low noise functions in analog circuits
operating under power dissipation constraints.
This mechanism does not take place in P-channel devices and in enclosed
NMOSFETs, which may be used instead of standard interdigitated devices if a low
noise p
performance after the exposure
p to high
g TID levels ((as in inner SLHC
layers) is an essential requirement.
Backup slides
Operating region
Drain current in DUTs: from tens of μA to 1 mA Æ low power operation as in high
density front-end circuits
100
Strong inversion law
Weak inversion law
NMOS
g /I [1/V]
10 PMOS
m D
CMOS 90 nm
CMOS 130 nm
*
I *
I
*
I
Z,P,130
I*Z = 2μC OX nV T2
Z P 90
Z,P,90 Z N 90
Z,N,90
1
-9 -8 -7 -6 -5
10 10 10 10 10 • μ carrier mobility
y
*
I L/W [A] I
Z,N,130 • COX specific gate oxide
D
capacitance
Characteristic normalized drain current I*Z may • VT thermal voltage

provide a reference p
p point to define device operating
p g • n proportional to ID(VGS)
subthreshold characteristic
region
Noise in different CMOS generations
100
W/L = 2000/0.45, 0.25 um process

V/Hz 1/2]
W/L = 1000/0.5, 0.13 um process

W/L = 600/0.5, 0.09 um process
pectrum [nV
C = 6 pF 250 nm TSMC
10 IN
130 nm STM
Noise Voltage Sp
I = 100 μA 90 nm STM
D
NMOS
1
3 4 5 6 7 8
10 10 10 10 10 10
Frequency [Hz]
Noise vs gate length – STM 130 nm
100 NMOS 100 PMOS

ctrum [nV/Hz ]
e Voltage Spectrum [nV/Hz ]

L=0.13 μm
1/2
2
L=0.13 μm
1/2
L=0.35 μm L=0.35 μm
L=1.00 μm L=1.00 μm
10 10
e Voltage Spec
130 nm tech 130 nm tech

1 000 μ
W=1000 μm 1 W=1000 μm
Noise
Noise
I =0.25 mA I =0.25 mA
D
D
V =600 mV |V |=600 mV
DS
DS
3 4 5 6 7 8 2 3 4 5 6 7 8
10 10 10 10 10 10 10 10 10 10 10 10 10
High frequency, white noise virtually independent of the gate length L, in

agreement with gm behavior
1/f noise contribution decreases with increasing channel length, as predicted by the
noise equation
Noise vs drain current - NMOS
100 100
STM 130 nm STM 90 nm

ctrum [nV/Hz ]
e Voltage Specttrum [nV/Hz ]

1/2
2
Id=0.10
Id 0 10 mA
A
1/2
Id=0.10 mA
Id=0.25 mA Id=0.25 mA
Id=1.00 mA Id=1.00 mA
10 10
e Voltage Spec
1 1
NMOS NMOS
Noise
Noise
W/L=1000/0.35 W/L=600/0.2
V =600 mV V =600 mV
DS DS
0.1 0.1
3 4 5 6 7 8 3 4 5 6 7
10 10 10 10 10 10 10 10 10 10 10
High frequency, white noise decreases with increasing drain current in both
technologies in agreement with gm behavior
technologies,
1/f noise contribution is to a large extent independent of the drain current
Flicker noise
100
90 nm tech
e Spectrum [nV/Hz ]
1/2
W/L=600/0.2
I =1 mA
α =0.84 D
f
|V |=600 mV
DS
10
Noise Voltage
α =1.12
f
1
NMOS
PMOS
3 4 5 6 7
10 10 10 10 10
Frequency [Hz]
Slope αf of the 1/f noise term is significantly smaller than 1 in NMOS transistors
and larger than 1 in PMOS devices

CMOS Technologies in The 100 NM Range CMOS Technologies in The 100 NM Range For Rad-Hard Front-End Electronics in Future Collider Experiments P

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CMOS Technologies in The 100 NM Range CMOS Technologies in The 100 NM Range For Rad-Hard Front-End Electronics in Future Collider Experiments P

Uploaded by

Copyright:

Available Formats

CMOS technologies in the 100 nm range

for rad-hard front-end electronics in

V. Rea,c, L. Gaionib,c, M. Manghisonia,c,

bUniversità degli Studi di Pavia

aUniversità degli Studi di Bergamo

Inner SLHC detectors: ultra-deep submicron systems exposed to ionizing

10 Mrad irradiation 100 Mrad irradiation

10 keV X-rays – PMOS and enclosed NMOS from 2nd

In PMOSFETs and in enclosed 130 -3

Radiation-induced positive charge trapped in isolation oxides may invert a

Lateral parasitic transistors turn N+

We developed a model to account

V. Re et al, “Impact of lateral isolation Main

total contribution from lateral

The drain current is more -4

This could be explained by a

Noise vs power performance and radiation effects on noise are crucial

SW - white noise S1/f - 1/f noise

Γ = α W nγ • γ channel thermal noise

oise Voltage Spectrum [nV

At 100 Mrad, there is no sizable difference in radiation effects with respect to 10

STM 130 nm process

Frequency [Hz] Frequency [Hz]

Noise Voltage Spectrum [nV//Hz ]

Id=100 μA @ Vds=0.6 V Id=1 mA @ Vds=0.6 V

Drain Current [μA]

Circuit designers can take advantage of single device characterization to predict

Equivalent noise charge is the figure of merit to be minimized:

It is interesting to assess the impact of ionizing radiation effects on the S/N

3 STM 130 nm process C =0.5 pF

3 2nd 130 nm vendor

Characteristic normalized drain current I*Z may • VT thermal voltage

W/L = 2000/0.45, 0.25 um process

W/L = 1000/0.5, 0.13 um process

100 NMOS 100 PMOS

e Voltage Spectrum [nV/Hz ]

130 nm tech 130 nm tech

High frequency, white noise virtually independent of the gate length L, in

STM 130 nm STM 90 nm

e Voltage Specttrum [nV/Hz ]

1/f noise contribution is to a large extent independent of the drain current

You might also like