S6

Introduction to Embedded
Software Development

Software development flow

Software development flow

Software development flow

 Create project
 Add files to project
 Setup project options
 Compile and link
 Flash programming
 Execute program and debug
 During execution of the compiled program, you can check the
program execution status and results by outputting information via
various I/O mechanisms such as a UART interface or an LCD
module

1
 Compiling your applications

Some basic concepts of the compilation process

Common software compilation flow 4

Toolchaine
 ARM Toolchaine
Most development
 GNU ToolChaine
suites contain the
tools listed

5
Various Tools in a Development Suite

Software development flow

Software flow
There are many ways to
construct program flow for
an application :

Polling
Polling method
for simple
application
processing

2
 Software development flow
 The processor can enter sleep mode to
Interrupt driven
save power when no servicing is needed

Simple
interrupt-driven
application

Software
development flow

Application with
both polling
method and
interrupt-driven
arrangement

Software development flow

Multi-tasking systems

 When the applications get more complex, some tasks that can
take a long time to execute might need to be processed
concurrently.

 This can be done by dividing the processor’s time into a number

of time slots and allocating the time slots to these tasks

 In these applications, a Real-Time Operating System(RTOS) can

be used to handle the task scheduling

 An RTOS allows multiple processes to be executed concurrently

(time slots for the processes that require services )

3
 Software development flow
RTOS
at the end of each time slot, a
timer generates a timer interrupt,
which triggers the task
scheduler and decides if context
switching should be carried out.
If yes, the current executing
process is suspended and the
rocessor executes another
process.

Using an RTOS to handle multiple tasks

10

Instruction Set

 In most situations, application code

will be written in C or other high- level
languages and therefore it is not
necessary for most software
developers to know the
details of the instruction set .

 knowledge of assembly language

syntax can be very useful for
debugging

Simplified view of the instruction sets

supported by Cortex-M processor

11

What you need to start

Development suites :
The current available choices included various products from the
following vendors:
 Keil Microcontroller Development Kit (MDK-ARM)
 ARM DS-5 (Development Studio 5)
 IAR Systems (Embedded Workbench for ARM Cortex-M)
 Altium Tasking VX-toolset for ARM Cortex-M
 Rowley Associates (CrossWorks)
 Coocox
 Texas Instruments Code Composer Studio (CCS)
 Raisonance RIDE
 GNU Compiler Collection (GCC)
 ImageCraft ICCV8
 Cosmic Software C Cross Compiler for Cortex-M
 mikroElektronika mikroC
 Arduino
12

4
SOFTWARE DEVELOPMENT TOOLS
There are many software tools (IDE :Integrated Development Envirenment)

and resources available to support the MSP432(www.ti.com) :

 Code Composer Studio: CCS Desktop

 CCS Cloud

 Other IDEs: TI Resource Explorer

 Energia:

 Driver Library

 MSPWare:
13

It’s all in MSPWare

Your one-stop shop for
all technical collateral

• User’s Guides
• Application Notes
• Deep-dive Training
• Code Examples

14

EnergyTrace+TM technology
 Provides a complete ecosystem for real-time power debugging and quickens time to
market. Spends less time debugging and more time developing.
 Graphical User Interface in TI’s Code Composer Studio integrated development
environment (IDE) and IAR Systems’ Embedded provides energy profiles of your
application
 Current measurement and CPU states can be tracked over time to help identify
power black holes

15

5
 SW Development Environment

Editor KeilTM uVision®

Simulated Processor
Source code Start Microcontroller
Start
; direction register Debug
LDR R1,=P2DIR Session Memory
LDRB R0,[R1]
ORR R0,R0,#0x0F
; Port2 bits 3-0 output I/O
STRB R0, [R1]

Build Target (F7)

Object code Real Processor

Microcontroller
0x00000142
0x00000144
4912
6808
Download
0x00000146 F040000F Memory
0x0000014A 6008 Start
Debug
Session I/O
Address Data

16

What you need to start

Development boards TI, STMicroelectronics, Keil,

IAR Systems, and Code Red
Technologies all have a
number of development
boards available.

A Cortex-M3
development board
from Keil
STM32 Value TI MSP432 LaunchPad (MCBSTM32)
Line Discovery 17

What you need to start

Debug adaptor
 In order to download your program code to the microcontroller, and
to carry out debug operations like halting and single stepping, a
debug adaptor is needed to convert a USB connection from your PC
to a debug communication protocol used by the microcontrollers
 Most C compiler vendors have their own debug adaptor products.
 For example, Keil has the ULINK product family and IAR provides
the I-Jet product, ST has STLink

The Keil ULINK

debug adaptor
family

18

6
What you need to start : MSP432 LaunchPad
Develop high performance applications
that benefit from low power operation

Features
• Low-power, high performance MSP432P401R MCU
• 40 pin BoosterPack Connector, and support for 20 pin BoosterPacks
• Onboard XDS-110ET emulator featuring EnergyTrace+ Technology
• 2 buttons and 2 LEDs for User Interaction
• Back-channel UART via USB to PC

Kit Includes
 Development board with demo application
 USB cable
 Quick start guide

Software
 MSPWare featuring example code, User’s Guides, Application notes,
training, and more
 Out-of-box LaunchPad GUI
MSP-EXP432P401R
$12.99
19

MSP432 LaunchPad

20

MSP432 LaunchPad

21

7
 22

23

Differences Between Rev 1.0 (Black)

and Rev 2.0 (Red)

24

8
 25

Block Diagram

26

Block diagram of the XDS110-ET isolation block.

(Courtesy Texas Instruments.) 27

9
 Schematics (1 of 6)

30
29
28

Copyright © 2015–2018, Texas Instruments Incorporated

10
 BoosterPack Pinout

 The MSP-EXP432P401R LaunchPad adheres to the 40-pin

LaunchPad pinout standard. A standard was

 created to aid compatibility between LaunchPad and BoosterPack

tools across the TI ecosystem.

31

LaunchPad to BoosterPack Connector Pinout

32

LaunchPad to BoosterPack Connector Pinout

33

11
Flowcharts

34

64

Embedded C
Anatomy of a program

35

64C program : ANATOMY OF A PROGRAM

//*************************************************************
//Comments containing program information
// - file name: …………… // - author: …………… // - revision history: ……………
// - compiler setting information:
// - hardware connection description to microcontroller pins
// - program description
//*************************************************************
//include files
#include<file_name.h>
//function prototypes
A list of functions and their format used within the program
//program constants
#define TRUE 1
//interrupt handler definitions
Used to link the software to hardware interrupt features
//global variables
Listing of variables used throughout the program
//main program
void main(void) {
body of the main program
}
//*************************************************************
//function definitions: A detailed function body and definition for each function used within the program.
For larger programs, function definitions may be placed in accompanying //header files.
//************************************************************* 36

12
 PORT CONFIGURATION
There are two approaches to configure MSP432 subsystems :
 the registers may be configured directly using C programming techniques
 or via higher level application program interface (APIs).
The MSP432 has an extensive complement of APIs for all MSP432 subsystems within the
MSPWare library for example, the following APIs available for I/O:
 void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t
selectedPins)
 void GPIO_setAsInputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
 void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort, uint_fast16_t
selectedPins)
 void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
 uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort, uint_fast16_t
selectedPins)
37

PORT CONFIGURATION
 Register configuration: The “msp.h” header file within the CCS compiler
provides the link between software and the MSP432 hardware.

//******************************************************************
*****
// DIO Registers
//
//Copyright, Texas Instruments, [www.TI.com]
//****************************************************************
#define PAIN (HWREG16(0x40004C00)) //Port A Input
#define PAOUT (HWREG16(0x40004C02)) //Port A Output
#define PADIR (HWREG16(0x40004C04)) //Port A Direction
#define PAREN (HWREG16(0x40004C06)) //Port A Resistor Enable
#define PADS (HWREG16(0x40004C08)) //Port A Drive Strength
#define PASEL0 (HWREG16(0x40004C0A)) //Port A Select 0
#define PASEL1 (HWREG16(0x40004C0C)) //Port A Select 1
//****************************************************************

38

PORT CONFIGURATION
 the 16-bit PORTA is comprised of two 8-bit ports P1 and P2. snapshot of the
file containing memory locations for the Port P1 and P2 associated registers

//***************************************************************
// DIO Registers [www.TI.com]
//*************************************************************
#define P1IN (HWREG8(0x40004C00)) //Port 1 Input
#define P2IN (HWREG8(0x40004C01)) //Port 2 Input
#define P2OUT (HWREG8(0x40004C03)) //Port 2 Output
#define P1OUT (HWREG8(0x40004C02)) //Port 1 Output
#define P1DIR (HWREG8(0x40004C04)) //Port 1 Direction
#define P2DIR (HWREG8(0x40004C05)) //Port 2 Direction
#define P1REN (HWREG8(0x40004C06)) //Port 1 Resistor Enable
#define P2REN (HWREG8(0x40004C07)) //Port 2 Resistor Enable
#define P1DS (HWREG8(0x40004C08)) //Port 1 Drive Strength
#define P2DS (HWREG8(0x40004C09)) //Port 2 Drive Strength
#define P1SEL0 (HWREG8(0x40004C0A)) //Port 1 Select 0
#define P2SEL0 (HWREG8(0x40004C0B)) //Port 2 Select 0
#define P1SEL1 (HWREG8(0x40004C0C)) //Port 1 Select 1
#define P2SEL1 (HWREG8(0x40004C0D)) //Port 2 Select 1 39
//*****************************************************************

13
PORT CONFIGURATION
 Also included in the header file are definitions for each register. For example,
provided below is the definition for the PADIR register referred to as “rPADIR.”

union
{ //PADIR Register
__IO uint16_t r;
Struct { //PADIR Bits
__IO uint16_t bP1DIR : 8; //Port 1 Direction
__IO uint16_t bP2DIR : 8; //Port 2 Direction
}b;
}rPADIR;

 Definitions are also provided for the constituent bP1DIR and bP2DIR bits:
//PADIR[P1DIR] Bits
#define P1DIR_OFS ( 0) //P1DIR Offset
#define P1DIR_M (0x00ff) //Port 1 Direction
//PADIR[P2DIR] Bits
#define P2DIR_OFS ( 8) //P2DIR Offset
#define P2DIR_M (0xff00) //Port 2 Direction
40

PORT CONFIGURATION
The following example toggles the LED at pin P1.0.
• disabling the watchdog timer.
• The next line configures pin P1.0 as an output pin.
• Note how the specific bit related to pin P1.0 is accessed within the PADIR register.

//******************************************************************
// MSP432 main.c - P1.0 port toggle [www.TI.com]
//******************************************************************
#include "msp.h"
void main(void) {
volatile uint32_t i;
WDT_A->rCTL.r = WDTPW | WDTHOLD; //Stop watchdog timer
DIO->rPADIR.b.bP1DIR |= BIT0; //Configure P1.0 as output

while(1) { //Code toggles P1.0 port

DIO->rPAOUT.b.bP1OUT ^= BIT0; //Toggle P1.0
for(i=10000; i>0; i--); //Delay
}
}
//****************************************************************** 41

72 MSPWare API approach

 The “driverlib.h” header file pulls in other multiple header files containing API
definitions for the subsystems aboard the MSP432. the following example
toggles the LED connected to P1.0 using APIs

//*****************************************************************
//MSP432 main.c - P1.0 port toggle ////Built with Code Composer Studio v6
//*****************************************************************
#include <driverlib.h>
void main(void) {
volatile uint32_t i;
WDT_A_hold(WDT_A_BASE); //Stop watchdog timer
//Set P1.0 to output
GPIO_setAsOutputPin(GPIO_PORT_P1, GPIO_PIN0);

while(1) {
//Toggle P1.0 output
GPIO_toggleOutputOnPin(GPIO_PORT_P1, GPIO_PIN0);
for(i=10000; i>0; i--); //Delay
}
} 42

14
//*****************************************************
Frequently, within a microcontroller application, the program begins
with system initialization
actions. Once initialization activities are completed, the processor
enters a continuous loop.
this may be accomplished using the following code fragment.
//*****************************************************
while(1)
{
….
….
…
}
//*****************************************************43

if_example.c
#include "msp.h"
void main(void) {
unsigned char switch_value;
WDT_A->rCTL.r = WDTPW | WDTHOLD; //Stop watchdog timer
DIO->rPADIR.b.bP1DIR |= 0x01; //Bit 0 to logic 1
//Configure P1.1 as input (0) for switch with pullup resistor enabled:
// PxDIR = 0, PxREN = 1, PxOUT = 1
DIO->rPADIR.b.bP1DIR &= 0xfd; //Bit 1 to logic 0
DIO->rPAREN.b.bP1REN |= 0x02; //Bit 1 to logic 1
DIO->rPAOUT.b.bP1OUT |= 0x02; //Bit 1 to logic 1

while(1) {
switch_value = DIO->rPAIN.b.bP1IN;
if((switch_value & 0x02) == 0x02) {
DIO->rPAOUT.b.bP1OUT |= 0x01; //P1.0 to logic one
printf("high\n"); }
Else {
DIO->rPAOUT.b.bP1OUT &= 0xFE; //P1.0 to logic zero
printf("low\n"); } }
}
44

Exercises: GETTING ACQUAINTED WITH ENERGIA AND C

 Procedure 1: Energia.
 1. Create a counter that counts continuously from 1–100 with a 50 ms
delay between counts. the red LED should illuminate for odd numbers
and green LED for even

 Procedure 2: C.
 1. Develop a program that prompts the user for two integer numbers. If the
first number is less than the second, the program should count up
continuously from the lower to the higher number with a 50 ms delay
between counts. e onboard red LED should illuminate forodd numbers and
the onboard green LED for even numbers. If the first number is higher, the
program should count down

45

15
 ASSEMBLER
Msp432 Instruction Set

46

Instruction Set

 In most situations, application code

will be written in C or other high- level
languages and therefore it is not
necessary for most software
developers to know the
details of the instruction set .

 knowledge of assembly language

syntax can be very useful for
debugging

Simplified view of the instruction sets

supported by Cortex-M processor

47

Instruction Types
 A general-purpose instruction set can be expected to include
instructions in the following categories:
• Data processing: e.g., add, subtract, multiply
• Data movement: that copy data between memory and memory, or
between memory and register.
• Control flow instructions: that switch execution from one part of
the program to another, possibly depending on data values.
• Special instructions to control the processor’s state: for
instance to switch into a privileged mode to carry out an OS function.
Orthogonal:
An instruction set is said to be orthogonal if each choice in the
building of an instruction is independent of the other choices. An
orthogonal instruction set is easier for the assembly language
programmer to learn and easier for the complier writer to target. The
hardware implementation will usually be more
efficient too.

48

16
Addressing Modes
 When accessing an operand for a data processing or movement
instruction, there are several standard techniques used specify the
desired location.

• Immediate
• Absolute
• Indirect
• Register
• Register indirect
• Base plus offset
• Base plus index
• Base plus scaled index
• Stack addressing

49

Control Flow Instructions

 A control flow instruction is used to modify the PC explicitly.
 • Conditional Branches
 - Branch if a particular register is zero
 - Branch if two specified registers are equal
 • Condition Code Register
 - A special-purpose register to control the conditional branches
 • Subroutine Calls
 - The return address could be placed in a register, memory, or
pushed onto a stack.
 • Subroutine Return
 • System Calls
 • Exceptions

50

Processor Design Trade-offs

 CISC vs. RISC
 What processors do
 How to make them go faster
 - Pipelining
 - Cache memory

51

17
Instruction Set
 A number of different directives are available in both ARM assembler
and GNU assembler for inserting data into a program

52

Instruction Set : Commonly Used Directives

53

Instruction Set
-- - Moving data within the processor

APSR : Application Program Status Register

54

18
Instruction Set
 Memory access instructions for various Data Sizes

Note: The LDRSB and the LDRSH automatically perform a sign extend
operation on the loaded data to convert it to a signed 32-bit value. For
example, if 0x83 is read in a LDRB instruction, the value is converted into
0xFFFFFF83 before being placed in the destination register

55

Instruction Set
 Immediate offset (pre-
index)

LDRB R0, [R1, #0x3]

; Read a byte value
from address R1+0x3,
and store the read data
in R0.
 The offset value can be
positive or negative
 This addressing mode
supports write back of the
register holding the
address. For example:
LDR R0, [R1, #0x8]! ;
After the access to
memory[R1+0x8], R1 is
updated to R1+0x8
56

 Memory access instructions for Floating Point Unit

57

19
Instruction Set
 PC-related addressing (Literal)
A memory access can generate the address value from the current
PC value and an offset value (Table). This is commonly needed for
loading immediate values into a register, also known as literal pool
accesses (LDR pseudo instruction).

58

Instruction Set
-- Register offset (pre-index)
For example:
LDR R3, [R0, R2, LSL #2] ; Read memory[R0+(R2 << 2)] into R3
The shift operation is optional.

59

Instruction Set
 Memory access instructions with post indexing
One of the key advantages of the ARM architecture is that it allows you
to read or write multiple data that are contiguous in memory. The
LDM (Load Multiple
registers) and STM
(Store Multiple registers)
instructions only support
32-bit data.
They support two types
of pre-indexing:

• IA: Increment address

After each read/write
• DB: Decrement
address Before each
read/write
60

20
Instruction Set
-- Arithmetic operations
For example, an ADD instruction can operate between two registers or
between one register and an immediate data value:
ADD R0, R0, R1 ; R0 = R0 + R1
ADDS R0, R0, #0x12 ; R0 = R0 + 0x12 with APSR (flags) update
ADC R0, R1, R2 ; R0 = R1 + R2 + carry
 in Unified Assembly Language (UAL) syntax, the S suffix should be
used if the following operation depends on the flags:
ADD R0, R1, R2 ; Flag unchanged
ADDS R0, R1, R2 ; Flag change

 The arithmetic functions that the Cortex-M3 supports include SUB

(subtract), MUL (multiply), and UDIV/SDIV (unsigned and signed
divide)
 These instructions can be used with or without the “S” suffix to
specify whether the APSR should be updated
61

Instruction Set
Instractions for arithmetic data operations

62

Instruction Set
Instructions for Logical operations

63

21
Instruction Set
Instructions for Shift and Rotate Operations

64

Instruction Set
 Instructions for Shift and Rotate Operations

65

Instruction Set
Bit-field processing instructions

BFC (Bit Field Clear) clears 1 to 31 adjacent bits in any position of a

register. The syntax of the instruction is:
BFC <Rd>, <#lsb>, <#width>
For example:
LDR R0,=0x1234FFFF
BFC R0, #4, #8 This will give R0 = 0x1234F00 F
66

22
Instruction Set
Bit-field processing instructions
 BFI (Bit Field Insert ) copies 1 to 31 bits (#width) from one register to
any location (#lsb) in another register.
 The syntax is: BFI <Rd>, <Rn>, <#lsb>, <#width>
For example:
LDR R0,=0x12345678
LDR R1,=0x3355AACC
BFI R1, R0, #8, #16 ; Insert R0[15:0] to R1[23:8]
This will give R1 = 0x335678CC.
 The RBIT instruction reverses the bit order in a data word.
The syntax is: RBIT <Rd>, <Rn>
This instruction is very useful for processing serial bit streams in data
communications. For example, if R0 is 0xB4E10C23 (binary value
1011_010 0_1110_0001_000 0_1100_0010 _0011) , executing :
RBIT R0, R1
R0 will become 0xC430872D (binary value 1100_010 0_0011_0
000_1000 _0111_001 0_1101) 67

Bit-field processing instructions

UBFX
UBFX <Rd>, <Rn>, <#lsb>, <#width>
SBFX <Rd>, <Rn>, <#lsb>, <#width>

UBFX extracts a bit field from a register starting from any location
(specified by the < #lsb> operand) with any width (specified by the
< #width> operand), zero extend s it, and puts it in the destina tion
register. For example:

LDR R0,=0x5678ABCD
UBFX R1, R0, #4, #8

This will give R1 = 0x0000 00BC (zero extend of 0xBC).

68

Instruction Set
Program flow control
 There are several types of instructions for program flow control:

69

23
Instruction Set
Compare and branches
CBZ (Compare and Branch if Zero) and CBNZ (Compare and Branch if
NonZero). CBZ and CBNZ are very useful in loop structures such as
while loops.
For example:
i = 5;
while (i != 0 ){
func1(); // call a function
i--;
}
This can be compiled into:
MOV R0, #5 ; Set loop counter
loop1 CBZ R0, loop1exit ; if loop counter = 0 then exit the loop
BL func1 ; call a function
SUBS R0, #1 ; loop counter decrement
B loop1 ; next loop
loop1exit
70

Instruction Set
Conditional execution (IF-THEN instruction)

 Support conditional execution . After an IT (IF-THEN) instruction is

executed, up to four of the subsequent instructions can be
conditionally executed based on the condition specified by the IT
instruction and the APSR (Application Program Status Register )
value For example :

CMP R0, #1 ; Compare R0 to 1

ITE EQ ; The next instruction executes if Z is set (EQ),
; the one after next executes if Z is cleared(NE)
MOVEQ R3, #2 ; Set R3 to 2 if EQ
MOVNE R3, #1 ; Set R3 to 1 if not EQ (NE)

71

Instruction Set
 Table branches
The TBB instruction has the syntax:
TBB [Rn, Rm]
where Rn stores the base address of the branch table and Rm is the
branch table index. The immediate value for the TBB offset
calculation is located in
memory[Rn + Rm]. If R15/PC is used as Rn

72

24
Instruction Set
 TBH instruction is very similar, except that each entry in the branch
table is two bytes in size, so that the array indexing is different and
the branch offset range is larger. The syntax of TBH is slightly
different to reflect the indexing difference:

TBH [Rn, Rm, LSL #1]

Again, the following diagram assumes that Rn is set to the PC, as

shown

The TBB and TBH instructions are typical ly used by C

compiler s in switch(case) statemen ts 73

Instruction Set
In ARM assembler (armasm), including the Keil MD K-ARM , the TBB
branch table can be created in assembly in the following way

when the TBB instruction is executed, the current PC value is the address of
TBB instruction plus 4 (due to the pipe line structure ), which is the same as
the start of the branch table because the TBB instruction is 4 bytes in size.
(Both TBB and TBH are 32-bit instructions.) 74

Adresses physiques
static const uint8_t RED_LED = 75; //RGB LED - red component
static const uint8_t GREEN_LED = 76; //RGB LED - green component
static const uint8_t BLUE_LED = 77; //RGB LED - blue component
static const uint8_t YELLOW_LED = 78; //Mapped to the other RED LED
static const uint8_t PUSH1 = 73; //Switch 1
static const uint8_t A9 = 27;
static const uint8_t PUSH2 = 74; //Switch 2 static const uint8_t A10 = 6;
static const uint8_t A0 = 30; //analog-to-digital converter static const uint8_t A11 = 25;
static const uint8_t A1 = 29; //channels 0 to 23 static const uint8_t A12 = 5;
//static const uint8_t A2 = n/a; static const uint8_t A13 = 24;
static const uint8_t A14 = 23;
static const uint8_t A3 = 12;
static const uint8_t A15 = 2;
static const uint8_t A4 = 33; static const uint8_t A16 = 59;
static const uint8_t A5 = 13; static const uint8_t A17 = 42;
static const uint8_t A6 = 28; static const uint8_t A18 = 58;
static const uint8_t A7 = 8; static const uint8_t A19 = 57;
static const uint8_t A20 = 41;
static const uint8_t A8 = 27;
static const uint8_t A21 = 43;
static const uint8_t A22 = 69;
static const uint8_t A23 = 44

75

25