KAMBAYASHI: LOGIC DESIGN 617

ACKNOWLEDGMENT [9] Y. Kambayashi, "Optimum logic design using memory-type arrays,"

in Proc. IEEE Int. Symp. on Uniformly Structured Automata and
The author wishes to thank Prof. S. Yajima for valuable Logic, Tokyo, Japan, Aug. 1975, pp. 199-205.
discussions and comments on the subject and J. L. Goodsell [10] Y. Kambayashi, K. Okada, and S. Yajima, "Prime implicant genera-
tion of logic functions using clause selection method" (in Japanese)
(now with the Amdahl Corporation) for his kind help in Trans. IECEJ (Inst. Electron. Commun. Eng. Japan), vol. J62-D, pp.
preparing the final manuscript. 89-96, Feb. 1979.
REFERENCES
[1] E. J. McCluskey, Jr., "Minimal sums for Boolean functions having
many unspecified fundamental products," AIEE Commun. Electron.,
Nov. 1962.
[2] J. R. Slagle, C. L. Chang, and R. C. Lee, "A new algorithm for Yhko Kambayashi (S'67-M'70) was born in
generating prime implicants," IEEE Trans. Comput., vol. C-19, pp. Osaka, Japan, on February 15, 1943. He received
304-310, Apr. 1970. the B.E., M.E., and Ph.D. degrees in electronic
[3] R. C. De Vries, "Minimal set of distinct literals for a logically passive engineering from Kyoto University, Kyoto,
function," J. Assoc. Comput. Mach., vol. 18, no. 3, pp. 431-443, Japan, in 1965, 1967, and 1970, respectively.
July 1971. During 1970-1971 he was a Research Associate
[4] G. Reyling, "PLAs enhance digital processor speed and cut compo- at Kyoto University. From 1971 to 1973 he was
nent count," Electronics, Aug. 8, 1974. a Research Associate at the University of Illinois,
[5] J. Lambert, "Providing decimal output for a calculator chip," Elec- Urbana. In 1973 he joined the Department of In-
tronics, p. 105, Aug. 8, 1974. formation Science, Kyoto University, where he is
[6] J. Southway, "IC trio converts 7-segment code to decimal," Elec- currently an Associate Professor. His research
tronics, p. 113, Nov. 28, 1974. interests include switching and automata theory, graph theory, and data-
[7] D. Howells, "Convert 7-segment numerical code to decimal or BCD base theory.
outputs," Electron. Design, p. 96, Feb. 15, 1975. Dr. Kambayashi is a member of the Association for Computing
[8] H. Fleisher and L. 1. Maissel, "An introduction to array logic," IBM Machinery, the Institute of Electronics and Communication Engineers of
J. Res. Develop., vol. 19, pp. 98-109, Mar. 1975. Japan, and the Information Processing Society of Japan.

Fault Analysis and Test Generation for

Programmable Logic Arrays (PLA's)
DANIEL L. OSTAPKO, MEMBER, IEEE, AND SE JUNE HONG, SENIOR MEMBER, IEEE

Abstract-Programmable logic arrays (PLA's) are the logic INTRODUCTION

implementation vehicle for many applications. Due to their regular
structure, one is able to model and analyze many more of the likely
physical faults than the conventional stuck faults considered for
random combinational logic implementations. We investigate shorts
between the lines and crosspoint defects (spurious absence or
presence), as well as stuck faults in a PLA. It is shown that a complete
crosspoint test set also detects most of all faults analyzed. The
crosspoint-oriented test set is compact, easy to generate, and
technology-invariant. For the test generation, the regularity of the
PLA structure is utilized for ease of computation and for test set
optimality. Groups of crosspoint defects are sensitized simultan-
eously. For each such fault group, a test configuration which contains
the totality of the tests for the faults under consideration is efficiently
generated. When the configuration is empty, there exists no test that
detects the particular group of faults. A covering set of tests is then
selected from the configuration. Our test generation method (TPLA)
uses two basic and effective heuristics; they are the initial word
ordering for processing and the use of look-ahead merit function
whenever there is a free choice of values in a test input variables.
Manuscript received February 28, 1979.
The authors are with the IBM Thomas J. Watson Research Center,
Yorktown Heights, NY 10598.
0018-9340/79/0900-0617$00.75 (D 1979 IEEE
PROGRAMMABLE logic array (PLA) is a structure
that is finding increasing usage. The PLA, which is
conceptually a two-level AND-OR, is attractive in LSI due to
its memory-like regular structure. Fig. 1 shows an example
of an eight-input, five-output PLA in a NOR-NOR implemen-
tation. The logic model in the figure shows that 0's denote
connections in the input portion and l's denote connections
in the output portion. In general, PLA is a combinational
logic device, comprised of the input decoders and AND and
OR arrays. Fleisher and Maissel [1] describe various technol-
ogy implementations and structures of PLA. This paper
considers the generation and analysis of tests for PLA's.
Because of the increasing circuit density in LSI chips,
faults other than the usual stuck variety are receiving
increasing attention [2], [3]. As a result, memory is often
tested by patterns generated by a special algorithm rather
than by a general-purpose test generation procedure for
stuck faults. The walking 0/1 tests [4] and the test set of
Hayes [5] are examples of special-purpose test generation
618 IEEE TRANSACTIONS ON COMPUTERS, VOL. c-28, NO. 9, SEPTEMBER 1979

OUTPUT INVE RTI NG

DRIVERS
DECODERS

1 2
I-
P M
78
~
_
-
9410 112- - -
II- IIFI
t }2 34S
I 4I1 T 11
41 I I
W
I I I I I I
a
I
1-l 'I l

AND ARRAY (NOR) iOR ARRAY (NOR)

1 1 1 0 10 1 1 0 1 1 1 1 0 0 1 I 1 0 0 1
1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1
0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 0 1 1
I 1 1 1 11 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 .1I0 0 1 1

CONNECTIONS DENOTED BY O' CONNECTIONS

DENOTED BY" 1's
Fig. 1. The PLA description, physical and logical.

algorithms. These algorithms generate tests that take into
account faults due to the physical proximity of signal lines in
the circuit.
Since a PLA can be viewed as a memory that behaves like
a logic network, it should be possible to utilize the regular
structure to generate good tests efficiently. In addition, the
analysis of tests generated for random logic using a single
fault assumption has indicated that a large percentage of
multiple faults are also tested. Using the regular structure of
the array, it should be possible to analyze what classes
of faults are detected by tests generated to detect single faults
within the array.
In order to generate tests efficiently for PLA's, the genera-
tion process should utilize the regularity, structure, and
efficiency of the bit array. The faults to be detected, however,
are hardware-dependent. Therefore, the approach to be
followed in the analysis is to model the fault being con-
sidered as a change in the corresponding bit pattern. Using
this approach, it is possible to show that several classes of
faults are tested simply by properly testing all single
crosspoint faults of the array.
The conventional approach to test generation is to model
the PLA in a functionally equivalent random logic network
[6], [7]. The equivalent network can be processed by a stuck
fault test algorithm such as D-ALG [8]. There are two
problems with this approach. First, if only the personalized
crosspoints are modeled, other types of faults due to the high
density of circuits may be undetected by the test set. Second,
if all crosspoints are modeled, every rectangle that can be
drawn across the AND and OR array becomes a reconvergent
fan-out path.
This presents an enormous computational burden in
conventional test generation methods. Most random logic
test generation algorithms require fault sensitizing to out-
puts and consistency operations to inputs. When a cross-
point is redundant, these processes must exhaust all locally
viable signal values, or give up early after a given number of
trials. A PLA inherently produces redundant points. For
instance, A J+ B can be implemented as A + B, A + AB, or
AB + B. Most practical test generation algorithms resort to
the "give up" policy; thus, many untested points cannot be
declared untestable. The coverage percentage of such a test
set can be meaningless.
Our method, called TPLA, is based on an abstract array
representation of AND-OR personality as shown in Fig. 1.
The TPLA takes advantage ofthe regularity of PLA to cover
all testable crosspoint faults and supplies a coverage array
(COV) indicating the testable crosspoints. An output stuck
at one test, if needed, is appended at the end ofthe process to
complete the test set. The whole process is programmed in
APL. Many of the subroutines are borrowed from the MINI
program [9]. The process uses the complementary array F,
generated in the course of array minimization of F; if the
array is already fixed, F is generated in a preprocess.
EFFECT OF UNTESTABLE POINTS
For the analysis of various faults, assume that tests have
been generated to all 0's, all l's, and all outputs stuck at 1.
For a given array it may not be possible to test some of the
bits. Fig. 2 shows an example of an array that contains a 1
and a 0 for which no test can be generated. A complete test
set is a set of tests that tests every point that can be tested.
After the generation process, the bits are divided into
testable and untestable. The superscripts in Figs. 2-11
denote the equivalent personality bit changes resulting from
the given fault.
OSTAPKO AND HONG: FAULT ANALYSIS AND TEST GENERATION
1 1 1 0 1 0 1 1 0 1 1
1 01 0 10 O 1 0 1 0 0 1 0
0 1 0 1 1 1 0 1 0 0 1
1 1 1 1 1 1 0 0 1 1 1
1 0 0 1 1 0 1 0 1 1 1
Fig. 2. Untestable crosspoints, a 0 and a 1.
Within an array, there may be several untestable points.
However, it is not possible, in general, to change more than
one untestable point without affecting the operation of the
array. The following theorems describe the sets of untestable
points that can be altered simultaneously without altering
the function of the array. The portion of a word, product
term, or cube [9] that is associated with a decoder or the
output field will be called a part.
Since the tests were generated on a single fault assump-
tion, the following theorem holds by definition.
Theorem 1: Any single untestable point can be inverted
without altering the output of the array.
The decoders driving the first, or AND array, allow the set
of alterable points to be enlarged, as follows.
Theorem 2: All untestable points in one part of a row
(product term) can be altered without altering the output of
the array.
Proof: Since each input part is associated with a
decoder, only one entry in the part is activated at a time. This
independence allows the entire set to be altered, while in
operation only one altered point will be activated. The
untestable points in the output part do not interact because
they influence different outputs. Hence, they also can be
altered as a set.
In order to enlarge the set of untestable points that can be
altered without altering the operation of the array, the
product terms will have to be considered in more detail. Let
aki, i = 1, -.., p be the bit patterns for the parts of a product
term. Let akj = tkj v okj where tkj is the vector of testable l's
and okj is the vector of untestable l's in thejth part of word k.
Let zkj be a vector with l's denoting the untestable O's in the
jth part of word k.
Lemma 1: The cube akl, ak2, ,kj' akp is covered by
the other words in the array.
Proof: Assume the contrary; then there exists an input
combination for which only this word is activated. However,
if only this word is activated, setting one of the untestable l's
in okj to 0 would alter the output, contrary to the definition
of untestable.
A similar lemma is true for the untestable O's.
Lenuna 2: The cube akl, ak2, * * Zkj * , akp is covered by
the other words in the array.
Proof: Assume the contrary; then there exists an input
combination for which only this word would be activated if
the untestable O's were made l's. This contradicts the
assumption of untestable O's.
Leuna 3: All untestable l's in a row can be altered
without altering the output of the array.
Proof: Using Lemma 1, it is seen that any subcube of
619
1 1 0 0 1 I 1 0 0 1
0 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 0 1 1
1 01 1 0 1 1 0 1
1 1 1 1 1 1 0'0 1 1
row k that contains only untestable bits in any part is
covered by the other cubes in the array. Any covered cube
can be eliminated without altering the operation of the
array.
The set of untestable points that can be altered in a single
word is summarized by the following theorem.
Theorem 3: All untestable l's in the input of a row and all
untestable O's and l's in the output may be altered without
altering the output of the array.
Proof: The alteration of the l's follows from Lemma 3.
From Lemma 2, it follows that the cube akl, ak2, * * * Zkp is
covered by the other cubes in the array. Thus, the cube tk1,
tk2, * ** Zkp is covered by the other cubes in the array and can
be added or deleted at will. Hence, the theorem.
In the column dimension, the following theorem describes
the allowed alterations.
Theorem 4: All untestable O's in any one part of all words
can be altered without altering the output of the array.
Proof: Using Lemma 2, it is seen that akl, ak2, ,
Zkj, akp, an altered word k, is covered by the other words
.
in the array. Since any covered cube can be added without
altering the operation of the array, all cubes of the type
described above can be -added to the array.
From the above, it can be seen that the structure of the
array yields considerable information about the interaction
of untestable points.
ANALYSIS OF FAULTS
In order to determine whether a class of faults is detected
by the complete crosspoint test set, it is necessary to
determine the equivalent bit pattern change that results
from that class of faults. The resulting change can then be
analyzed to see whether or not it would be detected. In the
following, several classes of faults are analyzed, and the
degree of their coverage is determined.
An extra or missing device in the input or output portion
causes a single bit change in the bit pattern. Since this is
exactly the assumption on the test generation process, the
fault is detected by the test for the crosspoint if the cro-
sspoint is testable; otherwise the PLA function remains
unaffected by Theorem 1.
Fig. 3 shows the effect of a decoder line stuck, high, or low.
If a line such as the first column is stuck low, it will not
activate the devices, and it thus appears that the devices are
absent. Thus, the column becomes logically all l's because
l's correspond to the absence of a device. This change would
be detected by the test for a testable 0 in the altered column.
If all the O's are untest-able, the change will not influence the
operation because of Theorem 4. If a line such as the tenth
620 IEEE TRANSACTIONS ON COMPUTERS, VOL. c-28, NO. 9, SEPTEMBER 1979

1 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1
1 0 01 0 1 0 1 O 0 10° 0 1 1 1 1 1 0 1 1
01 1 01 1 1 0 1 0 0 1°1° 1 1 1 1 1 1 0 1 1
1 1 11 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1
1 0 01 1 0 1 0 1 111 1 1 1 1 1 0 0 1 1
Fig. 3. Decoder line 1 stuck low and line 10 stuck high.

1 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 I°1 01 O 1
1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 101 0 1 1
0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 1° 1 01 1 1
1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 100 1 1 1
Fig. 4. Output line 1 stuck low and output line 3 stuck high.

1 1 1 0 10 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1
1 0 0 1 0 1 010
1 0 1 0 0 1 1 1 1 1 0 1 1
0 1 0 1 1 1 010
1 0 1 1 1 1 1 1 1 1 0 1 1
1 1i 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1
Fig. 5. Decoder lines 7 and 8 active instead of just 8, and line 9 active
instead of 10.

column is stuck high, its devices are always active, and thus
can logically be associated with all the other columns in the
same part. Since devices correspond to O's, that part of
the word becomes all O's.
This change would be detected by the test for any altered
testable 1. It follows from Lemma 1 that the word is
redundant if all the l's in the part are untestable. Thus,
decoder lines stuck high or low will be detected if there are
no redundant words.
An output line or driver stuck high or low makes the
output column all O's or all l's, as shown in Fig. 4. If the line
or driver is stuck low, it will be detected by the test for a
testable 1 in the column. If there is no testable 1 in the
column, let W be the set of output parts of the words having
a 1 (untestable) in the faulted column. If there is a testable 1
in the set W, then the test for that 1 detects the faulted
output. If there is no testable 1 in W, then at least one word is
redundant by Lemma 1. If the line or driver is stuck high, it
will be detected by the test for a testable 0 in the column or
the one added test for outputs stuck at 1. If all the O's are
untestable, the function is unchanged by Theorem 4. Thus,
stuck faults on output lines or drivers will be detected ifthere
are no redundant words.
Decoder failures may cause the wrong line or lines to
come up. Fig. 5 illustrates decoder failures. If the wrong line
comes up, it will be detected by the test for any altered
testable entry. If only untestable O's are changed, the func-
tion remains unchanged by Theorem 4. If all altered entries
are untestable and include some untestable l's, then the test
set is not guaranteed to detect the failure. If no lines come up,
the intended column is replaced by all l's. This would be
detected by the test for any testable 0 in the column. Again, if
the column contained only untestable O's, then no change
would result in the function by Theorem 4. If more than one
line comes up, the intended column is replaced by the AND of
the columns that came up, as shown in the figure. The
analysis is then the same as if the wrong line came up.
In the following, shorts between various pairs of lines are
considered. The technology used will determine what effect
the short will have. Generally, either high or low will
dominate. The fault will be analyzed using both
assumptions.
If two output lines are shorted and high dominates, both
are replaced by the OR of the two columns, as shown in Fig. 6.
This fault would be detected by the test for any altered
testable 0. If all the altered O's are untestable, then the
function would remain unchanged by Theorem 4. If low
dominates, both of the lines would be replaced by the AND of
the two lines as shown in the figure. This fault would be
detected by the test for any altered testable 1. If, however, the
set of altered l's consists of more than one untestable 1, then
the function may be altered, and the test is not guaranteed to
detect the fault.
Fig. 7 gives the analysis of shorts between decoder drive
lines. These faults are somewhat more difficult to analyze
since there will be no effect unless exactly one of the shorted
pairs is addressed. Shorts within a part have the property
that exactly one of the pair will be addressed. Since it is not
possible to make a similar statement about shorts between
parts, the corresponding bit pattern change cannot be made,
OSTAPKO AND HONG: FAULT ANALYSIS AND TEST GENERATION 621

1 I 1 0 1 0 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1
1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1°1
0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 0 1° 1
1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 011 1 0 1
1 O 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 010 1°1
Fig. 6. Outputs 1 and 2 shorted high and outputs 3 and 4 shorted low.

I 11 0 10° 1 1 0 1 1 1 1 0 0 1 I 1 0 0 1
0 10 1 0 0 1 0 0 1 1 1 1 1 0 1 1
01 01 1 1 0 1 0 0 1 1 1 1 1 1 I 1 0-1 1
1 11 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1
1 0101 1° O 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1
Fig. 7. Decoder lines 2 and 3 shorted low and decoder lines 4 and 5
shorted high.

1 10100 100 101 0 101 10 100 0 1 1 1 0 0 1

1 0 0 1 1 0010 0 10 10 1 1 1 0 1 1
0 1 0 1 1 1 01 0 0 1 1 111 1 1 0 1 1
11 1 1 1 olo 1 o' o' ol 1 1 1 O'1
1 0l 0 1 1 100 1 1
1 I1100 1 11 010-1 1
Fig. 8. Words 1 and 2 shorted low and words 4 and 5 shorted high.

1 1 1 0 10 1 1 0 1 1 1 1 0 0 I 1 1 0 0 1
1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1
0 1 0 1 1 1 01 0011 1111 11011
1 1 1 1 11 0 0 1 1 1 1 0 0 0 1 0111 01 1

1 0 0 1 1 0 1 0 1 1 11 1.1 11 1 o1 o111
Fig. 9. Isolated arrays: words 1 and 2 shorted low and words 4 and 5
shorted high.

and the test set does not guarantee to detect the fault.
However, for shorts within a part, if low dominates, the
shorted columns are replaced with all l's. The fault would be
detected by the test for any altered testable 0. If all O's are
untestable, the function is unchanged by Theorem 4. If high
dominates, each of the shorted columns within a part is
replaced by the AND of the columns. The analysis of this fault
is the same as for more than one decoder line up; hence, the
fault is guaranteed to be detected if any testable l's are
altered. However, if the altered set consists of more than one
untestable 1, the function may be altered and the test set is
not guaranteed to detect the fault.
Fig. 8 shows the analysis of two word lines shorted in the
input portion. If low dominates, both words are the AND of
the input and the OR of the output. The fault would be
detected by the tests for the testable l's in the input or O's in
the output. If all ofthe changes are untestable, the function is
unchanged by Theorem 3. If high dominates, both words are
replaced by the OR of the shorted words. This fault would be
detected by the test for an altered testable 0. If, however, the
altered O's are all untestable and do not meet the conditions
of Theorem 2, then the function may be altered and the test
set is not guaranteed to detect the fault.
Fig. 9 shows the analysis of a short between the output
portion of two word lines. If there is no isolation between the
input and output arrays, the fault is the same as a short in the
input portion. If there is isolation between the arrays, then
the output portion of both words becomes the OR if high
dominates and the AND if low dominates. In either case
the fault will be detected by the test for the altered entries or
the function will be unchanged by Theorem 2.
The last two classes of faults to be considered are shorts
between word lines and output lines and shorts between
word lines and decoder drive lines.
The analysis of shorts between a word line and an output
line is shown in Fig. 10. If there are no other l's in the faulted
output column, the fault appears as a single device failure
and is therefore detected. If low dominates, the other words
with a 1 in the column remain down unless the faulted word
comes up. Logically, this alters the input portion of each
word having a 1 in the faulted column. The input of each of
these words is ANDed with the input portion of the faulted
word. The fault would be detected by the test for any altered
testable 1. If, however, the altered l's which may be located
in more than one word.are all untestable and do not meet the
conditions of Theorem 2, the function may be altered and
622 IEEE TRANSACTIONS ON COMPUTERS, VOL. c-28, NO. 9, SEPTEMBER 1979

1 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 I 1 0 0 1
1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1
0 1 0 1 1 1 00 10 111 1 1 1 0 1 1
1 1 1 1° 1 1° O 0 1° 1 1 1 0 0 0 1 0 1 1 0 1
1 01 0 1 1 01 1 01 1 1 1 1 1 1 1 1 1 O-0 1 1
Fig. 10. Word line 1 and output line 3 shorted low modifying word 4,
and word line 5 and output line 4 shorted high modifying word 5.

1 I I 0 1 0 1 1 0 1
1 1 1 0 0 1 I 1 0 0 1
1 O 0 1 0 1 0 1 0 1
0 0 0 1 1 1 1 1 0 1 1
0 10 11 1 1 0 1 0 0
1 1 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 0 0 1 1
1 1 0 0 0 1 0 1 1 0 1
1 O 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1
Fig. 11. Word line 3 and decoder line 3 shorted low.

A B C D f1f2f3

1 1 1 1 1 1 1 1 0 1 fF = A+B+CD
1111 01 01 110 F f2=AC+CD
1 0 0 0 1 1 1 01 f3 = AC+BC A+B+C

1 0 00 1 0 1 1 1 0 1)
0011 11 10 0101 f1 = ABC+ABD
1000 11 10 100
1 1 1 1 1 0 1 1 0 1 0J ff3 = ABC
Fig. 12. An example of function F and its complement F.

the test set is not guaranteed to detect the fault. If high
dominates, the shorted word comes up if any word with a 1
in the faulted column comes up. Logically, the input portion
of the faulted word is replaced by the OR of its input portion
and the input portions ofall ofthe other words with a 1 in the
faulted column. Again, this is detected by altered testable O's
in the input portion, but if only untestable O's are altered,
and they do not meet the conditions of Theorem 2, the
function may be altered and the test set is not guaranteed to
detect the fault.
Fig. 11 shows the analysis of a short between a decoder
drive line and a word line. If low dominates, the shorted
word stays low unless the bit line is addressed. If the fault
point is a testable 0, the test for that point will detect the
fault. If the fault point is untestable, there must be a testable
1 elsewhere in the part, or the word is redundant. The test for
a testable 1 elsewhere in the part will fail because the word
will not come up. Ifthe fault point is the only testable 1 in the
part, it will be detected by a test for a testable 0 in other input
parts of the word. If all the O's in the other input parts are
untestable and fail to meet the conditions of Theorem 2, the
function may be altered and the test set is not guaranteed to
detect the fault. If high dominates, the shorted word comes
up whenever the bit line is addressed. This fault will be
detected if the fault point is a testable 0. If the fault point is
the only 1 in the part, the fault is detected by the tests for
testable O's in other input parts. Ifall ofthe O's are untestable
and fail to meet the conditions of Theorem 2, the function
may change and the test set is not guaranteed to detect the
fault. If there is a in the part other than the fault point, the
interaction is more extensive. When the faulted word-comes
up, words with a 0 in the faulted column will not come up.
The test set is not guaranteed to detect this situation.
THE FUNCTION REPRESENTATION
The function implemented in a PLA is viewed as a list of
cubes in a multidimensional logic universe [9]. Each decoder
group forms an axis, and the multiple outputs together form
an OUTPUT axis. Each axis has multiple values correspond-
ing to the number of decoder outputs or to the number of
primary outputs of the PLA. The personality shown in Fig. 1
represents the overall function F in such a universe. The
array words denote the cubes that are the Cartesian product
of occupied coordinate values represented by l's in each
part. The array F shown in Fig. 12 has four parts, including
the output part. They represent the variables (AB), (C), (D)
and (f, f2 f3).
OSTAPKO AND HONG: FAULT ANALYSIS AND TEST GENERATION
When a test input arrives at the PLA and passes through
the decoders, it forms an input minterm cube in the gener-
alized universe, i.e., it has one and only one 1 in each input
part. Henceforth, tests will be assumed to be in the decoded
form, since the conversion to primary input value is a
straightforward process. If a test matches a 1 value in every
input part of a cube in F, we say the testfully matches (FM)
the cube. When a test matches a 1 in all but one input part of
a cube, the test almost matches (AM) the cube.
The complement of a given function F is denoted as F. The
F in Fig. 12 represents a PLA personality whose outputs are
the complements of the original array F. The MINI process
[9], while minimizing the number of words of F, produces F
as a byproduct. (See [9] for the F generation process.)
In general, an H- G operation in cube format is called the
sharp operation, after Roth [10]. The MINI process [9], which
can be used to minimize the number of PLA words, employs
the DSHARP subprocess that returns H G in mutually
disjoint cubes. For later use, an input disjoint sharp
(IDSHARP) process is developed. IDSHARP of a cube h against
G, denoted as h$G, is the h G function in cubes whose input
parts are disjoint. Let h be denoted as it1 in27t3 ... it,p. For
example, the first cube in Fig. 12, 0111 11 11 101, has
1Z1 = 0111, Xr2 = ir3 = 11, and i4 = 101. Let g be another
cube given as PI1P2 /'3 ... pp. The h$g is defined as p (the
number of parts) cubes generated as follows:
(7[1P1*2'3 '-* p
(it1P1)J(2i2t 3*.. **p
(O1 p1)(7r2112)(it3 93) * * PP)
where some of the cubes may be null. The ji denotes the
bit-by-bit complement of p, and (itp) denotes the bit-by-bit
AND of X and p. Any null cube (i.e., some parts have all 0's) is
removed from the above. The order of the input parts may be
changed without affecting the input disjointness of the
resultant cubes.
Example: h = 011 1 11 1101, and g = 1111 01 01 110
produces
0000 11 11 101 null cube
0111 10 11 101
0111 01 10 101 Uh$g
0111 01 01 001
The IDSHARP with G = U becomes
h$G = ((h$gl)$92) ..
)$glast
where gi's may be taken in any order.
Example: Let h be the first cube and let G be the rest ofthe
cubes in F of Fig. 12. The h$G becomes
0111 10 11 101
0011 01 01 001 h$G.
0011 01 10 101
0100 01 10 100
The property of h$G is that any input portion of a minterm
of h$G matches one and only one of the cubes in h$G. In
other words, given an input vector T, the output ofthe array
implementing h$G is either all zeros or an exact copy of the
output part of the single cube that is matched.
623
FAULT SIMULATION AND TEST COVERAGE
The regularity of the PLA renders the crosspoint fault
simulation of a given test pattern a simple process. We say
the test covers a fault ifthe test detects the fault. Given a PLA
personality, crosspoint fault detection is the same as testing
that the zeros and ones of the personality are functionally
correct. The algorithm described below determines all tested
ones and zeros.
Algorithmfor Fault Simulation (FS): The array F and the
test T are given.
FS 1) Let FM be the fully matched cubes of F.
FS2) Let AM be the almost matched cubes of F.
FS3) The OR along the columns of the output part of FM
is the good PLA output Y.
FS4) Mark all FM output line 0's where the correspond-
ing Y value is 0, as tested.
FS5) Let UFM be the subset of FM cubes such that each
cube in UFM contributes a unique output 1 in an output
column of FM.
FS6) Mark all addressed input l's and the unique output
l's of UFM cubes, as tested.
FS7) Mark as tested the "missed" input 0's of the AM
cubes if the cube has a 1-output bit where the corresponding
Y value is 0.
Example: Let F be as shown in Fig. 12 and let T be
1000 01 10:
T 1000 01 10
0111 11 11 101
F 1111 01 01 110 1 AM
1100 01 11 011 IFM = UFM
Covered Bits (l's)
'1000 00 00 000
.0000 00 10 000
1000 01 10 111
Correct output: Y = 011.
Theorem 5: The personalized crosspoint of a PLA is
tested by the given test Tifand only ifthe corresponding 1 or
0 are marked by the FS algorithm. (The proof follows from
the single fault assumption and AND-OR sensitization.)
Corollary: A given input vector T is a test for some
crosspoint only if T either matches or almost matches at
least one cube in the PLA.
THE GLOBAL STRATEGY FOR TEST GENERATION
Since every test must either match a word (cube) or almost
match a word, smaller isolated cubes do not allow much
choice in test selections. Therefore, the global strategy used
in our TPLA is to process the small isolated cubes first. This
is done by a simple reordering routine described in [9] as
ORDF:
ORDF1) Sum the number of l's in every input column
of F.
ORDF2) For every cube in F, obtain the weight of the
cube as the inner product of the cube and the column sums.
ORDF3) Order the cubes of F in ascending order oftheir
weights.
In the example of Fig. 12, the column sums are 2322 13 23,
624
and the cube weights are 16, 15, and 13. Thus, the cubes are
ordered in a reverse order for TPLA processes.
The following procedures are performed for each cube in
the determined order:
1) Untested ones tests.
2) Coverage of other crosspoints by FS.
3) Untested output zeros tests.
4) Coverage of other crosspoints by FS.
5) Untested input zeros tests.
6) Coverage of other crosspoints by FS.
In the following sections, the procedures for generating
the Ones Tests, the Output Zeros Tests, and the Input Zeros
Tests will be described. TPLA also generates the coverage
matrix COV, which is identical in size to the given PLA
function. Each time a crosspoint is covered, a 1 is entered
into the COV matrix. The 0's in the final COV array denote
the untestable crosspoints.
INPUT AND OUTPUT ONES TESTS
All the ones of the given cube are treated at one pass, since
any ones test checks all addressed ones in the input and all
unique ones in the output. Let the current cube of F be CC.
The configuration (CONF) for ones tests ofCC is defined as
the totality of tests that cover the testable ones of the cube.
The following theorem is stated without proof.
Theorem 6: The CONF for ones tests of CC is
CC (F - CC) where (F - CC) denotes the rest of the cubes
in F.
The concept of CONF is similar to the complete test set
for a stuck fault generated by Yau and Tang [11]. The
differences are that CONF contains a complete test set for
all ones faults; CONF is calculated by CC$(F - CC), which
is much more efficient than producing the complete test set
for a stuck fault in an arbitrary conventional combinational
network.
Theorem 7: Any input minterm of CONF tests the input
ones of CC that are addressed and the output ones of CC
that correspond to the output ones in the CONF cube to
which the minterm belongs. (The proof follows from the
definition of $ and FS6.)
After the CONF is formed, a minimal covering routine is
used to cover all the untested testable ones of CC by the
minterms of CONF. The ones of CC that do not appear in
any CONF cube are untestable.
Example: Let CC= 0011 1111 0110 10101 where the
underlined ones are already tested. Suppose the CONF is as
follows:
CC: 0011 1111 0110 10101
CONF iI0011
0100 0110 10000 a
0010 0001 0100 10100 b
0011 0010 0110 00001 c
111 111- ones to be covered
3 01 2 2 1 number of times the bit
is covered
untestable one of CC
IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 9, SEPTEMBER 1979
A test vector is built by successively selecting a single one
in each part. A test bit is fixed in a part when a bit is chosen in
the part.
Test-Build:
1) Let W be CONF, initially.
2) Fix a test bit to cover an untested 1 that is covered by
the least number of cubes in CONF. (See above example.)
3) Let the subset of W that contains the fixed bit be the
new W. Mark the fixed bit of CC as tested.
4) Do 2) and 3) until no additional coverage occurs.
5) Fix all free choice bits using the merit preference,
shown below.
The resultant W, after 4), may contain cubes where not all
parts contain fixed bits. In the parts where no bit is fixed yet,
there may be a choice ofbits to be fixed. A typical situation is
shown below.
0100 1101 0010 101
w X 0100 0101 0010 001
0100 0011 0010 010
t I fixedi hitc
FREE choice
(all previously covered)
The merit value for each free choice bit is defined as
M = 1 + LI x L2
where LI is the number of l's in the remaining unprocessed
words in the same bit position and U2 is the number of
untested bits in the remaining words in the same bit position.
The idea is to force a 1 where many unprocessed cubes have
l's, to increase the probability of this being a test for those
cubes, and to force a coverage of the not-yet-tested points by
addressing the bit.
By first fixing the free choice bit having the highest merit,
the test is biased toward being a test for many unprocessed
cubes and covering their untested crosspoints by addressing
them.
When a test bit is fixed in every part, the test is completely
formed and then simulated for other cube coverages. If more
ones in CC remain to be covered, the CONF is used again to
build additional tests until all ones are covered.
OUTPUT ZEROS TEST
The CONF for the untested output zeros of the current
cube CC is stated in the following theorem.
Theorem 8: Let CCO denote CC whose output part is
modified such that the untested output zeros of CC are l's in
CCO. The total tests are given by CONF = CCO * F.
The l's in the output part of the CONF now denote the
sensitized output lines of the PLA whose output is 0 in the
fault-free PLA. The cubes of output zeros CONF are not
input disjoint. The intersection of the input portion of the
cubes of CONF covers the union of each cubes coverage.
One greedy algorithm works as follows.
1) Let the pseudotest-be a cube of CONF that covers the
OSTAPKO AND HONG: FAULT ANALYSIS AND TEST GENERATION 625

FAIJ LT C OVERAGE
DESCRIPTION CLASS

Extra or missing device . . . . . . . . . .

. 1
Stuck decoder drive lines ..........
Stuck output or driver lines. . . . . ... . . l
Decoder failures. . . . . . . . . . . . . . . 2
Shorts between output lines
High dominates. . . . . . . . . . . . . . . . . . . . 2
Low dominates ....................
Shorts between drive lines of one decoder
High dominates. . . . . . . . . . . . . . . . . . . .
Low dominates .......
Shorts between drive lines of two decoders. 3
Shorts between input portion-of word lines
High dominates. . . . . . . . . . . . . . . . . . . . 1
Low dominates ....................
Shorts only between output portion of word lines
High dominates. . . . . . . . . . . . . . . . . . . .
Low dominates ....................
Shorts between word and output line
High dominates. . . . . . . . . . . . . . . . . . . . 2
Low dominates ....................
Shorts between decoder and word line
High dominates. . . . . . . . . . . . . . . . . . . . 3
Low dominates .................... 2
Class 1. Fault detection guaranteed
Class 2. Fault detected if any testable bit altered
Class 3. Fault detection not guaranteed
Fig. 13. Summary of fault coverage.

most untested output zeros. Mark the covered output zeros
as tested.
2) Find another cube that has a nonnull intersection with
the input portion of the pseudotest and provides the most
additional coverage. Mark the additionally covered output
zeros as tested. The intersection is the new pseudotest.
3) Repeat 2) until no cube in CONF has a nonnull
intersection with the pseudotest or until no additional
coverage results.
The parts of the pseudotest that contain more than a
single 1 bit represent free choice bits. Again the look-ahead
bit merit M is used to fix a bit in all such parts. The process
above is repeated to cover all testable untested output zeros.
If after all cubes are processed, all the zeros of an output
column are not testable, then that output may never have
been a 0 in the generated test set. Should this occur, our APL
program for TPLA adds an additional output stuck-at-I test
to the test set. Any input minterm that has a 1 in that output
in F can be chosen for the purpose. It can be shown that one
such test is sufficient, even when there are multiple output
lines that were not stuck-at-1 tested.
INPUT ZEROS TEST
Each untested input zero bit of the current cube CC needs
a unique test. Let CCI denote CC modified by replacing the
part containing the zero bit to be tested, with all 0 bits except
for a 1 at the position of the zero bit to be tested. Theorem 5
defines the CONF of the given input zero tests.
Theorem 5: The totality of tests that cover the given input
zero is given by CONF = CCI F (proof omitted).
Any input minterm that matches a cube in CONF
constitutes the test. If the CONF is empty, the input zero bit
is untestable. Again the look-ahead merit M is used to fix
bits from the CONF to build a test. (Every p art could be free
choice.)
CONCLUSION
It has been shown that a complete set of tests is effective
for detecting many classes of faults that were not included in
the single crosspoint failure assumption. Fig. 13 gives a
summary of the coverage of faults considered. It is seen that
the detection of the majority of faults is guaranteed. Those
faults for which detection is not guaranteed require unusual
conditions that would not occur in most practical
applications.
A PLA crosspoint fault detection test set generation
algorithm, TPLA, is presented. The method uses global cube
ordering and a powerful look-ahead merit on the bits
whenever there exists a free choice of assigning a test bit.
TPLA takes advantage of the regular structure of PLA in
simulating and generating the tests.
The test set generated for the PLA in Fig. 12 is shown in
Fig. 14. The cubes are shown in the order processed by
TPLA. Further inspection shows that these nine tests also
cover all testable stuck faults, decoder faults, shorts at
crosspoints, and shorts between adjacent lines.
The cube ordering and look-ahead fixing are shown to be
powerful heuristics. In Fig. 14, for instance, the third cube c
was not even processed by TPLA, for all its testable points
were covered already. Another example illustrates the
efficiency of TPLA. An 8-bit PLA adder has a total of 16
primary. inputs divided among 8 two-input decoders and 9
primary outputs, including a complemented carry output.
The adder was implemented using prime cubes. The array
has 58 words with 41 bits each. TPLA generates 172 tests for
testing 2378 crosspoints in about 10 min of S/370/145 CPU
time. After the first six cubes are processed (60 tests), about
one-half of all the remaining crosspoints are covered. Of
these 2378 crosspoints, 165 are marked untestable (about 7
percent), which represents typical PLA testability.
626 IEEE TRANSACTIONS ON COMPUTERS, VOL. c-28, NO. 9, SEPTEMBER 1979

1100 01 11 01 1 - a

F 1 111 01 01 1 1
0111 11 11 10 I - c

Ones Test for a . . . . . . . . . .foioo 01 10 111

1 00 0 01 01 1 1 1

Output Zeros Test for a . . . . . 1 0 0 0 0 1 10 011

01 0 01 10 101
Input Zeros Test for a. . . . . . . O O0 1 01 10 101
0 10 0 10 01 1 0 1

Input Ones Test for b . . . . . . . 01 0 01 01 1 I 1

(OO01 01 01 1 11

Augmented Test. . . . . . . . . . . 1 0 0 0 1 0 1 0 0 0 0

coV' 1111 11 11 11 1
(0's Denote the 1011 11 11 110

Untestables) 1 1 1 1 I 1 I 1 1 1 1
Fig. 14. Test set and coverage array for the example in Fig. 12.

ACKNOWLEDGMENT [11] S. S. Yau and Y. S. Tang, "An efficient algorithm for generating test
sets for combinational logic circuits," IEEE Trans. Comput., vol.
The authors acknowledge the contributions of Dr. H. C-20, pp. 1245-1251, Nov. 1971.
Fleisher in providing encouragement for the work done
when the authors were assigned to the IBM Poughkeepsie
Development Laboratory.
REFERENCES Daniel L Ostapko (S'67-M'70) received the B.S.
[1] H. Fleisher and L. l. Maissel, "An introduction to array logic," IBM and B.S.E.E. degrees from Trinity College, Hart-
J. Res. Develop., vol. 19, pp. 98-109, Mar. 1975. ford, CT, in 1963 and 1964, respectively, and the
[2] K. C. Y. Mei, "Bridging and stuck at faults," in Dig. Papers of Fault M.S. and Ph.D. degrees in electrical engineering
Tolerant Computing Conf. FTC-3, Palo Alto, CA, June 1973, pp. from Northwestern University, Evanston, IL, in

91-94, IEEE Catalog No. 73 CHO772-4C. 1966 and 1968, respectively.

[3] A. D. Friedman, "Diagnosis of short faults in combinational cir-
cuits," in Dig. Papers of Fault Tolerant Computing Conf. FTC-3, Palo
Alto, CA, June 1973, pp. 95-99, IEEE Catalog No. 73 CHO772-4C.
[4] J. R. Brown, "Pattern sensitivity in MOS memories," in Dig. Symp.
Testing to Integrate Semiconductor Memories into Comput. Main
Frames, Cherry Hill, NJ, Oct. 1972, pp. 33-46.
[5] J. P. Hayes, "Detection of pattern sensitive faults in random-access
memories," IEEE Trans. Comput., vol. C-24, pp. 150-157, Feb. 1975.
[6] C. W. Cha, "A testing strategy for PLA's," submitted to 15th Design
Automation Conf., Las Vegas, NV, June 19-21, 1978.
[7] E. I. Muehldorf and T. W. Williams, "Optimized stuck fault test
pattern generation for PLA macros," in Dig. Semiconductor Test
Symp., Cherry Hill, NJ, Oct. 25-27, 1977, pp. 88-101, IEEE Catalog
No. 77CH126-7C.
[8] J. P. Roth, W. G. Bouricius, and P. R. Schneider, "Programmed
algorithms to compute tests to detect and distinguish between fai-
lures in logic circuits," IEEE Trans. Electron. Comput., vol. EC-16,
pp. 567-579, Oct. 1967.
[9] S. J. Hong, R. G. Cain, and D. L. Ostapko, "MINI: A heuristic
approach for logic minimization," IBM J. Res. Develop., vol. 18, pp.
444 458, Sept. 1974.
[10] J. P. Roth, "A calculus and an algorithm for the multiple output
2-level minimization problem," IBM Thomas J. Watson Research
Center, Yorktown Heights, NY, Res. Rep. RC 2007, Feb. 1968.
In 1968 he joined IBM, where he has done
research in wireability, test pattern generation,
logic minimization, design automation, and array
logic. During the 1973-74 academic year he was
a Visiting Fellow at Johns Hopkins University,
Baltimore, MD. Currently he is at the IBM T. J. Watson Research Center,
Yorktown Heights, NY.
Dr. Ostapko is a member of Sigma Xi.
Se June Hong (S'68-M'69-SM'78) was born in
Seoul, Korea, on May 15, 1944. He received the
B.Sc. degree in electronics engineering from Seoul
National University in 1965, and the M.S. and
Ph.D. degrees in electrical engineering from the
Univ. -citv of Illinois, Urbana, in 1967 and 1969,
respctively.
During the summers of 1965 and 1966 he par-
ticipated in the development of a computer
_graphic display oscilloscope at Tektronix, Inc.
He joined International Business Machines Cor-
IEEE TRANSACTIONS ON COMPUTERS, VOL. c-28, NO. 9, SEPTEMBER 1979
poration in 1969. He was engaged in research of advanced reliability
technology, array logic, and related areas. Since 1978 he has been with
IBM T. J. Watson Research Center, Yorktown Heights, NY, in the High
End Machine Group. He spent the 1974-1975 academic year at the
University of Illinois as a Visiting Associate Professor. He has written
papers in the areas of coding theory, test pattern generation, and Boolean
algebra. His interests are in the areas of cybernetics, coding theory, test-
Associative-Search
Content-Addressable Memory
and Array Logic
SHARE YOUNG LEE
Abstract-Bubble latches (switches with memory capability) pro-
vide very simple associative-search devices in shift-register type
memories. Such devices allow a simple implementation of content-
addressable memories (CAM's), only requiring small addition of
area, circuits, and interconnections to those of a conventional
shift-register memory. Moreover, such devices, in combination with
a multi-input or circuit, implements a versatile logic array.
Index Terms-Array logic, associative search, content-address-
able, (magnetic) bubbles, multiple match, pipelining, shift register
memory.
I. INTRODUCTION
A CONTENT-ADDRESSABLE memory (CAM) or
associative memory is a memory which can be accessed
by specifying data content rather than address or location.
All words in such a memory can be searched simultaneously,
thus greatly reducing the processing time for data manipula-
tions such as sorting, file searching, cross referencing, and
list processing. Since the access mechanism is independent of
physical locations, defective storage locations can be easily
disenabled. Thus, the LSI manufacture yield can be
significantly improved.
CAM's have been implemented by various devices, such
as ferrite cores, permalloy thin films, semiconductors, cryo-
trons, etc. [1], [2]. Typical random-access memories such as
the above equip each memory cell with associative-search
logic. It results in high speed, but also in high per-cell area
and cost (three times or more) over that of conventional
memories. Moreover, the large power dissipation associated
with these devices prohibits the construction of a large
CAM.
By contrast, bubble devices could utilize their own serial
nature to make each search device serve a long shift register
Manuscript received February 20, 1979. Part of this paper
has been presented at the 10th Annual IEEE Computer Society Interna-
tional Conference, Washington, DC, September 1975.
S. Y. Lee is with the National Taiwan University, Taipei, China
H. Chang is with the IBM Thomas J. Watson Research Center, York-
town Heights, NY 10598.
0018-9340/79/0900-0627$00.75 © 1979 IEEE
627
ing and diagnosis, systems reliability problems, and design automation.
Dr. Hong is a member of the Mathematical Association of America,
the Association of Korean Scientists and Engineers in America, the
Association for Computing Machinery, and Sigma Xi. He was a Distin-
guished Visitor of the IEEE Computer Society from 1972 to 1975. He
received an Honorable Mention Award for the Outstanding Young Elec-
trical Engineer of 1974 from Eta Kappa Nu.
Bubble Devices for
AND HSU CHANG
rather than a single memory cell. Hence, the per-cell area
and cost are not significantly different from those of simple
shift registers. Commercial bubble devices have already
achieved high-density (> 106 bits/in2), large-capacity chip
(> 105 bits), and low-power dissipation ( 10-6 W/bit)
with more improvements to come. It appears that the
technology holds a promising potential for implementing a
large CAM.
The first attempt to perform associative search in bubble
memories by Bobeck et al. [3], failed to take advantages of
the serial nature. Their stationary random-access structure
and logic per-cell operations result in excessive space as well
as time requirements. Murakami [4], [5] recognized the
serial nature and proposed a bit-serial word-parallel search
scheme in shift-register bubble memories, which marks all
the matched shift registers, and then uses a multimatch
processing scheme to read/write all matched shift registers
one by one.
In this paper, an even simpler device structure for associa-
tive search will be presented. Its operation will not only
mark the matched shift registers but also automatically open
their passages for interrogation. A multimatch processing
scheme will then sequentially read out or write into the
matched shift registers one by one. Moreover, an associative
array logic structure which allows variable and universal
logic operation will be described. The present scheme will
then be compared to two bubble array logic schemes
proposed earlier.
II. ASSOCIATIVE SEARCH
Bubble devices have several unique properties to facilitate
the construction of content addressable memories: serial
access, switching capability, memory capability in switches,
etc. To share the search facilities, the memory is organized to
use bit-serial word-parallel search; i.e., all the words in the
memory are searched simultaneously, bit by bit. The search