Advanced CMOS-Processes Devices: and Their Influences On

© Rudolf Stierstorfer
Advanced CMOS-Processes
and their influences on
DEVICES
1 BASIC CMOS PROCESS FLOW............................................................................... 3
1.1 Process steps ..................................................................................................................................................... 3

1.1.1 Deposition .............................................................................................................................................3
1.1.2 Lithography...........................................................................................................................................3
1.1.3 Etching ..................................................................................................................................................3
1.1.4 Implantation – Doping ..........................................................................................................................3
1.1.5 Diffusion / Anneals – Activation ..........................................................................................................4
1.1.6 CMP ......................................................................................................................................................4
1.2 Process modules (10sf)..................................................................................................................................... 5

1.2.1 Isolation – STI.......................................................................................................................................5
1.2.2 n-well / p-well / triple-well ...................................................................................................................5
1.2.3 Vt’s........................................................................................................................................................6
1.2.4 Gateoxides.............................................................................................................................................6
1.2.5 Poly (PC)...............................................................................................................................................6
1.2.6 Spacer 1 and Halo/Extension-Implants .................................................................................................7
1.2.7 Spacer 2 and Source/Drain-Implants.....................................................................................................7
1.2.8 Silicidation ............................................................................................................................................7
1.2.9 CA-Nitride liner (Stress liner) and CA..................................................................................................8
1.2.10 BEOL - possible 9 Metal layers in C45 ...............................................................................................9
2 ADVANCED-CMOS PROCESS FLOW ................................................................... 10
2.1 Front end of line – FEOL .............................................................................................................................. 10

2.1.1 STI-Process - ISOLATION.................................................................................................................10
2.1.1.1 STI - Lithography .............................................................................................................................. 11
2.1.1.1.1 Lithography SEM-pictures............................................................................................................ 11
2.1.1.2 STI-RIE ............................................................................................................................................. 12
2.1.1.3 STI-Liners.......................................................................................................................................... 12
2.1.1.4 STI-fill and CMP ............................................................................................................................... 13
2.1.1.5 STI-stress effect................................................................................................................................. 13
2.1.1.5.1 90nm-technology at UMC (L90) ................................................................................................. 13
2.1.1.5.2 Results........................................................................................................................................... 14
2.1.1.5.3 Explanation of STI-stress effect.................................................................................................... 15
2.1.1.6 Summary STI – Hints for Designer ................................................................................................... 16
2.1.2 Well module (N-well, P-well, Triple-Well) ........................................................................................17
2.1.2.1 N-well (‘NW’) ................................................................................................................................... 17
2.1.2.2 P-well: BF-mask ................................................................................................................................ 17
2.1.2.3 Triple-well ......................................................................................................................................... 18
2.1.2.4 Well-edge proximity effect................................................................................................................ 18
2.1.3 GOX....................................................................................................................................................20
2.1.4 PC – Poly and Spacer..........................................................................................................................22
2.1.4.1 Post-Pc-Rie TEM :............................................................................................................................. 22
2.1.4.2 Isolated vs nested devices.................................................................................................................. 22
2.1.4.3 Spacer 1 ............................................................................................................................................. 23
2.1.4.4 spacer 2.............................................................................................................................................. 24
2.1.5 Source-/Drain-anneal ..........................................................................................................................25
2.1.6 Silicidation ..........................................................................................................................................25
2.1.7 CA-nitride liner ...................................................................................................................................25
2.1.7.1 C65-Base ........................................................................................................................................... 26
2.1.7.2 C45 – base: Dual Stress liner with SPT ............................................................................................. 26
Technology – Advanced CMOS logic 1 / 37 14.05.2008

Rudolf Stierstorfer, Dipl.-Physiker, L90 / C65 / C45 – CMOS development engineer at UMC and IBM
2.1.7.3 Liner – stress: geometry dependance................................................................................................. 27

2.1.8 FEOL-Stress........................................................................................................................................28
2.1.8.1 Theorie of channel stress ................................................................................................................... 28
2.1.8.2 SPT .................................................................................................................................................... 28
2.1.8.3 SMT................................................................................................................................................... 28
2.1.8.4 eSiGe ................................................................................................................................................. 29
2.2 Back end of line – BEOL ............................................................................................................................... 30

2.2.1 Just some facts – C65:.........................................................................................................................30
2.2.2 Just a picture: 1X-metal level..............................................................................................................30
2.2.3 What you should know: ......................................................................................................................30
3 SUMMARY OF FEOL-EFFECTS ON DEVICES ...................................................... 31
3.1 STI................................................................................................................................................................... 31
3.2 N-Well / P-Well / Triple-Well ....................................................................................................................... 32
3.3 Poly.................................................................................................................................................................. 32
3.4 CA-liner-Stress............................................................................................................................................... 32
3.5 General guidelines.......................................................................................................................................... 32
4 DEVICE PERFORMANCE IMPROVEMENT – WHAT’S LEFT? ............................. 33
5 TASKS ..................................................................................................................... 34
5.1 Technology...................................................................................................................................................... 34
5.1.1 process steps........................................................................................................................................34
5.1.2 well edge proximity effect ..................................................................................................................34
5.1.3 STI-stress ............................................................................................................................................35
5.1.4 Layout style.........................................................................................................................................35
6 MOS-FET ................................................................................................................. 36
6.1 Threshhold voltage ........................................................................................................................................ 36
6.2 DIBL – drain induced barrier lowering....................................................................................................... 36
6.3 Body-Effect ..................................................................................................................................................... 37

1 Basic CMOS process flow

1.1 Process steps
1.1.1 Deposition
Deposition is used to combine either conducting or nonconducting materials with silicon.
Different methodes include but are not restricted to
oxidation: silicon surface can be oxidized in a furnace (TEOS = thermal oxide)
CVD: chemical vapour deposition (eg nitride); RT-CVD (room temperature CVD), LP-
CVD (low pressure CVD) or PE-CVD (plasma enhanced CVD) or a combination are
methodes to get the desired material properties (eg stress liner can be PE-CVD nitride–
liners ‘Si3N4’); PE-CVD is also used for metals and silicides (W, Ta..).
1.1.2 Lithography
Lithography is the transfer of geometric shapes from a mask onto the wafers surface. Todays
lithography is rather complex since a wavelength of 193nm (deep UV) is used to get structures of
less than 50nm width printed exactly. Usually printing geometric shapes in the order of used
wavelength is already critical but printing structures in the order of only a quarter of used
wavelength needs more sophisticated processes. Interference and corner rounding is usually what
occurs and makes exact printing very difficult.
Techniques like OPC (optical proximity correction) and PSM (phase shift masks, either attenuated
or alternating) can overcome those difficulties.
45nm CMOS-generation and below looks for further improvement techniques like DE/DP (double
exposition, double patterning) and immersion lithography (currently being introduced for 45/32nm
technology).
1.1.3 Etching
Most commonly used is a technique called RIE (reactive ion etching) which is a plasma etching
technique. Ionized atoms get accelerated in an electrical field towards the wafers surface and
create the desired pattern.
Etching removes areas not protected by a photo mask in order to create islands which
subsequently maybe specially treated to get the desired material properties.
Wet etching is also common and provides a good through put but cannot be performed at critical
dimensions.
1.1.4 Implantation – Doping
To get desired device behaviour and doping profiles implantation is one of the most used process
steps in semiconductor manufacturing. Doping of n- or p-atoms is used for pn-junctions, poly-
predoping (n-fet only) or relaxation of stress liners just to name a few.

1.1.5 Diffusion / Anneals – Activation
Implantation is only the first step. After implantation of n- or p-type atoms into the silicon lattice
those atoms need to be activated. This can be done by annealing steps which mean always at the
same time diffusion.
Diffusion in a furnace usually has the disadvantage that due to the thermal capacity the ramp rate
is slow and wide diffusion in all directions of implanted atoms will occur. This step cannot be used
for Source-Drain-anneal since the atoms in advanced CMOS-processes would diffuse under the
gate and depletion regions of source and drain may contact each other and current would leak from
source to drain (SCE).
Source-Drain-anneals in advanced CMOS are short Spike-anneals – called ‘RTA’ (rapid thermal
annealing). They are vey fast (220°C/sec) and have very low lateral diffusion, are single wafer
processes and therefore more expensive.
C45 has already a combination of spike anneal and LSA (Laser spike anneal) instead of RTA only
to further reduce lateral diffusion and create sharper junction profiles at the same activation level.
1.1.6 CMP
After deposition and/or implantation and resist removal the surface needs to be prepared for
further process steps. To ensure a high uniformity of the whole wafer CMP (chemical mechanical
polishing) is used to get an even surface.
Since some materials are hard (SiO2) and some are soft there has to be a certain ratio of soft to
hard area otherwise dishing or erosion can occur. This is taken care of automatically by data
preparation.
CMP is being used in FEOL (STI) and BEOL-processes.

1.2 Process modules (10sf)
MODULE LITHO LEVEL
STI RX, KV
Wells NW, BF, N3
Vt implants XW, LW, NV, PV, PR, NR,IP,
IN, JP, JN
Gate Oxide EG, DG, IG
Poly PC, ZP, BK (>120nm)
Spacer1 ---
Extension/Halo implants PH, BH, GP, GN, DE, DF
Spacer2 ---
Source / Drain implants BN, BP
Silicide Block OP
Stress Liner XN (single liner), WP, WN (dual
liner)
Contact CA
BEOL – Process Finish
1.2.1 Isolation – STI

STI
STI
STI
STI
STI
STI
substrate
1.2.2 n-well / p-well / triple-well
triple-well P-well
N-well P-well
P-well
N-band

1.2.3 Vt’s
PFET device NFET device
LVT RVT HVT HSIO I/O LVT RVT HVT HSIO I/O
LW
XW
PV
NV
PR
NR
IP
IN
JP
JN
N-well P-well & Triple well
1.2.4 Gateoxides
thick intermediate thin
resist
N-well or P-well
1.2.5 Poly (PC)

poly
poly
N-well or P-well

1.2.6 Spacer 1 and Halo/Extension-Implants

Example below is not to be understood that those implants are at the same time – for every device
family every halo/extension is implanted seperately!
gate oxide
thin intermediate thick thin intermediate thick
PH mask
resist resist
N-well P- or Triple well
1.2.7 Spacer 2 and Source/Drain-Implants
N-well P-well
1.2.8 Silicidation
silicide area silicide blocked
Ni & TiN
N- or P-well

1.2.9 CA-Nitride liner (Stress liner) and CA
Nitride liner
HDP
CA CA CA
N- or P-well

1.2.10 BEOL - possible 9 Metal layers in C45
TASK: NFET-Device – technology elements

2 Advanced-CMOS Process Flow

The following guidelines are based on the 10sf_HP-CMOS-process flow at IBM (65nm CMOS
high performance), Jun 2007. Figures and numbers are subject to any changes.
Every CMOS-process is in constant motion of changing hence while writing this document this
process flow has very highly likely changed already.
The 10sf-process flow was chosen due to the fact that it was the first process with enhanced device
performance due to stress techniques. 10lp (the low power version of the 10sf-process) in contrast
had only a minor tensile liner stress to improve NFET-device performance and thus degrading
PFET-device performance not too much (see also CA-liner stress).
Although the 10sf-process is the first process with active device performance boost techniques due
to stress one can also find influences on device performance in earlier generations like L90 (90nm
CMOS from UMC) or even C11 (130nm CMOS).This document contains also expamples of other
CMOS-process flows like L90 (UMC 90nm-process) or 45nm-CMOS-generation.
2.1 Front end of line – FEOL

2.1.1 STI-Process - ISOLATION
some comments:
STI stands for shallow trench isolation.

Process step is called ‘RX’. Mask level ‘RX’
The RX-layer defines the ‘active area’ respectively isolation. Everything which is ‘out of
RX’ is STI-region.
To isolate devices in modern CMOS-processes STI is being used. In older generations locos or P-
locos (poly buffered local oxidation) was used for isolation. STI offers a good electrical isolation
at very small dimension.
Since C8 (130nm CMOS generation) it was discovered that STI can affect device performance in
both ways positive and negative. This effect is called STI-stress effect and it is due to the different
lattice constants of Silicon (n- or p-doped) and SiO2 (STI) which causes silicon band structure to
bend and affects electrons and holes effective mass. This effect can cause channel strain and
therefore degrade or improve device performance depending on the strain and the type of FET
used.
(see also: STI-stress effect)

2.1.1.1 STI - Lithography
mask
resist
ARC
hard mask
Pad Nitride
Pad Oxide
substrate
A complex lithography scheme with a special hard mask is currently being used to perform the
following very complex STI-RIE-process. This is necessary to get the desired STI-depth and STI
aspect ratio.
This process defines RX – active aea width!
2.1.1.1.1 Lithography SEM-pictures

iso nested

2.1.1.2 STI-RIE
iso nested
this is a special ‘hard mask rie’ with built-in Si-spike reduction
2.1.1.3 STI-Liners
iso nested
after STI-rie 2 liners are applied:

Oxide
Nitride
although these two liners are very thin (70Å Oxide, and ~110Å Nitride) at IBM during development
phase a device performance dependance due to liner scheme and liner thicknesses was
noticed. The Reason for this device performance dependance is most likely due to different stress
inducements because of those liners.

2.1.1.4 STI-fill and CMP
DIVOT
HDP (high density plasma) is used to fill shallow trenches with SiO2. Subsequent HDP-CMP and
Pad nitride strip causes the so called ‘DIVOT’. The Divot-height is strongly dependant on HDP-
fill, HDP-CMP and liner scheme and thicknesses.
Narrow device performance can be strongly degraded by divot. ( Reverse narrow width
effect)
A Divot-Nitride-liner with subsequent divot etch (hot phosphoric acid) finishes the STI-process:
Note: The divot will be widened by all subsequent oxide etches (resist strips & GOX module) and
can cause poly stringers ( shorts) and corner device behavior.
2.1.1.5 STI-stress effect

2.1.1.5.1 90nm-technology at UMC (L90)
Three different device structures were used to determine the influence of STI-stress on device
performance. Nfet- and Pfet-teststructures have the same layout-style but of course different
doping. The only difference of those three structures is that STI-edge is getting closer towards PC-
edge i.e. the distance of SiO to Si is getting smaller. Minimum distance allowed at L90-technology
was 240nm (see following example).
Additionally: it is important to notice that dummy structures are being used for better printing at
minimum Lpoly-dimensions. (generally: whenever possible use dummy structures not only for
transistors but also for all other devices).

SP-Device 10/0.08 - teststructures

Y
[Wpoly]
Distance
PC/STI - edge
240 nm 640 nm 1250 nm
2.1.1.5.2 Results
PFET-device performance: IMPROVEMENT!
Ion vs Iof PMOS 10/0.08 SP
1.E-06
2600
largenm
1.E-07 medium
640 nm
small
240 nm
12uA/um (4%)
1.E-08
0.0022 0.0024 0.0026 0.0028 0.003 0.0032 0.0034
~4% Ion-improvement

NFET-device performance: DEGRADATION!

Ion vs Iof NMOS 10/0.08 SP
1.E-06
largenm
1250
1.E-07 medium
640 nm
small
240 nm
30uA/um (5%)
1.E-08
0.006 0.0065 0.007 0.0075 0.008
~5% Ion-degradation +(~2.5% Vts-shift )

2.1.1.5.3 Explanation of STI-stress effect
Under compressive stress (i.e. strain due to the different lattice constants of SiO2 and Si) STI
affects the carrier mobility of nearby transistors. STI-stress causes mainly compressive stress
along L_Poly (longitudinal stress). Compressive longitudinal stress changes the effective mass of
electrons and holes and therefore mobility changes too. Holes have a higher mobility with
compressive stress whereas electrons have a higher mobility with tensile stress.

Nota bene: Compressive stress due to STI is mostly beneficial for PFET (drain current increases at
the same Ioff) but degrades NFET-device performance (drain current decreases at the same Ioff)
and can lead to a Vt-shift for Nfet. Length and width of the device can modulate the effect.
An influence of PFET-Vt can be observed too but usually isn’t that strong compared to NFET.
Tip: Don’t use minimum PC-STI-distance in your layout! (rule of thumb: at least twice minimum
Pc-Sti-distance).
Tip: Be more careful if you design in latest technolgies (especially ‘high performance
technologies’ – called ‘base technologies’)! With latest CMOS-generations (it started in 130nm-
CMOS-technology and it is more pronounced in newer generations like 65/45nm CMOS-
technology) minimum Pc-Sti-distance is getting smaller and thus STI-stress effect is getting
worse.
Tip: Always check if stress related parameters in your model give you appropriate stress
dependances and use stress model if possible (hopefully this doesn’t slow you down too much!)
2.1.1.6 Summary STI – Hints for Designer
Avoid minimum RX (minimum width of devices) – at minimum RX effects like ‘Divot’

and stress effects due to liners are more pronounced and can influence device performance
and can cause corner device behaviour.
Avoid minimum PC-STI-distance due to STI-stress effect. This can cause a big device
performance change (i.e. improvement or degradation and Vt-shift).
general rule of thumb in C65base: PC-STI-distance shall be greater than 1um!
TASK:
1. Calculate the performance gain/loss-dependancy in L90 (or any other newer technology)
for a SP-Device when PC to RX-distance is less than 500nm!
2. Check your DM for STI-stress effect dependancy.
3. Check your model on a single NFET or PFET (or a similar inverter) and vary STI-Pc-
distance and see if stress model is appriopriate and responds to your layout!

4.
2.1.2 Well module (N-well, P-well, Triple-Well)
Lithography-layer: NW (N-well) is the layer to be drawn, p-well will be generated. With respect to
triple well layer check your latest design manual guidelines since those guidelines can vary from
technology to technology. There are different approaches for generating triple (= isolated pwell in
n-well with n-band around) and methodes change constantly.
Tip: always check booleans when working with triple well!
2.1.2.1 N-well (‘NW’)
N-well
Design-Layer: NW
N-well Mask
resist
N-well
Additionally to N-well generation one can also notice that the ‘N-Band-guard-ring’ is already
implanted (N3- or Triple-well approach – optional process).
********************
Very critical for analog design is Vt-matching.
N-well proximity effect can cause Vt-shifts (see ‘N-well-proximity’)
********************
********************
NOTE: Body –Effect!
********************
2.1.2.2 P-well: BF-mask

P-well
Design-Layer: BF P-well Mask
resist
N-well P-well
TWIN-well

Note: BF-mask is a block mask generated as the complement to NW. If you don’t want to have
any well implant BF-MOAT can be used to suppress both n-well and p-well implant
(useful for ‘LDMOS’-device.
2.1.2.3 Triple-well
Triple-well
Triple-well Mask Design-Layer:NW, N3
resist
P-well
N-well P-well
N-band
Triple-well
The deep N-band is a high energy implant followed by a pwell implant.
Note for Designers: Isolation in C45 was a problem since profiles getting shallower and energy of
well-implants had been reduced. Always check isolation (leakage currents in your design – esp.
for triple well designs).
2.1.2.4 Well-edge proximity effect

NFET and PFET devices less than 1 µm from n-well and triple-well edges will have a different
threshold voltage than devices located further away from well edges. NFETs located in the
substrate will behave differently than triple-well NFETs. The magnitude of the well edge-
proximity effect also depends on the oxide thickness.
The root cause for this phenomenon is assumed to originate from dopant atom scattering in the
photoresist which changes the effective doping of the adjacent devices.
A model is available to calculate this effect based on the device dimensions, device type,
proximity to, and the number of proximate well edges.
In general, for minimum-size devices (thin gate oxide) located in close proximity to a single well
edge, the effect is less than 20 mV in threshold shift.
Tip: If the design is Vt-critical (Vt-matching critical) as a rule of thumb the well edge has to be 3
µm away from the device (if possible).
Note also: N-well proximity-effect is more pronounced than p-well-proximity-effect due to the
mass of the dopant material. P-well-proximity-effect can be neglected in most cases.
For critical analog applications: see next page!

C65_Base well-edge-proximity effect due to dopant atom scattering – analog design guidelines for
threshhold voltage matching (design manual):
1. The n-well mask edge should be greater than or equal to 3 µm from the active area (PC over RX)
of the matched devices if threshold voltage (Vt) matching is required to stay within the limits
listed in Table 5-39.
At closer spacings, the threshold voltage associated with the active device is raised by an amount
that increases with a decrease in spacing. This phenomenon occurs in all types of thin- and thick-
oxide NFETs and PFETs. If 3 µm spacing cannot be achieved, then identical designs must be used.
The design must be identical with respect to placement of the n-well relative to the device source
and drain. Note that the absolute value of the threshold
voltage will be modified by the presence of mask edges. Mirror image designs are subject to n-
well misalignment-induced threshold voltage mismatch of 20 mV or higher depending on the
degree of n-well misalignment and the device type.
2. The circuits where threshold matching is critical also depend on current ratios. For precise current
ratios, always use different numbers of identically designed fingers and do not expect the ratio of
the current in a wide (or long) device to that in a narrow (or short) device to be precisely
represented by the model.
table 5-39: n-well proximity effect in C65-base

Example of 0,12um-technology well edge proximity effect:
Task – well proximity saftey region calculation!
2.1.3 GOX
Todays gate-oxides (GOX) can be very thin (eg C45-base device is ~12Å Tox-Gl).
There are two ways to measure gox-thickness:
Tox_gl: by applying a voltage from bulk to gate and measue the tunnel current – this is
equivalent to Tox_gl – it can also be called ‘geometric Tox’.
Note: geom. Tox < effective Tox (resp. geom. Cox > effective Cox)
Measurement:
    J is the current density through the

  J   oxide, with Vg=2V in accumalation.
Tox _ gl = −0,225 ∗ log  − 7,101 (Result in [nm])
  1 A 
 
  cm 2  
Tox_inv:
ε0 : vacuum permeability (=8,854 x 10-14 F/cm)
κ ox ∗ ε 0 κox : dielectric constant of SiO (=3,9)
Tox _ inv =
C inv Cinv : gate capacitance measured in inversion
Mostly DPN-oxides are being used. DPN stands for decoupled plasma nitrides and this means that
during oxidation the surface is being treated with nitride atoms very softly in order to increase
dielectric constant ε.
The following is a picture of the C45LP (low power process version) – target Lpoly is ~40nm and
target Tox_GL is ~18Å.

In a X-TEM one is able to

‘measure physical oxide thickness’:
Nota bene: Gate oxide leakage is a major contributor to device leakage for thin oxide devices in
base technologies and is for C65base already in the order of ~nA/um.
Gate oxide leakage depends strongly on the threshhold voltage. Devices with lower Vt can have
significant higher gate oxide leakage.
Additionally at higher temperature gate oxide leakage increases as well (25 85 DegC: ~15% for
C65base).

2.1.4 PC – Poly and Spacer
2.1.4.1 Post-Pc-Rie TEM :
Note: only N-Poly gets ‘ZP’mask which is a phosphorus-implant and is done after spacer 1
deposition to confine the dopants in the upper portion of the gate poly during poly stack etch.
2.1.4.2 Isolated vs nested devices

Tip: Avoid ‘Isolated Devices’ – ‘Lithography-printing of nested devices and as well etching of
nested devices is more controlled!
The example below shows the standard so called ‘sliver’ scaling structure 10 dummy PC’s on each
side. During development one tries to get an ‘ideal’ MOSFET-device with no parasitics.
In reality 4-5 dummy structures already ensure a reliable PC-printing.
Additionally don’t forget: very dense dummy PC’s can harm your CA-stress-liner! As a rule of
thumb use whenever possible 4-5 dummy PC’s and don’t pack them to close together (eg 2-3times
minimum PC-pitch, first dummy PC farther away if possible).

simple schematic (for later use):
Isolated Devcies like the following example can have a different Lpoly than expected due to
printing and/or etching. The advantage of such an isolated device though is that you get most
benefit out of stress liners (if you don’t use too many CA’s).
2.1.4.3 Spacer 1
poly
poly
N-well or P-well

Spacer 1 is a thin oxide spacer to bring halo and extension close to poly edge.
Both extension (also called ‘LDD’ = lightly doped drain) and halo (also sometimes called ‘pocket
implant’) have been introduced to have a better control of short channel effects (SCE).
Halo implant is high tilted implant (usually ~ 30°) and goes underneath poly.
N-well P- or Triple well
Short-channel-effect (SCE):
Due to the very short Lpoly (C45: Lpoly is ~40nm) it is more and more difficult to control
diffusion underneath the gate (lateral diffusion of LDD = lightly doped drain or ‘extension’) which
effectively reduces channel doping.
As an effect Vt is reduced with L decreasing! (SCE)
In order to better control SCE additionally halo-implants have been introduced (also called
‘pocket’). With halo Vt decreases while L increases (‘reverse short channel effect – RSCE’). (
see also: DIBL)
In addition nowadays one considers inhomogenous implant profiles as another likely cause for
channel doping (and therefore Vt-variation).
Tip: As a rule of thumb with 3xLmin-devices (3 times Lpoly) one should be in a ‘safety region in
terms of Vt-variation due to short channel effects.
2.1.4.4 spacer 2
After Halo- and Extension implant spacer 2 is deposited. Spacer 2 is a two-fold-spacer and consits
of oxide and RTCVD-nitride.
Since stress is introduced in new generation devices it has been discovered that the thin oxide of
spacer 2 has a big influence on how stress (eg due to stress liner) is effective in the channel.
Different shapes have been investigated – L-shape-spacer seem to be a good solution.
After nitride spacer deposition a high dose source-/drain implant can be performed.
This is called HDD – ‘highly doped drain’.
N-well P-well
The HDD-implant is to reduce source and drain series resistance.

2.1.5 Source-/Drain-anneal
Nowadays different methodes of annealing source and drain are being used. In C65 a spike-anneal
(in the range of ~1050 DegC) was used. Also common is a spoak-anneal which is a mixture of
spike and soak.
In general ramp rate, anneal temperature and time is very critical for device performance.
Another critical parameter being highly influenced by this anneal is the overlap capacitance (C-
overlap).
To further reduce diffusion under poly at the same activation level a combination of spike anneal
and LSA (laser spike anneal) has been introduced for C45_base-generation.
Generally one can say lower lateral diffusion is being achieved by shorter anneal time but may
also cause less activation.
2.1.6 Silicidation
To ensure a low ohmic contact to the devices (source/drain/bulk/Pc) NiSi or NiPtSi is being used
for 65nm generations. NiPtSi has offers lower contact resistance than CoSi (used in previous
generations). Another advantage of NiPtSi is a ‘better electromigration behaviour’ but this was of
disadvantage for efuse-programming (post-fuse resistance target in C65 had to be lowered to 2,1
kOhm).
To avoid devices being silicided the OP-layer has to be used. Esp. for higher ohmic resistors the
op-mask is important. With NiPtSi spiking is reduced and therefore currently used in C45.
silicide area silicide blocked
Ni & TiN
N- or P-well
Silicidation also plays an important role for ESD-devices.

ESD-devices usually have source and drain silicide-blocked. Due to blocking the source- resp.
drain-resistance increases by a factor of ~ 10 (NFET) or ~ 20 (PFET).
2.1.7 CA-nitride liner

A nitride liner is used before FTEOS or low-k dielectricum is deposited (also called ‘CESL’ –
contact etch stop layer).
Since 90nm-CMOS generation it was discovered that these CA-liners can also introduce stress
into the channel and thus boosting device performance.

2.1.7.1 C65-Base
In C65-base a high tensile nitride liner was used to improve Nfet-device performance (see also:
channel stress technique) and a special relaxation implant for Pfet-devices only removed this
tensile stress again to prevent degradation of Pfet performance.
ZN-mask
resist
Nitride
liner
N-well P-well
2.1.7.2 C45 – base: Dual Stress liner with SPT

In C45-base a dual stress liner scheme was introduced to boost both Pfet- and Nfet-device
performance.
Many different schemes of introducing maximum stress have been investigated. At IBM we used
the following approach: to bring stress as close as possible to the channel we removed spacer 2
(this technique is called ‘SPT’ = spacer proximity technique) and first deposited tensile nitride
liner (WN-mask) for NFET-region only. After that WP-mask was applied for PFET-region only to
boost PFET-performance with a compressive nitride liner. So PFET gets compressive stress (
device performance boost) and NFET gets tensile stress ( device performance improvement).
WP-mask WN-mask
(compressive stress) (tensile stress)
resist
Nitride liner
N-well P-well

Tip: When working with stress liners think of CA’s perforating the nitride liner and thus reducing
the stress capability of the nitride liner. Dummy poly gates too close to PC are even more effective
in reducing liner stress. Try to avoid as many as possible CA’s and try to put them as far as
possible away from PC (this is called in C45 ‘strap ratio’).
Of course don’t use single CA-approach – always look for redundancy!
At min contacted pitch, most of CA nitride is consumed by CA contact! The stress introduced in
channel by strain nitride film is proportional to volume and proximity of film to channel.
Critical dimensions that modulate film volume & proximity:
PC-to-PC distance
CA CD and CA-to-PC distance
CA pitch.
2.1.7.3 Liner – stress: geometry dependance

1.2
Normalized Average Channel Stress
0.8
0.6
0.4
0.2
0
1 2 3
Layout
min PC pitch min PC pitch with CA
channel stress is reduced for nested vs iso- devices

contacts further decrease channel stress

2.1.8 FEOL-Stress
Besides CA-nitride liner stress and STI-stress there are several more options introducing stress.
2.1.8.1 Theorie of channel stress
Mechanical stress deforms the silicon lattice and changes the band gap by shifting the ratio of
heavy to light electrons (resp. holes) towards the lighter ones (‘more light electrons’) which
reduces the effective mass of electrons (resp. holes) and thus improves mobility due to the fact that
lighter electrons (resp. holes) have less intra- resp. intervalley scattering.
Tip: while working with stress schemes check your band gap reference circuits!
2.1.8.2 SPT
This technique is the ‘spacer proximity technique’ and works the following way: to get most out of
your stress liner into the device you need to ‘bring’ the stress as close as possible to the device =
channel where mobility can be affected most. In order to reach this goal one removes spacer 2
again after S/D is implanted and annealed. After removing spacer 2 one can deposit a tensile or
compressive nitride liner which is more effective compared to a device with spacer 2 still aside
PC.
2.1.8.3 SMT
This technique is called ‘stress memory technique’ and works the following way: after implanting
source and drain (but before s/d-anneal) a tensile liner is applied. With the tensile liner s/d-anneal
is performed thus ‘storing’ stress for Nfet-devices. After s/d-anneal the tensile liner can be
removed but stress is still stored within si-lattice. – Nice, isn’t it?
For PFET: to produce a compressive liner isn’t that easy but up to now we didn’t manage to ‘save’
the compressivness at higher temperatures. Somehow there are some chemical reactions which
causes the compressive liner to loosing its compressibility thus we weren’t able to perform SMT
on Pfets.

2.1.8.4 eSiGe
But there is another way getting Pfets stress enhanced besides the options described above.
eSiGe = embedded Silicon Germanium! This is already introduced at C45 (base technology only)
and means the following:
Source and drain region of Pfet only are being completely removed and refilled with embedded
silicon germanium (black area). SiGe has a wider lattice and therefore introduces compressive
stress into the channel region.
NFET: use of SiC is possible to replace S/d-region – not being currently used in any technology.
(maybe to be explored in C32/22).

2.2 Back end of line – BEOL

2.2.1 Just some facts – C65:
Four to nine copper metal levels, including up to six 1x, five relaxed-pitch 2x, and two
relaxed-pitch 4x metal levels, last metal level is aluminium
Planarized passivation and interlevel low-k dielectrics
Wire-bond pads or controlled collapse chip connections (C4s)
2.2.2 Just a picture: 1X-metal level
2.2.3 What you should know:
- Copper is the material for newer CMOS generations due to better scaling and
electromigration, faster in terms of speed and easier to integrate with low-k materials
- low-k-material is still questionable in terms of process/material stability: C65base used
SiCoH (low-k) and FTEOS (higher k-value but process is mature)
- single damascene / dual damascene is used for copper metalization
- BEOL-Caps are strongly dependant on the groundrules and dielectrikum used (low-k or
older material) – see also: sandwich cap, grid cap and so on.

3 Summary of FEOL-Effects on Devices

Remark: If you want to design very stable and secure following guidelines might help. But it is
well known that in terms of area, speed and cost those guidelines might be contradictive.
3.1 STI
narrow – Effect: STI-etching, HDP-Fill and HDP-CMP (including STI-liners) can cause a
‘divot’ to occur and influence device performance esp. for narrow devices; it is best not to
use narrow devices! As a rule of thumb: at least use 2-3 times narrow width.
reverse-narrow-width-effect (RNWE): divot and in particular fringing fields and/or oxide
thinning at the edge of STI can lead to Vt-reduction which is also more pronounced with
width decreasing.
narrow-width-effect (NWE): in contrary to RNWE for older isolation technologies like
locos (P-locos) Vt increases with width decreasing
corner-effect: the above decribed ‘narrow-effect’ can cause a low-Vt-parasitic device turn
on (in parallel to the ‘original device’) thus leading to a different device behaviour the so
called corner device behaviour
STI-stress-Effect: STI-Stress causes mainly compressive, longitudinal stress along the
channel and can be therefore beneficial to PFET-device performance but can also shift
Nfet-Vt and degrade Nfet-device performance.
As a general rule of thumb: if you want to exclude STI-stress effect influencing device
performance leave a distance of >1µm to PC-edge.

3.2 N-Well / P-Well / Triple-Well

Well-edge-proximity – Effect: Due to well scattering device-threshhold can be influenced
(thicker oxide devices more than thinner) – as a general rule of thumb: if you are
absolutely critical in terms of vt-matching don’t place devices closer than 3um towards any
well edges.
3.3 Poly
Iso/Nested – effect: try to avoid isolated devices, nested devices are more reliable and
controlled in terms of printing and etching.
Note: if you work with ca-liner stress nested devices have less strain and can therefore
perform not as good as iso-devices (contradictive!)
short-channel-effect: Vt decreases with Lpoly decreasing. Vt-variation is huge for
minimum Lpoly-devices. If your design allows more space and/or is critical in terms of Vt-
variation consider not using Lmin-devices.
Reverse short-channel-effect: halo or pocket implant cause Vt increase with Lpoly
decrease.
General: if speed and space is not an issue consider not using minimum lpoly-devices. To
be on the safe side in terms of Vt-variation caused by SCE’s consider taking at least
3xLmin-Devices.
3.4 CA-liner-Stress
CA-Liner-stress – Effect: CA-nitride liner stress improves but also degrades device
performance. If you work with ‘stress technologies’ consider placing CA’s as far away
from PC as possible and as less CA’s as possible.
Note: This of course doesn’t mean that one should use a ‘single CA-approach’ – always
look for redundancy!
Check also: PC-to-PC distance, CA CD and CA-to-PC distance, CA pitch. Isolated
devices also have higher stress compared to nested devices.
3.5 General guidelines

Try to use not minimum dimensions (Lpoly, Wpoly, Pc-STI-distance and so on).
Always look for redundancy in your layout (esp. Ca’s)
Dummy structures: whenever possible use dummy structures in your layout to ensure
better lithography printing and etching. Dummy structures are always helpful if you work
with minimum dimensions but … see next line
Dummy structures are not helpful if work with stress liners! Due to dummy structures most
stress liners loose a big part of their ability to enhance device performance by channel
stress. So if you work with stress liners check recommended rules in the design manual.

4 Device performance improvement – what’s left?
Apart from gate stack and channel –

we’ve covered all!
C32: currently under development C32 has to adopt metal gates to further improve device
performance. Poly length scaling has reached already the limit with C45. Further shrinking will
need new lithography either higher immersion or EUV.

5 Tasks
5.1 Technology
5.1.1 process steps
Fill in the blanks! ……………………. …………………….
Mask:
RX…..
……………………. PC
Mask: …..
…………………….
…………………….
…………………….
…………………….
…………………….
…………………….
…………………….
…………………….
…………………….
…………………….
5.1.2 well edge proximity effect
Task: Mark the region where you expect more than 55 mV Vt-shift for the JP-Device!
(assume linear Delta-Vt/distance-dependancy and setup a formula!)
N-well P-well
P-well
1 µm

5.1.3 STI-stress
C65LP – PFET with STI under stress C65LP – NFET with STI under stress
Task: Design a device where you loose 10% NFET-performance resp. gain 2% PFET-
performance only due to STI-stress!
5.1.4 Layout style

Task: try to figure where you ‘loose’ 6% performance! (C65_base-technology)
Situation: device scaling structure ‚sliver‘ shows around 6% higher performance (i.e.
normalized Ion) than the monitoring structure on ‚blackbird‘ (Lpoly = 50nm).
Sliver (Lp = 55nm): Drawing not true to scale! Blackbird (Lp = 55nm):
Pc-pitch: 250nm
Pc-pitch: 510nm
2µm 1µm 0,2µm

NFET
• Nr of Ca‘s: 5 per µm • Nr of Ca‘s: 3 per µm
• Pc to Ca: 185 nm • Pc to Ca: 55 nm
• Pc-pitch: 510nm • Pc-pitch: 250nm
• Nr of dummy PC‘s: 13 • Nr of dummy PC‘s: 5
• Nr of Rx-fingers: 1 • Nr of Rx-fingers: 5 (0,2 µm space)
• Rx-space: 1 µm (5 fingers)

6 MOS-FET
6.1 Threshhold voltage
In newer technologies the threshhold voltage is defined when the source current reaches a
certain limit. The limit is defined as
Weff
VT = VG when I DS = I VT × , Ivt = 300 nA for NFET , Ivt = 70 nA for PFET
L poly
and:
Lpoly = Ldesign - ∆L
W eff = Wdesign - ∆W
Transfer-characteristics of NFET, C65_base: 2um width, 60nm Poly length:
Id_lin / Id_sat C65_base, NFET (3/0,06)
1,0E-02
1,0E-03
1,0E-04
1,0E-05
Id_lin
Id
Id_sat
1,0E-06
1,0E-07
1,0E-08
1,0E-09
-0,10 0,10 0,30 0,50 0,70 0,90 1,10
Vg
Task: Extract Vt!
6.2 DIBL – drain induced barrier lowering
VB = 0 V, Vtsat – Vtlin=DIBL
Drain side is biased high which lowers the barrier and leads to a decreased Vt of short channel
devices for increased Vds.
Task: Calculate DIBL for the example given before!

6.3 Body-Effect
Body-effect is the increase of Vt if a negative Voltage for NFET (or a positive Voltage of
PFET) is applied on the p-well i.e. drain/source – bulk diodes are reversed biased. An increase
in Vt is equivalent to a decrease in Idoff resp. Isoff.
This is a very important technique to reduce off-current resp. tune Vt.

Source/Drain – bulk diodes can also be biased forward as long as you stay below ~0,6V (Si
diode voltage). In this reagion Vt can be reduced resp. off-current is increased.
Defintion:
Vtlin @|Vbs| = 1,2V – Vtlin @Vbs = 0V
abs (Is) vs Vg: Bodyeffect in C65LP, NFET_DL 2/0,08
1,E-03
1,E-04
1,E-05
a b s (Is ) (@ V d =0 ,0 5 V
1,E-06
1,E-07 Vb= -1V
1,E-08 Vb = 0V
1,E-09
1,E-10
1,E-11
1,E-12
,1
1
1
2
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
-0
Vg
Task: ‘Extract body effect!’


Advanced CMOS-Processes Devices: and Their Influences On

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© Rudolf Stierstorfer

1 BASIC CMOS PROCESS FLOW............................................................................... 3

1.1 Process steps ..................................................................................................................................................... 3

1.2 Process modules (10sf)..................................................................................................................................... 5

2 ADVANCED-CMOS PROCESS FLOW ................................................................... 10

2.1 Front end of line – FEOL .............................................................................................................................. 10

Technology – Advanced CMOS logic 1 / 37 14.05.2008

2.1.7.3 Liner – stress: geometry dependance................................................................................................. 27

2.2 Back end of line – BEOL ............................................................................................................................... 30

3 SUMMARY OF FEOL-EFFECTS ON DEVICES ...................................................... 31

3.2 N-Well / P-Well / Triple-Well ....................................................................................................................... 32

3.5 General guidelines.......................................................................................................................................... 32

4 DEVICE PERFORMANCE IMPROVEMENT – WHAT’S LEFT? ............................. 33

6.1 Threshhold voltage ........................................................................................................................................ 36

6.2 DIBL – drain induced barrier lowering....................................................................................................... 36

6.3 Body-Effect ..................................................................................................................................................... 37

Technology – Advanced CMOS logic 2 / 37 14.05.2008

1 Basic CMOS process flow

1.1.4 Implantation – Doping

Technology – Advanced CMOS logic 3 / 37 14.05.2008

1.1.5 Diffusion / Anneals – Activation

Technology – Advanced CMOS logic 4 / 37 14.05.2008

1.2 Process modules (10sf)

MODULE LITHO LEVEL

1.2.1 Isolation – STI

1.2.2 n-well / p-well / triple-well

Technology – Advanced CMOS logic 5 / 37 14.05.2008

N-well P-well & Triple well

1.2.5 Poly (PC)

Technology – Advanced CMOS logic 6 / 37 14.05.2008

1.2.6 Spacer 1 and Halo/Extension-Implants

N-well P- or Triple well

1.2.7 Spacer 2 and Source/Drain-Implants

silicide area silicide blocked

Technology – Advanced CMOS logic 7 / 37 14.05.2008

1.2.9 CA-Nitride liner (Stress liner) and CA

Technology – Advanced CMOS logic 8 / 37 14.05.2008

1.2.10 BEOL - possible 9 Metal layers in C45

TASK: NFET-Device – technology elements

Technology – Advanced CMOS logic 9 / 37 14.05.2008

2 Advanced-CMOS Process Flow

2.1 Front end of line – FEOL

STI stands for shallow trench isolation.

Technology – Advanced CMOS logic 10 / 37 14.05.2008

2.1.1.1 STI - Lithography

2.1.1.1.1 Lithography SEM-pictures

Technology – Advanced CMOS logic 11 / 37 14.05.2008

this is a special ‘hard mask rie’ with built-in Si-spike reduction

after STI-rie 2 liners are applied:

Technology – Advanced CMOS logic 12 / 37 14.05.2008

2.1.1.4 STI-fill and CMP

2.1.1.5 STI-stress effect

Technology – Advanced CMOS logic 13 / 37 14.05.2008

SP-Device 10/0.08 - teststructures

Technology – Advanced CMOS logic 14 / 37 14.05.2008

NFET-device performance: DEGRADATION!

~5% Ion-degradation +(~2.5% Vts-shift )

Technology – Advanced CMOS logic 15 / 37 14.05.2008

2.1.1.6 Summary STI – Hints for Designer

Avoid minimum RX (minimum width of devices) – at minimum RX effects like ‘Divot’

Technology – Advanced CMOS logic 16 / 37 14.05.2008

2.1.2 Well module (N-well, P-well, Triple-Well)

Tip: always check booleans when working with triple well!