gsi op-amp has become an industry standard today. The pin configuration and the complete Duatin-tine package gehematic circuit diagram for 741 is shown in Offset nut NC 4 (a) and (b) respectively. Since this cir. Invert ° cait is quite complex compared to MC1530, only a ¥ the qualitative analysis is taken up. Non-inverting input & output In understanding an op-amp circuit as complex ¥ Offset nul transistors), first we identify the stages ide signal gain. The input stage diff. of transistors Q,—@, and Q, - Q,. Transistors Q,, and Q,; provide the second stay sistors are in cascode (CE-CB) configuration. Two transistors fn fares (@; lene Gr one Nick iain per stage needed to achieve the adequate open-loop gain in a two stage amplifier. The transistors Q;, Q, and Q; form the active load for Q, and Q,. Transistors Q, and Q, also function as a differential amplifier for the external offset nulling signal. The emitter current oftransistors Q, and Q, can be controlled by varying a 10 kQ potentiometer that is externally ‘connected between offset null terminals as shown by dotted line in Fig. 2.34(b). Bias currents the input stage are provided by a complicated arrangement of current mirror pairs. Qyy grates a current in Q,,. This current is reflected over to Qj, (though reduced because of emitter feedback due to R,). This, in turn, generates a series current in Qy which is r across another mirror pair to Q,. The bias current of Q, and Q, is effectively driven the mirror pair Qi. and Q,,. The output of the first diff-amp is taken at the junction of a Ba Ge (point x» Meee 2! asa “oes symmetry amplifier. The output at this proportional differenti ut signal. The output is now amplified by stage consisting of transistor Q,, and Q,; in flaitingion connection. eet output of common-collector-amplifier formed by Qi and Ry drives the CE-amplifier of Qi, Ry =e me ert current load Qs The output of CE-amplifier is a bias fortra nsistors as QJ ee * Gi “a Qs form a current mirror and supply transistors Qr7, he ork consisting of transistors Qi», Qyy and voltage level See shifting the voltage output of @,; by a fixed amount on stage Yormed by @,, and Qyp, The level shifter network stage in the linear region. The transistors Q,, and Q,, also Qeo by two diode drops and thus temperature compensate Qu. performs two functions, It serves as a buffer between feedback to Qs. The final output is taken at the itary pair operates so that depending upon the transistors @,, or Qys is conducting at any time. With no off, resulting in a low quiescent current drain in the Fig. 2.34 (a) Pin configuration % , protect the circuit by limiting current to the ou! Poad) current exceeds the safe limit, the voltage dvon Qs and Qs, which in turn makes Q,5 on. This