8085AH/8085AH-2/8085AH-1 8-BIT HMOS MICROPROCESSORS, 1 Single +5V Power Supply with 10% | On-Chip System Control Voltage Margine Cycle Status Information Available for = 3 MHz, 5 MHz and 6 MHz Selections Large System Control Avaliable 1 Four Vectored Interrupt inputs (One Is Non-Maskable) Plus an 8080A- 1 20% Lower Power Consumption than 085A for 3 MHz and 5 MHz Compatibie interrupt = 13 ns Instruction Cycle (@0s5AH); 0.8 SetlalIn/Serlal Out Port 13 (@085AH-2); 0.67 1.8 (008SAH-1) 1 Decimal, Binary and Double Precision 100% Software Compatible with 80808 Arithmetic. '= On-Chip Clock Generator (with External Direct Addressing Capability 1o 64K Crystal Le or RC Networs) Bytes of Memory 1 Available in 40-Lead Cerdip and Plastic Packages ‘The Intel 8085AH is a complete &-bt parallel Central Processing Unit (CPU) implemented in N-channol U to relinquish the bus when sts through with by floating tho Adcross and Data Busos. SYSTEM INTERFACE “Tho 8085AH family incuces memory components, which are directly compatibie to the 8085AH CPU. For oxamplo, a systom consisting of he tree chips, BOB5AN, 875SH and B7S5A wal have the Tolowing features: * 2k Bytos EPROM * 256 Bylos RAM 1 Timer/Counter + 4 eit /0 Ports #1 6bit/0 Port + 4 Inerupt Levels + Serial n/Serial Out Ports‘This minimum system, using the standard 1/0 tech nique Is a8 shown in Figue 7, In addition fo the standard 1/0, the mamery mapped 170 olters an efficient 1/0 addressing techmaus, ‘Wath ths technique, an area of memory address. space is assignod for I/O address, thoreby, using ‘8085AH/B0B5AH-2/B085AH-1 shows the system configuration of Memory Mappec 10 using e095AH “The 80@SAH CPU can also interface withthe stan- dar memory that doos not have the muliploned ad- ‘ross/data bus. It will rogue a simple Bit atch as shown in Figure 9. the memory adéress for 7 manipulation, Figure 8 0h Thy oman Spt Comecon Figure 7. 8085AH Minimum System (Standard /0 Technique)Aoasareosati2/e00sai-1 intel. “ry : oo # Figure 8. 0006 Minimum System (Memory Mapped 1/0)‘8085AH/B0B5AH-2/B085AH-1 IT [Ww ves AW ce Figure 9, 085 System (Using Standard Memories)‘8085AH/8085AH-2/8085AH-1 BASIC SYSTEM TIMING ‘The 8085AH has @ muliploxed Data Bus. ALE is Used as a strobe to sample the lower Bis of ace ‘fess on the Data Bus, Figure 10 shows an insruc- tion fotch, memory road: and 1/0 write cyclo (as would occur during processing of the OUT instuc- tion) Note that curing the I/O write and read cyclo that the 1/0 port adress is copied on both the up- er and lower hal ofthe address. ‘There are seven possible types of machine cycles Which of these seven takes pace is defines bythe status of the vee slalus lines (IO/M, Sy, Sq) and intel. {he tinge contol signals (RD, WR, and INA). (See “Table 2.) The slaus lines can bo used as advanced controls (ior device solecton, for example), since thay become active at the 7 stat, at the outset of jeach machine cycle. Control ines FO and WR be- come active later, al the time whon the transfer of Galas 0 take piace, so aro used as command ines. ‘A mactine cycle normally consists of three T stats, ‘with the exception of OPCODE FETCH, whicn ner mally has other four or six T states (unless WAIT or HOLD states aro forced by the rocsipt of READY or HOLD inputs). Any T state must be one of ton poss- bie stats, shown in Table 4 ‘Table 3, 9085AH Machine Cycle Chart Machine Cycte ao et voi] sr [50 Ro] wm | rR cone FaTG_08 oftspef ts TORY ADO) op pepe tts eR WATE Ca oper pets VOREAD 008) oppo vownT= fom cette pe ts AonLEDEE Sam ey Lp Lf. eusme eo | © |*fofr| +] + Stor rere} (a) a [als maar’ | we fo] [el tel 3 Tile AoA Matin Sa chr vacine [Sts Dine co State | $1,80 | 10/M | Ag-Ars | ADs~AD; | RD, WR | INTA | ALE nx pe | pte mfx peo Twatr x x x x x o oo a tea [oc De [sss 8 Tow Dx Ds [sss be LS “ae ot gona dung 2 or ree HOt hg TT Bk mt 10intel. Aoasaueonsana/e0esai Figure 10. 8085AH Basie System Timing