IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.

6, JUNE 2011 1741

DC-Link Ripple Current Reduction for Paralleled

Three-Phase Voltage-Source Converters
With Interleaving
Di Zhang, Member, IEEE, Fei (Fred) Wang, Fellow, IEEE, Rolando Burgos, Member, IEEE,
Rixin Lai, Member, IEEE, and Dushan Boroyevich, Fellow, IEEE

Abstract—This paper presents a complete analysis of study-

ing the impact of interleaving on the ripple current in the dc-
side passive components of paralleled three-phase voltage-source
converters (VSCs). The analysis considers the effects of different
pulsewidth modulation scheme, the modulation index, the inter-
leaving angle, and the power factor or displacement angle. In the
analysis, the rms value of the total ripple current in the dc-side is
used as figure of merit and calculated in the frequency domain. The
results obtained show that all of the factors considered can strongly
affect the rms value one way or another. Based on the analysis,
the interleaving angle-optimization method is shown to minimize
the rms in different cases. The effect of circulating currents on the Fig. 1. Definition of interleaving angle (κ) showing specifically the case of
ripple currents in the dc-side passive components is also taken into two converters.
consideration to perform a more accurate analysis. All the anal-
ysis is based on an example system containing two VSCs, but the
proposed analysis method in the frequency domain can be easily (VSCs) are very popular because of their many advantages, such
expandable for multiple paralleled VSCs. Experimental results are as low harmonics, high power factor, and high efficiency [1]. The
used to verify the analysis conducted. parallel operation of VSCs has also become a popular choice
Index Terms—Harmonic current, interleaving, parallel, ripple in order to achieve ever-increasing power ratings [2]–[10]. In
current, voltage-source converter (VSC). addition, parallel VSCs can also increase the system reliability
through so-called N +1 configuration [11]–[14], as well as allow
for the easy and flexible implementation of power management
I. INTRODUCTION at the system level [15].

I N AC medium and high-power applications, three-phase
pulsewidth modulation (PWM) voltage-source converters
Manuscript received April 16, 2010; revised July 10, 2010, and September
13, 2010; accepted September 17, 2010. Date of current version July 22, 2011.
This work was supported by the National Science Foundation under Award
EEC-9731677. This paper was presented at the 2008 IEEE Applied Power
Electronics Conference (APEC), Austin, TX, March 2008. Recommended for
publication by Associate Editor V. Agarwal.
D. Zhang and R. Lai were with the Center for Power Electronic Systems, Vir-
ginia Polytechnic Institute and State University, Blacksburg, VA 24060 USA.
They are now with the Electronic Power Conversion Laboratory, Global Re-
search Center, General Electric Company, Niskayuna, NY 12309 USA (e-mail:
zd06@vt.edu; lairixin@vt.edu).
F. (Fred) Wang was with the Center for Power Electronic Systems, Virginia
Polytechnic Institute and State University, Blacksburg, VA 24060 USA. He is
now with the University of Tennessee and Oak Ridge National Lab, Knoxville,
TN 37996 USA (e-mail: fred.wang@utk.edu).
R. Burgos was with the Center for Power Electronic Systems, Virginia Poly-
technic Institute and State University, Blacksburg, VA 24060 USA. He is now
with the Electrical and Computer Engineering Department, North Carolina State
University, Raleigh, NC 27695 USA (e-mail: rburgos@ieee.org).
D. Boroyevich was with the Center for Power Electronic Systems, Virginia
Polytechnic Institute and State University, Blacksburg, VA 24060 USA. He is
now with the Bradley Department of Electrical and Computer Engineering, Vir-
ginia Polytechnic Institute and State University, Blacksburg, VA 24060 USA
(e-mail: dushan@vt.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2010.2082002
0885-8993/$26.00 © 2011 IEEE
In a VSC system, dc-link capacitors with certain capacitance
are required to provide energy storage function to maintain the
dc-link voltage. In addition, these capacitors must also handle
the dc-link ripple currents as a result of PWM switching. Very
often, the dc-side passive components such as dc-link capaci-
tors are usually the weakest points, as such determine the system
reliability and lifetime [16]. This is mainly caused by thermal is-
sues related to the ripple current flowing through the capacitors.
To mitigate this problem, more capacitors can be paralleled to
reduce the ripple current stress in them, at the expense of an in-
crease system cost and volume. In fact, when the system current
rating is increased by paralleling VSCs, the dc-link capacitors
indeed become one of the most bulky components in the system.
It is then apparent that the benefits of reducing the ripple current
in a system of paralleled VSCs is threefold, namely, increased
lifetime, reliability, and power density.
As mentioned earlier, the use of interleaving in parallel three-
phase VSCs can help reduce the ripple current flowing through
the dc-link capacitors. This PWM technique interleaves or phase
shifts the converter switching cycles, which is done by phase
shifting the gate control signals of the converters [17], [18].
To represent such phase-shifted switching cycles, the interleav-
ing angle κ (0 ≤ κ ≤ 2π) is defined in Fig. 1. In the case of
carrier-based PWM, this is done by the actual phase shifting of
the carrier signals for each converter, or in the case of space
1742 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

vector modulation (SVM), by interleaving their switching cycle

clock. As a result, interleaving has as main benefit the reduction
of harmonic currents at the input and output terminals of the
converters, i.e., at the dc capacitor and ac boost inductors.
So far, several papers have shown the benefits of interleaving
in paralleled three-phase VSC systems [19]–[21]. Asiminoaei
et al. [19], [20] shown the reduction of dc-side ripple current
in two paralleled VSCs for an active power filter application.
Miller et al., using double-integral Fourier analysis method, the-
oretically proved the dc-side ripple current cancellation effect of
interleaving for N paralleled three-phase VSC systems. A sym-
metric interleaving angle was used in [19]–[21], which means
that the interleaving angle κ was fixed to 2π/N for N paral-
leled three-phase VSCs system. The authors in [22] and [23]
discussed the effect of interleaving with asymmetric κ on har- Fig. 2. Sample converter system architecture with two paralleled VSCs.
monic currents reduction, and an example was shown in [24].
However, the effects discussed in the earlier study were mostly
Fig. 2. There is no electrical isolation in the system, such as
on the ac-side. There is still—to the best knowledge of the
transformer or isolated dc buses.
authors—no discussion or analysis on the selection criteria of κ
As shown in [26], the switched output voltage of the phase leg
to fully utilize the benefit of interleaving in the reduction of the
between the ac terminal (e.g., point A1 ) and the dc-link midpoint
dc-side ripple currents.
(N ), v A1N , can be decomposed into different harmonic com-
Furthering past study, this paper presents a comprehensive
ponents. The frequencies of these can be expressed as (mω c +
analysis of the impact of interleaving on the dc-side ripple cur-
nω 0 ), where ω c is the angular frequency of the carrier wave, ω 0
rents of paralleled three-phase VSCs with respect to: PWM
is the fundamental line frequency, and m and n are the carrier
scheme, the modulation index (M , defined as the ratio between
and baseband integer indices, respectively. Then, based on the
the peak value of line–line voltage to dc-bus voltage), displace-
double-integral Fourier analysis, the harmonic component for
ment angle between the fundamental frequency currents and
voltage v A1N corresponding to frequency (mω c + nω 0 ) can be
voltages (θ), and the interleaving angle (κ). In this analysis,
expressed as [26]
the rms value of total dc-side ripple currents is used as the
figure of merit. Based on the results obtained, the methods to vA1N (m, n) = Cm n ej (m θ c 1 +n θ 0 1 +θ m n ) (1)
improve the benefit of interleaving by changing the interleaving
where Cm n is the harmonic amplitude, θc1 and θ01 are the initial
angle under different operating conditions are presented, which
angles of the carrier and reference waves for VSC1, and θm n is
can be extended for an N paralleled VSC systems.
a constant value depending on the PWM scheme and operating
Specifically, Section II of this paper introduces the exam-
condition.
ple system and generally explains the impact of interleaving
For each phase leg, the switching function is defined as
on dc-side ripple currents. In Section III, the impact of different !
variables on dc-side ripple currents is explained, and the method 1, (if top switch is turned ON)
Si = (2)
to optimize the interleaving angle for the minimization of these 0, (if bottom switch is turned ON).
currents is presented. In Section IV, the impact of the circulat-
Then, from the spectrum of v A1N , the spectrum of the switch-
ing current on the dc-side ripple current is analyzed. To verify
ing function of phase A in VSC1 can be expressed as
the analysis conducted, experimental results are presented in
Section V. vA1N (m, n) Cm n ej (m θ c 1 +n θ 0 1 +θ m n )
SA1 (m, n) = = . (3)
Vdc Vdc
II. DC-SIDE RIPPLE CURRENTS ANALYSIS FOR INTERLEAVED The spectrum of the switching functions of other phases can
VSC SYSTEMS be calculated in a similar way as
The impact and benefit of interleaving is generally attained SB1 (m, n) = SA1 (m, n)e−j (2/3)π n (4)
through the selected harmonic current cancellation or reduc- j (2/3)π n
SC1 (m, n) = SA1 (m, n)e . (5)
tion. Consequently, the analysis in this paper will be mainly
performed in the frequency domain using the double-integral Now, in the time domain, the current on the dc-side for VSC1
Fourier analysis [26]. For the sake of clarity and simplicity, the can be expressed as
analysis and discussion will be first carried out for the example
idc1 = iA1 SA1 + iA1 SB1 + iC1 SC1 . (6)
system shown in Fig. 2, which is compounded by two paralleled
VSCs fed from a common ac bus and connected to a common Correspondingly, the spectra of idc1 can be calculated as
dc bus. In this system, the power flows from the ac source to the
F (idc1 )(m, n) = F (iA1 ) ⊗ SA1 (m, n) + F (iB1 )
load represented by a dc-link resistor. The naming conventions
for various currents and passive components are indicated in the ⊗ SB1 (m, n) + F (iC1 ) ⊗ SC1 (m, n) (7)
ZHANG et al.: DC-LINK RIPPLE CURRENT REDUCTION FOR PARALLELED THREE-PHASE VOLTAGE-SOURCE CONVERTERS 1743

where F () is a Fourier transfer function and ⊗ is the convolution

operator.
The rms value of idc1 can be calculated as
"
# ∞ ∞
#% %
rmsi d c 1 = $ i2idc1 (m, n). (8)
m =1 n =−∞

For VSC2, based on the similar analysis of VSC1

vA2N (m, n) = Cm n ej (m θ c 2 +n θ 0 2 +θ m n ) (9)
vA2N (m, n) Cm n ej (m θ c 2 +n θ 0 2 +θ m n )
SA2 (m, n) = =
Vdc Vdc Fig. 3. Harmonic components before interleaving.

(10)
−j (2/3)π n
SB2 (m, n) = SA2 (m, n)e (11)
SC2 (m, n) = SA2 (m, n)ej (2/3)π n (12)
where θc2 and θ02 are the initial angles of the carrier and refer-
ence waves for VSC2.
Since interleaving can only change the relative angle of the
carrier waveforms
θc2 = θc1 + κ
θ02 = θ01 (13)
Fig. 4. Harmonic components after interleaving.
where κ is the interleaving angle, which is defined in Fig. 1.
From (3)–(5) and (10)–(13)
switching frequency harmonics and not affect the even-order
SA2 (m, n) = SA1 (m, n)ej m κ switching frequency harmonics. The phase shifting by π/2 can
SB2 (m, n) = SB1 (m, n)ej m κ eliminate harmonics when m is (4k+2), such&√ as 2, 6, and 10,
and reduce the harmonics by 30% (i.e., 1 2 of the original)
SC2 (m, n) = SC1 (m, n)ej m κ . (14) when m is odd, and not affect other even-order harmonics [18].
Considering the even distribution of output currents in VSC1 The concept can be easily expanded to N parallel VSCs. For ex-
and VSC2 ample, the mth-order harmonic, in N paralleled VSC systems,
can always be eliminated with interleaving angle 2π/(mN).
F (idc2 )(m, n) = F (idc1 )(m, n)ej m κ
and III. SELECTION OF INTERLEAVING ANGLE

F (idc )(m, n) = F (idc1 )(m, n) + F (idc2 )(m, n)
= F (idc1 )(m, n)(1 + ej m κ )
it follows that the amplitude of the harmonic current in idc is
mκ
|F (idc )(m, n)| = 2 |F (idc1 )| (m, n) cos . (16)
2 component. A tradeoff appears then in the case, where several
When κ is 0, which means no interleaving
|F (idc )(m, n)| = 2 |F (idc1 )| (m, n).
By comparing (16) and (17), it is obvious that interleaving
can reduce the amplitude of harmonic currents in idc . Also from
(16), it can be seen that, if κ is set to be π/m, i.e., interleav-
ing the carrier wave of VSC2 by 1/mth of the switching cycle
keeping the carrier wave of VSC1 unchanged, F (idc )(m, n)
will be zero. In general, when certain κ is used, the relation-
ship between the two vectors representing the two harmonic
components at (mω c + nω 0 ) in idc1 and idc2 can be shown as
illustrated in Figs. 3 and 4. Especially, for the sample system
shown in Fig. 2, the phase-shifting π can eliminate all odd-order
The objective of the selection of the interleaving angle is to
minimize the rms value of the total ripple current in idc , which
(15) is used as the figure of merit in this paper. From Section II, it
follows that different interleaving angles can eliminate different
harmonic currents. It is straightforward then that the interleaving
angle should be selected to eliminate the dominant harmonic
harmonic components are dominant. As a result, the interleaving
angle should be selected based on the spectrum of the harmonic
(17)
currents in idc under different operating conditions, such as
PWM schemes, power factor, modulation index, and the number
of paralleled VSCS in the system.
To explain the effects of different variables in the selection
of the interleaving angle, two examples are used. In the first
one, an analytical analysis is used for simple sinusoidal PWM
(SPWM), and numerical analysis is used for the more complex
SVM scheme. In these two examples, the system shown in
Fig. 2 is used, which means that only two paralleled VSCs are
considered. The method used can be extended and used for N
paralleled VSCs system.
1744 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

The method to calculate the spectrum of the harmonic currents ponents at ±ω 0 , can be expressed as in the matrix in which
in idc has been introduced in several papers [21], [25], but the three components, from left to the right, are the harmonic
the impact of different variables, especially power factor and components at – ω 0 , 0, and ω 0 .
modulation index, on the harmonics components distribution
are not discussed much. Since such impact is the key to select ) *
iA1 −j θ iA1 j θ
interleaving angle, the process to obtain the spectrum of the F (iA1 ) = e 0 e
2 2
harmonic currents in idc is explained in detail in this paper. )
iB1 −j (θ −(2/3)π ) iB1 j (θ −(2/3)π )
*
F (iB1 ) = e 0 e
2 2
) *
A. Analytical Analysis for SPWM iC1 −j (θ +(2/3)π ) iC1 j (θ +(2/3)π )
F (iC1 ) = e 0 e (19)
2 2
To clearly explain the effect of different variables on the
rms value of the total dc-side ripple analytically, SPWM is
assumed to be the PWM scheme first. For SPWM, the harmonic where θ is the displacement angle.
components of the switching functions can be calculated as Together with (18), the spectrum of idc1 can be calculated
follows [26]: from (7), if the ac-side currents are balanced as shown in (20)
at the bottom of this page, where I p eak is the peak value of the
' √ ( fundamental component of the ac-side currents.
4 π 3M ) π*
SA1 (m, n) = Jn m sin (m + n) Since |F (idc )(m, n)| = 2 |F (idc1 )| (m, n) cos(mκ/2), if the
πm 4 2 dominant harmonic component is located at mth switching fre-
quency, the interleaving angle should be selected to π/m to
× ej (m θ c 1 +n θ 0 1 +θ m n ) (18) eliminate it. From (20), the amplitude of the harmonic compo-
nent of idc1+at mω√c + nω 0, is determined + by√a pair of,compo-
where M is the modulation index (0 < M < 1), m is the nents Jn −1 m(π 3M/4) and Jn +1 m(π 3M/4) , which
carrier index variable, n is the baseband index variable, and also determine the amplitude of the harmonic components at
Jn (x) is a Bessel function. In this paper, since only the harmonic mω c ± nω 0 , as shown in (18). From [26], the highest harmonic
components are studied, m ≥ 1. components in (18) are located around the switching frequency
To simplify the analysis, only the fundamental component (m = 1, n = ±2) and twice its value (m = 2, n = ±1); therefore,
in the ac-side currents is considered first. In fact, even though the possible dominant harmonic components may be located at a
the ac-side currents contain fundamental and harmonic com- given frequency represented as a pair of (m, n), e.g., as (1, −3),
ponents, the contribution of the ac-side harmonic currents on (1, −1). (1, 1), (1, 3), (2,−2), (2, 0) and (2, 2), which are related
the dc-side ripple current is negligible compared with that of to the dominant components of the ac-harmonic components.
the ac-side fundamental current, if the total harmonic distortion Also, from (20), only when n is multiple of three, the ampli-
of the ac-side current is within reasonable levels. Experimental tude of such harmonic component is not zero; therefore, only
results will prove this assumption. Some special ac-harmonic (1, −3), (1, 3), and (2, 0) may be the dominant components.
currents, which are circulating currents related to interleaving, For unity power factor operation, θ is 0, that is in (21), as
will be analyzed in Section IV in order to focus the analysis shown at the bottom of this page.
hereinafter. For some special applications where the harmonic The amplitude of the harmonic components is then
currents are high in magnitude compared to the fundamental
current, the method to calculate the rms value of idc1 is still cor-
rect, but the spectra of the ac-side currents cannot be simplified |F (idc1 )(m, n)|
- ' √ ( ' √ (-
in that case and the analytical analysis will be more complex.
3Ip eak -- π 3M π 3M --
As mentioned earlier, the spectrum of the fundamental com- = -Jn −1 m − Jn +1 m -.
πm - 4 4 -
ponent of the ac-side currents, which only contains two com-
(22)

. / 01 2 ' √ (
)
Ip eak j (m θ c 1 +n θ 0 1 +θ m n ) 2 π 3M π * −j θ
F (idc1 )(m, n) = e 1 + 2 cos n π Jn −1 m sin (m + n − 1) e
πm 3 4 2
' √ ( 3
π 3M ) π * jθ
+ Jn +1 m sin (m + n + 1) e (20)
4 2
3Ip eak j (m θ c 1 +n θ 0 1 +θ m n )
F (idc1 )(m, n) = e
πm
2 ' √ ( ' √ ( 3
π 3M ) π* π 3M ) π*
× Jn −1 m sin (m + n − 1) +Jn +1 m sin (m + n + 1) . (21)
4 2 4 2
ZHANG et al.: DC-LINK RIPPLE CURRENT REDUCTION FOR PARALLELED THREE-PHASE VOLTAGE-SOURCE CONVERTERS 1745

Fig. 5. Spectrum of dc-side ripple current when power factor is 1. (a) M = 0.9. (b) M = 0.5.

Since the Bessel function is an odd function As a result, F (idc1 )(2, 0) will be zero and F (idc1 )(1, 3) and
- ' √ (- F (idc2 )(1, −3) become the dominant components, and π should
3Ip eak -- π 3M -- be used as interleaving angle in order to eliminate the second-
|F (idc1 )(2, 0)| = -J1 - (23)
π - 2 - order switching harmonic components.
- ' √ ( When system power factor is increased from 0 to 1, the in-
3Ip eak -- π 3M terleaving angle will also vary from π to π/2 accordingly. In
|F (idc1 )(1, 3)| = |F (idc1 )(1, −3)| = -J2
π - 4 other words, a tradeoff in the reduction of the harmonic compo-
' √ (- nents around the switching frequency and twice the switching
π 3M -- frequency is expected. Also, from (24), M is always a key vari-
−J4 - (24)
4 - able to determine the amplitude of the harmonic components;
therefore, M also affects the impact of interleaving.
and since J 2 () is very close to J 4 (), the amplitude of F (idc1 )(1, 1) Numerical Analysis for SVM: For more complex PWM
3) and F (idc1 )(1, −3) are very small. Therefore, F (idc1 )(2, 0) is schemes, it is not easy to carry out the analytical analysis, but
the dominant component and π/2 interleaving angle should be an alternative numerical approach can be used to conduct it.
used, which can eliminate the second-order switching harmonic Specifically, Cm n and θm n can be obtained as in (29) from the
components as shown in Section II. double-integral Fourier analysis [26]. Note that Cm n is only a
For zero-power-factor operation, θ is π/2, and function of the PWM scheme and the modulation index M . An
3Ip eak j (m θ c 1 +n θ 0 1 +θ m n ) example for central aligned SVM is given in the Appendix (see
F (idc1 )(m, n) = e Table A.I) [27]. Assuming the same carrier and symmetrical ref-
πm
2 ' √ ( erences (120◦ apart) for the three phases for the converter VSC1,
π 3M ) π*
× Jn −1 m sin (m + n − 1) its phase B and C voltage harmonic v B 1 N (m, n), v C 1 N (m, n)
4 2 will be similar to (1), with identical Cm n and θm n , but θ0 will
' √ ( 3 be displaced by 120◦
π 3M ) π*
−Jn +1 m sin (m + n + 1) . 4 4
4 2 Vdc π x f j (m x+n y )
Cm n ej θ m n = e dxdy. (29)
2π 2 −π x r
(25)
The integral limits for the example SVM system are also
The amplitude of the harmonic components is then given in Table A.I in the Appendix.
- ' √ (
3Ip eak -- π 3M Based on the same analysis method presented in Section III,
|F (idc1 )(m, n)| = -Jn −1 m the spectra of ripple currents on dc-side under different condi-
πm - 4
tions are shown in Figs. 5 and 6. In these figures, the y-axes are
' √ (- the amplitudes of the harmonic components normalized based
π 3M --
+Jn +1 m -. (26) on the peak value of the ac-side fundamental current. The x-
4 - axes are the orders of switching frequencies. From Fig. 5, when
Since the Bessel function is an odd function the power factor is high, the dominant harmonic component
is located at the second- and sixth-order harmonic, which can
|F (idc1 )(2, 0)| = 0 (27) be eliminated by phase shifting by π/2. From Fig. 6, when the
power factor is low, the dominant component is located at the
|F (idc1 )(1, 3)| = |F (idc1 )(1, −3)|
- ' √ ( ' √ (- first- and third-order harmonics, which can be eliminated by
3Ip eak -- π 3M π 3M -- phase shifting by π. The conclusion then is similar to that of the
= -J2 + J4 -. SPWM case, a tradeoff.
π - 4 4 -
The impact of the interleaving angle, modulation index, and
(28) displacement angle on the rms value of the total dc-side ripple
1746 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

Fig. 6. Spectrum of dc-side ripple current when power factor is 0. (a) M = 0.9. (b) M = 0.5.

Fig. 8. Impact of interleaving angle on dc-side ripple currents for low-power-

Fig. 7. Impact of interleaving angle on dc-side ripple currents for high-power- factor system for SVM.
factor system for SVM.

current are presented in Figs. 7 and 8. In these plots, the z-axes

are the rms values of the total dc-side ripple currents (considered
up to 20th-order of switching frequency in this paper) normal-
ized based on the peak value of the ac-side fundamental current.
The x- and y-axes are the modulation index and displacement
angle, respectively. The impact of three interleaving angles (0,
π/2, and π) is shown and compared in three different planes, as
illustrated.
Fig. 7 shows that when the power factor is high, θ is close
to zero, π/2 interleaving is much better than π. In fact, π can
barely reduce the rms value of dc-side ripple currents. On the
contrary, π/2 can help especially when the modulation index
is close to 0.5, which without interleaving is usually the worst
Fig. 9. Interleaving angle for minimized dc-side ripple current. (M = 0.85).
case. Fig. 8 on the other hand depicts the same plot as Fig. 7,
but viewed from a different direction in order to see better, the
effect on cases with low power factor. As seen in Fig. 8, when angle changes from π/2 to π from 1 to 0, and modulation index
power factor is low, π phase shifting is better than π/2 phase is 0.85, which is also similar for SPWM.
shifting, which also agrees with the analytical results. The impact of interleaving angle has a high dependency on
Another point of view is when the modulation index is fixed the specific PWM scheme. For minimum loss or discontinuous
as in rectifier operation. In this case, the optimized interleaving SVM (DPWM) [28], the spectrum of idc can be calculated using
angle to minimize the rms value of the dc-side ripple current can (29). The double Fourier integral limits for DPWM are given
be determined, and it is highlighted by the thick curve in Fig. 9. in the Appendix (Table A.II). In a similar way, for DPWM,
Fig. 9 shows, for constant load, how the optimized interleaving the impact of the interleaving angle, modulation index, and the
ZHANG et al.: DC-LINK RIPPLE CURRENT REDUCTION FOR PARALLELED THREE-PHASE VOLTAGE-SOURCE CONVERTERS 1747

duce additional common-mode (CM) circulating current [18],

which could end up being the dominant circulating current in
the system. These currents are analyzed in this section as they
can impact the accuracy of the prediction of the ripple currents
when carrying out the converter design.
In this paper, the circulating currents for VSC1 are defined as

icir A1 = 0.5(iA1 − iA2 ) (30)

icir B1 = 0.5(iB1 − iB2 ) (31)
icir C1 = 0.5(iC1 − iC2 ). (32)

Because of the characteristic of circulating currents

icir A2 = −icir A1 (33)

icir B2 = −icir B1 (34)
icir C2 = −icir C1 . (35)
Fig. 10. Impact of interleaving angle on dc-side ripple current for high-power-
factor system for DPWM. As a result, in the time domain it follows that

idc cir = icir A1 SA1 + (−icir A1 ) SA2 + icir B1 SB1

+ (−icir B1 ) SB2 + icir C1 SC1 + (−icir C1 ) SC2 .

(36)

Without interleaving

SA1 = SA2 (37)

SB1 = SB2 (38)
SC1 = SC2 (39)

which replacing in (36) yields

idc cir = 0. (40)

As a result, the system circulating current cannot generate any

Fig. 11. Impact of interleaving angle on dc-side ripple current for low-power-
factor system for DPWM.
power-factor angle on the rms value of the dc-side ripple current
can also be calculated numerically. Figs. 10 and 11 show the
corresponding plots to Figs. 8 and 9, which show that π is better
than π/2 in most of the cases for DPWM, which is an opposite
result when compared to SVM.
IV. IMPACT OF CIRCULATING CURRENT
Other than the output ac-side currents, there are also circu-
lating currents in the system that may also generate dc-side
ripple currents. Interleaving can make the magnitude of these
currents worse, if no precautions are taken, since it can intro-
ripple current in the dc capacitor without interleaving. On the
contrary, interleaving will indeed generate it, and its spectrum
can be calculated as shown in the frequency domain as follows
in (41), shown at the bottom of this page.
From [26], the dominant component in F (S) is located at the
switching frequency, which is a CM component so that S A1 (1,
0) = S B 1 (1, 0) = S C 1 (1, 0). As a result, the convolution be-
tween the differential-mode component in icir A1 , icir B1 , and
icir C1 , and the CM harmonic components in (41) are zero. Only
the CM components in icir A1 , icir B1 , and icir C1 are, therefore,
analyzed in this paper. And furthermore, only the dc-component
and the circulating current at the switching frequency are con-
sidered, since they are the dominant circulating currents in the
system. The experimental results will verify the validity of such
assumption.
The dc-component in the circulating current can be caused
by the sampling error or other nonideal experimental condition.

F (idc cir )(m, n) = F (icir A1 ) ⊗ F (SA1 ) + F (icir B1 ) ⊗ F (SB1 ) + F (icir C1 ) ⊗ F (SC1 )

− F (icir A2 ) ⊗ F (SA2 ) − F (icir B2 ) ⊗ F (SB2 ) − F (icir C2 ) ⊗ F (SC2 ). (41)
1748 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

Fig. 13. Interphase inductor.

Fig. 12. Schematic of the experimental setup.

For such dc-component, (41) can be simplified to

F (idc cir )(m, n) = 2 (icir A1 × F (SA1 ) + icir B1 × F (SB1 )
+icir C1 × F (SC1 )) . (42)
It is apparent then that the dominant harmonic current related
to the dc circulating current is located at the switching frequency.
For CM circulating currents at the switching frequency, the
spectrum contains two components located at +ω c and −ω c .
As a result, the convolution between such circulating current
and the CM harmonic component at the switching frequency
contains two components located at dc, and at twice the switch-
ing frequency.
Since it is hard to predict the amplitude of the circulating
current, especially the dc circulating current, the analyses of the
previous sections did not consider the effect of the circulating Fig. 14. Waveform of iA , id c 1 , id c 2 , and id c when M = 0.5, θ = 0, and
κ = 0◦ .
current, specifically in the calculation of the rms value of the
total dc-side ripple current. Such simplification can naturally
The experimental setup comprised: two six-pack insulated
introduce a certain relative error between the experimental and
gate bipolar transistor (IGBT) intelligent power modules from
analytical results. Furthermore, even though the amplitude of
Fuji (6MBP20RH060), implementing the power stage of the
such dc-side harmonic currents is much smaller than the har-
two VSCs, one common digital signal processing (DSP)-FPGA
monic currents at the same frequency caused by the fundamental
digital controller, three interphase inductors as shown in Fig. 13,
current, their contribution to the rms value of the total dc-side
and a Helionetics three-phase ac power supply used as an ideal
ripple current can be considerable, and be observed when the
three-phase voltage source. As discussed earlier, the leakage
ripple currents related to the output fundamental frequency cur-
inductance of the interphase inductor Lleak was used as ac boost
rents have been reduced by interleaving. As such, the use of
inductor (320 µH), and the main inductance Lip was used to limit
interleaving is seen to augment the relative effect of the dc cir-
the circulating current (3 mH). The dc voltage was 250 V, and the
culating current. This will be verified in Section V.
fundamental and switching frequencies were chosen as 60 Hz
and 10 kHz, respectively. The rms value of the fundamental
V. EXPERIMENTAL RESULTS current on the ac-side was about 8 A. To verify the case with 0.9
The experiment is designed to verify three key points in the modulation index, an ac line voltage of 90 V was used. A 50-V
aforementioned analysis. First, that the impact of the interleav- ac-line voltage was used to verify the case with 0.5 modulation
ing angle has a high relationship with the system power factor. index. Two PWM schemes were used in the experiment, central
Second, that the PWM scheme can also affect the selection of aligned SVM and DPWM. When DPWM is used, the circulating
interleaving angle. And third, that the effect of the circulating current control methods proposed in [29] and [30] were used.
current on dc-side ripple current can be observed when inter- For the unity power factor case, 30-Ω and 52-Ω loads were used
leaving is applied. for the 0.9 and 0.5 modulation index cases separately in order
In the experiment, the rectifier configuration in Fig. 12 was to keep the ac-side fundamental current constant.
used whose power factor can be controlled. To limit the circulat- Figs. 14 and 15 show the experimental results when central
ing current on the ac-side efficiently, an interphase inductor was aligned SVM is used. In this case M is 0.5, the displacement
used [18]. Also, the function of the boost inductor in Fig. 12 was angle is 0, and κ is 0 and π/2. From these two figures, it is
realized by the leakage inductance of the interphase inductors. clear that π/2 interleaving can reduce the dc-side ripple currents
ZHANG et al.: DC-LINK RIPPLE CURRENT REDUCTION FOR PARALLELED THREE-PHASE VOLTAGE-SOURCE CONVERTERS 1749

Fig. 17. Spectrum of id c when M = 0.5, θ = 0, and κ = π/2.

Fig. 15. Waveform of iA , id c 1 , id c 2 , and id c when M = 0.5, θ = 0,

and κ = π/2.

TABLE I
EXPERIMENTAL RESULTS ON DC-SIDE FOR SVM WHEN M = 0.5 AND θ = 0◦

Fig. 18. Waveform of iA , id c 1 , id c 2 , and id c when M = 0.9, θ = π/2, and

κ = 0◦ .

Fig. 16. Spectrum of id c when M = 0.5, θ = 0, and κ = 0◦ .

significantly barely affecting idc1 and idc2 . The experimental

data are summarized in Table I. The spectrum of idc without
and with π/2 interleaving when modulation index is 0.5 and
power factor is 1 are shown in Figs. 16 and 17. By compar-
ing the results, it is easy to see that the second-order harmonic
currents (at 2fs ) is the dominant harmonic current without in-
terleaving and can be reduced by π/2 interleaving. The reason
why the second-order harmonic current has not been eliminated
and the first-order harmonic current (at fs ) is increased a little is
the circulating current analyzed in Section IV.
Figs. 18 and 19 show the experimental results when central
aligned SVM is used, but M is 0.9, the displacement angle is π/2,
and κ is 0 and π. These results also show that π/2 interleaving can
reduce the dc-side ripple current significantly without affecting Fig. 19. Waveform of iA , id c 1 , id c 2 , and id c when M = 0.9, θ = 90, and
idc1 and idc2 , reducing it to 72%, but the interleaving angle κ = π.
1750 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

TABLE II
EXPERIMENTAL RESULTS ON DC-SIDE FOR SVM WHEN M = 0.9 AND θ = π/2

Fig. 22. Waveform of iA , id c 1 , id c 2 , and id c when M = 0.9, θ = 0, and

κ = 0.

Fig. 20. Spectrum of id c when M = 0.9, θ = π/2, and κ = 0◦ .

Fig. 21. Spectrum of id c when M = 0.9, θ = π/2, and κ = π.

of π is better as it can reduce the rms ripple to 45%, which Fig. 23. Waveform of iA , id c 1 , id c 2 , and id c when M = 0.9, θ = 0, and
matches the theoretical analysis. The spectrum of idc without κ = π.
and with π interleaving when modulation index is 0.9 and power
factor is 0 are shown in Figs. 20 and 21. By comparing the
results, it is easy to see that all odd-order harmonic currents are TABLE III
eliminated by interleaving. Because of the switching-frequency EXPERIMENTAL RESULTS ON DC-SIDE FOR DPWM WHEN M = 0.9
ac-side circulating current, the second-order harmonic current
(at 2fs ) is increased, as analyzed in section IV.
Finally, Figs. 22 and 23 show the experimental results using
DPWM, with M equal to 0.9, a power factor angle of 0, and
κ is 0 and π. From the figures, it can be clearly observed how
an interleaving angle of π can reduce the dc-side ripple current
significantly without affecting idc1 and idc2 . In fact, as detailed
in Table III, κ = π provides a better dc-ripple cancellation for
both unity- and zero-power-factor operation, reducing the ripple results without considering the effects of the circulating current
content by 54% and 47%, respectively. This is in accordance shown in Table IV. The case with SVM, M = 0.5, and θ = 0 is
with the analysis presented in Figs. 10 and 11. used as an example. This table shows a relative error between
Further, as predicted in Section IV, the circulating currents 2% and 14%. As seen, the difference is high, especially when
can generate dc-side ripple currents when interleaving is used. interleaving is used, as the ripple currents have been reduced
This can be seen by comparing the experimental and calculated significantly by interleaving as predicted in Section IV.
ZHANG et al.: DC-LINK RIPPLE CURRENT REDUCTION FOR PARALLELED THREE-PHASE VOLTAGE-SOURCE CONVERTERS
TABLE IV
EXPERIMENTAL RESULTS ON DC-SIDE
To solve this inaccuracy, the dc and CM circulating currents
at the switching frequency can be calculated from the experi-
mental data and used to correct the prediction. The recalculated
results are also listed in Table IV, which shows that the rela-
tive error between the experimental and calculated results can
be effectively reduced to a reasonable level. This also verifies
the previous assumption in the Section IV regarding the type of
currents that affect the circulating current, as only the dc and the
switching frequency CM circulating currents were considered
in the reduction of the relative error, and those are shown to be
enough to correct the results.
VI. CONCLUSION
This paper presents a comprehensive analysis of the impact of
interleaving on the ripple currents in dc-side passive components
of paralleled three-phase VSCs. The analysis considered mod-
ulation schemes, the modulation index, and both displacement
(power factor) and interleaving angles. The effects of interleav-
ing on the dc-side ripple currents were analyzed analytically
for the simpler SPWM scheme, and numerically for more com-
plex modulation schemes. The analysis results showed that the
operating conditions can highly affect the selection of the inter-
leaving angle to minimize the rms value of total dc-side ripple
current. The effects of the system circulating currents were also
presented to increase the accuracy of the analysis. The complete
analysis was verified experimentally using two 2-kW prototype
converters in parallel operation.
APPENDIX I
TABLE. A.I
DOUBLE FOURIER INTEGRAL LIMITS FOR SVM (PHASE A)
1751
TABLE. A.II
DOUBLE FOURIER INTEGRAL LIMITS FOR DPWM (PHASE A)
ACKNOWLEDGMENT
This paper has been fully revised and partially expanded prior
to its submission for consideration to the IEEE Transactions on
Power Electronics.
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Di Zhang (S’09–M’10) received the B.S. and M.S.
degrees in electrical engineering from Tsinghua Uni-
versity, Beijing, China, and the Ph.D. degree from
the Center for Power Electronics Systems (CPES),
Virginia Polytechnic Institute and State University
(Virginia Tech), Blacksburg, in 2004, 2006 and 2010,
respectively.
He is currently at Electronic Power Conversion
Laboratory, Global Research Center, General Elec-
tric Company, Niskayuna, NY. His research inter-
ests include three-phase converter design and control,
high-frequency high power motor control, and parallel converter operation with
emphasis on passive components, and harmonics minimization via interleaving.
Fei (Fred) Wang (S’85–M’91–SM’99–F’10) re-
ceived the B.S. degree from Xi’an Jiaotong Uni-
versity, Xi’an, China, and the M.S. and Ph.D. de-
grees from the University of Southern California, Los
Angeles, in 1982, 1985, and 1990, respectively, all in
electrical engineering.
From 1990 to 1992, he was a Research Scien-
tist in the Electric Power Laboratory, University of
Southern California. He joined the GE Power Sys-
tems Engineering Department, Schenectady, NY, as
an Application Engineer in 1992. From 1994 to 2000,
he was a Senior Product Development Engineer with GE Industrial Systems,
Salem, VA. During 2000–2001, he was the Manager of Electronic & Photonic
Systems Technology Laboratory, GE Global Research Center, Schenectady, NY,
and Shanghai, China. In 2001, he joined the Center for Power Electronics Sys-
tems (CPES), Virginia Tech, Blacksburg, VA as a Research Associate Professor,
where he became an Associate Professor in 2004. From 2003, he also served as
the CPES Technical Director. Since 2009, he has been a Professor and Condra
Chair of Excellence in Power Electronics with The University of Tennessee and
Oak Ridge National Lab, Knoxville, TN. His current research interests include
power electronics, power systems, controls, electric machines, and motor drives.
Rolando Burgos (S’96–M’03) received the B.S. de-
gree in electronics engineering, the Electronics Engi-
neering Professional degree, and the M.S. and Ph.D.
degrees in electrical engineering from the University
of Concepción, Chile, in 1995, 1997, 1999, and 2002,
respectively.
In 2002, he joined the Center for Power Electronics
Systems (CPES), Virginia Polytechnic Institute and
State University (Virginia Tech), Blacksburg, VA, as
a Postdoctoral Fellow, where he became a Research
Scientist in 2003, and a Research Assistant Professor
in 2005. In 2009, he joined, as a Scientist, ABB Corporate Research, Raleigh,
NC, where was a Principal Scientist till 2010. Since July 2010, he has been
an Adjunct Associate Professor in the Electrical and Computer Engineering
Department, North Carolina State University, Raleigh. His current research in-
terests include multiphase multilevel power conversion, stability of ac and dc
power electronics systems, hierarchical modeling, control theory, and the syn-
thesis of power electronics conversion systems.
Dr. Burgos is a member of the IEEE Power Electronics Society, where he is
currently a Secretary of the Committee on Simulation, Modeling and Control,
and an Associate Editor for the IEEE POWER ELECTRONICS LETTERS and the
IEEE TRANSACTIONS ON POWER ELECTRONICS.
ZHANG et al.: DC-LINK RIPPLE CURRENT REDUCTION FOR PARALLELED THREE-PHASE VOLTAGE-SOURCE CONVERTERS
Rixin Lai (S’07–M’10) received the B.S. and M.S.
degrees in electrical engineering from Tsinghua Uni-
versity, Beijing, China, and the Ph.D. degree from the
Center for Power Electronics Systems (CPES), Vir-
ginia Tech, Virginia, USA, in 2002, 2005, and 2008,
respectively.
Since 2009, he has been with the Electronic Power
Conversion Laboratory, Global Research Center,
General Electric Company, Niskayuna, NY. His re-
search interests include the passive filter design, elec-
tromagnetic interference (EMI) technology, model-
ing and control of three-phase converters, and high power density converter
development.
1753
Dushan Boroyevich (S’81–M’86–SM’03–F’06) re-
ceived the Dipl. Ing. degree from the University of
Belgrade, Belgrade, Serbia, in 1976, the M.S. degree
from the University of Novi Sad, Novi Sad, Serbia,
in 1982, and the Ph.D. degree from Virginia Poly-
technic Institute and State University (Virginia Tech),
Blacksburg, in 1986.
From 1986 to 1990, he was an Assistant Professor
and the Director of the Power and Industrial Elec-
tronics Research Program, Institute for Power and
Electronic Engineering, University of Novi Sad. He
then joined the Bradley Department of Electrical and Computer Engineering,
Virginia Tech as an Associate Professor, where he is currently an American Elec-
tric Power Professor and the Co-Director of the Center for Power Electronics
Systems (CPES). His research interests include multiphase power conversion,
electronic power distribution systems, power electronics systems modeling and
control, and multidisciplinary design optimization.
Prof. Boroyevich is a recipient of the IEEE William E. Newell Power Elec-
tronics Technical Field Award. He is president elect of the IEEE Power Elec-
tronics Society for 2011-12.