HITEC UNIVERSITY TAXILA

Department of Electrical Engineering

3rd Semester, Session-2019
PLO-4 and PLO10 Based Assignment, Fall-2020 Semester

Subject: EE-203L Digital Logic Design (LAB) February 25, 2021

Max Marks: 50

Instruction:
• Please be specific and analytical.

Implementation of 10-bit Array Multiplier (using gate level

modeling and Instantiation) in Verilog
Marks Distribution:
➢ Designing = 20% PLO-4
➢ Coding = 20% PLO-4
➢ Viva (Understanding) = 20% PLO-10
➢ Project report = 13% PLO-10
➢ Simulation = 10% PLO-4
➢ Presentation / Uniqueness =17% PLO-10

Objective:
➢ To understand use of basic building blocks in implementation of complex circuitry.

Note:
Project has to be done in Groups. Each group can have maximum of three students.

Project Details:

Extend the Given 5 bit multiplier to 10 Bit array Multiplier

8 Bit array multiplier

Constraints:
This project should be designed by following the given below constraints.
➢ Block Diagram
➢ VERILOG CODE with proper comments
➢ Simulation Waveforms
➢ Conclusion/ Lesson Learnt
➢ Problems faced
.

Project Deliverables:
• Project Report
• Code + Simulation Files
Estimated Time Frame:

Week1 Study of theoretical concepts for designing of

multiplier.
Week 2 Design of Logic and coding in Verilog

Week 3 Simulation and Verification of desired results and

submission of deliverables.

Note:
Project, Viva, Presentation & Report (or any other assessment tool as decided by the
instructor) would be marked as per defined Rubrics.