COP888

Understanding and Eliminating EMI in Microcontroller Applications

Literature Number: SNOA382


Understanding and
Eliminating EMI in
Microcontroller
Applications
1.0 ABSTRACT
In today’s world, with increasing numbers of both fixed and
mobile electronic devices, electromagnetic compatibility
(EMC) is becoming a critical issue. Disastrous, if not annoy-
ing, results occur if a system, subsystem or component in-
terferes with another through electromagnetic means. The
EMC problem is first explained, and then the basic theory is
presented with an explanation on how to use it to control an
EMC problem during the initial design phase. The methods
that some silicon manufacturers are using to control EMC
and how these changes affect our systems will be exam-
ined. A total system (automobile radio) will be examined in
detail to prove the effectiveness of a EMC reduced COP8TM
(8-bit microcontroller). Overall design guidelines will also be
given so that the designer can minimize EMI before it be-
comes a problem .
2.0 INTRODUCTION AND BACKGROUND
Electromagnetic Interference with Powered
Wheelchairs
August 26, 1994
FDA is receiving inquiries about reports that electromagnet-
ic interference (EMI) can cause some power-driven wheel-
chairs and scooters to move unexpectedly. The agency has
investigated this matter and determined that EMI can cause
unexpected movement in some power-driven wheelchairs
when they are turned on. Not all brands and models of pow-
er wheelchairs and scooters have this problem. Some have
greater immunity levels than others that may protect against
EMI. Common sources of EMI include cellular phones, CB
radios, TV and radio stations, amateur (HAM) radios and
police, fire and ambulance radios.
After receiving reports of problems, FDA tested sample
wheelchairs and scooters in its laboratories and obtained
information from manufacturers and users about possible
EMI-related incidents. As a result of its review, the agency
last May asked wheelchair manufacturers to take steps to
protect powered wheelchair users from the potential haz-
ards of EMI. FDA required all firms to clearly label wheel-
chairs and scooters with the immunity level, or else state
that the immunity level is not known. It also required them to
label wheelchairs and scooters to warn users of the poten-
tial hazards of EMI. The agency also asked manufacturers
to:
1. Establish a minimum recommended immunity level of
20V per meter for all new motorized wheelchairs and
scooters. This would provide a reasonable degree of pro-
tection against the more common sources of EMI.
COP8TM is a trademark of National Semiconductor Corporation.
C1996 National Semiconductor Corporation TL/DD12857
Understanding and Eliminating EMI in Microcontroller Applications
National Semiconductor
Application Note 1050
Robin Getz
Bob Moeckel
August 1996
2. Undertake an educational campaign to inform users and
those who care for them about the risks of EMI and ways
to avoid it; and
3. Solicit reports of possible EMI incidents and continue to
monitor the full scope of the problem.
FDA first learned of a possible problem with motorized
wheelchairs from a complaint in June 1992. As a result, the
agency began testing sample wheelchairs in its laboratories.
Those tests, on several brands of power-driven wheelchairs
and scooters, revealed that mostÐbut not allÐof those
sampled were susceptible to interference at various radio
frequencies. In some tests, the brakes released. In others,
the wheels moved uncontrollably. Sometimes both occurred
at once. The extent to which this happens in actual use is
not known. In early 1993, FDA began inspecting facilities of
all domestic and foreign motorized wheelchair and scooter
manufacturers to gather information on the problem. The
agency reviewed warranty and complaint files and looked at
any manufacturing practices that could contribute to this
type of problem. The inspections revealed numerous com-
plaints about erratic, unintentional wheelchair movement,
sometimes resulting in injuries. It is unclear, however, exact-
ly what caused the chairs to move in those cases. In addi-
tion to EMI, unexpected movement can be caused by failure
of an electronic component or by user error.
In May 1993, FDA sent letters to all U.S. manufacturers ask-
ing them to provide any information they had about possible
problems with radio wave interference, including com-
plaints, reports of injuries and studies on power-driven
wheelchairs. In July 1993, the agency alerted consumer
groups that represent wheelchair users about the possible
problem and requested similar information. An estimated
10,000 motorized wheelchairs and 50,000 motorized scoot-
ers are sold annually in this country.
ÐFDA Report, August 1994
The control and minimization of EMC is a technology that is,
out of necessity, growing rapidly. Manufacturers and regula-
tory agencies have made efforts to control this problem but
the issue of meeting these ever tightening specifications is
left to the system designer. EMC can no longer be a fix,
designed in at the last moment, but must be a directed effort
between the circuit designer, layout engineer, software engi-
neer and purchaser. This paper will examine what can be
done to reduce the chance of having a product fail EMC
approval.
AN-1050
RRD-B30M106/Printed in U. S. A. http://www.national.com
 2.1 The EMC World Map TABLE II. List of Designer Efforts
Before jumping into the midst of the EMC design methods to Reduce EMI Emissions
used, it is best to gain an understanding of the problem Method Complexity Cost Time
situation and review or learn applicable electromagnetic
(EM) theory. To begin, look at what I call the map of the 1. Revise PCB Layout Medium Low High
EMC world, Table I. The EMC problem is between an emis- 2. Add Components Medium Medium Medium
sion culprit and susceptible victim which are coupled (Filters)
through a means, either radiation through space or conduct-
ed through wires (Figure 1) . We can map out the EMC prob- 3. Change Crystal High Low High
lem cases with columns headed by radiation and conduc- Frequency
tion, and rows headed by emission and susceptibility, to get
4. Rewrite Software High Low High
four cases abbreviated as RE, CE, RS, CS.
5. Add Shielding Low High Low
TABLE I. ElectroMagnetic Compatibility Map
6. Relocate PCB Low Low Low
Radiation Conduction
7. Change IC Supplier High Medium Medium
Emission RE CE
8. Fail EMC High High High
Susceptibility RS CS
QualificationÐDon’t
Sell Product
2.2 What Designers Do Upon A Discovery of an EMC
Problem
Typically, the first time system designers realize that they 3.0 DESCRIPTION OF NOISE
have a RE problem is after the prototype system has been
3.1 ElectroMagnetic Interference
built and evaluated. Instead of being close to market re-
lease they now find themselves applying costly and often EMI is a form of electrical-noise pollution. Consider the time
ineffective patches and going back into redesign. The steps when an electric drill or some other power tool jammed a
outlined in Table II are what a typical person does at this nearby radio with buzzing or crackling noise. At times it got
point. First reaction is to make the printed circuit board so bad that it prevented you from listening to the radio while
(PCB) trace length short or to upgrade to a higher cost PCB the tool was in use. Or the ignition of an automobile idling
with a full ground plane. Although most system companies outside your house caused interference to your TV picture
have experienced and good layout design rules for their making lines across the screen or even losing sync alto-
PCBs, enforcing these rules is sometimes difficult to do as gether making the picture flip. These examples are annoy-
more and more components are being packed into smaller ing but are not catastrophic.
packages on a smaller board. Layout is often subcontracted More serious, how about a sudden loss in telephone com-
and the designer may not have the necessary experience munication caused by electrical interference or noise while
and motivation, cost reduction is the goal. Next, filters (RC, you are negotiating an important business deal? Now EMI
RL, or ferrite beads) are added in hopes that this may fix the can be economically damaging.
problem. Also, the crystal frequency may be reduced by The results of EMI incidents can be even further reaching
about 2x to run the system clock at a slower rate. Software than these examples. Aircraft navigation errors resulting
may have to be rewritten to compensate for this new time from EMI or interruption of air traffic controller service and
base. Software can be redone to toggle the outputs less may be even computer memory loss due to noise, could
frequently. Shielding is added or the PCB is put into an elec- cause two aircraft to collide resulting in the loss of lives and
trically out of the way place (like hiding a monster in the property.
basement). Having exhausted their design tricks, the de-
These were just a few instances to help identify the results
signers now search other semiconductor suppliers to find a
of EMI in a familiar context. To help understand an EMI
quieter part. Finally, when all the time and money runs out
situation, the problem can be divided into three areas. They
with EMC qualification failing, the decision is made not to
are the source, the victim, and the coupling path. Secondary
market the product and everyone loses business.
categories involve the coupling path itself. If the source and
It is from this examination that we can understand that EMC victim are separated by space with no hard wire connection,
design issues have to be considered properly at the begin- then the coupling path may be a radiated path and we are
ning of the design cycle, in order to reduce complex design dealing with radiated noise. If the source and victim are con-
changes which must be done at the completion of the proj- nected together through wires, cables, or connectors, then
ect if EMC testing is failing. the coupling path may be a conducted path and we are
dealing with conducted noise. It is possible for both types of
noise to exist at the same time.

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3.2 ElectroMagnetic Compatibility
EMI or electrical noise is of world wide concern. Govern-
mental agencies and certain industry bodies have issued
specifications with which all electrical, electromechanical,
and electronic equipment must comply. These specifica-
tions and limitations are an attempt to ensure that proper
EMC techniques are followed by manufacturers during the
design and fabrication of their products. When these tech-
niques are properly applied, the product can then operate
and perform with other equipment in a common environ-
ment so that no degradation of performance exists due to
internally or externally conducted or radiated electromag-
netic emissions. This is defined as ElectroMagnetic Com-
patibility or EMC.
TL/DD/12857 – 1
FIGURE 1. EMI Situation
3.3 Inter-System EMI
For the purpose of this paper, when the source of noise is a
module, board, or system and the victim is a different and
separate module, board, or system under the design or con-
trol of a different person, it will be considered an inter-sys-
tem interference situation. Examples of inter-system inter-
ference situations could be a Personal Computer interfering
with the operation of a TV or an anti-lock brake module in a
FIGURE 2. Intra-System EMI Manifestations
3 http://www.national.com
car causing interference in the radio. This type of interfer-
ence is more difficult to contain because, as mentioned ear-
lier, the systems are generally not designed by a single per-
son. However, design methods and control techniques used
to contain the intra-system form of EMI, which are almost
always under the control of a single user, will inherently help
reduce the inter-system noise.
This paper will address problems and solutions in the area
of intra-system noise. Intra-system interference situations
occur when the sources, victims, and coupling paths are
entirely within one system, module or PCB. Systems may
provide emissions that are conducted out of power lines or
be susceptible to emissions conducted through them. Sys-
tems may radiate emissions through space in addition to
being susceptible to radiated noise. Noise conducted out
antenna leads turns into radiated noise. By the same token,
radiated noise picked up by the antenna is turned into con-
ducted noise within the system. A perfect example is a PCB
ground loop, which makes an excellent antenna. The sys-
tem itself is capable of degrading its own performance due
to its own internal generation of conducted and radiated
noise and its susceptibility to it.
Some results of EMI within a system: Noise on power lines
causing false triggering of logic circuits, rapidly changing
signals causing ‘‘glitches’’ on adjacent steady state signal
lines (crosstalk) causing erratic operation, multiple simulta-
neously switching logic outputs propagating ground bounce
noise throughout system, etc.
3.4 Coupling Paths
The modes of coupling an emitter source to a receptor vic-
tim can become very complicated. Remember, each EMI
situation can be classified into two categories of coupling,
conducted and radiated. Coupling can also result from a
combination of paths. Noise can be conducted from an
emitter to a point of radiation at the source antenna, then
picked up at the receptor antenna by induction, and re-con-
ducted to the victim. A further complication that multiple
coupling paths presents is that it makes it difficult to deter-
mine if eliminating a suspected path has actually done any
good. If two or more paths contribute equally to the prob-
lem, eliminating only one path may provide little apparent
improvement.
TL/DD/12857 – 2
 3.5 Conducted Interference
In order to discuss the various ways in which EMI can cou-
ple from one system to another, it is necessary to define a
few terms. There are two varieties of conducted interfer-
ence which concern us. The first variety is differential-mode
interference. That is an interference signal that appears be-
tween the input terminals of a circuit. The other variety of
conducted interference is called common-mode interfer-
ence. A common-mode interference signal appears be-
TL/DD/12857 – 4
tween each input terminal and a third point, the common-
FIGURE 4. Differential-Mode Interference
mode reference. That reference may be the equipment
chassis, an earth ground, or some other point.
Let’s look at each type of interference individually. In Figure
3 we show a simple circuit consisting of a signal source, VS,
and a load, RL. In Figure 4 we show what happens when
differential-mode interference is introduced into the circuit
by an outside source. As is shown, an interference voltage,
VD, appears between the two input terminals, and an inter-
ference current, ID, flows in the circuit. The result is noise at
the load. If, for instance, the load is a logic gate in a comput-
er, and the amplitude of VD is sufficiently high, it is possible
for the gate to incorrectly change states.
Figure 5 shows what happens when a ground loop is added
to our circuit. Ground loops, which are undesirable current
paths through a grounded body (such as a chassis), are TL/DD/12857 – 5

usually caused by poor design or by the failure of some
component. In the presence of an interference source, com-
mon-mode currents, IC, and a common-mode voltage, VC,
can develop, with the ground loop acting as the common-
mode reference. The common-mode current flows on both
input lines, and has the same instantaneous polarity and
direction (the current and voltage are in phase), and returns
through the common-mode reference. The common-mode
voltage between each input and the common-mode refer-
ence is identical.
TL/DD/12857–3
FIGURE 3. Simple Circuit
FIGURE 5. Common-Mode Interference
3.6 Radiated Interference
Radiated coupling itself can take place in one of several
ways. Some of those include field-to-cable coupling, cable-
to-cable coupling, and common-mode impedance coupling.
Let’s look at those types of coupling one at a time.
The principle behind field-to-cable coupling is the same as
that behind the receiving antenna. That is, when a conduc-
tor is placed in a time-varying electromagnetic field, a cur-
rent is induced in that conductor. That is shown in Figure 6 .
In this figure, we see a signal source, VS, driving a load, RL.
Nearby there is a current carrying wire (or other conductor).
Surrounding the wire is an electromagnetic field induced by
the current flowing in the wire. The circuit acts like a loop
antenna in the presence of this field. As such, an interfer-
ence current, IN, and an interference voltage, VN, are in-
duced in the circuit. The magnitude of the induced interfer-
ence signal is roughly proportional to the magnitude of the
incoming field, the frequency of the incoming field, the size
of the loop, and the impedance of the loop.

TL/DD/12857 – 6
FIGURE 6. Field-to-Cable Coupling

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Cable-to-cable coupling occurs when two wires or cables
are run close to each other. Figure 7 shows how cable-to-
cable coupling works. Figure 7a shows two lengths of cable
(or other conductors) that are running side-by-side. Because
any two conducting bodies have capacitance between
them, called stray capacitance, a time-varying signal in one
wire can couple via that capacitance into the other wire.
That is referred to as capacitive coupling. This stray capaci-
tance, as shown in Figure 7c makes the two cables behave
as if there were a coupling capacitor between them.
Another mechanism of cable-to-cable coupling is mutual in-
ductance. Any wire carrying a time-varying current will de-
velop a magnetic field around it. If a second conductor is
placed near enough to that wire, that magnetic field will in-
duce a similar current in the second conductor. That type of
coupling is called inductive coupling. Mutual inductance, as
shown in Figure 7b, makes the cables behave as if a poorly
wound transformer were connected between them.
In cable-to-cable coupling, either or both of those mecha-
nisms may be responsible for the existence of an interfer-
ence condition. Though there is no physical connection be-
tween the two cables, the properties we have just described
make it possible for the signal on one cable to be coupled to
the other. These effects, when combined are known as the
transmission line effect and have been studied and de-
scribed thoroughly in other texts.
The basic transmission line equations are derived for distrib-
uted parameters R (series resistance), G (shunt conduct-
ance), L (series inductance), and C (shunt capacitance), all
defined per unit length of line.
Either or both of the above-mentioned properties cause the
cables to be electromagnetically coupled such that a time-
varying signal present on one will cause a portion of that
signal to appear on the other. The ‘‘efficiency’’ of the cou-
pling increases with frequency and inversely with the dis-
tance between the two cables. One example of cable-to-ca-
ble coupling is telephone ‘‘crosstalk’’, in which several
phone conversations can be overheard at once. The term
crosstalk is now commonly used to describe all types of
cable-to-cable coupling.
TL/DD/12857 – 7
FIGURE 7a. Parallel Conductors
TL/DD/12857 – 9
FIGURE 7b. Inductive Coupling
TL/DD/12857 – 8
FIGURE 7c. Capacitive Coupling
5 http://www.national.com
TL/DD/12857 – 10
FIGURE 7d. Transmission Line Model
Common-mode impedance coupling occurs when two cir-
cuits share a common bus or wire. In Figure 8 we show a
circuit that is susceptible to that type of coupling. In that
figure a TL092 op-amp and a 555 timer share a common
return or ground. Since any conductor (including a PCB
trace) is not ideal, that ground will have a non-zero imped-
ance, Z. Because of that, the current, I, from pin 1 of the 555
will cause a noise voltage, VN, to develop; that voltage is
equal to I x Z. That noise voltage will appear in series with
the input to the op-amp. If that voltage is of sufficient ampli-
tude, a noise condition will result.
TL/DD/12857 – 11
FIGURE 8. Common-Mode Impedance Coupling
While not all inclusive, these coupling paths account for,
perhaps, 98% of all intra-system EMI situations.
4.0 SOURCE OF NOISE
We will look at sources of EMI which involve components
that may conduct or radiate electromagnetic energy. These
sources, (component emitters), are different from the equip-
ment and subsystems we have been talking about. Compo-
nent emitters are sources of EMI which emanate from a
single element rather than a combination of components
such as was previously described. Actually, these compo-
nent emitters require energy and connecting wires from oth-
er sources to function. Therefore, they are not true sources
of EMI, but are EMI transducers. They convert electrical en-
ergy to electromagnetic noise.
4.1 Cables and Connectors
The three main concerns regarding the EMI role of cables
are conceptualized in Figure 9. They act as (1) radiated
emission antennae, (2) radiated susceptibility antennae, and
(3) cable-to-cable or crosstalk couplers. Usually, whatever is
done to harden a cable against radiated emission will also
work in reverse for controlling EMI radiated susceptibility.
The reason for this is usually, when differential-mode radiat-
ed emission or susceptibility is the failure mode, twisting
leads and shielding cables reduces EMI. If the failure mech-
anism is due to common-mode currents circulating in the
cable, twisting leads has essentially no effect on the rela-
 tionship between each conductor and the common-mode
reference. Cable shields may help or aggravate EMI de-
pending upon the value of the transfer impedance of the
cable shield. Transfer impedance is a figure of merit of the
quality of cable shield performance defined as the ratio of
coupled voltage to surface current in X/meter. A good ca-
ble shield will have a low transfer impedance. The effective-
ness of the shield also depends on whether or not the
shield is terminated and, if so, how it is terminated.
Connectors usually are needed to terminate cables. When
no cable shields or connector filters or absorbers are used,
connectors play essentially no role in controlling EMI. The
influence of connector types, however, can play a major role
in the control of EMI above a few MHz. This applies espe-
cially when connectors must terminate a cable shield and/
or contain lossy ferrites or filter-pins.
FIGURE 9. Cables and Connectors
FIGURE 10. Diode Recovery Periods and Spikes
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Connectors and cables should be viewed as a system to
cost-effectively control EMI rather than to consider the role
of each separately, even though each offers specific inter-
ference control opportunities.
4.2 Components
Under conditions of forward bias, a semiconductor stores a
certain amount of charge in the depletion region. If the di-
ode is then reverse-biased, it conducts heavily in the re-
verse direction until all of the stored charge has been re-
moved as shown in Figure 10. The duration, amplitude, and
configuration of the recovery-time pulse (also called switch-
ing time or period) is a function of the diode characteristics
and circuit parameters. These current spikes generate a
broad spectrum of conducted transient emissions. Diodes
with mechanical imperfections may generate noise when
physically agitated. Such diodes may not cause trouble if
used in a vibration-free environment.
TL/DD/12857 – 12
TL/DD/12857 – 13
6
4.3 Power Supply Noise
Power-supply spiking is perhaps the most important contrib-
utor to system noise. When any element switches logic
states, it generates a current spike that produces a voltage
transient. If these transients become too large, they can
cause logic errors because the supply voltage drop upsets
internal logic, or because a supply spike on one circuit’s
output feeds an extraneous noise voltage into the next de-
vice’s input.
With CMOS logic in its quiescent state, essentially no cur-
rent flows between VCC and ground. But when an internal
gate or an output buffer switches state, a momentary cur-
rent flows from VCC to ground. The switching transient
caused by an unloaded output changing state typically
equals 20 mA peak. Using the circuit shown in Figure 11, TL/DD/12857 – 15
you can measure and display these switching transients un- FIGURE 12a. VIN, VCC, ICC for CL e 0 pF
der different load conditions.
Figure 12a shows the current and voltage spikes resulting
from switching a single unloaded (CL e 0 in Figure 11 )
NAND gate. These current spikes, seen at the switching
edges of the signal on VIN, increase when the output is
loaded. Figures 12b, 12c, and 12d show the switching tran-
sients when the load capacitance, CL, is 15 pF, 50 pF, and
100 pF, respectively. The large amount of ringing results
from the test circuit’s transmission line effects. This ringing
occurs partly because the CMOS gate switches from a very
high impedance to a very low one and back again. Even for
medium-size loads, load capacitance current becomes a
major current contributor.

TL/DD/12857 – 16
FIGURE 12b. VIN, VCC, ICC for CL e 15 pF

TL/DD/12857 – 17
FIGURE 12c. VIN, VCC, ICC for CL e 50 pF

TL/DD/12857 – 14
FIGURE 11. Test Circuit

TL/DD/12857 – 18
FIGURE 12d. VIN, VCC, ICC for CL e 100 pF

7 http://www.national.com
 Although on standard CMOS logic internal gates generate low logic levels. ACT CMOS logic families have noise immu-
current spikes when switching, the bulk of a spike’s current nity of 2.9V for high logic levels and 700 mV for low logic
comes from output circuit transitions. Figure 13 shows the levels.
ICC current for a NAND gate, as shown in the test circuit, TABLE III. Logic Family Comparisons
with one input switching and the other at ground resulting in
no output transitions. Note the very small power-supply LS/
Charac-
glitches provoked by the input-circuit transitions. Symbol ALS HCMOS AC ACT
teristic
/TTL
Input VIH (Min) 2.0V 3.15V 3.15V 2.0V
Voltage V (Max) 0.8V 0.9V 1.35V 0.8V
IL
(Limits)
Output VOH (Min) 2.7V VCCb0.1V VCCb0.1V VCCb0.1V
Voltage V
OL (Max) 0.5V 0.1V 0.1V 0.1V
(Limits)
To illustrate noise margin and immunity, Figures 14b and
14c show the output that results when you apply several
types of simulated noise to a 74HC00’s input, Figure 14a .
Typically, even 2V or more input noise produces little
change in the output. The top trace shows noise present on
the input logic level signal and the bottom trace shows re-
sultant noise induced on the output logic level signal.

TL/DD/12857–19
FIGURE 13a. Test Circuit
TL/DD/12857 – 23
FIGURE 14a. Test Circuit

TL/DD/12857–20
FIGURE 13b. VIN, VCC, ICC TL/DD/12857 – 24
FIGURE 14b. VIN, VOUT
4.4 High Speed CMOS Logic Switching
The magnitude of noise which can be tolerated in a system
relates directly to the worst case noise immunity specified
for the logic family. Noise immunity can be described as a
device’s ability to prevent noise on its input from being
transferred to its output. It is the difference between the
worst case output levels (VOH and VOL) of the driving circuit
and the worst case input voltage requirements (VIH and VIL,
respectively) of the receiving circuit.
Using Table III as a guide, it can be seen that for TTL (LS or
ALS) devices the worst case noise immunity is typically
700 mV for the high logic level and 300 mV for the low logic
level. For HCMOS devices the worst case noise immunity is
typically 1.75V for high logic levels and 800 mV for low logic
levels. AC high speed CMOS logic families have noise im-
TL/DD/12857 – 25
munity of 1.75V for high logic levels and 1.25V for
FIGURE 14c. VIN, VOUT

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Figure 15b shows how noise affects 74HC74’s clock input.
Again, no logic errors occur with 2V or more of noise on the
clock input.
TL/DD/12857 – 21
FIGURE 15a. Test Circuit
TL/DD/12857 – 22
FIGURE 15b. VIN, VOUT
When using high speed CMOS, even with its greater noise
immunity, crosstalk, induced supply noise and noise tran-
sients become factors. Higher speeds allow the device to
respond more quickly to externally induced noise transients
and accentuate the parasitic interconnection inductances
and capacitances that increase self-induced noise and
crosstalk.
4.5 Signal Crosstalk
The problem of crosstalk, and how to deal with it, is becom-
ing more important as system performance and board den-
FIGURE 16. Crosstalk
9 http://www.national.com
sities increase. Our discussion on cable-to-cable coupling
described crosstalk as appearing due to the distributed ca-
pacitive coupling and the distributed inductive coupling be-
tween two signal lines. When crosstalk is measured on an
undriven sense line next to a driven line (both terminated at
their characteristic impedances), the near end crosstalk and
the far end crosstalk have quite distinct features, as shown
in Figure 16. It should be noted that the near end compo-
nent reduces to zero at the far end and vice versa. At any
point in between, the crosstalk is a fractional sum of the
near and far end crosstalk waveforms as shown in the fig-
ure. It also can be noted that the far end crosstalk can have
either polarity whereas the near end crosstalk always has
the same polarity as the signal causing it.
The amplitude of the noise generated on the undriven
sense line is directly related to the edge rates of the signal
on the driven line. The amplitude is also directly related to
the proximity of the two lines. This is factored into the cou-
pling constants KNE and KFE by terms that include the dis-
tributed capacitance per unit length, the distributed induc-
tance per unit length, and the length of the line. The lead-to-
lead capacitance and mutual inductance thus created caus-
es ‘‘noise’’ voltages to appear when adjacent signal paths
switch.
Several useful observations that apply to a general case
can then be made:
# The crosstalk always scales with the signal amplitude VI.
# Absolute crosstalk amplitude is proportional to slew rate
VI/tr not just 1/tr.
# Far end crosstalk width is always tr.
# For tr kk 2 TL, where tr is the transition time of the
signal on the driven line and TL is the propagation or bus
delay down the line, the near end crosstalk amplitude,
VNE, expressed as a fraction of signal amplitude, VI, is
KNE which is a function of physical layout only.
# The high the value of ‘‘tr’’ (slower transition times) the
lower the percentage of crosstalk (relative to signal am-
plitude).
TL/DD/12857 – 26
 Although all circuit conductors have transmission line prop-
erties, these characteristics become significant when the
edge rates of the drivers are equal to or less than about
three times the propagation delay of the line. Significant
transmission line properties may be exhibited, for example,
where devices having edge rates of 3 ns (or less) are used
to drive traces of 8 inches or greater, assuming propagation
delays of 1.7 ns/ft for an unloaded printed circuit trace.
4.6 Signal Interconnects
Of the many properties of transmission lines, two are of
major interest to the system designer: ZOE, the effective
equivalent impedance of the line, and tpde, the effective
propagation delay down the line. It should be noted that the
intrinsic values of line impedance and propagation delay, ZO
and tpd, are geometry-dependent. Once the intrinsic values
are known, the effects of gate loading can be calculated.
The loaded values for ZOE and tpde can be calculated with:
Zo
ZOE e
01 a Ct/Cl
tpde e tpd 01 a Ct/Cl
where Ci e intrinsic line capacitance
Ct e additional capacitance due to gate loading.
These formulas indicate that the loading of lines decreases
the effective impedance of the line and increases the propa-
gation delay. As was mentioned earlier, lines that have a
propagation delay greater than one third the rise time of the
signal driver should be evaluated for transmission line ef-
fects. When performing transmission line analysis on a bus,
only the longest, most heavily loaded and the shortest, least
loaded lines need to be analyzed. All lines in a bus should
be terminated equally; if one line requires termination, all
lines in the bus should be terminated. This will ensure simi-
lar signal quality on all of the lines.
4.7 Ground Bounce
Ground bounce occurs as a result of the intrinsic character-
istics of the leadframes and bond wires of the packages
used to house CMOS devices. As edge rates and drive cap-
FIGURE 17a. Test Circuit for Ground Bounce
http://www.national.com
ability increase in advanced logic families, the effects of
these intrinsic electrical characteristics become more pro-
nounced. One of these parasitic electrical characteristics is
the inductance found in all leadframe materials.
Figure 17 shows a simple circuit model for a CMOS device
in a leadframe driving a standard test load. The inductor L1
represents the parasitic inductance in the ground lead of the
package; inductor L2 represents the parasitic inductance in
the power lead of the package; inductor L3 represents the
parasitic inductance in the output lead of the package; the
resistor R1 represents the output impedance of the device
output, and the capacitor and resistor CL and RL represent
the standard test load on the output of the device.
The three waveforms shown represent how ground bounce
is generated. The top waveform shows the voltage (V)
across the load as it is switched from a logic HIGH to a logic
LOW. The output slew rate is dependent upon the charac-
teristics of the output transistor, and the inductors L1 and
L3, and CL, the load capacitance. In order to change the
output from a HIGH to a LOW, current must flow to dis-
charge the load capacitance. The second waveform shows
the current that is generated as the capacitor discharges
[I e bCL*(dV/dt)]. This current, as it changes, causes a
voltage to be generated across the inductances in the cir-
cuit. The formula for the voltage across an inductor is
V e L(dI/dt). The third waveform shows the voltage that is
induced across the inductance in the ground lead due to the
changing currents [VGB e L1*(dI/dt)]. This induced voltage
creates what is known as ground bounce.
Because the inductor is between the external system
ground and the internal device ground, the induced voltage
causes the internal ground to be at a different potential than
the external ground. This shift in potential causes the device
inputs and outputs to behave differently than expected be-
cause they are referenced to the internal device ground,
while the devices which are either driving into the inputs or
being driven by the outputs are referenced to the their own
device ground. External to the device, ground bounce caus-
es input thresholds to shift and output levels to change.
TL/DD/12857 – 27
TL/DD/12857 – 28
FIGURE 17b. VIN, VCC, ICC
10

FIGURE 18. Intra-System EMI Manifestations
Although this discussion is limited to ground bounce gener-
ated during HIGH-to-LOW transitions, it should be noted
that the ground bounce is also generated during LOW-to-
HIGH transitions. This ground bounce though, has a much
smaller amplitude and therefore does not present the same
concern.
There are many factors which affect the amplitude of the
ground bounce. Included are:
# Number of outputs switching simultaneously: more out-
puts results in more ground bounce.
# Type of output load: capacitive loads generate two to
three times more ground bounce than typical system
traces. Increasing the capacitive load to approximately
60 pF –70 pF, increases ground bounce. Beyond 70 pF,
ground bounce drops off due to the filtering effect of the
load itself. Moving the load away from the output also
reduces the ground bounce.
# Location of the output pin: outputs closer to the ground
pin exhibit less ground bounce than those further away
due to effectively lower L1 and L3.
# Voltage: lowering VCC reduces ground bounce.
Ground bounce produces several symptoms:
# Altered device states.
# Propagation delay degradation.
# Undershoot on active outputs. The worst-case under-
shoot will be approximately equal to the worst-case quiet
output noise.
5.0 NOISE SUPPRESSION TECHNIQUES
EMI control techniques involve both hardware implementa-
tions/methods and procedures. They may also be divided
into intra-system and inter-system EMI control. Our major
concern in this paper is intra-system EMI control, however,
an overview of each may be appropriate at this time.
Figure 18 illustrates the basic elements of concern in an
intra-system EMI problem. The test specimen may be a sin-
gle box, an equipment, subsystem or system (an ensemble
of boxes with interconnecting cables). From a strictly near-
sighted or selfish point-of-view, the only EMI concern would
appear to be degradation of performance due to self jam-
ming such as suggested at the top of the figure. While this
11
TL/DD/12857 – 29
might be the primary emphasis, the potential problems as-
sociated with either (1) susceptibility to outside conducted
and/or radiated emissions or (2) tendency to pollute the
outside world from its own undesired emissions, come un-
der the primary classification of intra-system EMI. Corre-
sponding EMI-control techniques, however, address them-
selves to both self-jamming and emission/susceptibility in
accordance with applicable EMI specifications. The tech-
niques that will be discussed include filtering, shielding, wir-
ing and grounding.
Inter-system EMI distinguishes itself by interference be-
tween two or more discrete and separate systems or plat-
forms which are frequently under independent user control.
Culprit emissions and/or susceptibility situations are divided
into two classes: (1) antenna entry/exit and (2) back-door
entry/exit. More than 95% of inter-system EMI problems
involve the antenna entry/exit route of EMI. We can group
inter-system EMI-control techniques by four fundamental
categories: frequency management, time management, lo-
cation management and direction management.
The first step in determining a solution is to identify the
problem as either inter-system or intra-system EMI. Gener-
ally, if the specimen has an antenna and the problem devel-
ops from what exits or enters the antenna from another
specimen or ambient, then the problem is identified as inter-
system EMI. Otherwise, it is intra-system EMI which we will
discuss now.
5.1 Intra-System EMI Control Techniques
5.1.1 Shielding
Shielding is used to reduce the amount of electromagnetic
radiation reaching a sensitive victim circuit. Shields are
made of metal and work on the principle that electromag-
netic fields are reflected and/or attenuated by a metal sur-
face. Different types of shielding are needed for different
types of fields. Thus, the type of metal used in the shield
and the shield’s construction must be considered carefully if
the shield is to function properly. The ideal shield has no
holes or voids and, in order to accommodate cooling vents,
buttons, lamps and access panels, special meshes and
‘‘EMI-hardened’’ components are needed.
http://www.national.com
 TABLE IV. Effective Shielding for Different Materials
Shielding Effectiveness dB
Shielding Material Surface Resistance (X/square)
At 10 MHz At 100 MHz At 1 GHz
Arc-Sprayed Zinc 0.002 106 92 98
Silver Acrylic Paint 0.004 67 93 97
Silver Deposition 0.05 57 82 89
Silver Epoxy Paint 0.1 59 81 87
Nickel Composite 3.0 35 47 57
Carbon Composite 10.0 27 35 41
Wire Screen (0.64 mm Grid) N.A. 86 66 48
Effectiveness of shielding materials with 25 mm thickness and for frequencies for which the largest dimension of the shielding plate is less than a quarter of a
wavelength.

Once a printed-circuit board design has been optimized for

minimal EMI, residual interference can be further reduced if
the board is placed in a shielded enclosure. A box’s shield-
ing effectiveness depends on three main factors: its skin,
the control of radiation leakage through the box’s apertures
or open areas (like cooling holes) and the use of filters or
shields at interconnection points depending on shield
grounding.
A box skin is typically fabricated from sheet metal or metal-
lized plastic. Normally sheet metal skin that is 1 mm thick is
more than adequate; it may have a shielding effectiveness
of more than 100 dB throughout the high-frequency spec-
trum from 1 MHz to 20 GHz. Conductive coatings on plastic
boxes are another matter. Table IV shows that at 10 MHz
the shielding effectiveness can be as low as 27 dB if a car-
bon composite (cheap) is used, or it can run as high as 106
dB for zinc sprayed on plastic by an electric arc process
(expensive). Plastic filled materials or composites having ei-
ther conductive powder, flakes, or filament are also used in
box shielding; they have an effectiveness similar to that of
metallized plastics.
In many cases shielding effectiveness of at least 40 dB is
required of plastic housings for microcontroller-based equip-
ment to reduce printed-circuit board radiation to a level that
meets FCC regulations in the United States or those of the
VDE in Europe. Such skin shielding is easy to achieve. The
problem is aperture leakage. The larger the aperture, the
greater its radiation leakage because the shield’s natural
attenuation has been reduced. On the other hand, multiple
small holes matching the same area as the single large ap-
erture can attain the same amount of cooling with little or no
loss of attenuation.
5.1.2 Filtering
Filters are used to eliminate conducted interference on ca-
bles and wires, and can be installed at either the source or
the victim. Figure 19 shows an AC power-line filter. The val-
ues of the components are not critical; as a guide, the ca-
pacitors can be between 0.01 and 0.001 mF, and the induc-
tors are nominally 6.3 mH. Capacitor C1 is designed to shunt
any high-frequency differential-mode currents before they
can enter the equipment to be protected. Capacitors C2 and
C3 are included to shunt any common-mode currents to
ground. The inductors, L1 and L2, are called common-mode
chokes, and are placed in the circuit to impede any com-
mon-mode currents.
TL/DD/12857 – 30
FIGURE 19. Filtering
5.1.3 Wiring
Now that the equipment in each box can be successfully
designed to combat EMI emission and susceptibility sepa-
rately, the boxes may be connected together to form a sys-
tem. Here the input and output cables and, to a lesser ex-
tent, the power cable form an ‘‘antenna farm’’ that greatly
threatens the overall electromagnetic compatibility of the
system. Most field remedies for EMI problems focus on the
coupling paths created by the wiring that interconnects sys-
tems. By this time most changes to the individual equipment
circuits are out of the question.
Let us address five coupling paths that are encountered in
typical systems comprised of two or more pieces of equip-
ment connected by cables. These should adequately cover
most EMI susceptibility problems. They are:
# common ground impedance couplingÐa conducting
path in which a common impedance is shared between
an undesired emission source and the receptor.
# common-mode, radiated field-to-cable couplingÐelec-
tromagnetic fields penetrate a loop formed by two pieces
of equipment, a cable connecting them, and a ground
plane.
# differential-mode, radiated field-to-cable couplingÐthe
electromagnetic fields penetrate a loop formed by two
pieces of equipment and an interconnecting transmission
line or cable.
# crosstalk couplingÐsignals in one transmission line or
cable are capacitively or inductively coupled into another
transmission line.
# conductive pathÐthrough power lines feeding the equip-
ment.
The first coupling path is formed when two pieces of equip-
ment are connected to the same ground conductor at differ-
ent points, an arrangement that normally produces a volt-

http://www.national.com 12
age difference between the two points. If possible, connect- pickup of differential-mode radiation. In a balanced trans-
ing both pieces of equipment to a single-point ground elimi- mission line, this is done by use of twisted-wire pairs and a
nates this voltage. Another remedy is to increase the high shielded cable.
frequency impedance along a loop that includes the path For crosstalk, the fourth coupling path, the reduction of ca-
between the ground connections of the two boxes. Exam- pacitive coupling, can be achieved by the implementation of
ples include the isolation of printed-circuit boards from their at least one of these steps:
cabinet or case, the use of a shielded isolation transformer
# Reducing the spacing between wire pairs in either or
in the signal path, or the insertion of an inductor between
both of the transmission lines.
one or both boxes and the ground conductor. The use of
balanced circuits, differential line drivers and receivers, and # Increasing the separation between the two transmission
absorbing ferrite beads and rods on the interconnecting ca- lines.
ble can further reduce currents produced by this undesir- # Reducing the frequency of operation of the source, if
able coupling path. possible.
# Adding a cable shield over either or both transmission
lines.
# Twisting the source’s or receptor’s wire pairs.
# Twisting both wire pairs in opposite directions.
The fifth coupling path conductively produces both com-
mon-mode and differential-mode noise pollution on the
power mains. Among several remedies that can suppress
the EMI there are filters and isolation transformers.
There are only about 50 common practical remedies that
can be used in most EMI situations. Of these, about 10
suffice in 80 percent of the situations. Most engineers are
aware of at least some of these remediesÐfor example,
TL/DD/12857 – 31 twisting wires to reduce radiation pickup.
FIGURE 20. Common Ground Impedance Coupling In order to attack the EMI problem, one can make use of the
information contained in Tables V and VI. First, decide what
A balanced circuit is configured so its two output signal coupling path has the worst EMI interference problem. From
leads are electrically symmetrical with respect to ground, as the 11 most common coupling paths listed at the top of the
the signal increases on one output, the signal on the other table, find the problem coupling path. Using the numbers
decreases. Differential line drivers produce a signal that is found in that table entry, locate the recommended remedy
electrically symmetrical with respect to ground from a sin- or remedies from the 12 common EMI fixes identified at the
gle-ended circuit in which only one lead is changing with bottom of the table. This procedure should be repeated until
respect to ground. Ferrite beads, threaded over electrical all significant coupling paths have been properly controlled
conductors, substantially attenuate electromagnetic inter- and the design goal has been met.
ference by turning radio-frequency energy into heat, which TABLE V. Electromagnetic Interference Coupling Paths
is dissipated in them.
In the second coupling path, a radiated electromagnetic Solution
Problem
field is converted into a common-mode voltage in the (See Table VI)
ground plane loop containing the interconnect cable and Radiated Field to Interconnecting Cable
both boxes. This voltage may be reduced if the loop area is 2, 7, 8, 9, 11
(Common-Mode)
trimmed.
Ferrite beads and ferrite filtered connectors applied to the Radiated Field to Interconnecting Cable
2, 5, 6
interconnecting cable can help reduce common mode cur- (Differential-Mode)
rents.
Interconnecting Cable to Radiated Field
1, 3, 9, 11
(Common-Mode)
Interconnecting Cable to Radiated Field
1, 3, 5, 6, 7
(Differential-Mode)
Cable-to-Cable Crosstalk 1, 2, 3, 4, 5,
6, 10, 11
Radiated Field to Box 12, 13
Box to Radiated Field 12, 13
Box-to-Box Radiation 12, 13
TL/DD/12857 – 32 Box-to-Box Conduction 1, 2, 7, 8, 9
FIGURE 21. Common-Mode, Radiated
Power Mains to Box Conduction 4, 11
Field-to-Cable Coupling
Box to Power Mains Conduction 4, 11
The third coupling path produces a differential-mode volt-
age that appears across the input terminals of the EMI re- Electromagnetic Interference Coupling
4
ceptor. One way of controlling this is to cancel or block the Paths

13 http://www.national.com
 TABLE VI. Electromagnetic Interference Fixes 5.2.3 Location Management
Solution Complexity Cost Location management refers to EMI control by the selection
of location of the potential victim receptor with respect to all
1. Insert Filter in Signal Low Medium other emitters in the environment. In this regard, separation
Source distance between transmitters and receivers is one of the
2. Insert Filter in Signal Low Medium most significant forms of control since interfering source
Receptor emissions are reduced greatly with the distance between
them. The relative position of potentially interfering transmit-
3. Insert Filter in Power Low Medium ters to the victim receiver are also significant. If the emitting
Source source and victim receiver are shielded by obstacles, the
degree of interference would be substantially reduced.
4. Insert Filter in Power Low Medium
Receptor 5.2.4 Direction Management
5. Twist Wire Pair Low Low Direction management refers to the technique of EMI con-
trol by gainfully using the direction and attitude of arrival of
6. Shield Cable Low Medium electromagnetic signals with respect to the potential vic-
7. Use Balanced Circuits Medium Medium tim’s receiving antennae.

8. Install Differential Line Medium Medium 6.0 SILICON CHANGES

Drivers and Receivers
9. Float Printed Circuit Medium Medium
Board(s)
10. Separate Wire Pair Low Medium
11. Use Ferrite Beads Low Medium
12. Use a Multilayer Instead of Medium High
a Single Layer Printed
Circuit Board(s)
5.2 Inter-System EMI-Control Techniques
There are many EMI controls that may be carried out to
enhance the chances of inter-system EMC. They can be
grouped into four categories which we will discuss briefly.
The following discussion is not intended to be complete but
merely provide an overview of some EMI control techniques
available to the inter-system designer and user.
5.2.1 Frequency Management
Frequency management suggests both transmitter emission
control and improvement of receptors against spurious re-
sponses. The object is to design and operationally maintain
transmitters so that they occupy the least frequency spec-
trum possible in order to help control electromagnetic pollu-
tion. For example, this implies that long pulse rise and fall
times should be used. Quite often one of the most conve-
nient, economic and rapid solutions to an EMI problem in
the field, is to change frequency of either the victim receiver
or the culprit source.
5.2.2 Time Management
In those applications where information is passed between
systems, a possible time management technique could be
utilized where the amount of information transferred is kept
to a minimum. This should reduce the amount of time that
the receptor is susceptible to any EMI. In communication
protocols, for example, essential data could be transmitted
in short bursts or control information could be encoded into
fewer bits.
If we examine the modes of EMI emissions and the meth-
ods of suppression that were described, on standard CMOS
silicon the techniques are exactly the same for what occurs
on a PCB. What silicon design engineers at National Semi-
conductor’s Embedded Technologies Division noticed, was
that a majority of the EMI emitted from a controller or proc-
essor is caused by the transient ICC current flowing in the
loop formed from the bypass capacitor to the VCC pin and
out of the GND pin. When this current was measured by
inserting a 1X resistor in this path, a 40 mA (10 ns) current
spike was revealed at every clock edge (repetition rate e
2x clock frequency). This occurred even when outputs were
toggling or tristated, and instructions that were being exe-
cuted had very little impact on the magnitude or duration of
the spike.
6.1 Chip Problems
Let’s note the four items that produce higher amplitude and
frequency fundamental and harmonics: large amplitude
change, fast rise time or fall time, high repetition rate and
finally large pulse width (a 50% duty cycle). Table VII lists
these.
TABLE VII. IC Chip Problems
1. Large Amplitude Change
2. Fast Rise or Fall Time
3. High Repetition Rate
4. Large Pulse Width (i.e. 50% Duty Cycle).
As a rule, the waveforms di/dt (rate of change of current)
and dv/dt (rate of change of voltage) must be kept to a
minimum. If a silicon design engineer could shape both cur-
rent and voltage waveforms around the device, these prob-
lems would be solved. If we look at the current and voltage
problems separately, we can solve them both and decrease
radiated emissions by more than 20 dB.
But, what about the antennae responsible for radiation?
This is where packaging technology comes into the picture.
The loop size of a typical system is approximately greater

http://www.national.com 14
than 90% PCB trace dimensions plus IC package dimen-
sions and less than 10% IC chip dimensions, which both
factor into the antenna gain. Therefore the IC package de-
sign should obey several rules, see Table VIII. First a ground
pin (current return) adjacent to each power pin will minimize
the loop sizes and simplify layout of decoupling circuits.
Also an output pin which sources or sinks a large and fre-
quent di/dt (for example crystal or clock pins) should also
be adjacent to the power/ground pin pair to keep its current
loops small. It helps to have small package dimensions. A
last point is that sharing of a common power/ground should
be limited to prevent their voltage from bouncing due to the
total Ldi/dt a iR. This bouncing is conducted to inputs shar-
ing the common power/ground which in several cases are
susceptible since their VIH and VIL trip points are referenced
to it. The bouncing is conducted through non-tristated out-
puts sharing this common power/ground and is passed on
outside the IC as additional conducted and radiated emis-
sions from bouncing VOH or VOL levels.
TABLE VIII. Package and PCB Traces form Loop or
Whip Antennae which Radiate
1. Ground pin (current return) not adjacent to power
pin). Pair should be together.
2. Power/Ground pair not adjacent to output pin
(especially crystal of clock pins).
3. Too much sharing of common power/ground
having voltage bounce due to its total Ldi/dt a iR.
a. Conducted emissions to susceptible I/O
b. Radiated emissions from susceptible I/O.
4. Large package dimensions.
6.2 Silicon Design Changes
National’s design goal was to reshape the IC pin current
waveforms from their original values as follows: ICC pulses
to 3X rise time, 0.2X amplitude and 5X width; IOL and IOH
pulses to 10X rise time. A second goal is to provide sepa-
rate power and ground bus systems on-chip for each of the
following groups: Chip digital logic, Chip I/O buffers, and if
present a chip A/D converter (or other analog intensive sec-
tions). This is an extension of proper IC packaging pinout
covered earlier to prevent conducted emissions to suscepti-
ble circuitry.
Inspection of these goals leads us to divide the chip into
separate areas which we named the nucleus, the perimeter
and the A/D. Also the partitioning of the nucleus (containing
the digital logic functions) and the perimeter (containing dig-
ital I/O, oscillator and comparator functions) allows use of
an on-chip device to choke the nucleus’ ICC current, thereby
wave shaping the ICC. The ICC choke, however, causes the
nucleus VCC voltage to dip by 0.5V to 1V at each clock
edge. These VCC voltage swings will be confined to within
the chip’s nucleus where the circuitry (digital logic) is toler-
ant and no significant radiation antennae exist.
15
On-chip level shifting circuitry is inserted as interface be-
tween the nucleus and the perimeter. It permits the nucleus
to operate at a lower VCC than the perimeter. This permits
the nucleus VCC to come through the on-chip ICC choke
emerging as a bouncing VCC.
In general, outputs toggle much less frequently than the
clock. This rate is limited by software execution rates. How-
ever, for the case of a clock or address/data bus outputs
this may not be the case. Looking at time domain EMI in-
stead of frequency domain EMI (which may have some time
averaging) may motivate one to take action and reduce EMI
from the chip’s output drivers. CMOS output drivers turn on
fast, in about 1 ns. This causes 2 problems. The first is
called ‘‘shoot through’’ current which flows from DVCC to
DGND when both the pull up and the pull down drivers are
on and the output load is small. The second is due to output
current magnitude increasing to maximum in about 1 ns
when the output changes state. Both problems are solved
by using fast turn off, gradual turn on device drivers.
Figure 22 illustrates, in block diagram form, how the chip is
partitioned for EMC. Note that the level shifter block is multi-
channel, and most channels need dedicated level shifting
devices in one direction only as shown. The power/ground
pads named DVCC (Driver VCC), LVCC (Logic VCC), VCC (a
global VCC to most of the chip), GND (a global GND to most
of the chip) and DGND (driver ground) are all available. To
minimize package pin count, DVCC and LVCC can be bond-
ed to the same pin, GND and DGND can be bonded to the
same pin, and the VCC pad is not bonded. A higher pin
count package is used to bring out each pad to a separate
pin to allow study of the several packaging options. The VCC
pad is not bonded when utilizing the on-chip ICC choke to
prevent RE (radiated emissions) from VCC bounce.
Three operating modes can be evaluated with GND and
DGND pads always connected together to 0V. The first
mode applies 5V to DVCC, LVCC and VCC to check the RE
improvements due to gradual turn on outputs alone. The
second mode applies 5V to DVCC and LVCC where VCC
floats as a test point. This checks the RE improvements due
to gradual turn on and ICC choking. The third mode applies
5V to DVCC and 3V to VCC and LVCC to check the RE
improvement in this mode which actually requires a VCC
additional package pin.
TABLE IX. Results of Various Pinout Configurations
Config- Config- Config-
Chip Pads
uration A uration B uration C
DVCC 5V 5V 5V
LVCC 5V 5V 3V
VCC 5V Test Point 3V
GND 0 0 0
DGND 0 0 0
EMI Baseline b 20 dB b 6 dB
Clock Speed 10 MHz l 5 MHz 4 MHz
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 TL/DD/12857 – 33
FIGURE 22. Block Diagram of EMC Circuitry

6.3 Packaging Changes

Recalling our IC packaging rules for EMC, and upon review-
ing the packaging pitfalls (Table VIII), one can now appreci-
ate an IC package build sheet (Figure 23) that illustrates
how to bond out and pin out the five power/ground pads on
the die. As advised, power pins having current return ground
pins adjacent are LVCC and GND, VCC and GND; but DVCC
and DGND are not adjacent. This is permitted since DVCC
current is returned via output high pins (not DGND), also
DGND current is sourced via output low pins. Therefore
placing DVCC adjacent to DGND does not contribute to
small area current loops. Note that CKI, CKO, LVCC, and
TL/DD/12857 – 34
GND are all adjacent pins for the sake of clustering the
oscillator external tank circuit into the smallest current loop FIGURE 23. EMC Pinout
area. Since the oscillator is supplied through LVCC and 6.4 Results of IC Circuit Changes
GND, added benefit of running both oscillator and nucleus Simulations give an idea of the expected improvement from
at 3V is possible if one were to choose defeating the on- addition of the ICC choke on the silicon. Figure 24a shows
chip choke by shorting LVCC to VCC in the choke block. actual ICC as measured by a series resistance during
switching transients. Simulation of an equivalent circuit with
the addition of the choke predicts a decrease of ICC from
about 37 mA to less than 4 mA.
This decrease of 10x would imply a 20 dB improvement in
gross emissions.

http://www.national.com 16
 Test results in Figure 26 show emissions of 45 dBmV re-
duced to less than 20 dBmV on the same device. Unchoked
tests were performed using the bonding options previously
discussed.
Figure 25 gives the predicted performance degradation from
implementing gradual turn-on outputs. High to low transition
time propagation delays are doubled and low to high tran-
sitions are slowed by about 50%. Remember, though, that
propagation delays for an embedded microcontroller are
usually of minimal concern since control is based on levels
or edges of individual signals or on timing which is under
software control. Software control is slow enough that the
change in hardware timing is probably negligible.
TL/DD/12857 – 35
FIGURE 24a. Original ICC An indication of the type of emission reduction resulting
from the implementation of gradual turn-on can be seen if
you look at the baselines of the plots of Figure 26. Changes
of the outputs occur at low frequency with large amplitude,
fast rise time current spikes. The low frequency of the signal
keeps the harmonic close together and makes the emis-
sions appear broadband. The fast rise time maintains a
higher level of emissions to a higher frequency.

TL/DD/12857 – 36
FIGURE 24b. ICC with Improvements

TL/DD/12857 – 39
FIGURE 26a. VOL

TL/DD/12857 – 37
FIGURE 25a. Emissions without VCC Choke

TL/DD/12857 – 40
FIGURE 26b. VOH

TL/DD/12857 – 38
FIGURE 25b. Emissions with Addition of VCC Choke

17 http://www.national.com
 7.0 SYSTEM PERFORMANCE USING EMI REDUCED
PARTS
We have discussed in previous sections that we can reduce
EMI by proper board design and by the selection of low EMI
devices. We will now investigate whether EMI reduced parts
are worth it. The goal of this testing is to determine the
relative electromagnetic emissions from various production
options of the COP8 microcontroller. Since most people use
OTPs to qualify their end product for emissions approval,
both OTPs and ROMmed devices will be tested. The op-
tions chosen were:
1. COP8788EGMH (OTP) part used for development and
Prototype approval
2. COP888EK (masked ROM) part used for final production
(EMI reduced)
3. COP8788GG (OTP) part used for development and Pro-
totype approval
4. COP888GG (masked ROM) part used for final production
(EMI reduced)
7.1 Test Procedure
These tests were performed in two ways:
1. Two DIP parts, a COP888EK and a COP888EGMH OTP
device, were programmed for use as the main processor
in an automotive radio and the relative performance of
the radio was measured for each device. The measure of
performance chosen was Usable Sensitivity. This is de-
fined as the minimum input required at the antenna in
FIGURE 27. PCB Layout for EMI Testing
http://www.national.com
order to achieve a predetermined signal to noise ratio
(SNR) at the speaker. In this case the input was chosen
to be a 22 kHz deviation of a frequency modulated signal
within the US commercial FM radio broadcast band. The
signal to noise criterion used was 30 dB.
2. Two other devices, a COP888GG and a COP87M88GG
OTP, were placed in a common two sided PCB in a TEM
cell and were programmed to run a standard EMI test
program included in National’s first silicon engineering
code. Load capacitors of 10 pF and 4.7 kX pull-up resis-
tors used on the eight pins of Port L. The port was pro-
grammed to count in a binary manner with the least sig-
nificant bit changing state every 100 ms. (Figure 27 illus-
trates the board layout.) Four AA batteries were attached
to the board and the supply voltage was regulated with a
Zener diode.
Emissions were measured with the TEM cell on a Tektro-
nix Model 2754P Spectrum Analyzer over the range of
DC to 750 MHz.
7.2 Radio Results
Worst case useable sensitivity is improved by about 17 dB
(25 dBmV to 8 dBmV) by the change from the
COP888EGMH OTP to the mask programmed COP888EK.
Of course not all frequencies show this improvement, but
there is some increased sensitivity throughout the spectrum.
Note that two local radio stations (at 105.7 MHz and 106.5
MHz) were received even without an external antenna.
TL/DD/12857 – 42
18
 TL/DD/12857 – 41
FIGURE 28. Usable Sensitivity Comparison

7.3 EMI Board Results Much more noticeable is the reduction of spectral density in
Except for the fundamental oscillator frequency of approxi- the noise. Off harmonic noise is not noticeable.
mately 5 MHz, emissions are down at least 10 dB on the
monolithic masked device over the multichip OTP device.
Emissions beyond 100 MHz are practically eliminated.

19 http://www.national.com
 TL/DD/12857 – 43
FIGURE 29. COP888GG with 5 MHz Crystal Oscillator

TL/DD/12857 – 44
FIGURE 30. COP87L88GG with 5 MHz Crystal Oscillator

http://www.national.com 20
7.4 Conclusions
Radiated Emissions do not come from a device, but from a
board. Devices have some control over the emissions be-
cause they generate the noise which is radiated. The equa-
tion normally used to predict emission from a system is:
2 (/2
1.32 c 10b3 cI cA cFreq 2
Ð # 2qD J (
l
lE lMax e D
c 1a
where,
lElMax is the maximum E-field in the plane of the loop in
mV/m
l is the current amplitude, at the frequency of interest, in
milliamps
A is the loop area is cm2
l is the wavelength at the frequency of interest
D is the observation distance in meters
Freq is the frequency in MHz
and the perimeter of the loop P kk l
When applied to a chip, the area is very small and current
is relatively low compared to current consumption in a
typical system, thus the emissions are low.
8.0 DESIGN GUIDELINES
The growth of concern over electromagnetic compatibility
(EMC) in electronic systems continues to rise in the years
since the FCC proclaimed that there shall be no more
pollution of the electromagnetic spectrum. Still, designers
have not yet fully come to grips with a major source and
victim of electromagnetic interferenceÐthe PCB. The
most critical stage for addressing EMI is during the circuit
board design. Numerous tales of woe can be recounted
about the eleventh hour attempt at solving an EMI prob-
lem by retrofit because EMC was given no attention dur-
ing design. This retrofit ultimately costs much more than
design stage EMC, holds up production and generally
makes managers unhappy. With these facts in mind, let’s
address electromagnetic compatibility considerations in
PCB design.
8.1 Logic Selection
Logic selection can ultimately dictate how much attention
must be given to EMC in the total circuit design. The first
guideline should be: use the slowest speed logic that will
do the job. Logic speed refers to transition times of output
signals and gate responses to input signals. Many emis-
sions and susceptibility problems can be minimized if a
slow speed logic is used. For example, a square wave
clock or signal pulse with a 3 ns rise time generates radio
frequency (100 MHz and higher) energy that is gated
about on the PCB. It also means that the logic can re-
spond to comparable radio frequency energy if it gets
onto the boards.
21
The type of logic to be used is normally an early design
decision, so that control of edge speeds and, hence, emis-
sions and susceptibiity is made early. Of course, other fac-
tors such as required system performance, speed, and tim-
ing considerations must enter into this decision. If possible,
design the circuit with as slow speed logic as possible. The
use of slow speed logic, however, does not guarantee that
EMC will exist when the circuit is built; so proper EMC tech-
niques should still be implemented consistently during the
remainder of the circuit design.
8.2 Component Layout
Component layout is the second stage in PCB design. Sche-
matics tell little or nothing about how systems will perform
once the board is etched, stuffed, and powered. A circuit
schematic is useful to the design engineer, but an experi-
enced EMC engineer refers to the PCB when trouble-shoot-
ing. By controlling the board layout in the design stage, the
designer realizes two benefits: (1) a decrease in EMI prob-
lems when the circuit or system is sent for EMI or quality
assurance testing; and (2) the number of EMI coupling
paths is reduced, saving troubleshooting time and effort lat-
er on.
Some layout guidelines for arranging components according
to logic speed, frequency, and function are shown in Figure
31. These guidelines are very general. A particular circuit is
likely to require a combination and/or trade-offs of these
arrangements. Isolation of the I/O from digital circuitry is
important where emissions or susceptibility may be a prob-
lem. For the case of emissions, a frequently encountered
coupling path involves digital energy coupling through I/O
circuitry and signal traces onto I/O cables and wires, where
the latter subsequently radiate. When susceptibility is a
problem, it is common for the EMI energy to couple from
I/O circuits onto sensitive digital lines, even though the I/O
lines may be ‘‘opto-coupled’’ or otherwise supposedly iso-
lated. In both situations, the solution often lies in the proper
electrical and physical isolation of analog and low speed
digital lines from high speed circuits. When high speed sig-
nals are designed to leave the board, the reduction of EMI is
usually performed via shielding of I/O cables and is not con-
sidered here.
Therefore, a major guideline in layout out boards is to iso-
late the I/O circuitry from the high speed logic. This method
applies even if the logic is being clocked at ‘‘only’’ a few
MHz. Often, the fundamental frequency is of marginal inter-
est, with the harmonics generated from switching edges of
the clock being the biggest emission culprits. Internal sys-
tem input/output PCB circuitry should be mounted as close
to the edge connector as possible and capacitive filtering of
these lines may be necessary to reduce EMI on the lines.
High speed logic components should be grouped together.
Digital interface circuitry and I/O circuitry should be physi-
cally isolated from each other and routed on separate con-
nectors, if possible as shown in Figure 27d.
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 8.3 Power Supply Bussing
Power supply bussing is the next major concern in the de-
sign phase. Isolated digital and analog power supplies must
be used when mixing analog and digital circuitry on a board.
The design preferably should provide for separate power
supply distribution for both the analog and digital circuitry.
Single point common grounding of analog and digital power
supplies should be performed at one point and one point
onlyÐusually at the motherboard power supply input for
TL/DD/12857–45 multi-card designs, or at the power supply input edge con-
FIGURE 31a. Board Layout nector on a single card system. The fundamental feature of
good power supply bussing, however, is low impedance and
good decoupling over a large range of frequencies. A low
impedance distribution system requires two design features:
(1) proper power supply and return trace layout and (2)
proper use of decoupling capacitors.
An exception to the rule of analog and digital ground sepa-
ration applies in the case of high speed interface between
analog and digital portions. If possible, the ground plane
should be continuous under these interface traces to im-
prove the proximity of the return trace and thus minimize the
TL/DD/12857–46 size of the loop.
FIGURE 31b. Board Layout At high frequencies, PCB traces and the power supply bus-
ses ( a VCC and 0V) are viewed as transmission lines with
associated characteristic impedance, ZO, as modeled in
Figure 28. The goal of the designer is to maximize the ca-
pacitance between the lines and minimize the self-induc-
tance, thus creating a low ZO. Table X, shows the character-
istic impedance of various two-trace configurations as a
function of trace width, W, and trace separation, h.

TL/DD/12857–47
FIGURE 31c. Board Layout

TL/DD/12857 – 49
FIGURE 32. Transmission Line Modelling of PCB Traces

TL/DD/12857–48
FIGURE 31d. Board Layout

http://www.national.com 22
 TABLE X. Characteristic Impedance of Any one of the three configurations may be viewed as a
Different Conductor Pairs possible method of routing power supply (or signal) traces.
The most important feature of this table is the noticeable
difference in impedance between the parallel strips and
strip over ground plane compared with the side-by-side con-
figurations.
As an example of the amount of voltage that can be gener-
ated across the impedance of a power bus, consider TTL
logic which pulls a current of approximately 16 mA from a
Strips Over supply that has a 25X bus impedance (this assumes no
W/h or Parallel Strips Side decoupling present). The transient voltage is approximately
Ground
D/W Strips by Side dV e 0.016 x 25X e 400 mV, which is equal to the noise
Plane immunity level of the TTL logic. A 25X (or higher) imped-
0.5 377 377 N/A ance is not uncommon in many designs where the supply
and return traces are routed on the same side of the board
0.6 281 281 N/A in a side-by-side fashion. In fact, it is not uncommon to find
0.7 241 241 N/A situations where the power supply and return traces are
routed quite a distance from each other, thereby increasing
0.8 211 211 N/A the overall impedance of the distribution system and the
0.9 187 187 N/A size of the loop antenna. This is obviously a poor layout.
Power and ground planes offer the lowest overall imped-
1.0 169 169 0
ance. The use of these planes leads the designer closer to
1.1 153 153 25 a multi-layer board. At the very least, it is recommended that
all open areas on the PCB be ‘‘landfilled’’ with an intercon-
1.2 140 140 34 nected 0V reference plane so that ground impedance is
1.5 112 112 53 minimized. This landfill technique may be ineffective, how-
ever if minimum width traces connect the filled areas.
1.7 99 99 62
Multi-layer boards offer a considerable reduction in power
2.0 84 84 73 supply impedance, as well as other benefits. Extending the
table we just saw, the impedance of a multi-layer power/
2.5 67 67 87
ground plane bus grows very small (on the order of an X or
3.0 56 56 98 less), assuming a W/h ratio greater than 100. Multi-layer
board designs also pay dividends in terms of greatly re-
3.5 48 48 107
duced EMI, and they provide close control of line impedanc-
4.0 42 42 114 es where impedance matching is important. In addition,
5.0 34 34 127
6.0 28 28 137
7.0 24 24 146
8.0 21 21 153
9.0 19 19 160
10.0 17 17 166
12.0 14 14 176
15.0 11.2 11.2 188
20.0 8.4 8.4 204
25.0 6.7 6.7 217
30.0 5.6 5.6 227
40.0 4.2 4.2 243
50.0 3.4 3.4 255

23 http://www.national.com

FIGURE 33. Decoupling Example
shielding benefits can be realized. For high-density, high-
speed logic applications, the use of a multi-layer board is
almost mandatory. The problem with multi-layer boards is
the increased cost of design and fabrication and increased
difficulty in board repair.
8.4 Decoupling
High-speed CMOS has special decoupling and PCB layout
requirements. Adhering to these requirements will ensure
that maximum advantage is gained with CMOS devices in
system performance and EMC performance.
Local high frequency decoupling is required to supply power
to the chip when it is transitioning from a LOW to a HIGH
value. This power is necessary to charge the load capaci-
tance or drive a line impedance.
For most power distribution networks, the typical impedance
can be between 50X and 100X. This impedance appears in
series with the load impedance and will cause a droop in the
VCC at the part. This droop limits the available voltage swing
at the local node, unless some form of decoupling is used.
This drooping of rails will cause the rise and fall times to
become elongated. Consider the example presented in Fig-
ure 29 used to help calculate the amount of decoupling nec-
essary. This circuit utilizes an octal buffer driving a 100X
bus from a point somewhere in the middle.
Being in the middle of the bus, the driver will see two 100X
loads in parallel, or an effective impedance of 50X. To
switch the line from rail to rail, a drive of 94 mA is needed
(4.8V/50X) and more than 75 mA wil be required if all eight
lines switch at once. This instantaneous current requirement
will generate a voltage drop across the impedance of the
power lines, causing the actual VCC at the chip to droop.
This droop limits the voltage swing available to the driver.
The net effect of the voltage droop will be to lengthen de-
vice rise and fall times and slow system operation. A local
decoupling capacitor is required to act as a low impedance
supply for the driver chip during high current demands. It will
maintain the voltage within acceptable limits and keep rise
and fall times to a minimum. The necesssary values for de-
coupling capacitors can be calculated with the formula giv-
en in Figure 30 .
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TL/DD/12857 – 53
TL/DD/12857 – 54
Specify VCC Droop e 0.1V max during switching time of 4 ns
Q e CV charge on capacitor
I e C dV/dt
C e I dt/dV e 750 mA c 4 ns/0.1V e 0.030 mF
Select CB e 0.047 mF or greater
FIGURE 34. Decoupling Example
In this example, if the VCC droop is to be kept below 0.1V
and the edge rate equals 4 ns, we can calculate the value of
the decoupling capacitor by use of the charge on a capaci-
tor equation: Q e CV. The capacitor must supply the high
demand current during the transition period and is repre-
sented by I e C(dV/dt). Rearranging this somewhat yields
C e I(dt/dV).
Now, I e 750 mA assuming all 8 outputs switch simulta-
neously for worst case conditions, dt e switching period or
4 ns, and dV is the specified VCC droop of 0.1V. This yields
a calculated value of 0.030 mF for the decoupling capacitor.
So, a selection of 0.047 mF or greater should be sufficient.
Higher gate count devices, e.g. microcontrollers, with high
internal edge rates present additional decoupling problems.
Capacitors often suffer from parasitic series inductive ef-
fects at high frequency. In fact, a poorly selected capacitor
can become almost entirely inductive at high frequency.
This can be counteracted by paralleling additional capaci-
tors of lower value and corresponding higher self-resonant
frequency. Of course the lower value capacitor should be
placed closer to the chip to reduce the size of the resultant
current loop.
Inductors or ferrite beads connected in series between the
capacitors can help to minimize noise currents and voltages
from reaching the rest of the circuit.
24
It is good practice to distribute decoupling capacitors evenly
throughout the logic on the board, placing at least one ca-
pacitor for every package as close to the power and ground
pins as possible. The parasitic inductance in the capacitor
leads can be greatly reduced or eliminated by the use of
surface mount chip capacitors soldered directly onto the
board at the appropriate locations. Decoupling capacitors
need to be of the high K ceramic type with low equivalent
series resistance (ESR), consisting primarily of series induc-
tance and series resistance. Capacitors using Z5U dielectric
have suitable properties and make a good choice for decou-
pling capacitors; they offer minimum cost and effective per-
formance.
8.5 Proper Signal Trace Layout
Although crosstalk cannot be totally eliminated, there are
some design techniques that can reduce system problems
resulting from crosstalk. In any design, the distance that
lines run adjacent to each other should be kept as short as
possible. The best situation is when the lines are perpendic-
ular to each other. Crosstalk problems can also be reduced
by moving lines further apart or by inserting ground lines or
planes between them.
For those situations where lines must run parallel, as in ad-
dress and data buses, the effects of crosstalk can be mini-
mized by line termination. Terminating a line in its character-
istic impedance reduces the amplitude of an initial crosstalk
pulse by 50%. Terminating the line will also reduce the
amount of ringing.
There are several termination schemes which may be used.
They are series, parallel, AC parallel and Thevenin termina-
tions. AC parallel and series terminations are the most use-
ful for low power applications since they do not consume
any DC power. Parallel and Thevenin terminations increase
DC power consumption.
Series terminations are most useful in high-speed applica-
tions where most of the loads are at the far end of the line.
Loads that are between the driver and the end of the line
will receive a two-step waveform. The first wave will be the
incident wave. The amplitude is dependent upon the output
impedance of the driver, the value of the series resistor and
the impedance of the line according to the formula:
VCC c ZOE
VW e
ZOE a RS a ZS
where RS is the series Resistor
ZS is the output impedance of the driver
ZOE is the equivalent line impedance
TL/DD/12857 – 56
FIGURE 35b. Parallel Termination
Parallel terminations are not generally recommended for
CMOS circuits due to their power consumption, which can
exceed the power consumption of the logic itself. The pow-
er consumption of parallel terminations is a function of the
resistor value and the duty cycle of the signal. In addition,
parallel termination tends to bias the output levels of the
driver towards either VCC or ground depending on which
bus the resistor is connected to. While this feature is not
desirable for driving CMOS inputs because the trip levels
are typically VCC/2, it can be useful for driving TTL inputs
where level shifting is desirable in order to interface with
CMOS devices.
AC parallel terminations work well for applications where
the increase in bus delays caused by series terminations are
undesirable. The effects of AC parallel terminations are sim-
ilar to the effects of standard parallel terminations. The ma-
jor difference is that the capacitor blocks any DC current
path and helps to reduce power consumption.
Thevenin terminations are not generally recommended due
to their power consumption. Like parallel terminations, a DC
path to ground is created by the terminating resistors. The
power consumption of a Thevenin termination, though, will
generally be independent of the signal duty cycle. Thevenin
terminations are more applicable for driving CMOS inputs
because they do not bias the output levels as paralleled
terminations do. It should be noted that output lines with
Thevenin terminations should not be left floating since this
will cause the undriven input levels to float between VCC
and ground, increasing power consumption.
TL/DD/12857 – 57
FIGURE 36a. AC Parallel Termination

TL/DD/12857 – 55
FIGURE 35a. Series Termination

The amplitude will be one-half the voltage swing if RS (the

series resistor) plus the output impedance (ZS) of the driver
is equal to the line impedance (ZOE). The second step of
the waveform is the reflection from the end of the line and
will have an amplitude equal to that of the first step. All
devices on the line will receive a valid level only after the TL/DD/12857 – 58
wave has propagated down the line and returned to the FIGURE 36b. Thevenin Termination
driver. Therefore, all inputs will see the full voltage swing
within two times the delay of the line.

25 http://www.national.com
 8.6 Ground Bounce
Observing either one of the following rules is sufficient to
avoid running into any of the problems associated with
ground bounce:
# First, use caution when driving asynchronous TTL-level
inputs from CMOS outputs. Ground bounce glitches may
cause spurious inputs that will alter the state of non-
clocked logic.
# Second, caution when running control lines (set, reset,
load, clock, chip select) which are glitch-sensitive
through the same devices that drive data or address
lines.
When it is not possible to avoid the above conditions, there
are simple precautions available which can minimize ground
bounce noise. These are:
# Choose package outputs that are as close to the ground
pin as possible to drive asynchronous TTL-level inputs.
# Use the lowest VCC possible or separate the power sup-
plies.
# Use board design practices which reduce any additive
noise sources, such as crosstalk, reflections, etc.
8.7 Components
The interference effect by rectifier diodes, typically found in
power supply sections of PCBs, can be minimized by one or
more of the following measures:
# Placing a bypass capacitor in parallel with each rectifier
diode
# Placing a resistor in series with each rectifier diode
# Placing an R-F bypass capacitor to ground from one or
both sides of each rectifier diode
# Operating the rectifier diodes well below their rated cur-
rent capability
TL/DD/12857–59
FIGURE 37a. RF Filtering of Diode
TL/DD/12857–60
FIGURE 37b. Connectors and Cables
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8.8 Cables and Connectors
Several options are available to reduce EMI from a typical
ribbon cable used to interconnect pieces of equipment.
These include:
# Reduce spacing between conductors (h in Figure 37 ) by
reducing the size of wires used and reducing the insula-
tion thickness. (This could have a negative impact on
crosstalk within the cable.)
# Join alternate signal returns together at the connectors
at each end of the cable.
# Twist parallel wire pairs in ribbon cables.
# Shield ribbon cable with metal foil cover (superior to
braid).
# Replace discrete ribbon cable with stripline flexprint ca-
ble.
In the case of joining alternate signal returns, wire N is car-
rying the signal current, IN, whereas its mates, N b 1 and
N a 1 wires are each carrying one half of the return cur-
rents, IN b 1 and IN a 1, respectively. Thus, radiation from
pair N and N b 1 is out of phase with radiation from pair N
and N a 1 and will tend to cancel. In practice, however, the
net radiation is reduced by 20 dB – 30 dB with 30 dB being a
good default value.
The opposite of this is to conserve signal returns by only
using one, or two, wires to service N data lines in a ribbon
cable. For data lines farther from the return line, the differ-
ential mode radiation becomes so great that this cable
tends to maximize EMI radiation. Another disadvantage of
this approach is poor impedance control in the resulting
transmission line. This could result in distortion of pulses
and causes reflections, especially for high-speed logic, and
common return impedance noise in this single ground wire.
Ideally, connectors should have negligible resistance for ob-
vious reasons other than EMI control. They should provide
for foolproof alignment to minimize the possibility of contact
damage over time and use which would increase the resist-
ance and be prone to vibration and shock. The required
force should be adequate to provide good mating between
contacts which will insure low resistance, but should be min-
imized to limit likelihood of damage. Connectors should
mate with little friction to minimize the effects of continual
disconnections and connections increasing the contact re-
sistance with use as the contacts wear out. A contamination
free design should be used to avoid corrosion and oxidation
increasing resistance and susceptibility to shock and vibra-
tion causing intermittent contact.
8.9 Special Considerations with Development Tools
The following set of guidelines have been compiled from the
experiences of the applications team at Embedded Tech-
nologies Division at National Semiconductor. They should
be considered additional techniques and guidelines to be
followed concurrently with the standard ones already pre-
sented. Some are general and some may be specific to de-
velopment systems use.
Ground bounce prevention and minimization techniques
presented in this paper should be strictly adhered to when
using ‘373 type transparent latches on any controller’s ex-
ternal address/data bus. Multiple simultaneously switching
outputs could produce ground bounce significant enough to
26

FIGURE 38a. Alternating Signal Return Minimizes Radiation
FIGURE 38b. Single Signal Return Maximizes Radiation
cause false latching. Observe good EMI planning by locat-
ing the latches as close to the controller as possible. The
use of multi-layer PCBs with good ground planes and follow-
ing appropriate layout techniques is also essential, especial-
ly if emulation will be done at frequencies above 10 MHz.
With the foregoing discussions about ‘‘antenna farms’’, radi-
ated noise and ideal connector characteristics, it becomes
obvious that wire-wrap boards and the use of IC sockets is
absolutely out of the question. The concern here is not so
much EMI affecting the outside world but EMI strangling the
operation of the module itself.
The inputs to the buffers in a ‘244 type octal buffer package
are placed adjacent or side-by-side outputs of other buffers
in the package. This configuration would tend to maximize
the crosstalk or noise coupling from the inputs to the out-
puts. On the other hand, the buffer inputs in a ‘544 type
package are on one side of the package and the outputs are
on the other. The use of these package types in high speed
designs can facilitate board layout to help reduce the ef-
fects of crosstalk.
Use extra heavy ground wires between emulator and target
board. Rely on the ground returns in the emulator cable for
reduction of differential-mode noise radiated from the cable
but heavy-duty help is required for reducing power line im-
pedance in the integrated development system.
Unused controller inputs, most importantly any external in-
terrupts and RDY, must be tied to VCC (or GND) directly or
through a pull-up (or pull-down) resistor. This not only tends
to reduce power consumption, but will avoid noise problems
triggering an unwanted action.
In order to reduce the effects of noise generated by high
speed signal changes, a sort of Frequency Management
technique might be applied. If possible, develop application
hardware and software at a slower crystal operating fre-
quency. If ringing, crosstalk, or other combination of radiat-
ed and conducted noise problems exists, the result may be
27
TL/DD/12857 – 61
TL/DD/12857 – 62
to move the problem from one point in the affected signal
waveform to a different point. Thus, apparent ‘‘noise glitch-
es’’ that caused a latch to erroneously trigger when the in-
put data was still changing, may now come at a time when
they are non-destructive such as at a point when the input
data is now stable.
Some applications require driving the controller clock input,
CKI, with an external signal. Most emulator tools are all
clocked using a crystal network with the controller so that
the generation of the system timing is contained on the tool
itself. Consequently, there is no connection between the
emulator cable connector on the tool and the CKI pin at the
controller. However, when the emulator cable is now insert-
ed into the target board, the target board’s clock signal trav-
eling along the cable couples noise onto adjacent signal
lines causing symptoms pointing to an apparent failure of
the emulator tool. The recommendation is to disable the
clock drive to the CKI pin at the controller pad on the target
board whenever the emulator tool is connected. The emula-
tor tools supply the system clock so there is no need for the
clock on the target and signal crosstalk on the emulator
cable can be greatly reduced with minimal implementation.
If one insists that the emulator tool and the target be syn-
chronous, then bring the clock signal from the target to the
emulator tool external to the emulator cable via twisted wire
pair or coax cable. Remove the clock drive connection to
CKI at the target to prevent the signal from entering the
cable. Finally, remove crystal components on the emulator
tool to prevent problems with the signal.
Connecting boards and modules together to make a totally
unique system in which EMC was practiced is necessary to
ensure little problem with the environment. But, connecting
an emulator tool makes it an entirely new and unique sys-
tem, both in physical and electrical properties. Treat the em-
ulator tool as part of the system during the design phase
and development phase.
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Understanding and Eliminating EMI in Microcontroller Applications
9.0 SUMMARY 4. Engineering Staff, Don White Consultants, Inc., The
The design and construction of an electromagnetically com- role of Cables & Connectors in Control of EMI , EMC
patible PCB does not necessarily require a big change in Technology, July 1982, pp 16-26
current practices. On the contrary, the implementation of 5. Fairchild Semiconductor, Design Considerations , Fair-
EMC principles during the design process can fit in with the child Advanced CMOS Technology Logic Data
ongoing design. When EMC is designed into the board, the Book, 1987, pp 4-3 to 4-12
requirements to shield circuitry, cables, and enclosures, as 6. Fairchild Semiconductor, Understanding and Minimizing
well as other costly eleventh hour surprises, will be drasti- Ground Bounce , Application Note DU-6, August 1987
cally reduced or even eliminated. Without EMC in the design
7. Interference Control Technology, Introduction to EMI/
stage, production can be held up and the cost of the project
RFI/EMC , Course Notebook on Electromagnetic
increases.
Compatibility, August 1988
REFERENCES 8. Violette, Michael F. and J.L., EMI Control in the Design
1. Alkinson, Kenn-Osburn, John-White, Donald, Taming and Layout of Printed Circuit Boards , EMC Technolo-
EMI in Microprocessor Systems , IEEE Spectrum, De- gy, March-April 1986, pp 19-32
cember 1985, pp 30-37 9. Violette, Michael F., Curing Electromagnetic Interfer-
2. Balakrishnan, R.V., Reducing Noise on Microcomputer ence , Radio-Electronics, November 1985, pp 50-56
Buses , National Semiconductor Application Note 10. Wakeman, Larry, High-speed-CMOS Designs Address
337, May 1983 Noise and I/O Levels , National Semiconductor Appli-
3. Brewer, Ron W., Test Methodology to Determine Levels cation Note 375, September 1984
of Conducted and Radiated Emissions from Computer 11. White, Donald R.J., EMI Control Methods and Tech-
Systems , EMC Technology, July 1982, p 10 niques . Electromagnetic Interference and Compati-
bilityÐVol 3, copyright 1988 by Interference Control
Technologies

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
AN-1050

National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: a49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2308
Arlington, TX 76017 Email: europe.support @ nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: a49 (0) 180-530 85 85 Tsimshatsui, Kowloon
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http://www.national.com Italiano Tel: a49 (0) 180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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