This Set of Digital Electronic1-Merged-merged-merged

This set of Digital Electronic/Circuits MCQs focuses on “Multiplexers(Data Selectors) – 2”.
1. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
View AnswerAnswer: c
Explanation: 4 to 1 multiplexer would have 4 inputs (X0, X1, X2, X3), 2 select lines (C1, C0) and 1 output (M). It can be
observed from this diagram:
advertisement
2. The two input MUX would have ____________
a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
View AnswerAnswer: a
Explanation: The two input multiplexer would have n select lines in 2n. Thus n =1. Therefore, it has 1 select line.
3. A combinational circuit that selects one from many inputs are ____________
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
View AnswerAnswer: d
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. Whereas, a
combinational circuit that divides one input into multiple outputs is known as Demultiplexer.
4. 4 to 1 MUX would have ____________
a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
5. Which of the following circuit can be used as parallel to serial converter?
a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. In multiplexer,
different inputs are inserted parallely and then it gives one output which is in serial form.
advertisement
6. A combinational circuit is one in which the output depends on the ____________
a) Input combination at the time
b) Input combination and the previous output
c) Input combination at that time and the previous input combination
d) Present output and the previous output
Explanation: A combinational circuit is one in which the output depends on the input combination at the time,
whereas, a sequential circuit is one in which the output depends on present input as well past outputs.
7. Without any additional circuitry an 8:1 MUX can be used to obtain ____________
a) Some but not all Boolean functions of 3 variables
b) All function of 3 variables but none of 4 variables
c) All functions of 3 variables and some but not all of 4 variables
d) All functions of 4 variables
Explanation: A 2^n:1 MUX can implement all logic functions of (n+1) variables without any additional circuitry. Thus
8:1 MUX can implement all logic functions of (3+1) variables, for 4 variables there are 16 possible combinations. So
to use 8:1 MUX use 3 inputs as select lines of MUX and the 4th input as input of MUX.
8. A basic multiplexer principle can be demonstrated through the use of a ____________
a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. A basic multiplexer
principle can be demonstrated through the use of a rotary switch. Because rotary switch gives one output
corresponding to their inputs.
9. One multiplexer can take the place of ____________
a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. One multiplexer can
take the place of several SSI logic gates or combinational logic circuits because it has a lot of functions to perform
different operations.
advertisement
10. The inputs/outputs of an analog multiplexer/demultiplexer are ____________
a) Bidirectional
b) Unidirectional
c) Even parity
d) Binary-coded decimal
Explanation: One multiplexer can be used as demultiplexer. Hence, it is called bidirectional or two-way transmission.
11. If enable input is high then the multiplexer is ______________

a) Enable
b) Disable
c) Saturation
d) High Impedance
View AnswerAnswer: b
Explanation: If enable input is high then the multiplexer is disabled because enable input is in inverted mode always
(i.e. E’).
12. What is data routing in a multiplexer?
a) It spreads the information to the control unit
b) It can be used to route data from one of several source to destination
c) It is an application of multiplexer
d) It can be used to route data and it is an application of multiplexer
Explanation: Multiplexing means passing more than one data through the same channel. Data routing is an
application of multiplexer and it can be used to route data from one of several source to destination.
Sanfoundry Global Education & Learning Series – Digital Circuits.
advertisement
To practice all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple Choice Questions
and Answers.
Participate in the Sanfoundry Certification contest to get free Certificate of Merit. Join our social networks below and
stay updated with latest contests, videos, internships and jobs!
Telegram | Youtube | LinkedIn | Instagram | Facebook | Twitter | Pinterest
Youtube | LinkedIn | Instagram | Facebook | Twitter | Pinterest

« Prev - Digital Circuits Questions and Answers – Multiplexers (Data Selectors) – 1» Next - Digital Circuits Questions
and Answers – Demultiplexers (Data Distributors) – 1This set of Digital Electronics/Circuits Multiple Choice Questions
& Answers (MCQs) focuses on “Demultiplexers (Data Distributors) – 1”.
1. The word demultiplex means ___________
a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor
Explanation: The word demultiplex means “one into many” and distributor. A demultiplexer sends a single input to
multiple outputs, depending on the select lines. It is clear from the diagram:
advertisement
2. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For one input,
the demultiplexer gives several outputs. That is why it is called a data distributor.
3. Most demultiplexers facilitate which type of conversion?
a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. Demultiplexer
converts single input into multiple outputs.
4. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. Therefore, for 1:4
demultiplexer, 2 select lines are required.
5. In a multiplexer the output depends on its ___________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As the select
input changes, the output of the multiplexer varies according to that input.
advertisement
6. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be ___________
a) Y0
b) Y1
c) Y2
d) Y3
Explanation: It can be calculated from the figure shown below:
For C0 =1 and C1 =0, Y1 will be the output as 0 and 1 are the bit combinations of 1.
a) Y0
b) Y1
c) Y2
d) Y3
8. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this case n = 3
since 23 = 8.
9. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Explanation: The number of AND gates required will be equal to the number of outputs in a demultiplexer, which are
8.
advertisement
10. The output Q4 of this 1-to-8 demultiplexer is ____________
a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
Explanation: The output Y4 = Q2.(Q1)’.(Q0)’.I. since the bit combinations of 4 are 100.
11. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.
To practice all areas of Digital Circuits, here is complete set of 1000+ Multiple Choice Questions and Answers.
advertisement
and Answers – Demultiplexers (Data Distributors) – 2This set of Digital Electronic/Circuits Multiple Choice Questions
& Answers focuses on “Demultiplexers(Data Distributors) – 2”.
d) Single input gives single output
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
4. In a multiplexer the output depends on its ____________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
5. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ____________
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
To practice all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple Choice Questions and
Answers.
advertisement
« Prev - Digital Circuits Questions and Answers – Demultiplexers (Data Distributors) – 1» Next - Digital Circuits
Questions and Answers – Liquid Crystal DisplaysThis set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Liquid Crystal Displays”.
1. The full form of LCD is ____________
a) Liquid Crystal Display
b) Liquid Crystalline Display
c) Logical Crystal Display
d) Logical Crystalline Display
Explanation: The full form of LCD is “Liquid Crystal Display”. They provide thinner displays as compared to Cathode
Ray Tubes.
advertisement
2. The optical properties of liquid crystals depend on the direction of ___________
a) Air
b) Solid
c) Light
d) Water
Explanation: The optical properties of liquid crystals depend on the direction of light travels through a layer of the
material.
3. By which properties, the orientation of molecules in a layer of liquid crystals can be changed?
a) Magnetic field
b) Electric field
c) Electromagnetic field
d) Gallois field
Explanation: In LCD, the electric field is induced by a small electric voltage applied across it; Due to which the
orientation of molecules in a layer of liquid crystals can be changed.
4. Electro-optical effect is produced in ___________
a) LED
b) LCD
c) OFC
d) OLED
Explanation: An electric field (induced by a small electric voltage) can change the orientation of molecules in a layer
of liquid crystal and thus affect its optical properties. Such a process is termed an electro-optical effect, and it forms
the basis for LCDs.
5. The direction of electric field in an LCD is determined by ___________
a) the molecule’s chemical structure

b) Crystalline surface structure
c) Molecular Orbital Theory
d) Quantum Cellular Automata
Explanation: For LCDs, the change in optical properties results from orienting the molecular axes either along or
perpendicular to the applied electric field, the preferred direction being determined by the details of the molecule’s
chemical structure.
advertisement
6. The first LCDs became commercially available in ___________
a) 1950s
b) 1980s
c) 1960s
d) 1970s
Explanation: The first LCDs became commercially available in the late 1960s and were based on a light-scattering
effect known as the dynamic scattering mode.
7. LCDs operate from a voltage ranges from ___________
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
Explanation: LCDs operate from a voltage ranges from 3 to 15V rms. They provide thinner displays as compared to
Cathode Ray Tubes.
8. LCDs operate from a frequency ranges from ___________
a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
d) None of the Mentioned
Explanation: LCDs operate from a frequency ranges from 30Hz to 60Hz. LCDs operate from a voltage ranges from 3
to 15V rms. They provide thinner displays as compared to Cathode Ray Tubes.
9. In 7 segment display, how many LEDs are used?
a) 8
b) 7
c) 10
d) 9
Explanation: There are 7 LEDs used in a 7 segment display. 7 segment displays are used for displaying decimal
numerals which are comparatively convenient to dot matrix displays.
advertisement
10. What is the backplane in LCD?
a) The ac voltage applied between segment and a common element
b) The dc voltage applied between segment and a common element
c) The amount of power consumed
d) For adjusting the intensity of the LCD
Explanation: The ac voltage applied between the segment and a common element is called the backplane(bp). In
which each segment is driven by an EX-OR gate.

Questions and Answers – EncodersThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Encoders”.
1. How many inputs will a decimal-to-BCD encoder have?
a) 4
b) 8
c) 10
d) 16
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus
producing the binary equivalent of the input. Thus, a Decimal-to-bcd converter has decimal values as inputs which
range from 0-9. So, a total of 10 inputs are there in a decimal-to-BCD encoder.
advertisement
2. How many outputs will a decimal-to-BCD encoder have?
a) 4
b) 8
c) 12
d) 16
producing the binary equivalent of the input. Thus, a decimal to BCD encoder has 4 outputs.
3. How is an encoder different from a decoder?
a) The output of an encoder is a binary code for 1-of-N input
b) The output of a decoder is a binary code for 1-of-N input
c) The output of an encoder is a binary code for N-of-1 output
d) The output of a decoder is a binary code for N-of-1 output
producing the binary equivalent of the input. It performs the opposite operation of a decoder which results in 2n
outputs from n inputs. Thus, an encoder different from a decoder because of the output of an encoder is a binary
code for 1-of-N input.
4. If we record any music in any recorder, such types of process is called ___________
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
Explanation: If we record any music in any recorder, it means that we are giving data to a recorder. So, such process
is called encoding. Getting back the music from the recorded data is known as decoding.
5. Can an encoder be a transducer?
a) Yes
b) No
c) May or may not be
d) Both are not even related slightly
Explanation: Of course, a transducer is a device that has the capability to emit data as well as to accept. Transducer
converts signal from one form of energy to another.
advertisement
6. How many OR gates are required for a Decimal-to-bcd encoder?
a) 2
b) 10
c) 3
d) 4
Explanation: An encoder is a combinational circuit encoding the information of 2^n input lines to n output lines, thus
producing the binary equivalent of the input.
This is clear from the diagram that it requires 4 OR gates:
7. How many OR gates are required for an octal-to-binary encoder?
a) 3
b) 2
c) 8
d) 10
producing the binary equivalent of the input. Thus, in octal to binary encoder there are 8 (=23) inputs, thus 3 output
lines.
8. For 8-bit input encoder how many combinations are possible?
a) 8
b) 2^8
c) 4
d) 2^4
producing the binary equivalent of the input. There are 28 combinations are possible for an 8-bit input encoder but
out of which only 8 are used using 3 output lines. It is a disadvantage of encoder.
9. The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using additional input known as
___________
a) Enable
b) Disable
c) Strobe
d) Clock
Explanation: Such problems are resolved by using enable input, which behaves as active if it gets 0 as input since it is
an active-low pin.
advertisement
10. Can an encoder be called a multiplexer?
a) No
b) Yes
c) Sometimes
d) Never
Explanation: A multiplexer or MUX is a combination circuit that contains more than one input line, one output line
and more than one selection line. Whereas, an encoder is also considered a type of multiplexer but without a single
output line and without any selection lines.
11. If two inputs are active on a priority encoder, which will be coded on the output?
a) The higher value
b) The lower value
c) Neither of the inputs
d) Both of the inputs
producing the binary equivalent of the input. If two inputs are active on a priority encoder, the input of higher value
will be coded in the output.
advertisement
« Prev - Digital Circuits Questions and Answers – Liquid Crystal Displays» Next - Digital Circuits Questions and
Answers – Parity Generators/Checkers – 1This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Parity Generators/Checkers – 1”.
1. How many outputs are present in a BCD decoder?
a) 4
b) 5
c) 15
d) 10
Explanation: A binary decoder is a combinational logic circuit which decodes binary information from n-inputs to a
maximum of 2n outputs. A BCD to Decimal decoder has 10 number of outputs because the decimal digit’s range is
from 0 to 9.
advertisement
2. Which digital system translates coded characters into a more useful form?
a) Encoder
b) Display
c) Counter
d) Decoder
maximum of 2n outputs. Decoder converts the coded characters into our required data form.
3. What control signals may be necessary to operate a 1-line-to-16 line decoder?
a) Flasher circuit control signal
b) A LOW on all gate enable inputs
c) Input from a hexadecimal counter
d) A HIGH on all gate enable circuits
Explanation: A LOW on all gate enable inputs is necessary to operate a 1-line-to-16 line decoder because enable pins
are usually, active-low pins.
4. How many inputs are required for a 1-of-10 BCD decoder?
a) 4
b) 8
c) 10
d) 2
maximum of 2n outputs. Therefore, for a BCD to decimal decoder, No. of inputs = 4 such that number of outputs is
<= 2n.
5. A BCD decoder will have how many rows in its truth table?
a) 10
b) 9
c) 8
d) 3
maximum of 2n outputs. Thus, BCD decoder will have 10 rows as it’s input ranges from 0 to 9.
advertisement
6. How many possible outputs would a decoder have with a 6-bit binary input?
a) 32
b) 64
c) 128
d) 16
Explanation: The possible outputs would be: 2n = 64 (Since n = 6 here).
7. Which is the way to convert BCD to binary using the hardware approach?
a) By using MSI IC circuits
b) By using a keyboard encoder
c) By using an ALU
d) By using UART
Explanation: One way to convert BCD to binary using the hardware approach is MSI (medium scale integration) IC
circuits.
8. How many inputs are required for a 1-of-16 decoder?
a) 2
b) 16
c) 8
d) 4
maximum of 2n outputs. Here, number of outputs = 16.
16 = 24 = 2n. Thus, number of inputs is 4.
9. A truth table with output columns numbered 0–15 may be for which type of decoder IC?
a) Hexadecimal 1-of-16
b) Dual octal outputs
c) Binary-to-hexadecimal
d) Hexadecimal-to-binary
Explanation: A binary decoder is a combinational logic circuit that decodes binary information from n-inputs to a
maximum of 2n outputs. A truth table with output columns numbered 0–15 may be for Hexadecimal 1-of-16.
Because hexadecimal occupies less space in a system.
advertisement
10. How can the active condition (HIGH or LOW) or the decoder output be determined from the logic
symbol?
a) A bubble indicates active-HIGH
b) A bubble indicates active-LOW
c) A triangle indicates active-HIGH
d) A triangle indicates active-LOW
Explanation: A bubble indicates active-LOW in a decoder always. Enable pin of the decoder is usually active-LOW and
is triggered on the input being at 0.
« Prev - Digital Circuits Questions and Answers – Encoders» Next - Digital Circuits Questions and Answers – Parity
Generators/Checkers – 2This set of Digital Electronic/Circuits online test focuses on “Parity Generators/Checkers –
2”.
1. Which error detection method uses one’s complement arithmetic?
a) Simple parity check
b) Two-dimensional parity check
c) CRC
d) Checksum
Explanation: A checksum is an error detection method used for the purpose of detecting errors that may have been
incorporated during transmission. The checksum can be generated simply by adding bits. Hence, one’s complement
arithmetic uses checksum.
advertisement
2. Which error detection method consists of just one redundant bit per data unit?
c) CRC
d) Checksum
Explanation: A parity checker is an error detection method used for the purpose of detecting errors that may have
been incorporated during transmission. Simple parity check method consists of just one redundant bit per data unit.
It is again classified as even parity and odd parity.
3. How many types of parity bits are found?
a) 2
b) 3
c) 4
d) 1
Explanation: There are two types of parity bits, namely even parity and odd parity. In even parity, a 1 bit is added in
order to make a group of data bits have even number of 1s. While, in odd parity, a 1 bit is added in order to make a
group of data bits have odd number of 1s.
4. What is a parity bit?
a) An error detection is achieved by adding an extra bit
b) After addition, the carry is found
c) Bit generated during data transmission
d) After addition, the total number of bits
Explanation: A simple form of error detection is achieved by adding an extra bit to the transmitted word. The
additional bit is known as parity bits.
5. The BCD number 101011 has _______ priority.
a) Even
b) Odd
c) Both even and odd
d) Undefined
Explanation: The given BCD number 101011 has even priority because it has an even number of 1’s (i.e. 4).
advertisement
6. Which error detection method involves polynomials?
b) CRC
c) Two-dimensional parity check
d) Checksum
Explanation: Cyclic Redundancy Check(CRC) involves parity check polynomials. In the even parity case of CRC, the 1-
bit is generated by checking the polynomial x+1.
7. The odd parity output of decimal number 9 is ___________

a) 0
b) 1
c) 1001
d) 0011
Explanation: The odd parity output of decimal number 9 is 1 because the BCD number for 9 is 1001 and it has even
number of 1’s.
8. If odd parity is used for ASCII error detection, the number of 0s per 8-bit symbol is _______
a) Indeterminate
b) 42
c) Even
d) Odd
Explanation: Odd parity bit is 1 when the group of data bits consists of even number of 1s. So to make the group of
data bits have odd number of 1s, 1 extra bit is added. If odd parity is used for ASCII error detection, the number of 0s
per 8-bit symbol is indeterminate because it is applicable only for 6-bit symbol.
9. Which error detection method can detect a single-bit error?
c) CRC
d) Checksum
Explanation: A single-bit error can be detected by using two-dimensional parity check method. Since it converts the
4-bit number into 8-bit and count the number of one’s.
advertisement
10. Which gates are ideal for checking the parity bits?
a) AND
b) NAND
c) EX-OR
d) EX-NOR
Explanation: Exclusive-OR gates are ideal for checking the parity of a binary number because they produce an output
when the input has an odd number of 1’s. Therefore, an even-parity input to an EX-OR gate produces a low output,
while an odd parity input produces a high output. While, in case of AND, it produces high output when all inputs are
1 else low. Whereas, NAND, does the opposite, by producing low output when all inputs are 1 else high.
To practice all areas of Digital Electronic Circuits for online test, here is complete set of 1000+ Multiple Choice
Questions and Answers.
« Prev - Digital Circuits Questions and Answers – Parity Generators/Checkers – 1» Next - Digital Circuits Questions
and Answers – Code ConvertersThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs)
focuses on “Code Converters”.
1. A code converter is a logic circuit that _____________
a) Inverts the given input
b) Converts into decimal number
c) Converts data of one type into another type
d) Converts to octal
Explanation: A code converter is a logic circuit that changes data presented in one type of binary code to another
type of binary code.
advertisement
2. Use the weighting factors to convert the following BCD numbers to binary ___________
0101 0011 & 0010 0110 1000
a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
d) 101011 001100001
Explanation: Firstly, convert every 4 sets of binary to decimal from the given: 0101=5, 0011=3. Then convert 53 to
binary, which will give 110101. Again, do the same with the next 4 set of binary digits.
3. The primary use for Gray code is ___________
a) Coded representation of a shaft’s mechanical position
b) Turning on/off software switches
c) To represent the correct ASCII code to indicate the angular position of a shaft on rotating machinery
d) To convert the angular position of a shaft on rotating machinery into hexadecimal code
Explanation: Gray code is useful because only one bit changes at a time, which is implemented easily in Coded
representation of a shaft’s mechanical position. In Gray Code, every sequence of successive bits differs by 1 bit only.
4. Code is a symbolic representation of ___________
a) Discrete information
b) Continuous information
c) Decimal information into binary
d) Binary information into decimal
Explanation: Code is a symbolic representation of discrete information. Codes can be anything like numbers, letter or
words, written in terms of group of symbols.
advertisement
5. One way to convert BCD to binary using the hardware approach is ___________
a) With MSI IC circuits
b) With a keyboard encoder
c) With an ALU
d) UART
Explanation: One way to convert BCD to binary using the hardware approach is MSI IC (i.e. medium scale integration)
circuits.
6. Why is the Gray code more practical to use when coding the position of a rotating shaft?
a) All digits change between counts
b) Two digits change between counts
c) Only one digit changes between counts
d) Alternate digit changes between counts
Explanation: The Gray code is more practical to use when coding the position of a rotating shaft because only one
digit changes between counts that is reflected to the next count.
7. Reflected binary code is also known as ___________
a) BCD code
b) Binary code
c) ASCII code
d) Gray Code
Explanation: The reflected binary code is also known as gray code because one digit reflected to the next bit. In Gray
Code, every sequence of successive bits differs by 1 bit only.
8. Why do we use gray codes?
a) To count the no of bits changes
b) To rotate a shaft
c) Error correction
d) Error Detection
Explanation: Today, Gray codes are widely used to facilitate error correction in digital communications such as digital
terrestrial television and some cable TV systems.
advertisement
9. Earlier, reflected binary codes were applied to ___________
a) Binary addition
b) 2’s complement
c) Mathematical puzzles
d) Binary multiplication
Code, every sequence of successive bits differs by 1 bit only. Reflected binary codes were applied to mathematical
puzzles before they became known to engineers.
10. The binary representation of BCD number 00101001 (decimal 29) is ___________
a) 0011101
b) 0110101
c) 1101001
d) 0101011
Explanation: The given BCD number 00101001 has three 1s. So, it can be rewritten as 0000001-1, 0001000-8,
0010100-20 and after addition, we get 0011101 as output.
11. Convert binary number into gray code: 100101.
a) 101101
b) 001110
c) 110111
d) 111001
Explanation: : Conversion from Binary To Gray Code:
1 (XOR) 0 (XOR) 0 (XOR) 1 (XOR) 0 (XOR) 1
↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1
advertisement
To practice all areas of Digital Circuits, here is complete set of 1000+ Multiple Choice Questions and
Answers.
and Answers – Magnitude ComparatorThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Magnitude Comparator”.
1. All the comparisons made by comparator is done using ____________
a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and results
whether one input is greater, lesser or equal to the other input. Because, all the input is compared to each other,
therefore it is possible only by using 1 circuit.
advertisement
2. One that is not the outcome of magnitude comparator is ____________
a) a > b
b) a – b
c) a < b
d) a = b
whether one input is greater, lesser or equal to the other input. In a digital comparator, only 3 outputs are possible
(i.e. A = B, A > B, A < B). So, a – b is an incorrect option.
3. If two numbers are not equal then binary variable will be ____________
a) 0
b) 1
c) A
d) B
(i.e. A = B, A >B, A < B). Other than this, the output will be 0.
4. How many inputs are required for a digital comparator?
a) 1
b) 2
c) 3
d) 4
whether one input is greater, lesser or equal to the other input. Thus, there are two inputs required for a digital
comparator (i.e. A & B).
5. In a comparator, if we get input as A>B then the output will be ____________
a) 1
b) 0
c) A
d) B
whether one input is greater, lesser or equal to the other input. If A > B, it means that it satisfies one of the condition
among three. Hence the output will be 1.
advertisement
6. Which one is a basic comparator?
a) XOR
b) XNOR
c) AND
d) NAND
Explanation: Generally, an XNOR outputs high for even number of 1s or all 0s and outputs low for otherwise. Thus,
an XNOR gate is a basic comparator, because its output is “1” only if its two input bits are equal.
7. Comparators are used in ____________
a) Memory
b) CPU
c) Motherboard
d) Hard drive
Explanation: Comparators are used in the central processing unit (CPUs). Because all the arithmetic and logical
operations are performed in the ALU(Arithmetic Logic Unit) part of the CPU.
8. A circuit that compares two numbers and determines their magnitude is called ____________
a) Height comparator
b) Size comparator
c) Comparator
d) Magnitude comparator
whether one input is greater, lesser or equal to the other input. A circuit that compares two numbers and determine
their magnitude is called magnitude comparator.
9. A procedure that specifies finite set of steps is called ____________
a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
Explanation: A procedure that specifies finite set of steps is called algorithm, While a flowchart is a pictorial
representation of the algorithm.
advertisement
10. How many types of digital comparators are?
a) 1
b) 2
c) 3
d) 4
Explanation: There are two main types of Digital Comparator available and these are: Identity Comparator &
Magnitude Comparator. Identity Comparator checks only the equality of the inputs and thus has one output
terminal. While Magnitude Comparator checks for greater than, less than as well as equality of the inputs, and thus
has 3 output terminals.
11. An identify comparator is defined as a digital comparator which has ____________
a) Only one output terminal
b) Two output terminals
c) Three output terminals
d) No output terminal
Explanation: An Identity Comparator is a digital comparator that has only one output terminal for when A = B either
“HIGH” A = B = 1 or “LOW” A = B = 0.
12. A magnitude comparator is defined as a digital comparator which has ____________
Explanation: A Magnitude Comparator is a digital comparator which has three output terminals, one each for
equality, A = B greater than, A > B and less than A < B.
13. The purpose of a Digital Comparator is ____________
a) To convert analog input into digital
b) To create different outputs
c) To add a set of different numbers
d) To compare a set of variables or unknown numbers
whether one input is greater, lesser or equal to the other input. The purpose of a Digital Comparator is to compare a
set of variables or unknown numbers, for example A (A1, A2, A3, …. An, etc) against that of a constant or unknown
value such as B (B1, B2, B3, …. Bn, etc) and produce an output condition or flag depending upon the result of the
comparison.
advertisement
14. TTL 74LS85 is a _____________
a) 1-bit digital comparator
b) 4-bit magnitude comparator
c) 8-bit magnitude comparator
d) 8-bit word comparator
Explanation: TTL 74LS85 is a 4-bit magnitude comparator.
« Prev - Digital Circuits Questions and Answers – Code Converters» Next - Digital Circuits Questions and Answers –
LatchesThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Latches”.
1. A latch is an example of a ___________
a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) 555 timer
Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one in which the circuit is
stable in either of two states. It can be flipped from one state to the other state and vice-versa.
advertisement
2. Latch is a device with ___________
a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states
Explanation: Since a latch works on the principal of bistable multivibrator. A Bistable multivibrator is one in which
the circuit is stable in either of two states. It can be flipped from one state to the other state and vice-versa. So a
latch has two stable states.
3. Why latches are called memory devices?
a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store infinite amount of data
Explanation: Latches can be memory devices, and can store one bit of data for as long as the device is powered.
Once device is turned off, the memory gets refreshed.
4. Two stable states of latches are ___________
a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high input
Explanation: A latch has two stable states, following the principle of Bistable Multivibrator. There are two stable
states of latches and these states are high-output and low-output.
5. How many types of latches are ___________
a) 4
b) 3
c) 2
d) 5
Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch is a modified form of SR
latch whereas, T latch is an advanced form of JK latch.
advertisement
6. The full form of SR is ___________
a) System rated
b) Set reset
c) Set ready
d) Set Rated
Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.
7. The SR latch consists of ___________
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states.
The diagram of SR latch is shown below:
8. The outputs of SR latch are ___________
a) x and y
b) a and b
c) s and r
d) q and q’
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The inputs
of SR latch are s and r while outputs are q and q’. It is clear from the diagram:
9. The NAND latch works when both inputs are ___________
a) 1
b) 0
c) Inverted
d) Don’t cares
Explanation: The NAND latch works when both inputs are 1. Since both of the inputs are inverted in a NAND latch.
advertisement
10. The first step of the analysis procedure of SR latch is to ___________
a) label inputs
b) label outputs
c) label states
d) label tables
Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so because the flip flops have
inverting gates inside them, hence in order to have both Q and Q complement available, we have atleast one output
labelled.
11. The inputs of SR latch are ___________
a) x and y
b) a and b
c) s and r
d) j and k
12. When a high is applied to the Set line of an SR latch, then ___________
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) Both Q and Q’ go high
Explanation: S input of an SR latch is directly connected to the output Q. So when a high is applied Q output goes
high and Q’ low.
13. When both inputs of SR latches are low, the latch ___________
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
Explanation: When both inputs of SR latches are low, the latch remains in it’s present state. There is no change in
output.
advertisement
14. When both inputs of SR latches are high, the latch goes ___________
a) Unstable
b) Stable
c) Metastable
d) Bistable
Explanation: When both gates are identical and this is “metastable”, and the device will be in an undefined state for
an indefinite period.
« Prev - Digital Circuits Questions and Answers – Magnitude Comparator» Next - Digital Circuits Questions and
Answers – Flip Flops – 1This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Flip Flops – 1”.
1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration
feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are directly
connected to the other’s output. Such types of structure is called cross coupling and due to which latches remain in
the latched condition.
advertisement
2. One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise
caused during the switching of electronic devices.
3. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State
occurs at both S and R being at 1.
4. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle,
it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K flip-flop has 4 stable states:
Latch, Reset, Set and Toggle.
5. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous
output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero. Like SR flip-
flop, the D-flip-flop also have an invalid state at both inputs being 1.
advertisement
6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates

Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling
means the output of second gate is fed to the input of first gate and vice-versa.
7. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past
outputs are called ________________
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at
any instant of time depends only on the present input but also on the past outputs are called sequential circuits.
Unlike sequential circuits, if output depends only on the present state, then it’s known as combinational circuits.
8. Whose operations are more faster among the following?
c) Latches
d) Flip-flops
Explanation: Combinational circuits are often faster than sequential circuits. Since the combinational circuits do not
require memory elements whereas the sequential circuits need memory devices to perform their operations in
sequence. Latches and Flip-flops come under sequential circuits.
9. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or
unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous
Sequential Circuits function in the absence of a clock signal.
advertisement
10. The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
d) Adder
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable of storing
one bit of information.
11. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second
output Q’ = 1 and vice versa.
12. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.
13. The output of latches will remain in set/reset untill ___________
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the state.
advertisement
14. What is a trigger pulse?
a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.
15. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
Explanation: The cross-coupled connections from the output of one gate to the input of the other gate constitute a
feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits.
Moreover, they are referred to as asynchronous because they function in the absence of a clock pulse.
« Prev - Digital Circuits Questions and Answers – Latches» Next - Digital Circuits Questions and Answers – Flip Flops
– 2This set of Digital Electronic/Circuits online quiz focuses on “Flip Flops – 2”.
1. What is an ambiguous condition in a NAND based S’-R’ latch?
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this
condition is called an ambiguous/forbidden state. This state is also known as an Invalid state as the system goes into
an unexpected situation.
advertisement
2. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________
a) No change
b) Set
c) Reset
d) Forbidden
Explanation: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the state. It remains in its prior
state. This state is used for the storage of data.
3. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
d) Both a D latch and an inverter at its input
Explanation: A NAND based S’-R’ latch can be converted into S-R latch by placing either a D latch or an inverter at its
input as it’s operations will be complementary.
4. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________
a) The inputs of NOR latch are 0 but 1 for NAND latch
b) The inputs of NOR latch are 1 but 0 for NAND latch
c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
d) The output of NOR latch is 1 but 0 for NAND latch
Explanation: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0 but 1 for NAND latch.
5. The characteristic equation of S-R latch is ____________
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the
truth table. The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R’.
advertisement
6. The difference between a flip-flop & latch is ____________
a) Both are same
b) Flip-flop consist of an extra output
c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one
Explanation: Flip-flop is a modified version of latch. To determine the changes in states, an additional control input is
provided to the latch.
7. How many types of flip-flops are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced version of S-R flip-flop,
while T flip-flop is an advanced version of J-K flip-flop.
8. The S-R flip flop consist of ____________
a) 4 AND gates
b) Two additional AND gates
c) An additional clock input
d) 3 AND gates
Explanation: The S-R flip flop consists of two additional AND gates at the S and R inputs of S-R latch.
9. What is one disadvantage of an S-R flip-flop?
a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State
Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are high, which is referred to
as Invalid State.
advertisement
10. One example of the use of an S-R flip-flop is as ____________
a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as binary
storage element. It functions as memory storage during the No Change State.
11. When is a flip-flop said to be transparent?
a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input
Explanation: Flip-flop have the property of responding immediately to the changes in its inputs. This property is
called transparency.
12. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH

c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Explanation: Edge triggered device will follow when there is transition. It is a positive edge triggered when transition
takes place from low to high, while, it is negative edge triggered when the transition takes place from high to low.
13. What is the hold condition of a flip-flop?
a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
Explanation: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It is the No Change State
or Memory Storage state if a flip-flop.
advertisement
14. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0,
the latch will be ________
a) SET
b) RESET
c) Clear
d) Invalid
Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it remains in
reset. If S=1, R=0, the flip flop is at the set condition.
15. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the
_____________
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit
Explanation: The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the
edge-detection circuit.
To practice all areas of Digital Electronic Circuits for online quizzes, here is complete set of 1000+ Multiple Choice
« Prev - Digital Circuits Questions and Answers – Flip Flops – 1» Next - Digital Circuits Questions and Answers – Flip
Flops – 3This set of Digital Electronic/Circuits question bank focuses on “Flip Flops – 3”.
1. Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of
inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
Explanation: Since, both inputs of the D flip-flop are connected through an inverter. And this causes reduction in the
number of inputs.
advertisement
2. The characteristic of J-K flip-flop is similar to _____________
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
d) Gated T flip-flop
Explanation: In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same behaviour is shown by J-K
flip-flop.
3. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
Explanation: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two AND gates.
4. How is a J-K flip-flop made to toggle?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Explanation: When j=k=1 then the race condition is occurs that means both output wants to be HIGH. Hence, there is
toggle condition is occurs, where 0 becomes 1 and 1 becomes 0. That is device is either set or reset.
5. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________
a) Parity error checking
b) Ones catching
c) Digital discrimination
d) Digital filtering
Explanation: Ones catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a
glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0’s catching.
advertisement
6. In J-K flip-flop, “no change” condition appears when ___________
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
Explanation: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.
7. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave
Explanation: The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles
whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-
triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to
time period and hence frequency gets halved.
8. What is the significance of the J and K terminals on the J-K flip-flop?
a) There is no known significance in their designations
b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J input is also
HIGH
c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
d) All of the other letters of the alphabet are already in use
Explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit. In J&K flip-
flops, the invalid state problem is resolved, thus leading to the toggling of states.
9. On a J-K flip-flop, when is the flip-flop in a hold condition?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Explanation: At J=0 k=0 output continues to be in the same state. This is the memory storing state.
advertisement
10. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input
clock pulses, the binary count is ________
a) 00
b) 11
c) 01
d) 10
Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used. So mod = 22 = 4). So after
4 clock pulses the O/P repeats i.e. 00.
11. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is
32 kHz, the output frequency (fout) is ________
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
Explanation: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:- fourth flip-flop. Since
the output frequency is determined on basis of the 4th flip-flop.
12. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock
frequency of 20.48 MHz.
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
Explanation: 12 flip flops = 212 = 4096
Input Clock frequency = 20.48*106 = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.
13. How many flip-flops are in the 7475 IC?
a) 2
b) 1
c) 4
d) 8
Explanation: There are 4 flip-flops used in 7475 IC and those are D flip-flops only.
advertisement
To practice Digital Electronic Circuits question bank, here is complete set of 1000+ Multiple Choice Questions and
Answers.
« Prev - Digital Circuits Questions and Answers – Flip Flops – 2» Next - Digital Circuits Questions and Answers – D
Flip FlopThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “D Flip Flop”.
1. In D flip-flop, D stands for _____________
a) Distant
b) Data
c) Desired
d) Delay
Explanation: The D of D-flip-flop stands for “data”. It stores the value on the data line.
advertisement
2. The D flip-flop has _______ input.
a) 1
b) 2
c) 3
d) 4
Explanation: The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.
3. The D flip-flop has ______ output/outputs.
a) 2
b) 3
c) 4
d) 1
Explanation: The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one input. The D of D-flip-flop
stands for “data”. It stores the value on the data line.
4. A D flip-flop can be constructed from an ______ flip-flop.
a) S-R
b) J-K
c) T
d) S-K
Explanation: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter between S and R and
assigning the symbol D to the S input.
5. In D flip-flop, if clock input is LOW, the D input ___________
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
Explanation: In D flip-flop, if clock input is LOW, the D input has no effect, since the set and reset inputs of the NAND
flip-flop are kept HIGH.
advertisement
6. In D flip-flop, if clock input is HIGH & D=1, then output is ___________
a) 0
b) 1
c) Forbidden
d) Toggle
Explanation: If clock input is HIGH & D=1, then output is 0. It can be observed from this diagram:
7. Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?
a) The logic level at the D input is transferred to Q on NGT of CLK
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
c) The Q output is ALWAYS identical to the D input when CLK = PGT
d) The Q output is ALWAYS identical to the D input
Explanation: By the truth table of D flip flop, we can observe that Q always depends on D. Hence, for every negative
trigger pulse, the logic at input D is shifted to Output Q.
8. Which of the following is correct for a gated D flip-flop?
a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH
Explanation: If clock is high then the D flip-flop operate and we know that input is equals to output in case of D flip-
flop. It stores the value on the data line.
9. With regard to a D latch ________
a) The Q output follows the D input when EN is LOW
b) The Q output is opposite the D input when EN is LOW
c) The Q output follows the D input when EN is HIGH
d) The Q output is HIGH regardless of EN’s input state
Explanation: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop output follows the input.
It stores the value on the data line.
advertisement
10. Which of the following is correct for a D latch?
b) Q output follows the input D when the enable is HIGH
d) The output complement follows the input when enabled
Explanation: If the clock is HIGH then the D flip-flop operates and we know that input equals to output in case of D
flip flop. It stores the value on the data line.
11. Which of the following describes the operation of a positive edge-triggered D flip-flop?
a) If both inputs are HIGH, the output will toggle
b) The output will follow the input on the leading edge of the clock
c) When both inputs are LOW, an invalid state exists
d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing
edge of the clock
Explanation: Edge-triggered flip-flop means the device will change state during the rising or falling edge of the clock
pulse. The main phenomenon of the D flip-flop is that the o/p will follow the i/p when the enable pin is HIGH.
12. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change
states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
Explanation: PGT refers to Positive Going Transition and NGT refers to negative Going Transition. Earlier, the DFF is in
a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and hence the stage will be changed.
13. A positive edge-triggered D flip-flop will store a 1 when ________

a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH
Explanation: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and the clock transitions
from LOW to HIGH. While a negative edge-triggered D flip-flop will store a 0 when the D input is HIGH and the clock
transitions from HIGH to LOW.
advertisement
14. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
a) Due to its capability to receive data from flip-flop
b) Due to its capability to store data in flip-flop
c) Due to its capability to transfer the data into flip-flop
d) Due to erasing the data from the flip-flop
Explanation: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value on the data line.
15. The characteristic equation of D-flip-flop implies that ___________
a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state
truth table. The characteristic equation of D flip-flop is given by Q(n+1) = D; which indicates that the next state is
independent of the present state.
« Prev - Digital Circuits Questions and Answers – Flip Flops – 3» Next - Digital Circuits Questions and Answers –
Triggering of Flip FlopsThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on
“Triggering of Flip Flops”.
1. The characteristic equation of J-K flip-flop is ______________
a) Q(n+1)=JQ(n)+K’Q(n)
b) Q(n+1)=J’Q(n)+KQ'(n)
c) Q(n+1)=JQ'(n)+KQ(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
truth table. The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K’Q(n).
advertisement
2. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
Explanation: In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.
3. In J-K flip-flop, the function K=J is used to realize _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
Explanation: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.
4. The only difference between a combinational circuit and a flip-flop is that _____________
a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present states
Explanation: Both flip-flop and latches are memory elements with clock/control inputs. They depend on the past as
well as present states. Whereas, in case of combinational circuits, they only depend on the present state.
5. How many stable states combinational circuits have?
a) 3
b) 4
c) 2
d) 5
Explanation: The two stable states of combinational circuits are 1 and 0. Whereas, in flip-flops there is an additional
state known as Forbidden State.
advertisement
6. The flip-flop is only activated by _____________
a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) Sinusoidal trigger
Explanation: Flip flops can be activated with either a positive or negative edge trigger.
7. The S-R latch composed of NAND gates is called an active low circuit because _____________
a) It is only activated by a positive level trigger
b) It is only activated by a negative level trigger

c) It is only activated by either a positive or negative level trigger
d) It is only activated by sinusoidal trigger
Explanation: Active low indicates that only an input value of 0 sets or resets the circuit.
8. Both the J-K & the T flip-flop are derived from the basic _____________
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
Explanation: The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are derived. A
latch is similar to a flip-flop, only without a clock input.
9. The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
Explanation: Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-flop has an invalid or
forbidden state where no output could be determined.
advertisement
10. What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered
Explanation: The triangle on the clock input of a J-K flip-flop mean edge triggered. Whereas the absence of triangle
symbol implies that the flip-flop is level-triggered.
11. What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Explanation: The circle on the clock input of a J-K flip-flop mean negative edge triggered. Whereas the absence of
triangle symbol implies that the flip-flop is level-triggered.
12. What does the direct line on the clock input of a J-K flip-flop mean?
a) Level enabled
d) Level triggered
Explanation: The direct line on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of
triangle symbol implies that the flip-flop is edge-triggered.
13. What does the half circle on the clock input of a J-K flip-flop mean?
a) Level enabled
d) Level triggered
Explanation: The half circle on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of
advertisement
14. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is _____________
a) Constantly LOW
b) Constantly HIGH

Explanation: As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is available at the
output.
Explanation: Edge triggered device will follow the input condition when there is a transition. It is said to be positive
edge triggered when transition occurs from LOW to HIGH. While it is said to be a negative edge triggered when a
transition occurs from HIGH to LOW.
« Prev - Digital Circuits Questions and Answers – D Flip Flop» Next - Digital Circuits Questions and Answers –
Master-Slave Flip-FlopsThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Master-Slave Flip-Flops”.
1. The asynchronous input can be used to set the flip-flop to the ____________
a) 1 state
b) 0 state
c) either 1 or 0 state
d) forbidden State
Explanation: The asynchronous input can be used to set the flip-flop to the 1 state or clear the flip-flop to the 0 state
at any time, regardless of the condition at the other inputs.
advertisement
2. Input clock of RS flip-flop is given to ____________
a) Input
b) Pulser
c) Output
d) Master slave flip-flop
Explanation: Pulser behaves like an arithmetic operator, to perform the operation or determination of corresponding
states.
3. D flip-flop is a circuit having ____________
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
Explanation: D flip-flop is a circuit having 4 NAND gates. Two of them are connected with each other.
4. In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output will oscillate back and forth
between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?
a) Conversion condition
b) Race around condition
c) Lock out state
d) Forbidden State
Explanation: A race around condition is a flaw in an electronic system or process whereby the output and result of
the process is unexpectedly dependent on the sequence or timing of other events.
5. Master slave flip flop is also referred to as?
a) Level triggered flip flop
b) Pulse triggered flip flop
c) Edge triggered flip flop
d) Edge-Level triggered flip flop

Explanation: The term pulse triggered means the data is entered on the rising edge of the clock pulse, but the output
does not reflect the change until the falling edge of the clock pulse.
advertisement
6. In a positive edge triggered JK flip flop, a low J and low K produces?
a) High state
b) Low state
c) Toggle state
d) No Change State
Explanation: In JK Flip Flop if J = K = 0 then it holds its current state. There will be no change.
7. If one wants to design a binary counter, the preferred type of flip-flop is ____________
a) D type
b) S-R type
c) Latch
d) J-K type
Explanation: If one wants to design a binary counter, the preferred type of flip-flop is J-K type because it has
capability to recover from toggle condition. SR flip-flop is not suitable as it produces the “Invalid State”.
8. S-R type flip-flop can be converted into D type flip-flop if S is connected to R through ____________
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
Explanation: S-R type flip-flop can be converted into D type flip-flop if S is connected to R through an Inverter gate.
9. Which of the following flip-flops is free from the race around the problem?
a) T flip-flop
b) SR flip-flop
c) Master-Slave Flip-flop
d) D flip-flop
Explanation: T flip-flop is free from the race around condition because its output depends only on the input; hence
there is no any problem creates as like toggle.
advertisement
10. Which of the following is the Universal Flip-flop?
a) S-R flip-flop
b) J-K flip-flop
c) Master slave flip-flop
d) D Flip-flop
Explanation: There are lots of flip-flops can be prepared by using J-K flip-flop. So, the name is a universal flip-flop.
Also, the JK flip-flop resolves the Forbidden State.
11. How many types of triggering take place in a flip flops?
a) 3
b) 2
c) 4
d) 5
Explanation: There are three types of triggering in a flip-flop, viz., level triggering, edge triggering and pulse
triggering.
12. Flip-flops are ____________
a) Stable devices
b) Astable devices
c) Bistable devices
d) Monostable devices
Explanation: Flip-flops are synchronous bistable devices known as bistable multivibrators as they have 2 stable
states.
13. The term synchronous means ____________
a) The output changes state only when any of the input is triggered
b) The output changes state only when the clock input is triggered
c) The output changes state only when the input is reversed
d) The output changes state only when the input follows it
Explanation: The term synchronous means the output changes state only when the clock input is triggered. That is,
changes in the output occur in synchronization with the clock.
advertisement
14. The S-R, J-K and D inputs are called ____________
a) Asynchronous inputs
b) Synchronous inputs
c) Bidirectional inputs
d) Unidirectional inputs
Explanation: The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to
the flip-flop’s output only on the triggering edge or level triggering of the clock pulse. Moreover, flip-flops have a
clock input whereas latches don’t. Hence, known as synchronous inputs.
15. The circuit that generates a spike in response to a momentary change of input signal is called ____________
a) R-C differentiator circuit
b) L-R differentiator circuit
c) R-C integrator circuit
d) L-R integrator circuit
Explanation: The circuit that generates a spike in response to a momentary change of input signal is called R-C
differentiator circuit.
« Prev - Digital Circuits Questions and Answers – Triggering of Flip Flops» Next - Digital Circuits Questions and
Answers – Realisation of one Flip-flop using other Flip-flopsThis set of Digital Electronic/Circuits Questions & Answers
for entrance exams focuses on “Realisation of one Flip-flop using other Flip-flops”.
1. To realise one flip-flop using another flip-flop along with a combinational circuit, known as ____________
a) PREVIOUS state decoder
b) NEXT state decoder
c) MIDDLE state decoder
d) PRESENT state decoder
Explanation: To realise one flip-flop using another flip-flop along with a combinational circuit, known as NEXT state
decoder which acts as like a flip-flop.
advertisement
2. For realisation of JK flip-flop from SR flip-flop, the input J and K will be given as ___________
a) External inputs to S and R
b) Internal inputs to S and R
c) External inputs to combinational circuit
d) Internal inputs to combinational circuit
Explanation: If a JK Flip Flop is required, the inputs are given to the combinational circuit and the output of the
combinational circuit is connected to the inputs of the actual flip flop. So, J and K will be given as external inputs to S
and R. As SR flip-flop have invalid state and JK flip-flop don’t.
3. For realisation of JK flip-flop from SR flip-flop, if J=0 & K=0 then the input is ___________
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
Explanation: If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both the AND gates which results
as S=0 & R=X(i.e. don’t care).
4. For realisation of JK flip-flop from SR flip-flop, if J=1, K=0 & present state is 0(i.e. Q(n)=0) then excitation input will
be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
Explanation: If J=1, K=0 & present state is 0(i.e. Q(n)=0) then next state will be 1 which results excitation inputs as
S=1 & R=0.
5. For realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from ___________
a) S and R
b) R input
c) J and K input
d) D input
Explanation: It is the reverse process of SR flip-flop to JK flip-flop. So, for realisation of SR flip-flop from JK flip-flop,
the excitation input will be obtained from J and K.
advertisement
6. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then next state will be
___________
a) 1
b) 0
c) Don’t care
d) Toggle
Explanation: For JK flip-flop to SR flip-flop, if S=1, R=0 & present state is 0 then next state will be 1 because next
stage is complement of present stage.
7. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation input will be
___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
Explanation: For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation input
will be J=1, K=X.
8. The K-map simplification for realisation of SR flip-flop from JK flip-flop is ___________
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
Explanation: The K-map simplification for realisation of SR flip-flop from JK flip-flop is given by: J=S, K=R.
9. For realisation of D flip-flop from SR flip-flop, the external input is given through ___________
a) S
b) R
c) D
d) Both S and R
Explanation: For realisation of D flip-flop from SR flip-flop, S and R are the actual inputs of the flip flop which is
connected together via NOT gate and it is called external input as D.
advertisement
10. For D flip-flop to JK flip-flop, the characteristics equation is given by ___________

a) D=JQ(p)’+Q(p)K’
b) D=JQ(p)’+KQ(p)’
c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
truth table. For D flip-flop to JK flip-flop, the characteristics equation is given by D=JQ(p)’+Q(p)K’.
To practice all areas of Digital Electronic Circuits for entrance exams, here is complete set of 1000+ Multiple Choice
« Prev - Digital Circuits Questions and Answers – Master-Slave Flip-Flops» Next - Digital Circuits Questions and
Answers – CountersThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on
“Counters”.
1. In digital logic, a counter is a device which ____________
a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
Explanation: In digital logic and computing, a counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred, often in relationship to a clock signal.
advertisement
2. A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
Explanation: A counter circuit is usually constructed of a number of flip-flops connected in cascade. Preferably, JK
Flip-flops are used to construct counters and registers.
3. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of
flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
Explanation: The maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of
flip-flops is 0 to 2n-1. For say, there is a 2-bit counter, then it will count till 22-1 = 3. Thus, it will count from 0 to 3.
4. How many types of the counter are there?
a) 2
b) 3
c) 4
d) 5
Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi-mode & (iii)modulus
counter. These further can be subdivided into Ring Counter, Johnson Counter, Cascade Counter, Up/Down Counter
and such like.
5. A decimal counter has ______ states.
a) 5
b) 10
c) 15
d) 20
Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also known as Decade
Counter counting from 0 to 9.
advertisement
6. Ripple counters are also called ____________
a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
Explanation: Ripple counters are also called asynchronous counter. In Asynchronous counters, only the first flip-flop
is connected to an external clock while the rest of the flip-flops have their preceding flip-flop output as clock to
them.
7. Synchronous counter is a type of ____________
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous Counters, the clock pulse is
supplied to all the flip-flops simultaneously.
8. Three decade counter would have ____________
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it would require 3 BCD
counters. Thus, a three decade counter will count from 0 to 29.
9. BCD counter is also known as ____________
a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
Explanation: BCD counter is also known as decade counter because both have the same number of stages and both
count from 0 to 9.
advertisement
10. The parallel outputs of a counter circuit represent the _____________
a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count
Explanation: The parallel outputs of a counter circuit represent the clock count. A counter counts the number of
times an event takes place in accordance to the clock pulse.
« Prev - Digital Circuits Questions and Answers – Realisation of one Flip-flop using other Flip-flops» Next - Digital
Circuits Questions and Answers – Asynchronous CounterThis set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Asynchronous Counter”.
1. How many natural states will there be in a 4-bit ripple counter?
a) 4
b) 8
c) 16
d) 32
Explanation: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.
advertisement
2. A ripple counter’s speed is limited by the propagation delay of _____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a series of Flip Flops. Output of
one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other
than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time
taken in producing an output when the input is altered.
3. One of the major drawbacks to the use of asynchronous counters is that ____________
a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting
applications
d) Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications
Explanation: One of the major drawbacks to the use of asynchronous counters is that High-frequency applications
are limited because of internal propagation delays. Propagation delay refers to the amount of time taken in
producing an output when the input is altered.
4. Internal propagation delay of asynchronous counter is removed by ____________
a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter
Explanation: Propagation delay refers to the amount of time taken in producing an output when the input is altered.
Internal propagation delay of asynchronous counter is removed by synchronous counter because clock input is given
to each flip-flop individually in synchronous counter.
5. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse
occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2
Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1st flip-flop is given to second
flip-flop as clock input. So, in case of binary down counter the output word decreases by 1.
advertisement
6. How many flip-flops are required to construct a decade counter?
a) 4
b) 8
c) 5
d) 10
Explanation: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n. 24=16and23=8, therefore,
4 flip flops needed.
7. The terminal count of a typical modulus-10 binary counter is ____________
a) 0000
b) 1010
c) 1001
d) 1111
Explanation: A binary counter counts or produces the equivalent binary number depending on the cycles of the clock
input. Modulus-10 means count from 0 to 9. So, the terminal count is 9 (1001).
8. How many different states does a 3-bit asynchronous counter have?

a) 2
b) 4
c) 8
d) 16
Explanation: In a n-bit counter, the total number of states = 2n.
9. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total
propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs
only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5 bits = 12ns * 5 = 60ns.
advertisement
10. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional
states are required?
a) 1
b) 2
c) 8
d) 15
Explanation: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore, transition states = 24 – 1 =
15. So, total transitional states are 15.
11. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns.
For the counter to recycle from 1111 to 0000, it takes a total of ____________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
only due to the flip-flops. One bit change is 15 ns, so 4-bit change = 15 * 4 = 60.
12. Three cascaded decade counters will divide the input frequency by ____________
a) 10
b) 20
c) 100
d) 1000
Explanation: Decade counter has 10 states. So, three decade counters are cascaded i.e. 10*10*10=1000 states.
13. A ripple counter’s speed is limited by the propagation delay of ____________
a) Each flip-flop
Explanation: A ripple counter is something that is derived by other flip-flops. Its like a series of Flip Flops. Output of
advertisement
14. A 4-bit counter has a maximum modulus of ____________
a) 3
b) 6
c) 8
d) 16
15. A principle regarding most display decoders is that when the correct input is present, the related output will
switch ____________
a) HIGH
b) To high impedance
c) To an open
d) LOW
Explanation: A principle regarding most display decoders is that when the correct input is present, the related output
will switch LOW. Since it’s an active-low device.
« Prev - Digital Circuits Questions and Answers – Counters» Next - Digital Circuits Questions and Answers –
Counter ICsThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Counter
ICs”.
1. What is the difference between a 7490 and a 7493?
a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
Explanation: The difference between a 7490 and a 7493 is that 7490 is a MOD-10, 7493 is a MOD-16 counter. Thus,
7490 traverses 10 states and 7493 traverses 16 states.
advertisement
a) 1
b) 4
c) 2
d) 8
Explanation: For a n-bit counter, total number of states = 2n. Thus, for 2-bit counter, total number of states = 22 = 4.
3. A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter,
and a modulus-10 counter. The lowest output frequency possible is ________
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
Explanation: Cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. So,
5*8*10=400. Applied clock frequency = 12 MHz; hence, the lowest output frequency possible is 12MHz/400=30 kHz.
4. Which one is a 4-bit binary ripple counter?
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
Explanation: IC 7493 is a 4-bit binary ripple counter. It is a MOD-16 counter with 24 = 16 states.
5. IC 7493 consist of ____________
a) 4 S-R flip-flop
b) 4 J-K flip-flop
c) 4 master-slave flip-flop
d) 4 D flip-flop
Explanation: IC 7493 consist of 4 J-K master-slave flip-flop. It is a MOD-16 counter with 24 = 16 states.
advertisement
6. A reset input is used in IC 7493, why?
a) For increment of bit by 1
b) For decrement of bit by 1
c) For reset the counter
d) For setting the counter
Explanation: The reset inputs are used to reset the counter to 0000.
7. In a 4-bit binary ripple counter, four master-slave flip-flops are internally connected to provide a ________ bit
counter.
a) Divide-by-2 & divide-by-6
b) Divide-by-6 & divide-by-8
c) Divide-by-2 & divide-by-8
d) Divide-by-4 & divide-by-8
Explanation: In a 4-bit binary ripple counter, four master-slave flip-flops are internally connected to provide a Divide-
by-2 & divide-by-8 bit counter.
8. Which of the following is a decade counter?
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
Explanation: IC 7490 is called as decade counter or MOD-10. Thus, it has 10 states.
9. In a 4-bit decade counter, four master-slave flip-flops are internally connected to provide a ________ bit counter.

Explanation: In a decade counter, four master-slave flip-flops are internally connected to provide a Divide-by-2 &
divide-by-5 bit counter.
advertisement
10. Reset inputs are used in IC 7490, why?
11. The set inputs are used in a decade counter, why?
a) To set the counter to 0011
b) To set the counter to 1000
c) To set the counter to 1001
d) To set the counter to 0001
Explanation: The set inputs are used in a decade counter to set the counter to 1001 which is 9 in decimal, as a
decade counter counts from 0 to 9.
12. List which pins need to be connected together on a 7493 to make a MOD-12 counter.
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
Explanation: IC-7493 is a MOD-16 counter. So maximum, it can have 16 states. A MOD-12 counter will have 12-
states. Thus, it is clear from the diagram shown below: 12 & 1 are clear pins, 11 & 3 are clock pins, 8 & 2 are input for
7493 FF.
13. Ripple counter IC has _____________
a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
Explanation: A ripple counter is of 4-bit and has 4 J-K flip-flops. Ripple counter IC has 14 pins.
advertisement
14. Integrated-circuit counter chips are used in numerous applications including ____________
a) Timing operations, counting operations, sequencing, and frequency multiplication
b) Timing operations, counting operations, sequencing, and frequency division
c) Timing operations, decoding operations, sequencing, and frequency multiplication
d) Data generation, counting operations, sequencing, and frequency multiplication
Explanation: There are no integrated circuit counter chips employed for frequency multiplication. In the rest of the
options, frequency multiplication is mentioned which is not related to counters in anyway. So, they are not the
correct answers. Thus, counters are used for timing operations, counting operations, sequencing and frequency
division.
15. What is the difference between 7490 and a 7492?
a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12
Explanation: From the properties of both ICs, we have 7490 is a MOD-10, 7492 is a MOD-12. Thus, IC-7490 can have
maximum 10 states, while IC-7492 can have maximum 12 states.
« Prev - Digital Circuits Questions and Answers – Asynchronous Counter» Next - Digital Circuits Questions and
Answers – Asynchronous Down CounterThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Asynchronous Down Counter”.
1. Which of the following statements are true?
a) Asynchronous events does not occur at the same time
b) Asynchronous events are controlled by a clock
c) Synchronous events does not need a clock to control them
d) Only asynchronous events need a control clock
Explanation: Asynchronous events does not occur at the same time because of propagation delay and they do need
a clock pulse to trigger them. Whereas, synchronous events occur in presence of clock pulse.
advertisement
2. A down counter using n-flip-flops count ______________
a) Downward from a maximum count
b) Upward from a minimum count
c) Downward from a minimum to maximum count
d) Toggles between Up and Down count
Explanation: As the name suggests down counter means counting occurs from a higher value to lower value (i.e. (2^n
– 1) to 0).
3. UP Counter is ____________
a) It counts in upward manner
b) It count in down ward manner
c) It counts in both the direction
Explanation: UP counter counts in an upward manner from 0 to (2n – 1).
4. DOWN counter is ____________
b) It count in downward manner
Explanation: DOWN counter counts in a downward manner from (2n – 1) to 0.
5. How many different states does a 3-bit asynchronous down counter have?
a) 2
b) 4
c) 6
d) 8
advertisement
6. In a down counter, which flip-flop doesn’t toggle when the inverted output of the preceeding flip-flop
goes from HIGH to LOW.
a) MSB flip-flop
b) LSB flip-flop
d) Latch
Explanation: Since the LSB flip-flop changes its state at each negative transition of clock. That is why LSB flip-flop
doesn’t have toggle.
7. In a 3-bit asynchronous down counter, the initial content is ____________
a) 000
b) 111
c) 010
d) 101
Explanation: Initially, all the flip-flops are RESET. So, the initial content is 000. At the first negative transition of the
clock, the counter content becomes 101.
8. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes
____________
a) 000
b) 111
c) 101
d) 010
Explanation: Since, in the down counter, the counter content is decremented by 1 for every negative transition.
Hence, in a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content
becomes 111.
____________
a) 000
b) 111
c) 101
d) 010
becomes 101.
advertisement
10. The hexadecimal equivalent of 15,536 is ________
a) 3CB0
b) 3C66
c) 63C0
d) 6300
Explanation: You just divide the number by 16 at the end and store the remainder from bottom to top.
11. In order to check the CLR function of a counter ____________
a) Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
b) Ground the CLR input and check to be sure that all of the Q outputs are LOW
c) Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
d) Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs
are toggling
Explanation: CLR stands for clearing or resetting all states of flip-flop. In order to check the CLR function of a counter,
apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state.
advertisement

« Prev - Digital Circuits Questions and Answers – Counter ICs» Next - Digital Circuits Questions and Answers –
Propagation Delay in Ripple CounterThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Propagation Delay in Ripple Counter”.
1. Modulus refers to ____________
a) A method used to fabricate decade counter units
b) The modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
c) An input on a counter that is used to set the counter state, such as UP/DOWN
d) The maximum number of states in a counter sequence
Explanation: Modulus is defined as the maximum number of stages/states a counter has. It is independent of the
number of states the counter will actually traverse.
advertisement
2. A sequential circuit design is used to ____________
a) Count up
b) Count down
c) Decode an end count
d) Count in a random order
Explanation: A sequential circuit design is used to count in a random manner which is faster than the combinational
circuit. It is used for storing data.
3. In general, when using a scope to troubleshoot digital systems, the instrument should be triggered by
____________
a) The A channel or channel 1
b) The vertical input mode, when using more than one channel
c) The system clock
d) Line sync, in order to observe troublesome power line glitches
Explanation: All the information is sent from one end to another end through the clock pulse which behaves like a
carrier. So, for troubleshooting it should be triggered by the same. Since the system clock is internally produced.
4. Which counters are often used whenever pulses are to be counted and the results displayed in decimal?
a) Synchronous
b) Bean
c) Decade
d) BCD
Explanation: BCD means Binary Coded Decimal, which means that decimal numbers coded of binary numbers. It
displays the decimal equivalent of corresponding binary numbers.
5. The ________ counter in the Altera library has controls that allow it to count up or down, and perform
synchronous parallel load and asynchronous cascading.
a) 74134
b) LPM
c) Synchronous
d) AHDL
Explanation: The library of parameterized modules (LPM) counter in the Altera library has controls that allow it to
count up or down, and perform synchronous parallel load and asynchronous cascading.
advertisement
6. The minimum number of flip-flops that can be used to construct a modulus-5 counter is ____________
a) 3
b) 8
c) 5
d) 10
Explanation: The minimum number of flip-flops used in a counter is given by: 2(n-1)<=N<=2n.
Thus, for modulus-5 counter: 22 <= N <= 23, where N = 5 and n = 3.
7. The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ____________
a) 20%
b) 50%
c) 10%
d) 80%
Explanation: There are 10 states, out of which MSB is high only for (1000, 1001) 2 times. Hence duty cycle is
2/10*100 = 20%. Since the duty cycle is the ratio of on-time to the total time.
8. Normally, the synchronous counter is designed using ____________
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
Explanation: Since J-K flip-flops have options of recovery from toggle condition and by using less number of J-K flip-
flops a synchronous counter can be designed. So, it is more preferred. Also, because JK-flip-flops resolves the
problem of Forbidden States.
9. MOD-16 counter requires ________ no. of states.
a) 8
b) 4
c) 16
d) 32
Explanation: 2n >= N >= 2(n-1), by using this formula we get the value of N=16 for n=4.
advertisement
10. What is a state diagram?
a) It provides the graphical representation of states
b) It provides exactly the same information as the state table
c) It is same as the truth table
d) It is similar to the characteristic equation
Explanation: The state diagram provides exactly the same information as the state table and is obtained directly
from the state table.
11. High speed counter is ____________
a) Ring counter
b) Ripple counter
d) Asynchronous counter
Explanation: Synchronous counter doesn’t have propagation delay. Propagation delay refers to the amount of time
taken in producing the output when the input is altered.
12. Program counter in a digital computer ____________
a) Counts the number of programs run in the machine
b) Counts the number of times a subroutine
c) Counts the number of time the loops are executed
d) Points the memory address of the current or the next instruction
Explanation: Program counter in a digital computer points the memory address of the current or the next instruction
which is to be executed.
13. Fundamental mode is another name for ____________
a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
Explanation: Whatever the input given to the devices are in the form of pulses always. That is why it is known as a
fundamental mode.
advertisement

« Prev - Digital Circuits Questions and Answers – Asynchronous Down Counter» Next - Digital Circuits Questions
and Answers – Counter Implementation and ApplicationsThis set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Counter Implementation and Applications”.
a) Each flip-flop
Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a series of Flip Flops. The output
of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other
advertisement
2. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The
total propagation delay (tp(tot)) is ________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
For the counter to recycle from 1111 to 0000, it takes a total of ________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
4. A ripple counter’s speed is limited by the propagation delay of __________
a) Each flip-flop
5. What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop
has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
Explanation: Maximum propagation delay is the longest delay between an input changing value and the output
changing value. Hence, 22 * n = 22*4 (Since there are 4 FFs) = 88ns.
advertisement
6. The main drawback of a ripple counter is that __________
a) It has a cumulative settling time
b) It has a distributive settling time
c) It has a productive settling time
d) It has an associative settling time
Explanation: The main drawback of a ripple counter is that it has a cumulative settling time (i.e. another bit is
transmitted just after one consequently).
7. A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop is 50 nsec, the
maximum clock frequency that can be used is equal to __________
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
only due to the flip-flops. Each bit has propagation delay = 50ns. So, 4 bits or FFs = 50ns * 4 = 200ns. Clock frequency
= 1/200ns = 5 MHz.
8. As the number of flip flops are increased, the total propagation delay of __________
a) Ripple counter increases but that of synchronous counter remains the same
b) Both ripple and synchronous counters increase
c) Both ripple and synchronous counters remain the same
d) Ripple counter remains the same but that of synchronous counter increases
Explanation: In ripple counter, the clock pulses are applied to one flip-flop only. Hence, as the number of flip-flops
increases the delay increases. In the synchronous counter, clock pulses to all flip-flops are applied simultaneously.
9. A reliable method for eliminating decoder spikes is the technique called ________
a) Strobing
b) Feeding
c) Wagging
d) Waving
Explanation: A reliable method for eliminating decoder spikes is the technique called strobing. A strobe signal
validates the availability of data on consecutive parallel lines.
advertisement
10. A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope
because of __________
a) It is a random event
b) It occurs less frequently than the normal decoded output
c) It is very fast
d) All of the Mentioned
Explanation: A glitch is a transition that occurs before a signal settles to a specific value. A glitch that appears on the
decoded output of a ripple counter is often difficult to see on an oscilloscope because it is a random event and very
fast and it occurs less frequently than the normal decoded output.
11. Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and fourth
stages will __________
a) Continue to count with correct outputs
b) Continue to count but have incorrect outputs
c) Stop counting
d) Turn into molten silicon
Explanation: The ripple counter would stop counting because next flip-flop’s input depends on the output of the
previous flip-flop.
advertisement

« Prev - Digital Circuits Questions and Answers – Propagation Delay in Ripple Counter» Next - Digital Circuits
Questions and Answers – Up Down CounterThis set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Up Down Counter”.
1. UP-DOWN counter is a combination of ____________
a) Latches
b) Flip-flops
c) UP counter
d) Up counter & down counter
Explanation: As the name suggests UP-DOWN, it means that it has up-counter and down-counter as well. It
alternatively counts up and down.
advertisement
2. UP-DOWN counter is also known as ___________
a) Dual counter
b) Multi counter
c) Multimode counter
d) Two Counter
Explanation: UP-DOWN counter is also known as multimode counter because it has capability of counting upward as
well as downwards.
3. In an UP-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
Explanation: In an UP-counter, each flip-flop is triggered by the normal output of the preceding flip-flop. UP-counter
counts from 0 to a maximum value.
4. In DOWN-counter, each flip-flop is triggered by ___________

Explanation: In DOWN-counter, each flip-flop is triggered by the inverted output of the preceding flip-flop. DOWN-
counter counts from a maximum value to 0.
5. Binary counter that count incrementally and decrement is called ___________
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
Explanation: Binary counter that counts incrementally and decrement is called UP-DOWN counter/multimode
counter. It alternately counts up and down.
advertisement
6. Once an up-/down-counter begins its count sequence, it ___________
a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) Can be altered
Explanation: In up/down ripple counter once the counting begins, we can simply change the pulse M (mode control)
M = 0 or 1 respectively for UP counter or Down counter.
7. In 4-bit up-down counter, how many flip-flops are required?
a) 2
b) 3
c) 4
d) 5
Explanation: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there are 4 J-K flip-flops
required.
8. A modulus-10 counter must have ________

a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
d) Synchronous clocking
Explanation: 2n-1 < = N < = 2n
For modulus-10 counter, N = 10. Therefore, 23 < = 10 < = 24. Thus, n = 4, and therefore, we require 4 FFs.
9. Which is not an example of a truncated modulus?
a) 8
b) 9
c) 11
d) 15
Explanation: An n-bit counter whose modulus is less than the maximum possible is called a truncated counter. Here,
9, 11 and 15 modulus counters are truncated counters. Whereas, modulus-8 is not a truncated counter.
advertisement
10. The designation means that the ________
a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
d) Up and down counts are both active-HIGH
Explanation: The designation means that the up count is active-HIGH, the down count is active-LOW. Active-High
means that up-count would be triggered when clock is 1 else when clock is 0, down-count would be triggered, which
is referred to as Active-low.
11. An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a
down counter by ________
a) Taking the output on the other side of the flip-flops (instead of Q)
b) Clocking of each succeeding flip-flop from the other side (instead of Q)

c) Changing the flip-flops to trailing edge triggering
Explanation: By all of the mentioned ideas, an asynchronous binary up counter, made from a series of leading edge-
triggered flip-flops, can be changed to a down counter. Edge-triggered FFs refer to FFs being triggered during a clock
transition from LOW to HIGH or HIGH to LOW.
12. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is
________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Explanation: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And MSB changes on 8th stage;
Hence, f = 10/8 = 1.25 kHz.
advertisement
Answers.

« Prev - Digital Circuits Questions and Answers – Counter Implementation and Applications» Next - Digital Circuits
Questions and Answers – RegistersThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Registers”.
1. A register is defined as ___________
a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
Explanation: A register is defined as the group of flip-flops suitable for storing binary information. Each flip-flop is a
binary cell capable of storing one bit of information. The data in a register can be transferred from one flip-flop to
another.
advertisement
2. The register is a type of ___________
a) Sequential circuit
b) Combinational circuit
c) CPU
d) Latches
Explanation: Register’s output depends on the past and present states of the inputs. The device which follows these
properties is termed as a sequential circuit. Whereas, combinational circuits only depend on the present values of
inputs.
3. How many types of registers are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are 4 types of shift registers, viz., Serial-In/Serial-Out, Serial-In/Parallel-Out, Parallel-In/Serial-Out
and Parallel-In/Parallel-Out.
4. The main difference between a register and a counter is ___________
a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data
Explanation: The main difference between a register and a counter is that a register has no specific sequence of
states except in certain specialised applications.
5. In D register, ‘D’ stands for ___________
a) Delay
b) Decrement
c) Data
d) Decay
Explanation: D stands for “data” in case of flip-flops and not delay. Registers are made of a group of flip-flops.
advertisement
6. Registers capable of shifting in one direction is ___________
a) Universal shift register
b) Unidirectional shift register
c) Unipolar shift register
d) Unique shift register
Explanation: The register capable of shifting in one direction is unidirectional shift register. The register capable of
shifting in both directions is known as a bidirectional shift register.
7. A register that is used to store binary information is called ___________
a) Data register
b) Binary register
c) Shift register
d) D – Register
Explanation: A register that is used to store binary information is called a binary register. A register in which data can
be shifted is called shift register.
8. A shift register is defined as ___________
a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
Explanation: The register capable of shifting information either to the right or to the left is termed as shift register. A
register in which data can be shifted only in one direction is called unidirectional shift register, while if data can
shifted in both directions, it is known as a bidirectional shift register.
9. How many methods of shifting of data are available?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two types of shifting of data are available and these are serial shifting & parallel shifting.
advertisement
10. In serial shifting method, data shifting occurs ____________
a) One bit at a time
b) simultaneously
c) Two bit at a time
d) Four bit at a time
Explanation: As the name suggests serial shifting, it means that data shifting will take place one bit at a time for each
clock pulse in a serial fashion. While in parallel shifting, shifting will take place with all bits simultaneously for each
clock pulse in a parallel fashion.

« Prev - Digital Circuits Questions and Answers – Up Down Counter» Next - Digital Circuits Questions and Answers
– Shift RegistersThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Shift
Registers”.
1. Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.
a) 2
b) 3
c) 4
d) 5
Explanation: The registers in which data can be shifted serially or parallelly are known as shift registers. Based on
how binary information is entered or shifted out, shift registers are classified into 4 categories, viz., Serial-In/Serial-
Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-In/Serial-Out (PISO), Parallel-In/Parallel-Out (PIPO).
advertisement
2. The full form of SIPO is ___________
a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out
Explanation: SIPO is always known as Serial-in Parallel-out.
3. A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
Explanation: A shift register can shift it’s data either left or right. The universal shift register is capable of shifting
data left, right and parallel load capabilities.
4. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
Explanation: Because no other flip-flops are connected with the output Q, therefore one can use the Q out of each
FF to take out parallel data.
5. What is meant by the parallel load of a shift register?
a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
Explanation: At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus input is definitely 1.
advertisement
6. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with
an initial state 01110. After three clock pulses, the register contains ________
a) 01110
b) 00001
c) 00101
d) 00110
Explanation: LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.
7. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will
be the 4-bit pattern after the second clock pulse? (Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111
Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a time with every clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
8. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After
four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000
Explanation: In Serial-In/Parallel-Out shift register, data will be shifted all at a time with every clock pulse. Therefore,
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
9. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
Explanation: f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded = 8 * 5 = 40 micro-
sec.
advertisement
10. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay
(td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
Explanation: One clock period is = (1⁄2) micro-s = 0.5 microseconds. In serial transmission, data enters one bit at a
time. So, the total delay = 0.5*8 = 4 micro seconds time is required to transmit information of 8 bits.

« Prev - Digital Circuits Questions and Answers – Registers» Next - Digital Circuits Questions and Answers –
Universal Shift RegistersThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Universal Shift Registers”.
1. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
a) Ring shift
b) Clock
c) Johnson
d) Binary
Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. Thus, it generates
equally spaced timing pulses.
advertisement
2. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to
be entered on the serial data-input line. After three clock pulses, the shift register is storing ________
a) 1101
b) 0111
c) 0001
d) 1110
Explanation: Mode is high means it’s a right shift register. Then after 3 clock pulses enter bits are 011 and remained
bit in register is 1. Therefore, 0111 is the required solution.
1011 | 1101
101 | 1110 -> 1st clock pulse
10 | 1111 -> 2nd clock pulse
1 | 0111 -> 3rd clock pulse.
3. To operate correctly, starting a ring shift counter requires __________
a) Clearing all the flip-flops
b) Presetting one flip-flop and clearing all others
c) Clearing one flip-flop and presetting all others

d) Presetting all the flip-flops
Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. To operate correctly,
starting a ring shift counter requires presetting one flip-flop and clearing all others so that it can shift to the next bit.
4. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for each
clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
Explanation: If register shifts towards left then it shift by a bit to the left and if register shifts right then it shift to the
right by one bit. Since, it receives parallel data, then by default, it will shift to right by one position.
5. How many clock pulses will be required to completely load serially a 5-bit shift register?
a) 2
b) 3
c) 4
d) 5
Explanation: A register is a collection of FFS. To load a bit, we require 1 clock pulse for 1 shift register. So, for 5-bit
shift register we would require of 5 clock pulses.
advertisement
6. How is a strobe signal used when serially loading a shift register?
a) To turn the register on and off
b) To control the number of clocks
c) To determine which output Qs are used
d) To determine the FFs that will be used
Explanation: A strobe is used to validate the availability of data on the data line. It (an auxiliary signal used to help
synchronize the real data in an electrical bus when the bus components have no common clock) signal is used to
control the number of clocks during serially loading a shift register.
7. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between
the serial input and the Q3 output?
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
Explanation: In serial-sifting, one bit of data is shifted one at a time. From Q0 to Q3 total of 4 bit shifting takes place.
Therefore, 4/150kHz = 26.67 microseconds.
8. What are the three output conditions of a three-state buffer?
a) HIGH, LOW, float
b) High-Z, 0, float
c) Negative, positive, 0
d) 1, Low-Z, float
Explanation: Three conditions of a three-state buffer are HIGH, LOW & float.
9. The primary purpose of a three-state buffer is usually ____________
a) To provide isolation between the input device and the data bus
b) To provide the sink or source current required by any device connected to its output without loading down the
output device
c) Temporary data storage
d) To control data flow
Explanation: The primary purpose of a three-state buffer is usually to provide isolation between the input device or
peripheral devices and the data bus. Three conditions of a three-state buffer are HIGH, LOW & float.
advertisement
10. What is the difference between a ring shift counter and a Johnson shift counter?
a) There is no difference
b) A ring is faster
c) The feedback is reversed
d) The Johnson is faster

Explanation: A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last one
connected to the input of the first, that is, in a ring. Whereas, a Johnson counter (or switchtail ring counter, twisted-
ring counter, walking-ring counter, or Moebius counter) is a modified ring counter, where the output from the last
stage is inverted and fed back as input to the first stage.
« Prev - Digital Circuits Questions and Answers – Shift Registers» Next - Digital Circuits Questions and Answers –
Shift Register CountersThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Shift Register Counters”.
1. What is a recirculating register?
a) Serial out connected to serial in
b) All Q outputs connected together
c) A register that can be used over again
d) Parallel out connected to Parallel in
Explanation: A recirculating register is a register whose serial output is connected to the serial input in a circulated
manner.
advertisement
2. When is it important to use a three-state buffer?
a) When two or more outputs are connected to the same input

b) When all outputs are normally HIGH
c) When all outputs are normally LOW
d) When two or more outputs are connected to two or more inputs
Explanation: When two or more outputs are connected to the same input, in such situation we use of tristate buffer
always because it has the capability to take upto three inputs. A buffer is a circuit where the output follows the
input.
3. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be
entered on the serial data-input line. After two clock pulses, the shift register is storing ________
a) 1110
b) 0111
c) 1000
d) 1001
Explanation: Given,
Stored nibble | waiting nibble
0111 | 1110, Initially
111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
4. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data
outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000
Explanation: Parallel in parallel out gives the same output as input. Thus, after three clock pulses, the data outputs
are 0001.
5. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an
initial state 11110000. After two clock pulses, the register contains ______________
a) 10111000
b) 10110111
c) 11110000
d) 11111100
Explanation: After first clock pulse, the register contains 11111000. After second clock pulse, the register would
contain 11111100. Since the bits are shifted to the right at every clock pulse.
6. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a ________ ________ and
________ out register.
a) Parallel-in, serial, parallel
b) Serial-in, parallel, serial
c) Series-parallel-in, series, parallel
d) Bidirectional in, parallel, series
Explanation: One bit shifting takes place just after the output obtained on every register. Hence, by adding
recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a Parallel-in, Serial, and Parallel-out
register. Since, the bots can be inputted all at the same time, while the data can be outputted either one at a time or
simultaneously.
advertisement
7. What type of register would have a complete binary number shifted in one bit at a time and have all the
stored bits shifted out one at a time?
a) Parallel-in Parallel-out
d) Serial-in Parallel-out
Explanation: Serial-in Serial-out register would have a complete binary number shifted in one bit at a time and have
all the stored bits shifted out one at a time. Since in serial transmission, bits are transmitted or received one at a
time and not simultaneously.
8. In a 4-bit Johnson counter sequence, there are a total of how many states or bit patterns?
a) 1
b) 3
c) 4
d) 8
Explanation: In johnson counter, total number of states are determined by 2N = 2*4 = 16
Total Number of Used states = 2N = 2*4 = 8

Total Number of Unused states = 16 – 8 = 8.
9. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
Explanation: After shifting 2-bit we get the output as 0011010000 (Since two zeros are at 1st position and 2nd
position which came from the last two bits). As in a ring counter, the bits rotate in clockwise direction.
10. How much storage capacity does each stage in a shift register represent?
a) One bit
b) Two bits
c) Four bits
d) Eight bits
Explanation: A register is made of flip-flops. And each flip-flop stores 1 bit of data. Thus, a shift register has the
capability to store one bit and if another bit is to store, in such a situation it deletes the previous data and stores
them.
advertisement

« Prev - Digital Circuits Questions and Answers – Universal Shift Registers» Next - Digital Circuits Questions and
Answers – Ring CounterThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Ring Counter”.
1. Ring shift and Johnson counters are ____________
a) Synchronous counters
c) True binary counters
d) Synchronous and true binary counters
Explanation: Synchronous counters are the counters being triggered in the presence of a clock pulse. Since all of the
clock inputs are connected through a single clock pulse in ring shift and johnson counters. So, both are synchronous
counters.
advertisement
2. What is the difference between a shift-right register and a shift-left register?
b) The direction of the shift
c) Propagation delay
d) The clock input
Explanation: In shift-right register, shifting of bit takes place towards the right and towards left for shift-left register.
Thus, both the registers vary in the shifting of their direction.
3. What is a transceiver circuit?
a) A buffer that transfers data from input to output
b) A buffer that transfers data from output to input
c) A buffer that can operate in both directions
d) A buffer that can operate in one direction
Explanation: A transceiver circuit is a buffer that can operate in both directions right as well as left.
4. A 74HC195 4-bit parallel access shift register can be used for ____________
a) Serial in/serial out operation
b) Serial in/parallel out operation
c) Parallel in/serial out operation
Explanation: 74HC195 is an IC, which can be used for all of the given operations, as well as for, parallel-in/parallel-
out.
5. Which type of device may be used to interface a parallel data format with external equipment’s serial format?
a) UART
b) Key matrix
c) Memory chip
d) Series in Parallel out
Explanation: UART means Universal Asynchronous Receiver/Transmitter which converts the bytes it receives from
the computer along parallel circuits into a single serial bit stream for outbound transmission. And also receives data
in serial form and converts it into parallel form and sent to the processor.
advertisement
6. What is the function of a buffer circuit?
a) To provide an output that is inverted from that on the input
b) To provide an output that is equal to its input
c) To clean up the input
d) To clean up the output
Explanation: The function of a buffer circuit is to provide an output that is equal to its input. A transceiver circuit is a
buffer that can operate in both directions right as well as left.
7. What is the preset condition for a ring shift counter?
a) All FFs set to 1
b) All FFs cleared to 0
c) A single 0, the rest 1
d) A single 1, the rest 0
Explanation: A ring shift counter is a counter in which the output of one FF connected to the input of the adjacent FF.
In preset condition, all of the bits are 0 except first one.
8. Which is not characteristic of a shift register?
a) Serial in/parallel in
b) Serial in/parallel out
c) Parallel in/serial out
d) Parallel in/parallel out
Explanation: There is no such type of register present who doesn’t have output end. Thus, Serial in/Parallel in is not a
characteristic of a shift register. There has to be an output, be it serial or parallel.
9. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ____________
a) Divide-by-4 clock pulse
b) Sequence generator
c) Strobe line
d) Multiplexer
Explanation: In computer or memory technology, a strobe is a signal that is sent that validates data or other signals
on adjacent parallel lines. Thus, in registers the strobe line is there to check the availability of data.
advertisement
10. Another way to connect devices to a shared data bus is to use a ____________
a) Circulating gate
b) Transceiver
c) Bidirectional encoder
d) Strobed latch
Explanation: A transceiver is a device comprising both a transmitter and a receiver which are combined and share
common circuitry or a single housing. When no circuitry is common between transmit and receive functions, the
device is a transmitter-receiver.
« Prev - Digital Circuits Questions and Answers – Shift Register Counters» Next - Digital Circuits Questions and
Answers – Introduction of Memory Devices – 1This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Introduction of Memory Devices – 1”.
1. Memory is a/an ___________
a) Device to collect data from other computer
b) Block of data to keep data separately
c) Indispensable part of computer
d) Device to connect through all over the world
Explanation: Memory is an indispensable unit of a computer and microprocessor based systems which stores
permanent or temporary data.
advertisement
2. The instruction used in a program for executing them is stored in the __________
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
Explanation: All of the program and the instructions are stored in the memory. The processor fetches it as and when
required.
3. A flip flop stores __________
a) 10 bit of information
b) 1 bit of information
c) 2 bit of information
d) 3-bit information
Explanation: A flip-flop has capability to store 1 bit of information. It can be used further after erasing previous
information.
4. A register is able to hold __________
a) Data
b) Word
c) Nibble
d) Both data and word
Explanation: Register is also a part of memory inside a computer. It stands there to hold a word. A word is a group of
16-bits or 2-bytes.
5. A register file holds __________
a) A large number of word of information
b) A small number of word of information
c) A large number of programs
d) A modest number of words of information
Explanation: A register file is different from a simple register because of capability to hold a modest number of
words of information. A word is a group of 16-bits or 2-bytes.
advertisement
6. The very first computer memory consisted of __________
a) A small display
b) A large memory storage equipment
c) An automatic keyboard input
d) An automatic mouse input
Explanation: The very first computer memory consisted of a minute magnetic toroid, which required large, bulky
circuit boards stored in large cabinates.
7. A minute magnetic toroid is also called as __________
a) Large memory
b) Small memory
c) Core memory
d) Both small and large memory
Explanation: A minute magnetic toroid is also called as core memory which is made up of a semiconductor. A
semiconductor is a device whose electrical conductivity lies between that of conductor and insulator.
8. Which one of the following has capability to store data in extremely high densities?
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
Explanation: Semiconductor has capability to store data in extremely high densities.
9. A large memory is compressed into a small one by using __________
a) LSI semiconductor
b) VLSI semiconductor
c) CDR semiconductor
d) SSI semiconductor
Explanation: VLSI (Very Large Scale Integration) semiconductor is used in modern computers to short the size of
memory.
advertisement
10. VLSI chip utilizes __________
a) NMOS
b) CMOS
c) BJT
Explanation: VLSI (Very Large Scale Integration) is a memory chip which is made up of NMOS, CMOS, BJT, and
BiCMOS. It can include 10,000 to 100,000 gates per IC.
11. CD-ROM refers to __________
a) Floppy disk
b) Compact Disk-Read Only Memory
c) Compressed Disk-Read Only Memory
d) Compressed Disk- Random Access Memory
Explanation: CD-ROM refers to Compact Disk-Read Only Memory.
12. Data stored in an electronic memory cell can be accessed at random and on demand using __________
a) Memory addressing
b) Direct addressing
c) Indirect addressing
d) Control Unit
Explanation: Direct addressing eliminates the need to process a large stream of irrelevant data in order to the
desired data word.
13. The full form of PLD is __________
a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) Programmable Lengthy Device
Explanation: The full form of PLD is Programmable Logic Device.
advertisement
14. The evolution of PLD began with __________

a) EROM
b) RAM
c) PROM
d) EEPROM
Explanation: The evolution of PLD (Programmable Logic Device) began with Programmable Read Only Memory (i.e.
PROM). Here, the ROM can be externally programmed as per the user.
15. A ROM is defined as __________
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
Explanation: A ROM is defined as Read Only Memory which can read the instruction stored in a computer.
« Prev - Digital Circuits Questions and Answers – Ring Counter» Next - Digital Circuits Questions and Answers –
Introduction of Memory Devices – 2This set of Digital Electronic/Circuits assessment questions focuses on
“Introduction of Memory Devices-2”.
1. The full form of ROM is __________
a) Read Outside Memory
b) Read Out Memory
c) Read Only Memory
d) Read One Memory
Explanation: The full form of ROM is Read Only Memory.

advertisement
2. ROM consist of __________
a) NOR and OR arrays
b) NAND and NOR arrays
c) NAND and OR arrays
d) NOR and AND arrays
Explanation: ROM consists of NAND and OR arrays which can be programmed by the user to implement
combinational & sequential functions. Combinational Operations like that of adders and subtractors and Sequential
Functions like that of storing in the memory.
3. For reprogrammability, PLDs use __________
a) PROM
b) EPROM
c) CDROM
d) PLA
Explanation: For reprogrammability, PLDs use EPROM (i.e. Erasable PROM). It erases the previous program and starts
uploading a new one. However, data is erased by exposing it to UV-light, which is a tedious and time-consuming
process.
4. The full form of PROM is __________
a) Previous Read Only Memory
b) Programmable Read Out Memory
c) Programmable Read Only Memory
d) Previous Read Out Memory
Explanation: The full form of PROM is Programmable Read Only Memory, where the ROM can be programmed by
the user.
5. The full form of EPROM is __________
a) Easy Programmable Read Only Memory
b) Erasable Programmable Read Only Memory

c) Eradicate Programmable Read Only Memory
d) Easy Programmable Read Out Memory
Explanation: The full form of EPROM is Erasable Programmable Read Only Memory, where the ROM can be erased
and re-used by the user.
advertisement
6. PLDs with programmable AND and fixed OR arrays are called __________
a) PAL
b) PLA
c) APL
d) PPL
Explanation: PLDs with programmable AND and fixed OR arrays are called PAL (i.e. Programmable Array Logic).
However, PAL is less flexible but has higher speed.
7. When both the AND and OR are programmable, such PLDs are known as __________
a) PAL
b) PPL
c) PLA
d) APL
Explanation: When both the AND and OR are programmable, such PLDs are known as PLA (i.e. Programmable Logic
Array). However, PLA is more flexible but has less speed.
8. ASIC stands for __________
a) Application Special Integrated Circuits
b) Applied Special Integrated Circuits
c) Application Specific Integrated Circuits
d) Applied Specific Integrated Circuits
Explanation: In digital electronics, ASIC stands for Application Specific Integrated Circuits. It is a customized
integrated circuit which is produced for a specific use and not for a common-purpose.
9. The programmability and high density of PLDs make them useful in the design of __________
a) ISAC
b) ASIC
c) SACC
d) CISF
Explanation: The programmability and high density of PLDs make them useful in the design of ASIC (i.e. Application
Specific Integrated Circuits) where design changes can be more rapidly and inexpensively.
advertisement
10. FPGA stands for __________
a) Full Programmable Gate Array
b) Full Programmable Genuine Array
c) First Programmable Gate Array
d) Field Programmable Gate Array
Explanation: In digital electronics, FPGA stands for Field Programmable Gate Array. This type of integrated circuit is
for general-purpose which is configured by the user as per their requirement.
11. Which of the following is a reprogrammable gate array?
a) EPROM
b) FPGA
c) Both EPROM and FPGA
d) ROM
Explanation: Both FPGA and EPROM are reprogrammable gate array.
12. The difference between FPGA and PLD is that __________
a) FPGA is slower than PLD
b) FPGA has high power dissipation
c) FPGA incorporates logic blocks
Explanation: The difference between FPGA and PLD is that FPGA incorporates logic blocks instead of fixed AND-OR
gates and is faster with low power dissipation. FPGAs are designed for having higher gate count whereas, PLDs are
used for lesser gate counts.
advertisement
To practice assessment questions on all areas of Digital Electronic Circuits, here is complete set of 1000+
Multiple Choice Questions and Answers.
« Prev - Digital Circuits Questions and Answers – Introduction of Memory Devices – 1» Next - Digital Circuits
Questions and Answers – Introduction of Memory Devices – 3This set of Digital Electronic/Circuits Puzzles focuses on
1. Memories are classified into _____ categories.
a) 3
b) 4
c) 5
d) 6
Explanation: Memory is typically classified of 2 types: Primary and Secondary. These are further classified into 5
types of memories and these are Secondary, RAM, Dynamic/Static, Volatile/Non-volatile, Magnetic/Semiconductor
Memory.
advertisement
2. Secondary memory is also known as ___________
a) Registers
b) Main Memory
c) RAM
d) Both registers and main memory
Explanation: Secondary memory is also known as Registers/Main Memory. In secondary memory, data is usually
stored for a long-term.
3. In a computer, registers are present __________
a) Within control unit
b) Within RAM
c) Within ROM
d) Within CPU
Explanation: In a computer, registers are present within the CPU to store data temporarily during arithmetic and
logical operations and during the functioning of the ALU.
4. Which of the following has the lowest access time?
a) RAM
b) ROM
c) Registers
d) Flag
Explanation: Registers has the lowest access time, as they are available inside the CPU. Registers are present within
the CPU to store data temporarily during arithmetic and logical operations and during the functioning of the ALU.
5. Main memories of a computer, usually made up of __________
a) Registers
b) Semiconductors
c) Counters
d) PLDs
Explanation: Main memories of a computer, usually made up of semiconductors which are available external to the
CPU to store program and data during execution of a program. Registers are present within the CPU to store data
temporarily during arithmetic and logical operations and during the functioning of the ALU.
advertisement
6. As the storage capacity of the main memory is inadequate, which memory is used to enhance it?
a) Secondary Memory
b) Auxiliary Memory
c) Static Memory
d) Both Secondary Memory and Auxiliary Memory
Explanation: As the storage capacity of the main memory is inadequate, Secondary memory is used to enhance it
and it is also known as auxiliary memory. Secondary memory is also known as Registers/Main Memory. In secondary
memory, data is usually stored for a long-term.
7. Which memories are if magnetic memory type?
a) Main Memory
b) Secondary Memory
c) Static Memory
d) Volatile Memory
Explanation: Usually, secondary memories are of magnetic memory type that are used to store large type quantities
of data. In secondary memory, data is usually stored for a long-term.
8. Which of the following comes under secondary memory/ies?
a) Floppy disk
b) Magnetic drum
c) Hard disk
Explanation: All of the mentioned equipments are of external storage which is known as secondary memories. In
secondary memory, data is usually stored for a long-term.
9. Based on method of access, memory devices are classified into ____________ categories.
a) 2
b) 3
c) 4
d) 5
Explanation: Based on the method of access, memory devices are classified into two categories and these are
sequential access memory and RAM. A sequential access memory is one in which a particular memory location is
accessed sequentially.
advertisement
10. A sequential access memory is one in which __________
a) A particular memory location is accessed rapidly
b) A particular memory location is accessed sequentially
c) A particular memory location is accessed serially
d) A particular memory location is accessed parallely
Explanation: A sequential access memory is one in which A particular memory location is accessed sequentially (i.e.
the ith memory location is accessed only after sequencing through previous (i-1) memory locations).
11. An example of sequential access memory is __________
a) Floppy disk
b) Hard disk
c) Magnetic tape memory
d) RAM
Explanation: A sequential access memory is one in which a particular memory location is accessed sequentially. In
magnetic tape memory, data is accessed sequentially.
12. A Random Access Memory is one in which __________
a) Any location can be accessed sequentially
b) Any location can be accessed randomly
c) Any location can be accessed serially
d) Any location can be accessed parallely
Explanation: A Random Access Memory is one in which any location can be accessed randomly.
13. An example of RAM is __________
a) Floppy disk
b) Hard disk
d) Semiconductor RAM
Explanation: A Random Access Memory is one in which any location can be accessed randomly. A semiconductor
RAM is too much fast and can occupy any space in the memory location.
advertisement
14. A static memory is one in which __________
a) Content changes with time
b) Content doesn’t changes with time
c) Memory is static always
d) Memory is dynamic always
Explanation: A static memory is one in which content doesn’t changes with time (i.e. stable). Dynamic memory is one
in which content changes with time (i.e. unstable).
15. A dynamic memory is one in which __________
Explanation: A static memory is one in which content doesn’t change with time (i.e. stable). Dynamic memory is one
To practice puzzles on all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple Choice Questions
and Answers.
Questions and Answers – Introduction of Memory Devices – 4This set of Advanced Digital Electronic/Circuits
Questions & Answers focuses on “Introduction of Memory Devices-4”.
1. Dynamic memory cells use _______________ as the storage device.
a) The reactance of a transistor
b) The impedance of a transistor
c) The capacitance of a transistor
d) The inductance of a transistor
Explanation: Capacitance of a transistor prevents from loss of information in a dynamic memory cell.
advertisement
2. To store 1-bit of information, how many transistor is/are used ____________
a) 1
b) 2
c) 3
d) 4
Explanation: Only one bit transistor is needed to store 1-bit of information.
3. Static memory holds data as long as __________
a) AC power is applied
b) DC power is applied
c) Capacitor is fully charged
d) High Conductivity
Explanation: In any semiconductor equipment, AC power can’t be supplied directly. So, static memory holds the data
as long as DC power is applied.
4. The example of dynamic memory is __________
a) CCD
b) Semiconductor dynamic RAM
c) Both CCD and semiconductor dynamic RAM
d) Floppy-Disk
Explanation: The examples of dynamic memories are CCD and semiconductor dynamic RAM because of the contents
of both the memories changes with time.
5. In dynamic memory, CCD stands for __________
a) Charged Count Devices
b) Change Coupled Devices
c) Charge Coupled Devices
d) Charged Compact Disk
Explanation: In dynamic memory, CCD stands for Charge Coupled Devices.
advertisement
6. Volatile memory refers to __________
a) The memory whose loosed data is achieved again when power to the memory circuit is removed
b) The memory which looses data when power to the memory circuit is removed
c) The memory which looses data when power to the memory circuit is applied
d) The memory whose loosed data is achieved again when power to the memory circuit is applied
Explanation: Volatile means ‘liable to change rapidly’ and volatile memory refers to the memory which looses data
rapidly when power to the memory circuit is removed. Thus, it looks after it’s data as long as it is powered. Non-
volatile means ‘not volatile’ and non-volatile memory refers to the memory which retains the data even if there is a
break in the power supply.
7. Non-volatile memory refers to __________
a) The memory whose loosed data is retained again when power to the memory circuit is removed/applied
8. The example of non-volatile memory device is __________
a) Magnetic Core Memory
b) Read Only Memory
c) Random Access Memory
d) Both Magnetic Core Memory and Read Only Memory
Explanation: Non-volatile means ‘not volatile’ and non-volatile memory refers to the memory which retains the data
even if there is a break in the power supply. The examples of non-volatile memory devices are Magnetic Core
Memory & ROM because both have capability to retain the data.
9. Based on material used for construction, memory devices are classifieds into ________ categories.
a) 2
b) 3
c) 4
d) 5
Explanation: Based on material used for construction, memory devices are classifieds into two categories, viz.,
Magnetic and Semiconductor memory. Magnetic recording is the process of storing data magnetically. Hard disk,
floppy disk, magnetic tape are examples of magnetic recording process.
advertisement
10. Magnetic recording is the process of __________
a) Storing data symmetrically

b) Storing data sequentially
c) Storing data magnetically
d) Both storing data symmetrically and
floppy disk, magnetic tape are examples of the magnetic recording process.
11. Magnetic drum is a storage medium using __________
a) The surface of a jumping magnetic drum
b) The surface of a rotating magnetic drum
c) The surface of a stopped magnetic drum
d) The surface of a moving magnetic drum
Explanation: Magnetic drum is a storage medium using the surface of a rotating magnetic drum which have tendency
to hold the data.
12. Magnetic core is the digital memory in which data is stored magnetically in individual cores operated by
__________
a) Up and down select wires
b) Row and column select wires
c) Serial and parallel select wires
d) Up and Serial select wires
Explanation: Magnetic core is the digital memory in which data is stored magnetically in individual cores operated by
row and column select wires, with data obtained from sense wire.
13. By which technology, semiconductor memories are constructed?
a) PLD
b) LSI
c) VLSI
d) Both LSI and VLSI
Explanation: Generally, semiconductor memories are constructed using Large Scale Integration (LSI) or Very Large
Scale Integration (VLSI) because these are made up of NMOS, CMOS, BJT, etc.
advertisement
To practice advanced questions on all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple
Choice Questions and Answers.
Questions and Answers – Introduction of Memory Devices – 5This set of Digital Electronic Circuits Questions &
Answers for campus interviews focuses on “Introduction of Memory Devices-5”.
1. When two or more devices try to write data in a bus simultaneously, is known as ______________
a) Bus collisions
b) Address multiplexing
c) Address decoding
d) Bus contention
Explanation: Bus contention is an undesirable state of the bus of a computer, in which more than one memory
mapped device or the CPU is attempting to place output values onto the bus at once.
advertisement
2. A memory is a collection of ____________
a) Unit cells
b) Storage cells
c) Data cells
d) Binary cells
Explanation: A memory is a collection of storage cells with associated circuits needed to transfer information.
3. To transfer the information from input to output and vice versa, the cells used are ____________
a) Storage cells
b) Data cells
c) Unit cells
d) Both data and unit cells
Explanation: To transfer the information from input to output and vice versa, the cells used are called storage cells.
The storage cells stores data in the form of binary information.
4. The data stored in a group of bits is called ____________
a) Nibble
b) Word
c) Byte
d) Address
Explanation: The data stored in a group of bits is called word. Usually, a word is a group of 16-bits or 2-bytes.
5. Each word consist of a sequence of ____________
a) Letters
b) Binary numbers
c) Hexadecimal numbers
d) Gray codes
Explanation: Each word consists of a sequence of 0s and 1s (i.e. binary numbers). Usually, a word is a group of 16-
bits or 2-bytes.
advertisement
6. Each word stored in a memory location is represented by ____________
a) RAM
b) ROM
c) Storage class
d) Address
Explanation: Each word stored in a memory location is represented by address. Usually, a word is a group of 16-bits
or 2-bytes.
7. The group of each 8-bit is called ____________
a) Nibble
b) Flag
c) Byte
d) Word
Explanation: 1 byte = 8-bit, 4-bits = 1 nibble and 16-bits = 1 word.
8. The capacity of a memory unit is ____________
a) The number of binary input stored
b) The number of words stored
c) The number of bytes stored
Explanation: The total number of bytes that can be stored, is the maximum capacity of a memory unit. However,
memory unit is the smallest unit of a processor.
9. The communication between memory and its environment is achieved through ____________
a) Control lines
b) Data input/output lines
c) Address selection lines
Explanation: Firstly, the data input is needed to transfer the information and it is passed through the address lines
and then controlled by control lines. The control lines are responsible for the timing and control of the signals sent
and received.
advertisement
10. One of the most important specifications on magnetic media is the ____________
a) Polarity reversal rate
b) Tracks per inch
c) Data transfer rate
d) Rotation speed
Explanation: The rate of data transfer depends on the properties of magnetic media.
To practice all areas of Digital Electronic Circuits for campus interviews, here is complete set of 1000+ Multiple
Questions and Answers – Read Only Memory (ROM) – 1This set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Read Only Memory (ROM) – 1”.
1. Which of the following has the capability to store the information permanently?
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
Explanation: ROM (Read Only Memory) has the capability to store the information permanently. RAM provides
random access to memory. Storage cells are responsible for the transfer of data from and into the memory.
advertisement
2. ROM has the capability to perform _____________
a) Write operation only
b) Read operation only
c) Both write and read operation
d) Erase operation
Explanation: ROM means “Read Only Memory”. Hence, it has the capability to perform read operation only. No write
or erase operation could be performed in the ROM.
3. Since, ROM has the capability to read the information only then also it has been designed, why?
a) For controlling purpose
b) For loading purpose
c) For booting purpose
d) For erasing purpose
Explanation: ROM means “Read Only Memory”. Hence, it has capability to perform read operation only. No write or
erase operation could be performed in the ROM. It has designed to provide the computer with resident programmes
and for booting purpose.
4. The ROM is a ___________
c) Magnetic circuit
d) Static circuit
Explanation: ROM is a combination of different ICs. So, it is a combinational circuit. It depends on present input and
not past states.
5. ROM is made up of ___________
a) NAND and OR gates
b) NOR and decoder
c) Decoder and OR gates
d) NAND and decoder
Explanation: ROM (Read Only Memory) has the capability to store the information permanently. ROM is made up of
decoder and OR gates within a single IC package.
advertisement
6. Why are ROMs called non-volatile memory?
a) They lose memory when power is removed
b) They do not lose memory when power is removed
c) They lose memory when power is supplied
d) They do not lose memory when power is supplied
Explanation: Volatile memory stores data as long as it is powered. ROMs are called non-volatile memory because of
they do not lose memory when power is removed.
7. In ROM, each bit is a combination of the address variables is called ___________
a) Memory unit
b) Storage class
c) Data word
d) Address
Explanation: In ROM, each bit combination that comes out of the output lines is called data word. Usually, a word
consists of 16-bits or 2-bytes.
8. Which is not a removable drive?
a) Zip
b) Hard disk
c) Super Disk
d) Jaz
Explanation: Hard disk is present inside a computer. So, it is not a removable drive.
9. In ROM, each bit combination that comes out of the output lines is called ___________
a) Memory unit
b) Storage class
c) Data word
d) Address
advertisement
10. VLSI chip utilizes ___________
a) NMOS
b) CMOS
c) BJT
Explanation: Very Large Scale Integration (VLSI) (ranging from 10,000 to 100,000 gates per IC) is a memory chip
which is made up of NMOS, CMOS, BJT, and BiCMOS.
Questions and Answers – Read Only Memory (ROM) – 2This set of tricky Digital Electronic/Circuits questions and
answers focuses on “Read Only Memory(ROM) – 2”.
1. The MOS technology based semiconductor ROMs are classified into _____ categories.
a) 2
b) 3
c) 4
d) 5
Explanation: The MOS technology based semiconductor ROMs are classified into three categories: Mask ROM,
PROM,& EPROM. PROM stands for Programmable Read Only Memory in which the ROM can be externally
programmed by the user. EPROM stands for Erasable Programmable Read Only Memory, where the ROM and be
cleared and re-programmed.
advertisement
2. MOS ROM is constructed using __________
a) FETs
b) Transistors
c) MOSFETs
d) BJTs
Explanation: MOS ROM is made up of MOSFETs. MOSFETs are Metal Oxide Semiconductor Field Effect Transistors.
3. The full form of EEPROM is __________
a) Erasable Electrically Programmable ROMs
b) Electrically Erasable Programmable ROMs
c) Electrically Erasable Programming ROMs
d) Electrically Erasable Programmed ROMs
Explanation: The full form of EEPROM is Electrically Erasable Programmable ROMs. In EPROM (Erasable
Programmable ROMs), the ROM is cleared by exposing it to UV radiation and also it’s a tedious process. Whereas, in
EEPROM, the ROM can be cleared electrically and thus is less time consuming and more efficient.
4. Which of the following best describes EPROMs?
a) EPROMs can be programmed only once
b) EPROMs can be erased by UV
c) EPROMs can be erased by shorting all inputs to the ground
d) EPROMs can be erased electrically
Explanation: EPROM (Erasable Programmable ROMs), the ROM is cleared by exposing it to UV radiation and also it’s
a tedious process. Whereas, in EEPROM, the ROM can be cleared electrically and thus is less time consuming and
more efficient.
5. The Width of a processor’s data path is measured in bits. Which of the following are common data paths?
a) 8 bits
b) 12 bits
c) 16 bits
d) 32 bits
Explanation: In generalised form, the data paths are of 8 bits. The data path, also known as data bus, is the channel
through which the processor sends and receives data.
advertisement
6. What type of memory is not directly addressable by the CPU and requires special software called EMS
(expanded memory specification)?
a) Extended
b) Expanded
c) Base
d) Conventional
Explanation: Expanded memory is not directly addressable by the CPU. Expanded memory is the additional memory
which is incorporated beyond the parent memory limit of the processor.
7. Which bus is used for input and output in case of microprocessor operation?
a) Address bus
b) System bus
c) Control bus
d) Data bus
Explanation: The input and output are used to control the function of a microprocessor. Hence, the control bus is
used to transfer the input and output signal from microprocessor to external peripherals and or from external
peripherals to microprocessor.
8. What is the major difference between DRAM and SRAM?
a) Dynamic RAMs are always active; static RAMs must reset between data read/write cycles
b) SRAMs can hold data via a static charge, even with power off
c) The only difference is the terminal from which the data is removed—from the FET Drain or Source
d) DRAMs must be periodically refreshed
Explanation: DRAMs must be periodically refreshed so that it can store the new information. DRAMs are slower
compared to SRAMs as the access time for SRAM is less than that of DRAM.
9. Which of the following is not a part of Hard disk?
a) Platter
b) Read/Write
c) Valve
d) Spindle
Explanation: A valve is a device that regulates, directs or controls the flow of a fluid (gases, liquids, fluidized solids, or
slurries) by opening, closing, or partially obstructing various passageways. So, it is not a part of hard disk.
advertisement
10. Which ROM can be erased by an electrical signal?
a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
Explanation: In EPROM (Erasable Programmable ROMs), the ROM is cleared by exposing it to UV radiation and also
it’s a tedious process. Whereas, in EEPROM, the ROM can be cleared electrically and thus is less time consuming and
more efficient.
11. In the floppy drive, data is written to and read from the disk via a magnetic _____ head mechanism.
a) Cluster
b) Read/Write
c) Cylinder
d) Recordable
Explanation: A floppy disk is a removable disk used for storing data via magnetic facilities. In the floppy drive, data is
written to and read from the disk via a magnetic read/write head mechanism.
12. What does the term “random access” mean in terms of memory?
a) Any address can be accessed in systematic order
b) Any address can be accessed in any order
c) Addresses must be accessed in a specific order
d) Any address can be accessed in reverse order
Explanation: “Random access” mean which can be accessed randomly and in other words any address can be
accessed in any order.
13. Which type of ROM has to be custom built by the factory?
a) EEPROM
b) Mask ROM
c) EPROM
d) PROM
Explanation: All types of ROM are programmable and can be programmed as per requirement but the mask ROM is
always programmed for specific application and it can’t be reprogrammed. PROM stands for Programmable Read
Only Memory in which the ROM can be externally programmed by the user. EPROM stands for Erasable
Programmable Read Only Memory, where the ROM and be cleared and re-programmed.
advertisement
14. The computer’s main memory is __________
a) Hard drive and RAM
b) CD-ROM and hard drive
c) RAM and ROM
d) CMOS and hard drive
Explanation: The computer’s main memory is RAM and ROM because all the storage related operation are
performed by the data present in RAM/ROM. RAM stands for Random Access Memory where any address can
accessed in any order. ROM stands for Read Only Memory wherefrom data can only be read.
15. A major disadvantage of the mask ROM is that ____________
a) It is time consuming to change the stored data when system requirements change
b) It is very expensive to change the stored data when system requirements change
c) It cannot be reprogrammed if stored data needs to be changed
d) It has an extremely short life expectancy and requires frequent replacement
Explanation: A major disadvantage of the mask ROM is that it cannot be reprogrammed if stored data needs to be
changed. PROM stands for Programmable Read Only Memory in which the ROM can be externally programmed by
the user. EPROM stands for Erasable Programmable Read Only Memory, where the ROM and be cleared and re-
programmed.
To practice tricky questions and answers on all areas of Digital Electronic Circuits, here is complete set of 1000+
« Prev - Digital Circuits Questions and Answers – Read Only Memory (ROM) – 1» Next - Digital Circuits Questions
and Answers – Read Only Memory (ROM) – 3This set of Digital Electronic/Circuits Aptitude Test focuses on “Read
Only Memory(ROM)-3”.
1. ROM may be programmed in _____ ways.
a) 2
b) 3
c) 4
d) 5
Explanation: ROM may be programmed in two different ways: (i) Mask Programming & (ii) PROM. Mask
Programming is done by the manufacture. Whereas, PROM(Programmable ROM) is programmed by the user.
advertisement
2. Which programming is done during the manufacturing process?
a) Mask Programming
b) PROM
c) Both PROM and mask programming
d) EPROM
Explanation: Mask ROM is permanently programmed during the manufacturing process. Whereas,
PROM(Programmable ROM) is programmed by the user.
3. A photographic negative is called a ____________
a) Photo
b) Negative
c) Mask
d) Virtual image
Explanation: A photographic negative is called a mask is used to control the electrical connections on the chip.
4. Mask programming is also known as __________
a) EPROM
b) PROM
c) Custom programming
d) Both PROM and EPROM
Explanation: Mask programming is also known as custom programming. Mask ROM is permanently programmed
during the manufacturing process. Whereas, PROM(Programmable ROM) is programmed by the user.
5. The total storage capacity of 16 * 8 ROM is __________
a) 8 bits
b) 16 bits
c) 128 bits
d) 64 bits
Explanation: ROM stands for Read Only Memory in which data is stored permanently and wherefrom data can only
be read and rarely modified. The total storage capacity of 16 * 8 ROM is 128 bits (i.e. 16 * 8 = 128).
advertisement
6. Which IC is a typical MSI/TTL based?
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
Explanation: MSI/TTL stands for Medium Scale Integration of Transistor-Transistor Logic. IC 74187 is a typical
MSI/TTL based.
7. IC 74187 is of __________
a) 512 bits
b) 1024 bits
c) 256 bits
d) 68 bits
Explanation: IC 74187 is of 1024 bits because it is organised as 256 * 4. Thus, it has 256 rows and 4 columns.
8. How many rows and columns are present in IC 74187?
a) 128, 3
b) 128, 4
c) 256, 3
d) 256, 4
Explanation: IC 74187 is organised as 256 * 4, hence it has 256 rows and 4 columns.
IC 74187 is of 1024 bits because it is organized as 256 * 4.
9. Which of the following IC is of 256 bit?
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
Explanation: IC 74188 is of 256 bits. Since, it is organised as 32 * 8 = 256. Thus, it has 32 rows and 8 columns.
10. Which IC is known as bipolar ROM?
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
Explanation: IC 74188 is known as bipolar ROM since it is made up of TTL logic.
advertisement
11. How many address location a bipolar ROM has?
a) 16
b) 32
c) 64
d) 8
Explanation: Bipolar ROM means IC 74188 and it is organized as 32 * 8. Thus, it has 32 rows and 8 columns. So, it has
32 address locations and each of which has 8 bits of storage.
12. Which of the following is known as MOS static ROM?
a) TMS 45276
b) TMS 45278
c) TMS 45279
d) TMS 45275
Explanation: TMS 45276 is known as MOS static ROM and it is made up of MOSFETs.
13. TMS 45276 is of __________
a) 32 KB
b) 56 KB
c) 8 bits
d) 4 bytes
Explanation: TMS 45276 is known as MOS static ROM and it is made up of MOSFETs. In ROM, the data remains even
when the power is switched off. TMS 45276 is of 32 KB.
14. Which of the following has the capability to store the highest bits of data?
a) TMS 45276
b) IC 74188
c) IC 74187
d) IC 74185
Explanation: TMS 45276 has the capability to store the highest bits of data because of 32768 * 8 = 12,62,144
organization.
15. What does CS mean in a chip?
a) Storing Capacity
b) Custom Select
c) Chip Select
d) Custom Storage
Explanation: CS means chip select and with the help of CS a chip is activated/deactivated. It is used for enabling or
disabling the function of the chip.
advertisement
16. ROMs are used to __________
a) Store bootstrap program
b) Character generation
c) Code conversion
Explanation: ROM stands for Read Only Memory in which data is permanently stored, even when the power is
turned off. It is used to store bootstrap program, character generation and code conversion.
To practice all areas of Digital Electronic Circuits for aptitude tests, here is complete set of 1000+ Multiple Choice
and Answers – Programmable Read Only Memory – 1This set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Programmable Read Only Memory -1”.
1. The time from the beginning of a read cycle to the end of tACS/tAA is called as ____________
a) Write enable time
b) Data hold
c) Read cycle time
d) Access time
Explanation: The time from the beginning of a read cycle to the end of tACS/tAA is called as access time. It is the time
in which data is fetched from the storage.
advertisement
2. Why did PROM introduced?
a) To increase the storage capacity
b) To increase the address locations
c) To provide flexibility
d) To reduce the size

Explanation: In order to provide some flexibility in the possible applications of ROM, PROM is introduced. PROM
stands for Programmable ROM, in which the ROM is programmed by the user.
3. Which of the following is programmed electrically by the user?
a) ROM
b) EPROM
c) PROM
d) EEPROM
Explanation: Programmable ROMs can be programmed electrically by the user but can’t be reprogrammed.
EEPROMs can be electrically erased and re-programmed by the user.
4. PROMs are available in ___________
a) Bipolar and MOSFET technologies
b) MOSFET and FET technologies
c) FET and bipolar technologies
d) MOS and bipolar technologies
Explanation: PROMs (Programmable ROMs) can be programmed electrically by the user but can’t be reprogrammed.
PROMs are available in both bipolar and MOS (Metal Oxide Semiconductor) technologies.
5. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ___________
a) 4096
b) 16384
c) 32768
d) 8129
Explanation: 1 address can store 8 bits. Therefore, total capacity of a memory having n addresses = 8 * n.
Therefore, for 2048 addresses,
total capacity of a memory = 2048 * 8 = 16384 bits.
advertisement
6. How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length
of eight bits?
a) Eight
b) Two
c) One
d) Four
Explanation: RAM stands for Random Access Memory in which any memory address can be accessed in any order. It
requires word of length 8 bits. So, one word needs of 1 bit and 8 bit requires 8 bits.
7. Which of the following best describes the fusible-link PROM?
a) Manufacturer-programmable, reprogrammable
b) Manufacturer-programmable, one-time programmable
c) User-programmable, reprogrammable
d) User-programmable, one-time programmable
Explanation: The fusible-link PROM is user programmable and one time programmable. It means that a written
program can not be reprogrammed. EPROMs can be erased and re-programmed.
8. How can ultraviolet erasable PROMs be recognized?
a) There is a small window on the chip
b) They will have a small violet dot next to the #1 pin
c) Their part number always starts with a “U”, such as in U12
d) They are not readily identifiable, since they must always be kept under a small cover
Explanation: An ultraviolet erasable PROMs have small window on the chip with black marked. Such type of PROMS
are called EPROMS which are cleared by exposing it to UV radiation. They are re-programmable.
9. Which part of a Flash memory architecture manages all chip functions?
a) Program verify code
b) Floating-gate MOSFET
c) Command code
d) Input/Output pins
Explanation: MOSFET technology is the best one in the manufacturing of chip because it has high flexibility and
storage capacity. Thus, Floating-Gate MOSFET part of a Flash Memory architecture manages all chip functions.
advertisement
10. How much locations an 8-bit address code can select in memory?
a) 8 locations
b) 256 locations
c) 65,536 locations
d) 131,072 locations
Explanation: An 8 bit address code requires 32 memory locations and it can hold maximum upto 32 * 8 = 256
locations = 28.
11. What is a fusing process?
a) It is a process by which data is passed to the memory
b) It is a process by which data is read through the memory
c) It is a process by which programs are burnout to the diode/transistors
d) It is a process by which data is fetched through the memory
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it can not be
reprogrammed if any error occurs.
12. Fusing process is ___________
a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
Explanation: Since, any program cannot be reprogrammed in a PROM, so this process is irreversible as PROMs are
programmed using the Fusing process. Fusing is a process by which programs are burnout to the diode/transistors
and it can not be reprogrammed if any error occurs.
13. The cell type used inside a PROM is ___________
a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
Explanation: The cell type used inside a PROM is fuse cells by which a program is burnout. Fusing is a process by
which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.
advertisement
14. How many types of fuse technologies are used in PROMs?
a) 2
b) 3
c) 4
d) 5
reprogrammed if any error occurs. Three types of fuse technologies are used in PROMs and these are: (i) Metal links,
(ii) Silicon links, & (iii) p-n junctions.
15. Metal links are made up of ___________
a) Polycrystalline
b) Magnesium sulphide
c) Nichrome
d) Silicon dioxide
Explanation: Metal links are made up of Nichrome materials.

and Answers – Programmable Read Only Memory – 2This set of Digital Electronic/Circuits Problems focuses on
“Programmable Read Only Memory-2”.
1. Silicon links are made up of _____________
a) Polycrystalline silicon
b) Polycrystalline magnesium
c) Nichrome
d) Silicon dioxide
Explanation: Metal links are made up of Nichrome materials. Silicon links are made up of polycrystalline silicon.
advertisement
2. During programming p-n junction is _____________
a) Avalanche reverse biased
b) Avalanche forward biased
c) Zener reverse biased
d) Zener reverse biased
Explanation: The sudden heavy flow of electrons in the reverse direction and heat cause aluminium ions to migrate.
So, during programming p-n junction is avalanche reversed biased.
3. The full form of FAMOS is _____________
a) Floating Gate Avalanche Injection MOS
b) Float Gate Avalanche Injection MOS
c) Floating Gate Avalanche Induction MOS
d) Float Gate Avalanche Induction MOS
Explanation: The full form of FAMOS is Floating Gate Avalanche Injection MOS. It is a floating gate transistor in which
the trapped electrons is responsible for the dropping of the voltage.
4. PROM is programmed by _____________
a) EPROM programmer
b) EEPROM programmer
c) PROM programmer
d) ROM programmer
Explanation: PROM is programmed by plugging it into a special device called PROM programmer. The ROM cannot
be clear and hence PROM is a one-time programmable device.
5. The PROM starts out with _____________
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
Explanation: PROM is a one-time programmable device, which is programmed by the user. The PROM starts out with
all 0s. These current pulses blow the fuse links, thus creating the desire pattern.
advertisement
6. For the implementation of PROM, which IC is used?
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
Explanation: For implementation of PROM, IC 74186 is used. IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62
rows and 8 columns.
7. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
Explanation: IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.
8. How many memory locations are addressed using 18 address bits?
a) 165,667
b) 245,784
c) 262,144
d) 212,342
Explanation: For n address bits, the memory location will consist of 2n bits. Using 18 address bits, 218 = 262,144 (=
256 K) words are addressed.
9. How many address bits are needed to operate a 2K * 8-bit memory?
a) 10
b) 11
c) 12
d) 13
Explanation: For n address bits, the memory location will consist of 2n bits. Thus, for 2K, only 11 address bits are
required, because 211 = 2K.
advertisement
10. What is the bit storage capacity of a ROM with a 1024 × 8 organization?
a) 1024
b) 4096
c) 2048
d) 8192
Explanation: For n address bits, the memory location will consist of 2n bits. 1024 = 210. So, 210 * 23 = 1024 * 8 =
8192 bit.
To practice problems on all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple Choice
« Prev - Digital Circuits Questions and Answers – Programmable Read Only Memory – 1» Next - Digital Circuits
Questions and Answers – Erasable Programmable Read Only MemoryThis set of Digital Electronics/Circuits Multiple
Choice Questions & Answers (MCQs) focuses on “Erasable Programmable Read Only Memory”.
1. EPROM uses an array of _______________
a) p-channel enhancement type MOSFET
b) n-channel enhancement type MOSFET
c) p-channel depletion type MOSFET
d) n-channel depletion type MOSFET
Explanation: EPROMs are Erasable Programmable ROMs which can be erased using UV radiation and re-
programmed. EPROM uses an array of n-channel enhancement type MOSFET with an insulated gate structure.
advertisement
2. The EPROM was invented by ______________
a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell
Explanation: The EPROM was invented by Dov Frohman of Intel in 1971. EPROMs are Erasable Programmable ROMs
which can be erased using UV radiation and re-programmed.
3. Address decoding for dynamic memory chip control may also be used for ______________
a) Chip selection and address location
b) Read and write control
c) Controlling refresh circuits

d) Memory mapping
Explanation: Address decoding for dynamic memory chip control may also be used for chip selection and address
location. Chip Selection enables or disables the functioning of the chip.
4. Which of the following describes the action of storing a bit of data in a mask ROM?
a) A 0 is stored by connecting the gate of a MOS cell to the address line
b) A 0 is stored in a bipolar cell by shorting the base connection to the address line
c) A 1 is stored by connecting the gate of a MOS cell to the address line
d) A 1 is stored in a bipolar cell by opening the base connection to the address line
Explanation: The action of storing a bit of data in a mask ROM is that when a 1 is stored by connecting the gate of a
MOS cell to the address line. Mask ROMs are programmed by the manufacturer and are custom made as per the
user.
5. The check sum method of testing a ROM ______________
a) Allows data errors to be pinpointed to a specific memory location
b) Provides a means for locating and correcting data errors in specific memory locations
c) Indicates if the data in more than one memory location is incorrect
d) Simply indicates that the contents of the ROM are incorrect
Explanation: If checking of a sum method goes wrong, it simply indicates that the contents of the ROM are incorrect.
advertisement
6. The initial values in all the cells of an EPROM is ______________
a) 0
b) 1
c) Both 0 and 1
d) Alternate 0s and 1s
Explanation: The initial values in all the cells of an EPROM is 1.
7. To store 0 in such a cell, the floating point must be ______________
a) Reprogrammed
b) Restarted
c) Charged
d) Power off
programmed. To store 0 in the cell of an EPROM, the floating point must be charged.
8. The major disadvantage of RAM is?
a) Its access speed is too slow
b) Its matrix size is too big
c) It is volatile
d) High power consumption
Explanation: RAM is volatile memory. Thus, RAM stores the data as long as it is powered on and once the power
goes out, it loses its data.
9. Which one of the following is used for the fabrication of MOS EPROM?
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
programmed. TMS 2516 is a MOS EPROM device.
advertisement
10. How many addresses a MOS EPROM have?
a) 1024
b) 512
c) 2516
d) 256
programmed. MOS EPROM (i.e. TMS 2516) has 2048 (211 = 2048) addresses.
11. To read from the memory, the select input and the power down/program input must be ______________
a) HIGH
b) LOW
c) Sometimes HIGH and sometimes LOW
d) Alternate HIGH and LOW
Explanation: To read from the memory, the select input and the power down/program input must be LOW.
12. ROMs retain data when ______________
a) Power is on
b) Power is off
c) System is down
Explanation: ROM retains the data when power is off/on/down because it has to read the data from memory only
and it is done in every condition. It is non-volatile memory.
13. Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could be stored in
this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Explanation: 8K = 8 * 1024 = 8192.
advertisement
14. When a RAM module passes the checker board test it is ______________
a) Able to read and write only 0s
b) Faulty
c) Probably good
d) Able to read and write only 1s

Explanation: When a RAM module passes the checker board test it is probably good. It is a volatile memory. Thus,
RAM stores the data as long as it is powered on and once the power goes out, it loses its data.
15. What is the difference between static RAM and dynamic RAM?
a) Static RAM must be refreshed, dynamic RAM does not
b) There is no difference
c) Dynamic RAM must be refreshed, static RAM does not
d) SRAM is slower than DRAM
Explanation: Dynamic RAM must be refreshed because it made up of capacitor, and capacitor required refresh. Static
RAM made up of flip flop and it doesn’t required a refresh.
Questions and Answers – Random Access Memory – 1This set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Random Access Memory – 1”.
1. What is the access time?
a) The time taken to move a stored word from one bit to other bits after applying the address bits
b) The time taken to write a word after applying the address bits
c) The time taken to read a stored word after applying the address bits
d) The time taken to erase a stored word after applying the address bits
Explanation: The access time is the time taken to read a stored word after applying the address bits in a MOS
EPROM. It is the time required to fetch data from the memory.
advertisement
2. What are the typical values of tOE?
a) 10 to 20 ns for bipolar
b) 25 to 100 ns for NMOS
c) 12 to 50 ns for CMOS
EPROM. It is the time required to fetch data from the memory. The typical values of tOE (i.e. access time) are 10 to
20 ns for bipolar, 25 to 100 ns for NMOS and 12 to 50 ns for CMOS.
3. Which of the following is not a type of memory?
a) RAM
b) FPROM
c) EEPROM
d) ROM
Explanation: EEPROM (Electrical Erasable Programmable ROM) is not a type of memory because it is used for erasing
purpose only. Through EEPROM, data can be erased electrically, thereby consuming less time.
4. The chip by which both the operation of read and write is performed __________
a) RAM
b) ROM
c) PROM
d) EPROM
Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the read and write operations
can be performed. Since it is volatile, therefore it stores data as long as power is on.
5. RAM is also known as __________
a) RWM
b) MBR
c) MAR
d) ROM
can be performed. Since it is volatile, therefore it stores data as long as power is on. RAM is also known as RWM (i.e.
Read Write Memory).
advertisement
6. If a RAM chip has n address input lines then it can access memory locations upto __________
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM
(i.e. Read Write Memory). If a RAM chip has n address input lines then it can access memory locations upto 2n.
7. The n-bit address is placed in the __________
a) MBR
b) MAR
c) RAM
d) ROM
Explanation: The n-bit address is placed in the Memory Address Register (MAR) to select one of 2n memory
locations. It stores the address of the instruction which is to be executed next.
8. Which of the following control signals are selected for read and write operations in a RAM?
a) Data buffer
b) Chip select
c) Read and write
d) Memory
Explanation: Read and write are control signals that are used to enable memory for read and write operations
respectively.
9. Computers invariably use RAM for __________
a) High complexity
b) High resolution
c) High speed main memory

d) High flexibility
(i.e. Read Write Memory). Computers invariably use RAM for their high high-speed main memory and then use
backup or slower-speed memories to hold auxiliary data.
advertisement
10. How many types of RAMs are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two types of RAM and these are static and dynamic. Static RAM(SRAM) is faster than dynamic
RAM(DRAM) as the access time for DRAM is more compared to that of SRAM.
11. Static RAM employs __________
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
Explanation: Static RAM employs bipolar or MOS flip-flops because both the semiconductor has storing capacity.
Thus, it’s access time is less and it is faster in operation.
12. Dynamic RAM employs __________
a) Capacitor or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
Explanation: Dynamic RAM employs a capacitor or MOSFET. Thus, it’s access time is more and it is slower in
operation.
13. Which one of the following is volatile in nature?
a) ROM
b) EROM
c) PROM
d) RAM
(i.e. Read Write Memory). RAMs are volatile because the stored data will be lost once the d.c. power applied to the
flip-flops is removed.
advertisement
14. The magnetic core memories have been replaced by semiconductor RAMs, why?
a) Semiconductor RAMs are highly flexible
b) Semiconductor RAMs have highest storing capacity
c) Semiconductor RAMs are smaller in size
(i.e. Read Write Memory). The magnetic core memories have been replaced by semiconductor RAMs because of
smaller in size, high storing capacity as well as flexibility.
15. The data written in flip-flop remains stored as long as __________
a) D.C. power is supplied
b) D.C. power is removed
c) A.C. power is supplied
d) A.C. power is removed
Explanation: Since flip-flops are made up of semiconductor materials. So, it can’t accept A.C. source and the data
written in flip-flop remains stored as long as the dc power is maintained.
« Prev - Digital Circuits Questions and Answers – Erasable Programmable Read Only Memory» Next - Digital
Circuits Questions and Answers – Random Access Memory – 2This set of tough Digital Electronic/Circuits Questions
focuses on “Random Access Memory-2”.
1. The memory capacity of a static RAM varies from ____________
a) 32 bit to 64 bit
b) 64 bit to 1024 bit
c) 64 bit to 1 Mega bit
d) 512 bit to 1 Mega bit
Explanation: Static RAM(SRAM ) is faster than dynamic RAM(DRAM) as the access time for DRAM is more compared
to that of SRAM. The memory capacity of a static RAM varies from 64 bits to 1 Mega bit.
advertisement
2. The input data bit is written into the cell by setting ____________
a) The flip-flop for 1
b) Resetting the flip-flop
c) The flip-flop for HIGH
d) Both the flip-flop for 1 and resetting the flip-flop
Explanation: The input data bit (1 or 0) is written into the cell by setting the flip-flop for 1 and the resetting the flip-
flop for a 0 when the R/W’ line is low, R/W is active-low pin.
3. When the READ/(WRITE)’ line is HIGH then the flip-flop is ____________

a) Activated
b) Deactivated
c) Unaffected
d) Both activated and deactivated
Explanation: When the READ/(WRITE)’ line is HIGH then the flip-flop is unaffected since it’s an active low pin. It
means that the stored bit (data) is gated to the data out line.
4. The flip-flop in static memory cell can be constructed using ____________
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
Explanation: The flip-flop in the static memory cell can be constructed using Bipolar Junction Transistor (BJT) and
MOSFETs because of it’s storing capability. Also, it’s access time is less and it is faster in operation.
5. Which of the following IC is TTL based static RAM?
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
MOSFETs because of it’s storing capability. Also, it’s access time is less and it is faster in operation. In IC 7489, TTL is
used which is static RAM.
advertisement
6. IC 7489 is of ____________
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
Explanation: The arrangement of IC 7489 is 16 * 4 = 64 bits. Thus, it has 16 columns and 4 rows.
7. Data is written in IC 7489 through ____________
a) Chip select
b) Enable
c) Data input
d) Memory enable
Explanation: Data can be written into the memory via the data inputs by supplying an address to the SELECT inputs
and holding both the memory enable and write enable LOW.
8. The first practical form of Random Access Memory (RAM) was the ____________
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
and holding both the memory enable and write enable LOW since it’s an active-low pin.
9. Magnetic-core memory was invented in ____________
a) 1946
b) 1948
c) 1947
d) 1945
Explanation: Magnetic-core memory was invented in 1947 and developed up until the mid-1970s. It became a
widespread form of random-access memory, relying on an array of magnetized rings. RAM is a volatile memory,
therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write Memory).
advertisement
10. Which of the following RAM is volatile in nature?
a) SRAM
b) DRAM
c) EEPROM
d) Both SRAM and DRAM
(i.e. Read Write Memory). Both static and dynamic RAM are considered volatile, as their state is lost or reset when
power is removed from the system.
11. Which one of the following IC is of 4KB?
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
Explanation: IC 2114 is of 4KB and it is a static RAM. Both static and dynamic RAM are considered volatile, as their
state is lost or reset when power is removed from the system.
12. Which of the following IC implements the static MOS RAM?
a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
Explanation: The IC TMS 4016 is a 2KB static MOS RAM. There are eleven address inputs available to select the 2014
locations.
13. What types of arrangements a TMS 4016 has?
a) 1024 * 4
b) 1024 * 8
c) 2048 * 4
d) 2048 * 8
locations.
Therefore, arrangements in TMS 4016 = 2048 * 8 = 2KB.
advertisement
14. How many address inputs are available in TMS 4016?
a) 10
b) 9
c) 12
d) 11
locations.
15. In TMS 4016, the data in/data out are ______________
a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional
Explanation: In TMS 4016, the data in/data out are bidirectional terminal. It means that the input/output can be
transmitted or received through the same terminal.
To practice tough questions on all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple Choice
« Prev - Digital Circuits Questions and Answers – Random Access Memory – 1» Next - Digital Circuits Questions and
Answers – Random Access Memory – 3This set of tough Digital Electronic/Circuits questions and answers focuses on
“Random Access Memory-3”.
1. Dynamic RAM is more preferable than static RAM, why?
a) DRAM is of the lowest cost, lowest density

b) DRAM is of the highest cost, reduced size
c) DRAM is of the lowest cost, highest density
d) DRAM is more flexible and lowest storage capacity
Explanation: The Dynamic Random Access Memory is the lowest cost, highest density random access memory
available. Nowadays, computers use DRAM for main memory. However, it’s access time is more compared to SRAM.
advertisement
2. The memory size of DRAM is ____________
a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
The memory size of DRAM lies between 16 to 256 MB.
3. The DRAM stores its binary information on __________
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
Explanation: Capacitor has high storing capability only, so DRAM stores its binary information in the form of electric
charges on capacitors. However, DRAM takes more time time to access data.
4. Most modern operating systems employ a method of extending RAM capacity, known as __________
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
Explanation: Most modern operating systems employ a method of extending RAM capacity, known as virtual
memory. Virtual memory is seen as part of main memory but is actually a secondary memory.
5. DRAM uses of integrated MOS capacitors as _______ instead of a flip-flop.
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
Explanation: DRAM uses of integrated MOS capacitors as memory cell instead of a flip-flop. The advantage of this
cell is that it allows very large memory arrays to be constructed on a chip at a lower cost per bit than in static
memories.
advertisement
6. What is the disadvantage of MOS capacitor in DRAM?
a) It can’t hold the data till a long period
b) It doesn’t holds the charge till a long period
c) It is highly densed
d) It is not flexible
Explanation: The disadvantage of MOS capacitor in DRAM is that it can’t hold the stored charge over a long period of
time and it has to be refreshed every few millisecond. Thus, DRAM is slow in operation.
7. The dynamic RAM offers __________
a) High power consumption, large storage capacity
b) Reduced power consumption, large storage capacity
c) Reduced power consumption, short storage capacity
d) High power consumption, short storage capacity
Explanation: The dynamic RAM offers reduced power consumption and large storage capacity in a single memory
chip. With the availability of such high packing density memory ICs, the capacity of memory will continue to grow.
However, it’s access time is more and thus operation is slow.
8. The main memory of a PC is made of __________
a) Cache
b) Dynamic RAM
c) Static RAM
d) Both cache and dynamic RAM
Explanation: The main memory of a PC is made of cache and DRAM. DRAM offers reduced power consumption and
large storage capacity in a single memory chip.
9. Virtual memory consists of __________
a) SRAM
b) DRAM
c) Magnetic memory
d) Main Memory
memory which consists of SRAM.
advertisement
10. Dynamic RAM is used as main memory in a computer system as __________
a) It has a lower cell density
b) It needs refreshing circuitry
c) Consumes less power
d) Has higher speed
Explanation: Dynamic RAM is used as main memory in a computer system as it has a higher speed due to the
presence of MOSFET technology. However, it’s access time is more compared to SRAM and operation is slow.
11. Cache memory acts between __________
a) RAM and ROM
b) CPU and RAM
c) CPU and Hard Disk
d) CPU and ROM
Explanation: In a computer, cache memory acts between CPU and RAM.

12. Which characteristic of RAM memory makes it not suitable for permanent storage?
a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile
Explanation: RAM is volatile. Therefore, it stores data only as long as the d.c power is on.
13. Why do a DRAM employ the address multiplexing technique?
a) To reduce the number of memory locations
b) To increase the number of memory locations
c) To reduce the number of address lines
d) To increase the number of address lines
Explanation: A Dynamic RAM usually employs a technique called address multiplexing to reduce the number of
address lines and thus the number of input/output pins on the IC package.
advertisement
14. An address multiplexing in DRAM is of _____ bits.
a) 10240
b) 15289
c) 16384
d) 17654
address lines and thus the number of input/output pins on the IC package. Address multiplexing has 214 = 16384
bits.
15. What is a sense amplifier?
a) It is an amplifier which converts ac current into dc current
b) It is an amplifier which lowers the input voltage
c) It is an amplifier which increases the input voltage

d) It is an amplifier which converts the low voltage to a sufficient voltage
Explanation: A sense amplifier for each column is necessary to convert from the low voltage and low energy to a
sufficient level on the I/O data line.
To practice tough questions and answers on all areas of Digital Electronic Circuits, here is complete set of 1000+
Answers – Random Access Memory – 4This set of Basic Digital Electronic/Circuits Interview questions and answers
1. DRAM is fabricated by using IC __________
a) 2114
b) 7489
c) 4116
d) 2776
Explanation: DRAM is Dynamic RAM which takes more access time compared to SRAM and is thus, slower in
operation comparatively. Although, in general it offers high speed and is used in most computers nowadays. DRAM
is fabricated by using IC 4116.
advertisement
2. IC 4116 is of ______ storage memory.

a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
Explanation: IC 4116 is a DRAM of 16 KB storage memory. It requires three supply voltages (+5V, -5V, and +12V) to
operate the IC unit.
3. How many supply voltage IC 4116 requires to operate the IC unit?
a) 3
b) 2
c) 1
d) 4
4. The full form of PSRAM is __________
a) Plugged Static RAM
b) Plugged Stored RAM
c) Pseudo Stored RAM
d) Pseudo Static RAM
Explanation: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM which is implemented as a SRAM.
5. Pseudo static RAM is a __________
a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM
Explanation: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM having built-in fresh logic, which is
implemented as an SRAM.
advertisement
6. When PSRAM is performing internal refresh __________
a) The read operation is performed
b) The write operation is performed
c) It can not be accessed for read or write
d) The voltage goes HIGH
implemented as a SRAM. So, it can not be accessed for read or write during the refresh operation.
7. RAMs are utilized in the computer as __________
a) Scratch-pad
b) Buffer
c) Main memory
Explanation: RAMs are utilized in the computer as a scratch-pad, buffer and main memories. These are the
applications of RAMs. Mostly, these RAMs are DRAMs as they provide high speed.
8. The advantages of RAMs are __________
a) Non destructive read out
b) Fast operating speed
c) Low power dissipation
Explanation: The advantages of RAM are Non-destructive read out, Fast operating speed and Low power dissipation.
9. Which one is more economical?
a) ROM
b) RAM
c) EROM
d) PROM
Explanation: RAM is more economical than ROM because MOS memories are more economical than the magnetic
core for small and medium sized systems.
advertisement
10. Which one is self-compatible?
a) ROM
b) RAM
c) EROM
d) PROM
Explanation: As semiconductor memories enjoy common interface and technology between sensing and decoding
circuitry and the storage element itself, so RAMs are self-compatible. Also, they provide high speed and fast
operation.
11. The memory which is used for storing programs and data currently being processed by the CPU is called
__________
a) PROM
b) Main Memory
c) Non-volatile memory
d) Mass memory
Explanation: PROM has the capability to store the data due to the presence of MOSFET which is processed by the
CPU. It is one-time programmable by the user.
12. CD-ROM is a __________
a) Memory register
b) Magnetic memory
c) Semiconductor memory
d) Non-volatile memory
Explanation: CD-ROM is a non-volatile memory. Once a program is uploaded in it then it can’t be erasable. Thus, it
stores the data permanently.
13. A place which is used as storage location in a computer __________
a) A bit
b) A record
c) An address
d) A byte
Explanation: A storage location of a computer is an address/memory location, used to store instructions and data.
advertisement
14. Which of the following is not a primary storage device?
a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM
Explanation: RAM (i.e. Random Access Memory) is not a primary storage device.
To practice basic questions on all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple Choice
Answers – Programmable Logic ArrayThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Programmable Logic Array”.
1. What is memory decoding?
a) The process of Memory IC used in a digital system is overloaded with data
b) The process of Memory IC used in a digital system is selected for the range of address assigned
c) The process of Memory IC used in a digital system is selected for the range of data assigned
d) The process of Memory IC used in a digital system is overloaded with data allocated in memory cell
Explanation: The Memory IC used in a digital system is selected or enabled only for the range of addresses assigned
to it and this process is called memory decoding. It decodes the memory to be selected for a specific address.
advertisement
2. The first step in the design of memory decoder is __________
a) Selection of a EPROM
b) Selection of a RAM
c) Address assignment
d) Data insertion
Explanation: Memory decoder decodes the memory to be selected for a specific address. The first step in the design
of memory decoder is address assignment in non-overlapped manner.
3. How many address bits are required to select memory location in the Memory decoder?
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
Explanation: Memory decoder decodes the memory to be selected for a specific address. Since the given EPROM and
RAM are of 4 KB (4 * 1024 = 4096) capacity, it requires 12 address bit to select one of the 4096 memory locations.
4. How memory expansion is done?
a) By increasing the supply voltage of the Memory ICs
b) By decreasing the supply voltage of the Memory ICs
c) By connecting Memory ICs together
d) By separating Memory ICs
Explanation: Memory ICs can be connected together to expand the number of memory words or the number of bits
per word.
5. IC 4116 is organised as _________
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2
Explanation: IC 4116 is organised as 16 * 1 K which has capability to store 16 KB.
advertisement
6. To construct 16K * 4-bit memory, how many 4116 ICs are required?
a) 1
b) 2
c) 3
d) 4
Explanation: Since, IC 4116 is organised as 16K * 1, which can store about 16KB data. So, four ICs are required for
16K * 4 memory implementation.
7. How many 1024 * 1 RAM chips are required to construct a 1024 * 8 memory system?
a) 4
b) 6
c) 8
d) 12
Explanation: One 1024 * 1 RAM chips is of 1-bit. SO, for construction of 1024 * 8 RAM chip of 8-bits, it will require 8
chips.
8. How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length of 8 bits?
a) 2
b) 4
c) 6
d) 8
Explanation: 16K * 4 = 64K RAM is of 64K. Therefore, for a word of length 8-bits,
64 * 8 = 512K RAM required. Thus, number of 16K * 4 RAMs = 512/64 = 8.
9. The full form of PLD is _________

a) Programmable Load Devices
b) Programmable Logic Data
c) Programmable Logic Devices
d) Programmable Loaded Devices
Explanation: The full form of PLD is Programmable Logic Devices. It is a collection of gates, flip-flops and registers on
a single chip.
advertisement
10. PLD contains a large number of _________
a) Flip-flops
b) Gates
c) Registers
Explanation: Programmable Logic Devices is a collection of a large number of gates, flip-flops, registers that are
interconnected on the chip. Thus, it is used for designing logic circuits.
11. Logic circuits can also be designed using _________
a) RAM
b) ROM
c) PLD
d) PLA
Explanation: Programmable Logic Devices is a collection of large number of gates, flip-flops, registers that are
12. In PLD, there are provisions to perform interconnections of the gates internally, because of _________
a) High reliability
b) High conductivity
c) The desired logic implementation
d) The desired output

interconnected on the chip. In PLD, there are provisions to perform interconnections of the gates internally so that
the desired logic can be implemented.
13. Why antifuses are implemented in a PLD?
a) To protect from high voltage
b) To increase the memory
c) To implement the programmes
d) As a switching devices
interconnected on the chip. Programming is accomplished by using antifuses in a PLD and it is fabricated at the cross
points of the gates.
advertisement
14. How many types of PLD is?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two types of PLD, viz., devices with fixed architecture and devices with a flexible architecture.
The main categories of PLDs are PROM, PAL and PLA.
15. PLA refers to _________
a) Programmable Loaded Array
b) Programmable Array Logic
c) Programmable Logic Array
d) Programmed Array Logic
Explanation: PLA refers to Programmable Logic Array. It is a type of PLD having programmable AND and OR gates.

Answers – Programmable Array LogicThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Programmable Array Logic”.
1. The inputs in the PLD is given through ____________
a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
Explanation: The inputs in the PLD is given through AND gate followed by inverting & non-inverting buffer. PLDs are
Programmable Logic Devices consisting of logic gates, flip-flops and registers connected together on a single chip.
Thus, it can be categorised into PROM, PAL and PLA.
advertisement
2. PAL refers to ____________
a) Programmable Array Loaded
b) Programmable Logic Array
c) Programmable Array Logic
d) Programmable AND Logic
Explanation: PAL refers to Programmable Array Logic consisting of programmable AND gates and fixed OR gates.
3. Outputs of the AND gate in PLD is known as ____________
a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
Explanation: Outputs of the AND gate in PLD is known as output lines.
4. PLA contains ____________
a) AND and OR arrays
b) NAND and OR arrays
c) NOT and AND arrays
d) NOR and OR arrays
Explanation: Programmable Logic Array is a type of fixed architecture logic devices with programmable AND gates
followed by programmable OR gates. It is a kind of PLD.
5. PLA is used to implement ____________
a) A complex sequential circuit
b) A simple sequential circuit
c) A complex combinational circuit
d) A simple combinational circuit
Explanation: Since, PLA is a combination of programmable AND and OR gates. So, it is used to implement complex
combinational circuit.
advertisement
6. A PLA is similar to a ROM in concept except that ____________
a) It hasn’t capability to read only
b) It hasn’t capability to read or write operation
c) It doesn’t provide full decoding to the variables
d) It hasn’t capability to write only
Explanation: A PLA is similar to a ROM in concept except that it doesn’t provide full decoding to the variables and
doesn’t generate all the minterms as in the ROM. Programmable Logic Array is a type of fixed architecture logic
devices with programmable AND gates followed by programmable OR gates. It is a kind of PLD.
7. For programmable logic functions, which type of PLD should be used?
a) PLA
b) PAL
c) CPLD
d) SLD
Explanation: Since PAL consists of programmable AND gates and fixed OR gates and also circuitry working is less.
8. The complex programmable logic device contains several PLD blocks and __________
a) A language compiler
b) AND/OR arrays
c) Global interconnection matrix
d) Field-programmable switches
Explanation: The complex programmable logic device contains several PLD blocks and a global interconnection
matrix by which it communicates through several devices. It is also known as Field-Programmable Gate Arrays
(FPGAs).
9. Which type of device FPGA are?
a) SLD
b) SROM
c) EPROM
d) PLD
Explanation: Field-Programmable Gate Arrays (FPGAs) are reprogrammable silicon chips. In contrast to processors
that you find in your PC, programming an FPGA rewires the chip itself to implement your functionality rather than
run a software application. Thus, FPGAs are PLD devices.
advertisement
10. The difference between a PAL & a PLA is ____________

a) PALs and PLAs are the same thing
b) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable
AND plane
c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable
AND plane
d) The PAL has more possible product terms than the PLA
Explanation: The main difference between a PAL & PLA is that PLA has a programmable OR plane and a
programmable AND plane, while the PAL only has a programmable AND plane and a fixed OR plane.
11. If a PAL has been programmed once ____________
a) Its logic capacity is lost
b) Its outputs are only active HIGH
c) Its outputs are only active LOW
d) It cannot be reprogrammed
Explanation: PAL only has a programmable AND plane and a fixed OR plane. Since, PAL is dynamic in nature. So, it
can’t be reprogrammed.
12. The FPGA refers to ____________
a) First programmable Gate Array
b) Field Programmable Gate Array
c) First Program Gate Array
d) Field Program Gate Array
Explanation: The FPGA refers to Field Programmable Gate Array. Field-Programmable Gate Arrays (FPGAs) are
reprogrammable silicon chips. In contrast to processors that you find in your PC, programming an FPGA rewires the
chip itself to implement your functionality rather than run a software application. Thus, FPGAs are PLD devices.
13. The full form of VLSI is ____________
a) Very Long Single Integration
b) Very Least Scale Integration
c) Very Large Scale Integration
d) Very Long Scale Integration
Explanation: The full form of VLSI is Very Large Scale Integration in which FPGA is implemented.
advertisement
14. In FPGA, vertical and horizontal directions are separated by ____________
a) A line
b) A channel
c) A strobe
d) A flip-flop
reprogrammable silicon chips. Vertical and horizontal directions is separated by a channel in an FPGA which
determines the location of the output.
15. Applications of PLAs are _____________
a) Registered PALs
b) Configurable PALs
c) PAL programming
Explanation: Applications of PLAs are Registered PALs, Configurable PALs, and PAL programming and these are
performed by using an extra flip-flop with PAL.

« Prev - Digital Circuits Questions and Answers – Programmable Logic Array» Next - Digital Circuits Questions and
Answers – Introduction to Hardware Description LanguageThis set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Introduction to hardware description language”.
1. The full form of HDL is _________________
a) Higher Descriptive Language
b) Higher Definition Language
c) Hardware Description Language
d) High Descriptive Language
Explanation: The full form of HDL is Hardware Description Language.
advertisement
2. The full form of VHDL is _____________
a) Very High Descriptive Language
b) Verilog Hardware Description Language
c) Variable Definition Language
Explanation: The full form of VHDL is Verilog Hardware Description Language.
3. VHSIC stands for _____________
a) Very High Speed Integrated Circuits
b) Very Higher Speed Integration Circuits
c) Variable High Speed Integrated Circuits
d) Variable Higher Speed Integration Circuits
Explanation: VHSIC stands for Very High Speed Integrated Circuits.
4. VHDL is being used for _____________
a) Documentation
b) Verification
c) Synthesis of large digital design

Explanation: The full form of VHDL is Verilog Hardware Description Language. The acronym of VHDL itself captures
the entire theme of the language and it describes the hardware in the same manner as does the schematic. So, it is
used as documentation, verification and synthesis of large digital designs.
5. The use of VHDL can be done in _____ ways.
a) 2
b) 3
c) 4
d) 5
Explanation: The VHDL has three coding styles are: (i) data flow, (ii) structural, (iii) behavioural.
advertisement
6. At high frequencies when the sampling interval is too long in a frequency counter _____________
a) The counter works fine
b) The counter undercounts the frequency
c) The measurement is less precise
d) The counter overflows
Explanation: Let the sampling time be 1 sec. This means the counter will count the number of pulses from the
unknown signal for 1sec duration and would display it after 1 sec. thus if the signal is of 800 Hz, at the end of 1 sec,
counter would have counted up to 800. Thus, in case of high frequencies and high sampling time, counter might
count beyond its limit and overflows.
7. The output frequency related to the sampling interval of a frequency counter as _____________
a) Directly with the sampling interval
b) Inversely with the sampling interval
c) More precision with longer sampling interval
d) Less precision with longer sampling interval
Explanation: Sampling interval means a particular frequency range in which the device operates correctly. Thus,
more precision is produced with longer sampling interval.
8. In an HDL application of a stepper motor, what is done next after an up/down counter is built?
a) Build the sequencer
b) Test it on a simulator
c) Test the decoder
d) Design an intermediate integer variable
Explanation: Simulator is a software which is used in the testing of the stepper motor using up/down counter.
9. In a digital clock application, the basic frequency must be divided down as _____________
a) 1 Hz
b) 60 Hz
c) 100 Hz
d) 1000 Hz
Explanation: Minimum count is 1 sec and time = 1/freq. So, t = 1/1 = 1Hz.
advertisement
10. What does the data signal do in the keypad application?
a) The row and column encoded data
b) The ring encoded data
c) The freeze locator data
d) The ring counter data
Explanation: The data signal arranges the information with the help of data flow in row and column manner. It
encodes the data to be sent.
11. When a key is pressed, what does the ring counter in the HDL keypad application do?
a) Count to find the row
b) Freeze
c) Count to find the column
d) Start the D flip-flop
encodes the data to be sent. When a key is pressed the ring counter in the HDL scans the information provided by
the user and counts to find the row.
12. A step which should be followed in project management is known as _____________
a) Overall definition
b) System documentation
c) Synthesis and testing
d) System integration
Explanation: System documentation is the second step of project management in which a result of the system is
noted simultaneously.
13. In the keypad application, the preset state of the ring counter define _____________
a) The NANDing of the columns
b) The NANDing of the rows
c) The proper output of the column encoder
d) The proper output of the row encoder
Explanation: When a key is pressed the ring counter in the HDL scans the information provided by the user and
counts to find the row. The preset state of the ring counter define the proper output of the row encoder.
advertisement
14. A major block which is not a part of an HDL frequency counter _____________
a) Timing and control unit
b) Decoder/display
c) Display register
d) Bit shifter
Explanation: Bit shifter is part of a register in which bit shifting takes place bit-by-bit either left or right.
15. A stepper motor HDL application must include _____________
a) Sequencers and multiplexers
b) Types and bits

c) Counters and decoders
d) Variables and processes
Explanation: A stepper motor (also referred to as step or stepping motor) is an electromechanical device achieving
mechanical movements through the conversion of electrical pulses. A stepper motor HDL application must include
counters and decoders for position control. It is tested on the simulator.
« Prev - Digital Circuits Questions and Answers – Programmable Array Logic» Next - Digital Circuits Questions and
Answers – MultivibratorsThis set of Digital Electronic/Circuits MCQs focuses on “Multiplexers(Data Selectors) – 2”.
1. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
advertisement
a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
4. 4 to 1 MUX would have ____________
a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
advertisement
b) DPDT switch
c) Rotary switch
d) Linear stepper
advertisement
a) Bidirectional
b) Unidirectional
c) Even parity
a) Enable
b) Disable
c) Saturation
d) High Impedance
(i.e. E’).

advertisement
and Answers.
a) One into many
b) Many into one
c) Distributor
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
advertisement
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answers.
advertisement
Ray Tubes.
advertisement
a) Air
b) Solid
c) Light
d) Water
material.
a) Magnetic field
b) Electric field
d) Gallois field
a) LED
b) LCD
c) OFC
d) OLED
the basis for LCDs.
chemical structure.
advertisement
a) 1950s
b) 1980s
c) 1960s
d) 1970s
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
Cathode Ray Tubes.
a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
a) 8
b) 7
c) 10
d) 9
advertisement

a) 4
b) 8
c) 10
d) 16
advertisement
a) 4
b) 8
c) 12
d) 16
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
a) Yes
b) No
advertisement
a) 2
b) 10
c) 3
d) 4
a) 3
b) 2
c) 8
d) 10
lines.
a) 8
b) 2^8
c) 4
d) 2^4
___________
a) Enable
b) Disable
c) Strobe
d) Clock
an active-low pin.
advertisement
a) No
b) Yes
c) Sometimes
d) Never
a) The higher value
b) The lower value
advertisement
a) 4
b) 5
c) 15
d) 10
from 0 to 9.
advertisement
a) Encoder
b) Display
c) Counter
d) Decoder
a) 4
b) 8
c) 10
d) 2
<= 2n.
a) 10
b) 9
c) 8
d) 3
advertisement
a) 32
b) 64
c) 128
d) 16
c) By using an ALU
d) By using UART
circuits.
a) 2
b) 16
c) 8
d) 4
advertisement
symbol?
2”.
c) CRC
d) Checksum
advertisement
c) CRC
d) Checksum
a) 2
b) 3
c) 4
d) 1
a) Even
b) Odd
d) Undefined
advertisement
b) CRC
d) Checksum
a) 0
b) 1
c) 1001
d) 0011
number of 1’s.
a) Indeterminate
b) 42
c) Even
d) Odd
c) CRC
d) Checksum
advertisement
a) AND
b) NAND
c) EX-OR
d) EX-NOR
advertisement
0101 0011 & 0010 0110 1000
a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
d) 101011 001100001
advertisement
c) With an ALU
d) UART
circuits.
a) BCD code
b) Binary code
c) ASCII code
d) Gray Code

c) Error correction
d) Error Detection
advertisement
a) Binary addition
b) 2’s complement
a) 0011101
b) 0110101
c) 1101001
d) 0101011
a) 101101
b) 001110
c) 110111
d) 111001
↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1
advertisement
Answers.
a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
advertisement
a) a > b
b) a – b
c) a < b
d) a = b
a) 0
b) 1
c) A
d) B
a) 1
b) 2
c) 3
d) 4
a) 1
b) 0
c) A
d) B
advertisement
a) XOR
b) XNOR
c) AND
d) NAND
a) Memory
b) CPU
c) Motherboard
d) Hard drive
b) Size comparator
c) Comparator
a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
advertisement
a) 1
b) 2
c) 3
d) 4
“HIGH” A = B = 1 or “LOW” A = B = 0.
comparison.
advertisement
14. TTL 74LS85 is a _____________

d) 555 timer
advertisement
a) One stable state
b) Two stable state
a) 4
b) 3
c) 2
d) 5
advertisement
a) System rated
b) Set reset
c) Set ready
d) Set Rated
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
a) x and y
b) a and b
c) s and r
d) q and q’
a) 1
b) 0
c) Inverted
d) Don’t cares
advertisement
a) label inputs
b) label outputs
c) label states
d) label tables
labelled.
a) x and y
b) a and b
c) s and r
d) j and k
high and Q’ low.
output.
advertisement
a) Unstable
b) Stable
c) Metastable
d) Bistable
feature?
c) Gate impedance
d) Cross coupling
advertisement
b) Racer
c) Switch debouncer
a) 1
b) 2
c) 3
d) 4
a) Be invalid
b) Change
c) Not change
d) Toggle

advertisement
a) AND or OR gates
d) AND or NOR gates
c) Latches
d) Flip-flops
c) Latches
d) Flip-flops
a) 2
b) 3
c) 4
d) 5
advertisement
a) Flip-flop
b) Latch
c) Strobe
d) Adder
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
a) Set
b) Reset
c) Previous state
d) Current state
advertisement
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
advertisement
a) No change
b) Set
c) Reset
d) Forbidden
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
advertisement
a) Both are same

a) 2
b) 3
c) 4
d) 5
a) 4 AND gates
d) 3 AND gates
d) Invalid State
as Invalid State.
advertisement
a) Racer
c) Only S is active
d) Only R is active
advertisement
a) SET
b) RESET
c) Clear
d) Invalid
_____________
b) NOR latch
c) NAND latch
inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
number of inputs.
advertisement
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
flip-flop.
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
b) Ones catching
advertisement
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
a) Constantly LOW
b) Constantly HIGH

HIGH
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
advertisement
a) 00
b) 11
c) 01
d) 10
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
a) 2
b) 1
c) 4
d) 8
advertisement
Answers.
a) Distant
b) Data
c) Desired
d) Delay
advertisement
a) 1
b) 2
c) 3
d) 4
a) 2
b) 3
c) 4
d) 1
a) S-R
b) J-K
c) T
d) S-K
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
advertisement
a) 0
b) 1
c) Forbidden
d) Toggle

advertisement
edge of the clock
states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
advertisement

b) Q(n+1)=J’Q(n)+KQ'(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
advertisement
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) 3
b) 4
c) 2
d) 5
advertisement
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
advertisement
a) Level enabled
b) Edge triggered
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
advertisement
a) Constantly LOW
b) Constantly HIGH
output.
a) 1 state
b) 0 state
d) forbidden State
advertisement
a) Input
b) Pulser
c) Output
states.
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
c) Lock out state
d) Forbidden State
advertisement
a) High state
b) Low state
c) Toggle state
d) No Change State
a) D type
b) S-R type
c) Latch
d) J-K type
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
a) T flip-flop
b) SR flip-flop
d) D flip-flop
advertisement
a) S-R flip-flop
b) J-K flip-flop
d) D Flip-flop
a) 3
b) 2
c) 4
d) 5
triggering.
12. Flip-flops are ____________
a) Stable devices
b) Astable devices
c) Bistable devices
states.
advertisement
advertisement
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
S=1 & R=0.
a) S and R
b) R input
c) J and K input
d) D input
advertisement
___________
a) 1
b) 0
c) Don’t care
d) Toggle
___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
will be J=1, K=X.
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
a) S
b) R
c) D
d) Both S and R
advertisement
c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K

“Counters”.
advertisement
flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
a) 2
b) 3
c) 4
d) 5
and such like.
a) 5
b) 10
c) 15
d) 20
advertisement
a) SSI counters
d) VLSI counters
them.
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
a) Parallel counter
b) Decade counter
d) VLSI counter
count from 0 to 9.
advertisement
b) Clock frequency
c) Counter modulus
d) Clock count
a) 4
b) 8
c) 16
d) 32
advertisement
a) Each flip-flop

applications
a) Ripple counter
b) Ring counter
c) Modulus counter
occurs?
advertisement
a) 4
b) 8
c) 5
d) 10
a) 0000
b) 1010
c) 1001
d) 1111
a) 2
b) 4
c) 8
d) 16
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
advertisement
a) 1
b) 2
c) 8
d) 15
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) 10
b) 20
c) 100
d) 1000
a) Each flip-flop

advertisement
a) 3
b) 6
c) 8
d) 16
switch ____________
a) HIGH
c) To an open
d) LOW
ICs”.
a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
advertisement
a) 1
b) 4
c) 2
d) 8
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
5. IC 7493 consist of ____________
a) 4 S-R flip-flop
b) 4 J-K flip-flop
d) 4 D flip-flop
advertisement
counter.

a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
advertisement
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
7493 FF.
a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
advertisement

division.
a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12
advertisement
– 1) to 0).
3. UP Counter is ____________
a) 2
b) 4
c) 6
d) 8
advertisement
a) MSB flip-flop
b) LSB flip-flop
d) Latch
a) 000
b) 111
c) 010
d) 101
____________
a) 000
b) 111
c) 101
d) 010
becomes 111.
____________
a) 000
b) 111
c) 101
d) 010
becomes 101.
advertisement
a) 3CB0
b) 3C66
c) 63C0
d) 6300
are toggling

advertisement
advertisement
a) Count up
b) Count down
____________
c) The system clock
a) Synchronous
b) Bean
c) Decade
d) BCD
a) 74134
b) LPM
c) Synchronous
d) AHDL
advertisement
a) 3
b) 8
c) 5
d) 10
a) 20%
b) 50%
c) 10%
d) 80%
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
a) 8
b) 4
c) 16
d) 32
advertisement
a) Ring counter
b) Ripple counter
a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
fundamental mode.
advertisement
a) Each flip-flop
advertisement
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) Each flip-flop
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
advertisement
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
= 1/200ns = 5 MHz.
a) Strobing
b) Feeding
c) Wagging
d) Waving
advertisement
c) It is very fast
c) Stop counting
previous flip-flop.

advertisement
a) Latches
b) Flip-flops
c) UP counter
advertisement
a) Dual counter
b) Multi counter
d) Two Counter
well as downwards.
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
advertisement
a) Starts counting
b) Can be reversed
d) Can be altered
a) 2
b) 3
c) 4
d) 5
required.
a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
a) 8
b) 9
c) 11
d) 15
advertisement
________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Hence, f = 10/8 = 1.25 kHz.

advertisement
Answers.
another.
advertisement
c) CPU
d) Latches
inputs.
a) 2
b) 3
c) 4
d) 5
a) Delay
b) Decrement
c) Data
d) Decay
advertisement
a) Data register
b) Binary register
c) Shift register
d) D – Register
a) 2
b) 3
c) 4
d) 5
advertisement
b) simultaneously
Registers”.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Tristate
b) End around
c) Universal
d) Conversion

advertisement
a) 01110
b) 00001
c) 00101
d) 00110
01110->initial
01011->second
00101->third.
a) 1100
b) 0011
c) 0000
d) 1111
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.

a) 0000
b) 1111
c) 0111
d) 1000
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
sec.
advertisement
(td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
a) Ring shift
b) Clock
c) Johnson
d) Binary
advertisement
a) 1101
b) 0111
c) 0001
d) 1110
1011 | 1101
clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
a) 2
b) 3
c) 4
d) 5
advertisement
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
a) HIGH, LOW, float
b) High-Z, 0, float
d) 1, Low-Z, float
output device
advertisement
b) A ring is faster

manner.
advertisement
input.
a) 1110
b) 0111
c) 1000
d) 1001
Explanation: Given,

111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
a) 1110
b) 0001
c) 1100
d) 1000
are 0001.
a) 10111000
b) 10110111
c) 11110000
d) 11111100
simultaneously.
advertisement
a) 1
b) 3
c) 4
d) 8
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
a) One bit
b) Two bits
c) Four bits
d) Eight bits
them.
advertisement
counters.
advertisement
d) The clock input
out.
a) UART
b) Key matrix
c) Memory chip
advertisement
a) All FFs set to 1
c) Strobe line
d) Multiplexer
advertisement
a) Circulating gate
b) Transceiver
d) Strobed latch
1. Memory is a/an ___________

advertisement
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
required.
information.
a) Data
b) Word
c) Nibble
16-bits or 2-bytes.
advertisement
a) A small display
a) Large memory
b) Small memory
c) Core memory
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
memory.
advertisement
a) NMOS
b) CMOS
c) BJT
a) Floppy disk
d) Control Unit
desired data word.
advertisement
a) EROM
b) RAM
c) PROM
d) EEPROM
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
b) Read Out Memory
c) Read Only Memory
d) Read One Memory
advertisement
a) PROM
b) EPROM
c) CDROM
d) PLA
process.
the user.
advertisement
a) PAL
b) PLA
c) APL
d) PPL
a) PAL
b) PPL
c) PLA
d) APL
a) ISAC
b) ASIC
c) SACC
d) CISF
advertisement

a) EPROM
b) FPGA
d) ROM
advertisement
a) 3
b) 4
c) 5
d) 6
Memory.
advertisement
a) Registers
b) Main Memory
c) RAM
b) Within RAM
c) Within ROM
d) Within CPU
a) RAM
b) ROM
c) Registers
d) Flag
a) Registers
b) Semiconductors
c) Counters
d) PLDs
advertisement
a) Secondary Memory
b) Auxiliary Memory
c) Static Memory

a) Main Memory
b) Secondary Memory
c) Static Memory
d) Volatile Memory
a) Floppy disk
b) Magnetic drum
c) Hard disk
a) 2
b) 3
c) 4
d) 5
advertisement

a) Floppy disk
b) Hard disk
d) RAM
a) Floppy disk
b) Hard disk
advertisement

and Answers.
advertisement
a) 1
b) 2
c) 3
d) 4
a) CCD
d) Floppy-Disk

advertisement
b) Read Only Memory
a) 2
b) 3
c) 4
d) 5
advertisement
to hold the data.
__________

a) PLD
b) LSI
c) VLSI
advertisement

a) Bus collisions
c) Address decoding
d) Bus contention
advertisement
a) Unit cells
b) Storage cells
c) Data cells
d) Binary cells
a) Storage cells
b) Data cells
c) Unit cells
a) Nibble
b) Word
c) Byte
d) Address
a) Letters
b) Binary numbers
d) Gray codes
bits or 2-bytes.
advertisement
a) RAM
b) ROM
c) Storage class
d) Address
or 2-bytes.
a) Nibble
b) Flag
c) Byte
d) Word

a) Control lines
and received.
advertisement
b) Tracks per inch
d) Rotation speed
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
advertisement
d) Erase operation

4. The ROM is a ___________
c) Magnetic circuit
d) Static circuit
not past states.
b) NOR and decoder
d) NAND and decoder
advertisement
a) Memory unit
b) Storage class
c) Data word
d) Address
a) Zip
b) Hard disk
c) Super Disk
d) Jaz
a) Memory unit
b) Storage class
c) Data word
d) Address
advertisement
a) NMOS
b) CMOS
c) BJT
a) 2
b) 3
c) 4
d) 5
advertisement
a) FETs
b) Transistors
c) MOSFETs
d) BJTs
more efficient.
a) 8 bits
b) 12 bits
c) 16 bits
d) 32 bits
advertisement
a) Extended
b) Expanded
c) Base
d) Conventional
a) Address bus
b) System bus
c) Control bus
d) Data bus
a) Platter
b) Read/Write
c) Valve
d) Spindle
advertisement
a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
more efficient.
a) Cluster
b) Read/Write
c) Cylinder
d) Recordable
a) EEPROM
b) Mask ROM
c) EPROM
d) PROM
advertisement
c) RAM and ROM
programmed.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Mask Programming
b) PROM
d) EPROM
a) Photo
b) Negative
c) Mask
d) Virtual image
a) EPROM
b) PROM
a) 8 bits
b) 16 bits
c) 128 bits
d) 64 bits
advertisement
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
MSI/TTL based.
7. IC 74187 is of __________
a) 512 bits
b) 1024 bits
c) 256 bits
d) 68 bits
a) 128, 3
b) 128, 4
c) 256, 3
d) 256, 4
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
advertisement
a) 16
b) 32
c) 64
d) 8
a) TMS 45276
b) TMS 45278
c) TMS 45279
d) TMS 45275
13. TMS 45276 is of __________
a) 32 KB
b) 56 KB
c) 8 bits
d) 4 bytes
a) TMS 45276
b) IC 74188
c) IC 74187
d) IC 74185
organization.
a) Storing Capacity
b) Custom Select
c) Chip Select
d) Custom Storage
advertisement
c) Code conversion
b) Data hold
c) Read cycle time
d) Access time
advertisement
a) ROM
b) EPROM
c) PROM
d) EEPROM

a) 4096
b) 16384
c) 32768
d) 8129
advertisement
of eight bits?
a) Eight
b) Two
c) One
d) Four
c) Command code
advertisement
a) 8 locations
b) 256 locations
c) 65,536 locations
locations = 28.

a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
advertisement
a) 2
b) 3
c) 4
d) 5
a) Polycrystalline
c) Nichrome
d) Silicon dioxide
c) Nichrome
d) Silicon dioxide
advertisement
a) EPROM programmer
c) PROM programmer
d) ROM programmer
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
advertisement
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
rows and 8 columns.
7. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
a) 165,667
b) 245,784
c) 262,144
d) 212,342
a) 10
b) 11
c) 12
d) 13
advertisement
a) 1024
b) 4096
c) 2048
d) 8192
8192 bit.

advertisement
a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell
d) Memory mapping
user.

advertisement
a) 0
b) 1
c) Both 0 and 1
a) Reprogrammed
b) Restarted
c) Charged
d) Power off
c) It is volatile
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
advertisement
a) 1024
b) 512
c) 2516
d) 256
a) HIGH
b) LOW
a) Power is on
b) Power is off
c) System is down
this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Explanation: 8K = 8 * 1024 = 8192.
advertisement
b) Faulty
c) Probably good
advertisement
a) RAM
b) FPROM
c) EEPROM
d) ROM
a) RAM
b) ROM
c) PROM
d) EPROM
a) RWM
b) MBR
c) MAR
d) ROM
Read Write Memory).
advertisement
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
a) MBR
b) MAR
c) RAM
d) ROM
a) Data buffer
b) Chip select
c) Read and write
d) Memory
respectively.
a) High complexity
b) High resolution
d) High flexibility
advertisement
a) 2
b) 3
c) 4
d) 5
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
operation.
a) ROM
b) EROM
c) PROM
d) RAM
advertisement
a) 32 bit to 64 bit
advertisement
a) Activated
b) Deactivated
c) Unaffected
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
advertisement
6. IC 7489 is of ____________
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
a) Chip select
b) Enable
c) Data input
d) Memory enable
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
a) 1946
b) 1948
c) 1947
d) 1945
advertisement
a) SRAM
b) DRAM
c) EEPROM
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
locations.
a) 1024 * 4
b) 1024 * 8
c) 2048 * 4
d) 2048 * 8
locations.
advertisement
a) 10
b) 9
c) 12
d) 11
locations.
a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional
advertisement
a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
memories.
advertisement
a) Cache
b) Dynamic RAM
c) Static RAM
a) SRAM
b) DRAM
c) Magnetic memory
d) Main Memory
advertisement
d) Has higher speed
a) RAM and ROM
b) CPU and RAM
d) CPU and ROM
a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile

advertisement
a) 10240
b) 15289
c) 16384
d) 17654
bits.
a) 2114
b) 7489
c) 4116
d) 2776
advertisement
a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
a) 3
b) 2
c) 1
d) 4
a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM
advertisement
a) Scratch-pad
b) Buffer
c) Main memory
a) ROM
b) RAM
c) EROM
d) PROM
advertisement
a) ROM
b) RAM
c) EROM
d) PROM
operation.
__________
a) PROM
b) Main Memory
d) Mass memory
12. CD-ROM is a __________
a) Memory register
b) Magnetic memory
a) A bit
b) A record
c) An address
d) A byte
advertisement
a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM
advertisement
d) Data insertion
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
per word.
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2
advertisement
a) 1
b) 2
c) 3
d) 4
a) 4
b) 6
c) 8
d) 12
chips.
a) 2
b) 4
c) 6
d) 8
a single chip.
advertisement
a) Flip-flops
b) Gates
c) Registers
a) RAM
b) ROM
c) PLD
d) PLA
a) High reliability
advertisement
a) 2
b) 3
c) 4
d) 5

a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
advertisement
2. PAL refers to ____________
a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
4. PLA contains ____________

advertisement
a) PLA
b) PAL
c) CPLD
d) SLD
b) AND/OR arrays
(FPGAs).
a) SLD
b) SROM
c) EPROM
d) PLD
advertisement
AND plane
AND plane

advertisement
a) A line
b) A channel
c) A strobe
d) A flip-flop
a) Registered PALs
c) PAL programming
advertisement
a) Documentation
b) Verification
a) 2
b) 3
c) 4
d) 5
advertisement
c) Test the decoder
a) 1 Hz
b) 60 Hz
c) 100 Hz
d) 1000 Hz
advertisement
b) Freeze

advertisement
b) Decoder/display
c) Display register
d) Bit shifter
b) Types and bits

1. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
advertisement
a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
4. 4 to 1 MUX would have ____________
a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
advertisement

b) DPDT switch
c) Rotary switch
d) Linear stepper
advertisement
a) Bidirectional
b) Unidirectional
c) Even parity
a) Enable
b) Disable
c) Saturation
d) High Impedance
(i.e. E’).
advertisement
and Answers.

a) One into many
b) Many into one
c) Distributor
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
advertisement

advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answers.
advertisement

Ray Tubes.
advertisement
a) Air
b) Solid
c) Light
d) Water
material.
a) Magnetic field
b) Electric field
d) Gallois field
a) LED
b) LCD
c) OFC
d) OLED
the basis for LCDs.
chemical structure.
advertisement
a) 1950s
b) 1980s
c) 1960s
d) 1970s
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
Cathode Ray Tubes.
a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
a) 8
b) 7
c) 10
d) 9
advertisement

a) 4
b) 8
c) 10
d) 16
advertisement
a) 4
b) 8
c) 12
d) 16
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
a) Yes
b) No
advertisement
a) 2
b) 10
c) 3
d) 4
a) 3
b) 2
c) 8
d) 10
lines.
a) 8
b) 2^8
c) 4
d) 2^4
___________
a) Enable
b) Disable
c) Strobe
d) Clock
an active-low pin.
advertisement
a) No
b) Yes
c) Sometimes
d) Never
a) The higher value
b) The lower value
advertisement
a) 4
b) 5
c) 15
d) 10
from 0 to 9.
advertisement
a) Encoder
b) Display
c) Counter
d) Decoder
a) 4
b) 8
c) 10
d) 2
<= 2n.
a) 10
b) 9
c) 8
d) 3
advertisement
a) 32
b) 64
c) 128
d) 16
c) By using an ALU
d) By using UART
circuits.
a) 2
b) 16
c) 8
d) 4
advertisement
symbol?
2”.
c) CRC
d) Checksum
advertisement
c) CRC
d) Checksum
a) 2
b) 3
c) 4
d) 1
a) Even
b) Odd
d) Undefined
advertisement
b) CRC
d) Checksum

a) 0
b) 1
c) 1001
d) 0011
number of 1’s.
a) Indeterminate
b) 42
c) Even
d) Odd
c) CRC
d) Checksum
advertisement
a) AND
b) NAND
c) EX-OR
d) EX-NOR
advertisement
0101 0011 & 0010 0110 1000
a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
d) 101011 001100001
advertisement
c) With an ALU
d) UART
circuits.
a) BCD code
b) Binary code
c) ASCII code
d) Gray Code
c) Error correction
d) Error Detection
advertisement
a) Binary addition
b) 2’s complement
a) 0011101
b) 0110101
c) 1101001
d) 0101011
a) 101101
b) 001110
c) 110111
d) 111001
↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1
advertisement
Answers.
a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
advertisement
a) a > b
b) a – b
c) a < b
d) a = b
a) 0
b) 1
c) A
d) B
a) 1
b) 2
c) 3
d) 4
a) 1
b) 0
c) A
d) B
advertisement
a) XOR
b) XNOR
c) AND
d) NAND
a) Memory
b) CPU
c) Motherboard
d) Hard drive
b) Size comparator
c) Comparator
a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
advertisement
a) 1
b) 2
c) 3
d) 4
“HIGH” A = B = 1 or “LOW” A = B = 0.
comparison.
advertisement
14. TTL 74LS85 is a _____________
d) 555 timer
advertisement
a) One stable state
b) Two stable state
a) 4
b) 3
c) 2
d) 5
advertisement
a) System rated
b) Set reset
c) Set ready
d) Set Rated
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
a) x and y
b) a and b
c) s and r
d) q and q’
a) 1
b) 0
c) Inverted
d) Don’t cares
advertisement
a) label inputs
b) label outputs
c) label states
d) label tables
labelled.
a) x and y
b) a and b
c) s and r
d) j and k
high and Q’ low.
output.
advertisement
a) Unstable
b) Stable
c) Metastable
d) Bistable
feature?
c) Gate impedance
d) Cross coupling
advertisement
b) Racer
c) Switch debouncer
a) 1
b) 2
c) 3
d) 4
a) Be invalid
b) Change
c) Not change
d) Toggle
advertisement
a) AND or OR gates
d) AND or NOR gates

c) Latches
d) Flip-flops
c) Latches
d) Flip-flops
a) 2
b) 3
c) 4
d) 5
advertisement
a) Flip-flop
b) Latch
c) Strobe
d) Adder
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
a) Set
b) Reset
c) Previous state
d) Current state
advertisement
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
advertisement
a) No change
b) Set
c) Reset
d) Forbidden
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
advertisement
a) Both are same
a) 2
b) 3
c) 4
d) 5
a) 4 AND gates
d) 3 AND gates
d) Invalid State
as Invalid State.
advertisement
a) Racer

c) Only S is active
d) Only R is active
advertisement
a) SET
b) RESET
c) Clear
d) Invalid
_____________
b) NOR latch
c) NAND latch
inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
number of inputs.
advertisement
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
flip-flop.
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
b) Ones catching
advertisement
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
a) Constantly LOW
b) Constantly HIGH
HIGH
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
advertisement
a) 00
b) 11
c) 01
d) 10
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
a) 2
b) 1
c) 4
d) 8
advertisement
Answers.
a) Distant
b) Data
c) Desired
d) Delay
advertisement
a) 1
b) 2
c) 3
d) 4
a) 2
b) 3
c) 4
d) 1
a) S-R
b) J-K
c) T
d) S-K
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
advertisement
a) 0
b) 1
c) Forbidden
d) Toggle
advertisement
edge of the clock
states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1

advertisement
b) Q(n+1)=J’Q(n)+KQ'(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
advertisement
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) 3
b) 4
c) 2
d) 5
advertisement

a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
advertisement
a) Level enabled
b) Edge triggered
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
advertisement
a) Constantly LOW
b) Constantly HIGH

output.
a) 1 state
b) 0 state
d) forbidden State
advertisement
a) Input
b) Pulser
c) Output
states.
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
c) Lock out state
d) Forbidden State

advertisement
a) High state
b) Low state
c) Toggle state
d) No Change State
a) D type
b) S-R type
c) Latch
d) J-K type
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
a) T flip-flop
b) SR flip-flop
d) D flip-flop
advertisement
a) S-R flip-flop
b) J-K flip-flop
d) D Flip-flop
a) 3
b) 2
c) 4
d) 5
triggering.
12. Flip-flops are ____________
a) Stable devices
b) Astable devices
c) Bistable devices
states.
advertisement
advertisement
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
S=1 & R=0.
a) S and R
b) R input
c) J and K input
d) D input
advertisement
___________
a) 1
b) 0
c) Don’t care
d) Toggle
___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
will be J=1, K=X.
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
a) S
b) R
c) D
d) Both S and R
advertisement

c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
“Counters”.
advertisement
flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
a) 2
b) 3
c) 4
d) 5
and such like.
a) 5
b) 10
c) 15
d) 20
advertisement
a) SSI counters
d) VLSI counters
them.
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
a) Parallel counter
b) Decade counter
d) VLSI counter
count from 0 to 9.
advertisement
b) Clock frequency
c) Counter modulus
d) Clock count
a) 4
b) 8
c) 16
d) 32
advertisement
a) Each flip-flop
applications
a) Ripple counter
b) Ring counter
c) Modulus counter
occurs?
advertisement
a) 4
b) 8
c) 5
d) 10
a) 0000
b) 1010
c) 1001
d) 1111

a) 2
b) 4
c) 8
d) 16
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
advertisement
a) 1
b) 2
c) 8
d) 15
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) 10
b) 20
c) 100
d) 1000
a) Each flip-flop
advertisement
a) 3
b) 6
c) 8
d) 16
switch ____________
a) HIGH
c) To an open
d) LOW
ICs”.
a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
advertisement
a) 1
b) 4
c) 2
d) 8
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
5. IC 7493 consist of ____________
a) 4 S-R flip-flop
b) 4 J-K flip-flop
d) 4 D flip-flop
advertisement
counter.
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492

advertisement
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
7493 FF.
a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
advertisement
division.
a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12
advertisement
– 1) to 0).
3. UP Counter is ____________
a) 2
b) 4
c) 6
d) 8
advertisement
a) MSB flip-flop
b) LSB flip-flop
d) Latch
a) 000
b) 111
c) 010
d) 101
____________
a) 000
b) 111
c) 101
d) 010
becomes 111.
____________
a) 000
b) 111
c) 101
d) 010
becomes 101.
advertisement
a) 3CB0
b) 3C66
c) 63C0
d) 6300
are toggling
advertisement

advertisement
a) Count up
b) Count down
____________
c) The system clock
a) Synchronous
b) Bean
c) Decade
d) BCD
a) 74134
b) LPM
c) Synchronous
d) AHDL
advertisement
a) 3
b) 8
c) 5
d) 10
a) 20%
b) 50%
c) 10%
d) 80%
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
a) 8
b) 4
c) 16
d) 32
advertisement
a) Ring counter
b) Ripple counter
a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
fundamental mode.
advertisement

a) Each flip-flop
advertisement
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) Each flip-flop
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
advertisement
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
= 1/200ns = 5 MHz.
a) Strobing
b) Feeding
c) Wagging
d) Waving
advertisement
c) It is very fast
c) Stop counting
previous flip-flop.
advertisement

a) Latches
b) Flip-flops
c) UP counter
advertisement
a) Dual counter
b) Multi counter
d) Two Counter
well as downwards.

a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
advertisement
a) Starts counting
b) Can be reversed
d) Can be altered
a) 2
b) 3
c) 4
d) 5
required.

a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
a) 8
b) 9
c) 11
d) 15
advertisement

________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Hence, f = 10/8 = 1.25 kHz.
advertisement
Answers.

another.
advertisement
c) CPU
d) Latches
inputs.
a) 2
b) 3
c) 4
d) 5
a) Delay
b) Decrement
c) Data
d) Decay
advertisement
a) Data register
b) Binary register
c) Shift register
d) D – Register
a) 2
b) 3
c) 4
d) 5
advertisement
b) simultaneously

Registers”.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Tristate
b) End around
c) Universal
d) Conversion
advertisement
a) 01110
b) 00001
c) 00101
d) 00110
01110->initial
01011->second
00101->third.
a) 1100
b) 0011
c) 0000
d) 1111
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
a) 0000
b) 1111
c) 0111
d) 1000
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
sec.
advertisement
(td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us

a) Ring shift
b) Clock
c) Johnson
d) Binary
advertisement
a) 1101
b) 0111
c) 0001
d) 1110
1011 | 1101

clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
a) 2
b) 3
c) 4
d) 5
advertisement
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
a) HIGH, LOW, float
b) High-Z, 0, float
d) 1, Low-Z, float
output device
advertisement
b) A ring is faster

manner.
advertisement

input.
a) 1110
b) 0111
c) 1000
d) 1001
Explanation: Given,
111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
a) 1110
b) 0001
c) 1100
d) 1000
are 0001.
a) 10111000
b) 10110111
c) 11110000
d) 11111100
simultaneously.
advertisement
a) 1
b) 3
c) 4
d) 8

a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
a) One bit
b) Two bits
c) Four bits
d) Eight bits
them.
advertisement

counters.
advertisement
d) The clock input
out.
a) UART
b) Key matrix
c) Memory chip
advertisement
a) All FFs set to 1
c) Strobe line
d) Multiplexer
advertisement
a) Circulating gate
b) Transceiver
d) Strobed latch
1. Memory is a/an ___________
advertisement
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
required.
information.
a) Data
b) Word
c) Nibble
16-bits or 2-bytes.
advertisement
a) A small display
a) Large memory
b) Small memory
c) Core memory
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
memory.
advertisement
a) NMOS
b) CMOS
c) BJT
a) Floppy disk
d) Control Unit
desired data word.
advertisement

a) EROM
b) RAM
c) PROM
d) EEPROM
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
b) Read Out Memory
c) Read Only Memory
d) Read One Memory

advertisement
a) PROM
b) EPROM
c) CDROM
d) PLA
process.
the user.

advertisement
a) PAL
b) PLA
c) APL
d) PPL
a) PAL
b) PPL
c) PLA
d) APL
a) ISAC
b) ASIC
c) SACC
d) CISF
advertisement
a) EPROM
b) FPGA
d) ROM
advertisement
a) 3
b) 4
c) 5
d) 6
Memory.
advertisement
a) Registers
b) Main Memory
c) RAM
b) Within RAM
c) Within ROM
d) Within CPU
a) RAM
b) ROM
c) Registers
d) Flag
a) Registers
b) Semiconductors
c) Counters
d) PLDs
advertisement
a) Secondary Memory
b) Auxiliary Memory
c) Static Memory
a) Main Memory
b) Secondary Memory
c) Static Memory
d) Volatile Memory
a) Floppy disk
b) Magnetic drum
c) Hard disk
a) 2
b) 3
c) 4
d) 5
advertisement
a) Floppy disk
b) Hard disk
d) RAM
a) Floppy disk
b) Hard disk
advertisement
and Answers.
advertisement
a) 1
b) 2
c) 3
d) 4
a) CCD
d) Floppy-Disk
advertisement
b) Read Only Memory
a) 2
b) 3
c) 4
d) 5
advertisement

to hold the data.
__________
a) PLD
b) LSI
c) VLSI
advertisement
a) Bus collisions
c) Address decoding
d) Bus contention
advertisement
a) Unit cells
b) Storage cells
c) Data cells
d) Binary cells
a) Storage cells
b) Data cells
c) Unit cells
a) Nibble
b) Word
c) Byte
d) Address
a) Letters
b) Binary numbers
d) Gray codes
bits or 2-bytes.
advertisement
a) RAM
b) ROM
c) Storage class
d) Address
or 2-bytes.
a) Nibble
b) Flag
c) Byte
d) Word
a) Control lines
and received.
advertisement
b) Tracks per inch
d) Rotation speed
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
advertisement
d) Erase operation
4. The ROM is a ___________
c) Magnetic circuit
d) Static circuit
not past states.
b) NOR and decoder
d) NAND and decoder
advertisement
a) Memory unit
b) Storage class
c) Data word
d) Address
a) Zip
b) Hard disk
c) Super Disk
d) Jaz
a) Memory unit
b) Storage class
c) Data word
d) Address
advertisement
a) NMOS
b) CMOS
c) BJT
a) 2
b) 3
c) 4
d) 5
advertisement
a) FETs
b) Transistors
c) MOSFETs
d) BJTs
more efficient.
a) 8 bits
b) 12 bits
c) 16 bits
d) 32 bits
advertisement
a) Extended
b) Expanded
c) Base
d) Conventional
a) Address bus
b) System bus
c) Control bus
d) Data bus
a) Platter
b) Read/Write
c) Valve
d) Spindle
advertisement
a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
more efficient.
a) Cluster
b) Read/Write
c) Cylinder
d) Recordable
a) EEPROM
b) Mask ROM
c) EPROM
d) PROM
advertisement
c) RAM and ROM
programmed.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Mask Programming
b) PROM
d) EPROM
a) Photo
b) Negative
c) Mask
d) Virtual image
a) EPROM
b) PROM
a) 8 bits
b) 16 bits
c) 128 bits
d) 64 bits
advertisement
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
MSI/TTL based.
7. IC 74187 is of __________
a) 512 bits
b) 1024 bits
c) 256 bits
d) 68 bits
a) 128, 3
b) 128, 4
c) 256, 3
d) 256, 4
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
advertisement
a) 16
b) 32
c) 64
d) 8
a) TMS 45276
b) TMS 45278
c) TMS 45279
d) TMS 45275
13. TMS 45276 is of __________
a) 32 KB
b) 56 KB
c) 8 bits
d) 4 bytes
a) TMS 45276
b) IC 74188
c) IC 74187
d) IC 74185
organization.
a) Storing Capacity
b) Custom Select
c) Chip Select
d) Custom Storage
advertisement
c) Code conversion
b) Data hold
c) Read cycle time
d) Access time
advertisement

a) ROM
b) EPROM
c) PROM
d) EEPROM
a) 4096
b) 16384
c) 32768
d) 8129
advertisement
of eight bits?
a) Eight
b) Two
c) One
d) Four
c) Command code
advertisement
a) 8 locations
b) 256 locations
c) 65,536 locations
locations = 28.
a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
advertisement
a) 2
b) 3
c) 4
d) 5
a) Polycrystalline
c) Nichrome
d) Silicon dioxide

c) Nichrome
d) Silicon dioxide
advertisement
a) EPROM programmer
c) PROM programmer
d) ROM programmer
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
advertisement
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
rows and 8 columns.
7. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
a) 165,667
b) 245,784
c) 262,144
d) 212,342
a) 10
b) 11
c) 12
d) 13
advertisement
a) 1024
b) 4096
c) 2048
d) 8192
8192 bit.
advertisement
a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell

d) Memory mapping
user.
advertisement
a) 0
b) 1
c) Both 0 and 1
a) Reprogrammed
b) Restarted
c) Charged
d) Power off
c) It is volatile
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
advertisement
a) 1024
b) 512
c) 2516
d) 256
a) HIGH
b) LOW
a) Power is on
b) Power is off
c) System is down
this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Explanation: 8K = 8 * 1024 = 8192.
advertisement
b) Faulty
c) Probably good

advertisement
a) RAM
b) FPROM
c) EEPROM
d) ROM
a) RAM
b) ROM
c) PROM
d) EPROM
a) RWM
b) MBR
c) MAR
d) ROM
Read Write Memory).
advertisement
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
a) MBR
b) MAR
c) RAM
d) ROM
a) Data buffer
b) Chip select
c) Read and write
d) Memory
respectively.
a) High complexity
b) High resolution

d) High flexibility
advertisement
a) 2
b) 3
c) 4
d) 5
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
operation.
a) ROM
b) EROM
c) PROM
d) RAM
advertisement
a) 32 bit to 64 bit
advertisement

a) Activated
b) Deactivated
c) Unaffected
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
advertisement
6. IC 7489 is of ____________
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
a) Chip select
b) Enable
c) Data input
d) Memory enable
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
a) 1946
b) 1948
c) 1947
d) 1945
advertisement
a) SRAM
b) DRAM
c) EEPROM
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
locations.
a) 1024 * 4
b) 1024 * 8
c) 2048 * 4
d) 2048 * 8
locations.
advertisement
a) 10
b) 9
c) 12
d) 11
locations.
a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional

advertisement
a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
memories.
advertisement
a) Cache
b) Dynamic RAM
c) Static RAM
a) SRAM
b) DRAM
c) Magnetic memory
d) Main Memory
advertisement
d) Has higher speed
a) RAM and ROM
b) CPU and RAM
d) CPU and ROM

a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile
advertisement
a) 10240
b) 15289
c) 16384
d) 17654
bits.

a) 2114
b) 7489
c) 4116
d) 2776
advertisement

a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
a) 3
b) 2
c) 1
d) 4
a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM
advertisement
a) Scratch-pad
b) Buffer
c) Main memory
a) ROM
b) RAM
c) EROM
d) PROM
advertisement
a) ROM
b) RAM
c) EROM
d) PROM
operation.
__________
a) PROM
b) Main Memory
d) Mass memory
12. CD-ROM is a __________
a) Memory register
b) Magnetic memory
a) A bit
b) A record
c) An address
d) A byte
advertisement
a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM
advertisement
d) Data insertion
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
per word.
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2
advertisement
a) 1
b) 2
c) 3
d) 4
a) 4
b) 6
c) 8
d) 12
chips.
a) 2
b) 4
c) 6
d) 8

a single chip.
advertisement
a) Flip-flops
b) Gates
c) Registers
a) RAM
b) ROM
c) PLD
d) PLA
a) High reliability

advertisement
a) 2
b) 3
c) 4
d) 5

a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
advertisement
2. PAL refers to ____________
a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
4. PLA contains ____________
advertisement
a) PLA
b) PAL
c) CPLD
d) SLD
b) AND/OR arrays
(FPGAs).
a) SLD
b) SROM
c) EPROM
d) PLD
advertisement

AND plane
AND plane
advertisement
a) A line
b) A channel
c) A strobe
d) A flip-flop
a) Registered PALs
c) PAL programming

advertisement
a) Documentation
b) Verification

a) 2
b) 3
c) 4
d) 5
advertisement
c) Test the decoder
a) 1 Hz
b) 60 Hz
c) 100 Hz
d) 1000 Hz
advertisement
b) Freeze
advertisement
b) Decoder/display
c) Display register
d) Bit shifter
b) Types and bits

Answers – MultivibratorsThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Number System – 1”.
1. Any signed negative binary number is recognised by its ________
a) MSB
b) LSB
c) Byte
d) Nibble
Explanation: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive.
advertisement
2. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
Explanation: It can be represented up to 16 different values with the help of a Word. Nibble is a combination of four
bits and Byte is a combination of 8 bits. It is “word” that is said to be a collection of 16-bits on most of the systems.
3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by
2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
Explanation: On multiplying the decimal number continuously by 2, the binary equivalent is obtained by the
collection of the integer part. However, if it’s an integer, then it’s binary equivalent is determined by dividing the
number by 2 and collecting the remainders.
4. The representation of octal number (532.2)8 in decimal is ________
a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the
value at that index position.
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10
5. The decimal equivalent of the binary number (1011.011)2 is ________
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10
advertisement
6. An important drawback of binary system is ________
a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
Explanation: The most vital drawback of binary system is that it requires very large string of 1’s and 0’s to represent a
decimal number. Hence, Hexadecimal systems are used by processors for calculation purposes as it compresses the
long binary strings into small parts.
7. The decimal equivalent of the octal number (645)8 is ______
a) (450)10
b) (451)10
c) (421)10
d) (501)10
The decimal equivalent of the octal number (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5 = 384 + 32 + 5 =

(421)10.
8. The largest two digit hexadecimal number is ________
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
Explanation: (FE)16 is 254 in decimal system, while (FD)16 is 253. (EF)16 is 239 in decimal system. And, (FF)16 is 255.
Thus, The largest two-digit hexadecimal number is (FF)16.
9. Representation of hexadecimal number (6DE)H in decimal:
a) 6 * 162 + 13 * 161 + 14 * 160

b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with
the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.
advertisement
10. The quantity of double word is ________
a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
Explanation: One word means 16 bits, Thus, the quantity of double word is 32 bits.
» Next - Digital Circuits Questions and Answers – Number System – 2

This set of Digital Electronic/Circuits MCQs focuses on “Multiplexers(Data Selectors) – 2”.
1. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
advertisement
a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
4. 4 to 1 MUX would have ____________
a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
advertisement
b) DPDT switch
c) Rotary switch
d) Linear stepper
advertisement
a) Bidirectional
b) Unidirectional
c) Even parity

a) Enable
b) Disable
c) Saturation
d) High Impedance
(i.e. E’).
advertisement
and Answers.

a) One into many
b) Many into one
c) Distributor
advertisement
c) AC to DC

a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
advertisement
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answers.
advertisement
Ray Tubes.
advertisement
a) Air
b) Solid
c) Light
d) Water
material.
a) Magnetic field
b) Electric field
d) Gallois field
a) LED
b) LCD
c) OFC
d) OLED
the basis for LCDs.

chemical structure.
advertisement
a) 1950s
b) 1980s
c) 1960s
d) 1970s
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
Cathode Ray Tubes.
a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
a) 8
b) 7
c) 10
d) 9
advertisement

a) 4
b) 8
c) 10
d) 16
advertisement
a) 4
b) 8
c) 12
d) 16
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
a) Yes
b) No
advertisement
a) 2
b) 10
c) 3
d) 4
a) 3
b) 2
c) 8
d) 10
lines.
a) 8
b) 2^8
c) 4
d) 2^4
___________
a) Enable
b) Disable
c) Strobe
d) Clock
an active-low pin.
advertisement
a) No
b) Yes
c) Sometimes
d) Never
a) The higher value
b) The lower value
advertisement
a) 4
b) 5
c) 15
d) 10
from 0 to 9.
advertisement
a) Encoder
b) Display
c) Counter
d) Decoder
a) 4
b) 8
c) 10
d) 2
<= 2n.
a) 10
b) 9
c) 8
d) 3
advertisement
a) 32
b) 64
c) 128
d) 16
c) By using an ALU
d) By using UART
circuits.
a) 2
b) 16
c) 8
d) 4
advertisement
symbol?
2”.
c) CRC
d) Checksum
advertisement
c) CRC
d) Checksum
a) 2
b) 3
c) 4
d) 1
a) Even
b) Odd
d) Undefined
advertisement
b) CRC
d) Checksum

a) 0
b) 1
c) 1001
d) 0011
number of 1’s.
a) Indeterminate
b) 42
c) Even
d) Odd
c) CRC
d) Checksum
advertisement
a) AND
b) NAND
c) EX-OR
d) EX-NOR
advertisement
0101 0011 & 0010 0110 1000
a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
d) 101011 001100001
advertisement
c) With an ALU
d) UART
circuits.
a) BCD code
b) Binary code
c) ASCII code
d) Gray Code
c) Error correction
d) Error Detection
advertisement
a) Binary addition
b) 2’s complement
a) 0011101
b) 0110101
c) 1101001
d) 0101011
a) 101101
b) 001110
c) 110111
d) 111001
↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1
advertisement
Answers.
a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
advertisement
a) a > b
b) a – b
c) a < b
d) a = b
a) 0
b) 1
c) A
d) B
a) 1
b) 2
c) 3
d) 4
a) 1
b) 0
c) A
d) B
advertisement
a) XOR
b) XNOR
c) AND
d) NAND
a) Memory
b) CPU
c) Motherboard
d) Hard drive
b) Size comparator
c) Comparator
a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
advertisement
a) 1
b) 2
c) 3
d) 4
“HIGH” A = B = 1 or “LOW” A = B = 0.
comparison.
advertisement
14. TTL 74LS85 is a _____________
d) 555 timer
advertisement
a) One stable state
b) Two stable state
a) 4
b) 3
c) 2
d) 5
advertisement
a) System rated
b) Set reset
c) Set ready
d) Set Rated
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
a) x and y
b) a and b
c) s and r
d) q and q’
a) 1
b) 0
c) Inverted
d) Don’t cares
advertisement
a) label inputs
b) label outputs
c) label states
d) label tables
labelled.
a) x and y
b) a and b
c) s and r
d) j and k
high and Q’ low.
output.
advertisement
a) Unstable
b) Stable
c) Metastable
d) Bistable
feature?
c) Gate impedance
d) Cross coupling
advertisement
b) Racer
c) Switch debouncer
a) 1
b) 2
c) 3
d) 4
a) Be invalid
b) Change
c) Not change
d) Toggle
advertisement
a) AND or OR gates
d) AND or NOR gates

c) Latches
d) Flip-flops
c) Latches
d) Flip-flops
a) 2
b) 3
c) 4
d) 5
advertisement
a) Flip-flop
b) Latch
c) Strobe
d) Adder
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
a) Set
b) Reset
c) Previous state
d) Current state
advertisement
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
advertisement
a) No change
b) Set
c) Reset
d) Forbidden
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
advertisement
a) Both are same
a) 2
b) 3
c) 4
d) 5
a) 4 AND gates
d) 3 AND gates
d) Invalid State
as Invalid State.
advertisement
a) Racer

c) Only S is active
d) Only R is active
advertisement
a) SET
b) RESET
c) Clear
d) Invalid
_____________
b) NOR latch
c) NAND latch
inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
number of inputs.
advertisement
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
flip-flop.
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
b) Ones catching
advertisement
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
a) Constantly LOW
b) Constantly HIGH
HIGH
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
advertisement
a) 00
b) 11
c) 01
d) 10
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
a) 2
b) 1
c) 4
d) 8
advertisement
Answers.
a) Distant
b) Data
c) Desired
d) Delay
advertisement
a) 1
b) 2
c) 3
d) 4
a) 2
b) 3
c) 4
d) 1
a) S-R
b) J-K
c) T
d) S-K
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
advertisement
a) 0
b) 1
c) Forbidden
d) Toggle
advertisement
edge of the clock
states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1

advertisement
b) Q(n+1)=J’Q(n)+KQ'(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
advertisement
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) 3
b) 4
c) 2
d) 5
advertisement

a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
advertisement
a) Level enabled
b) Edge triggered
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
advertisement
a) Constantly LOW
b) Constantly HIGH

output.
a) 1 state
b) 0 state
d) forbidden State
advertisement
a) Input
b) Pulser
c) Output
states.
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
c) Lock out state
d) Forbidden State

advertisement
a) High state
b) Low state
c) Toggle state
d) No Change State
a) D type
b) S-R type
c) Latch
d) J-K type
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
a) T flip-flop
b) SR flip-flop
d) D flip-flop
advertisement
a) S-R flip-flop
b) J-K flip-flop
d) D Flip-flop
a) 3
b) 2
c) 4
d) 5
triggering.
12. Flip-flops are ____________
a) Stable devices
b) Astable devices
c) Bistable devices
states.
advertisement
advertisement
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
S=1 & R=0.
a) S and R
b) R input
c) J and K input
d) D input
advertisement
___________
a) 1
b) 0
c) Don’t care
d) Toggle
___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
will be J=1, K=X.
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
a) S
b) R
c) D
d) Both S and R
advertisement

c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
“Counters”.
advertisement
flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
a) 2
b) 3
c) 4
d) 5
and such like.
a) 5
b) 10
c) 15
d) 20
advertisement
a) SSI counters
d) VLSI counters
them.
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
a) Parallel counter
b) Decade counter
d) VLSI counter
count from 0 to 9.
advertisement
b) Clock frequency
c) Counter modulus
d) Clock count
a) 4
b) 8
c) 16
d) 32
advertisement
a) Each flip-flop
applications
a) Ripple counter
b) Ring counter
c) Modulus counter
occurs?
advertisement
a) 4
b) 8
c) 5
d) 10
a) 0000
b) 1010
c) 1001
d) 1111

a) 2
b) 4
c) 8
d) 16
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
advertisement
a) 1
b) 2
c) 8
d) 15
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) 10
b) 20
c) 100
d) 1000
a) Each flip-flop
advertisement
a) 3
b) 6
c) 8
d) 16
switch ____________
a) HIGH
c) To an open
d) LOW
ICs”.
a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
advertisement
a) 1
b) 4
c) 2
d) 8
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
5. IC 7493 consist of ____________
a) 4 S-R flip-flop
b) 4 J-K flip-flop
d) 4 D flip-flop
advertisement
counter.
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492

advertisement
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
7493 FF.
a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
advertisement
division.
a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12
advertisement
– 1) to 0).
3. UP Counter is ____________
a) 2
b) 4
c) 6
d) 8
advertisement
a) MSB flip-flop
b) LSB flip-flop
d) Latch
a) 000
b) 111
c) 010
d) 101
____________
a) 000
b) 111
c) 101
d) 010
becomes 111.
____________
a) 000
b) 111
c) 101
d) 010
becomes 101.
advertisement
a) 3CB0
b) 3C66
c) 63C0
d) 6300
are toggling
advertisement

advertisement
a) Count up
b) Count down
____________
c) The system clock
a) Synchronous
b) Bean
c) Decade
d) BCD
a) 74134
b) LPM
c) Synchronous
d) AHDL
advertisement
a) 3
b) 8
c) 5
d) 10
a) 20%
b) 50%
c) 10%
d) 80%
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
a) 8
b) 4
c) 16
d) 32
advertisement
a) Ring counter
b) Ripple counter
a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
fundamental mode.
advertisement

a) Each flip-flop
advertisement
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) Each flip-flop
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
advertisement
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
= 1/200ns = 5 MHz.
a) Strobing
b) Feeding
c) Wagging
d) Waving
advertisement
c) It is very fast
c) Stop counting
previous flip-flop.
advertisement

a) Latches
b) Flip-flops
c) UP counter
advertisement
a) Dual counter
b) Multi counter
d) Two Counter
well as downwards.

a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
advertisement
a) Starts counting
b) Can be reversed
d) Can be altered
a) 2
b) 3
c) 4
d) 5
required.

a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
a) 8
b) 9
c) 11
d) 15
advertisement

________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Hence, f = 10/8 = 1.25 kHz.
advertisement
Answers.

another.
advertisement
c) CPU
d) Latches
inputs.
a) 2
b) 3
c) 4
d) 5
a) Delay
b) Decrement
c) Data
d) Decay
advertisement
a) Data register
b) Binary register
c) Shift register
d) D – Register
a) 2
b) 3
c) 4
d) 5
advertisement
b) simultaneously

Registers”.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Tristate
b) End around
c) Universal
d) Conversion
advertisement
a) 01110
b) 00001
c) 00101
d) 00110
01110->initial
01011->second
00101->third.
a) 1100
b) 0011
c) 0000
d) 1111
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
a) 0000
b) 1111
c) 0111
d) 1000
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
sec.
advertisement
(td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us

a) Ring shift
b) Clock
c) Johnson
d) Binary
advertisement
a) 1101
b) 0111
c) 0001
d) 1110
1011 | 1101

clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
a) 2
b) 3
c) 4
d) 5
advertisement
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
a) HIGH, LOW, float
b) High-Z, 0, float
d) 1, Low-Z, float
output device
advertisement
b) A ring is faster

manner.
advertisement

input.
a) 1110
b) 0111
c) 1000
d) 1001
Explanation: Given,
111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
a) 1110
b) 0001
c) 1100
d) 1000
are 0001.
a) 10111000
b) 10110111
c) 11110000
d) 11111100
simultaneously.
advertisement
a) 1
b) 3
c) 4
d) 8

a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
a) One bit
b) Two bits
c) Four bits
d) Eight bits
them.
advertisement

counters.
advertisement
d) The clock input
out.
a) UART
b) Key matrix
c) Memory chip
advertisement
a) All FFs set to 1
c) Strobe line
d) Multiplexer
advertisement
a) Circulating gate
b) Transceiver
d) Strobed latch
1. Memory is a/an ___________
advertisement
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
required.
information.
a) Data
b) Word
c) Nibble
16-bits or 2-bytes.
advertisement
a) A small display
a) Large memory
b) Small memory
c) Core memory
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
memory.
advertisement
a) NMOS
b) CMOS
c) BJT
a) Floppy disk
d) Control Unit
desired data word.
advertisement

a) EROM
b) RAM
c) PROM
d) EEPROM
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
b) Read Out Memory
c) Read Only Memory
d) Read One Memory

advertisement
a) PROM
b) EPROM
c) CDROM
d) PLA
process.
the user.

advertisement
a) PAL
b) PLA
c) APL
d) PPL
a) PAL
b) PPL
c) PLA
d) APL
a) ISAC
b) ASIC
c) SACC
d) CISF
advertisement
a) EPROM
b) FPGA
d) ROM
advertisement
a) 3
b) 4
c) 5
d) 6
Memory.
advertisement
a) Registers
b) Main Memory
c) RAM
b) Within RAM
c) Within ROM
d) Within CPU
a) RAM
b) ROM
c) Registers
d) Flag
a) Registers
b) Semiconductors
c) Counters
d) PLDs
advertisement
a) Secondary Memory
b) Auxiliary Memory
c) Static Memory
a) Main Memory
b) Secondary Memory
c) Static Memory
d) Volatile Memory
a) Floppy disk
b) Magnetic drum
c) Hard disk
a) 2
b) 3
c) 4
d) 5
advertisement
a) Floppy disk
b) Hard disk
d) RAM
a) Floppy disk
b) Hard disk
advertisement
and Answers.
advertisement
a) 1
b) 2
c) 3
d) 4
a) CCD
d) Floppy-Disk
advertisement
b) Read Only Memory
a) 2
b) 3
c) 4
d) 5
advertisement

to hold the data.
__________
a) PLD
b) LSI
c) VLSI
advertisement
a) Bus collisions
c) Address decoding
d) Bus contention
advertisement
a) Unit cells
b) Storage cells
c) Data cells
d) Binary cells
a) Storage cells
b) Data cells
c) Unit cells
a) Nibble
b) Word
c) Byte
d) Address
a) Letters
b) Binary numbers
d) Gray codes
bits or 2-bytes.
advertisement
a) RAM
b) ROM
c) Storage class
d) Address
or 2-bytes.
a) Nibble
b) Flag
c) Byte
d) Word
a) Control lines
and received.
advertisement
b) Tracks per inch
d) Rotation speed
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
advertisement
d) Erase operation
4. The ROM is a ___________
c) Magnetic circuit
d) Static circuit
not past states.
b) NOR and decoder
d) NAND and decoder
advertisement
a) Memory unit
b) Storage class
c) Data word
d) Address
a) Zip
b) Hard disk
c) Super Disk
d) Jaz
a) Memory unit
b) Storage class
c) Data word
d) Address
advertisement
a) NMOS
b) CMOS
c) BJT
a) 2
b) 3
c) 4
d) 5
advertisement
a) FETs
b) Transistors
c) MOSFETs
d) BJTs
more efficient.
a) 8 bits
b) 12 bits
c) 16 bits
d) 32 bits
advertisement
a) Extended
b) Expanded
c) Base
d) Conventional
a) Address bus
b) System bus
c) Control bus
d) Data bus
a) Platter
b) Read/Write
c) Valve
d) Spindle
advertisement
a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
more efficient.
a) Cluster
b) Read/Write
c) Cylinder
d) Recordable
a) EEPROM
b) Mask ROM
c) EPROM
d) PROM
advertisement
c) RAM and ROM
programmed.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Mask Programming
b) PROM
d) EPROM
a) Photo
b) Negative
c) Mask
d) Virtual image
a) EPROM
b) PROM
a) 8 bits
b) 16 bits
c) 128 bits
d) 64 bits
advertisement
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
MSI/TTL based.
7. IC 74187 is of __________
a) 512 bits
b) 1024 bits
c) 256 bits
d) 68 bits
a) 128, 3
b) 128, 4
c) 256, 3
d) 256, 4
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
advertisement
a) 16
b) 32
c) 64
d) 8
a) TMS 45276
b) TMS 45278
c) TMS 45279
d) TMS 45275
13. TMS 45276 is of __________
a) 32 KB
b) 56 KB
c) 8 bits
d) 4 bytes
a) TMS 45276
b) IC 74188
c) IC 74187
d) IC 74185
organization.
a) Storing Capacity
b) Custom Select
c) Chip Select
d) Custom Storage
advertisement
c) Code conversion
b) Data hold
c) Read cycle time
d) Access time
advertisement

a) ROM
b) EPROM
c) PROM
d) EEPROM
a) 4096
b) 16384
c) 32768
d) 8129
advertisement
of eight bits?
a) Eight
b) Two
c) One
d) Four
c) Command code
advertisement
a) 8 locations
b) 256 locations
c) 65,536 locations
locations = 28.
a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
advertisement
a) 2
b) 3
c) 4
d) 5
a) Polycrystalline
c) Nichrome
d) Silicon dioxide

c) Nichrome
d) Silicon dioxide
advertisement
a) EPROM programmer
c) PROM programmer
d) ROM programmer
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
advertisement
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
rows and 8 columns.
7. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
a) 165,667
b) 245,784
c) 262,144
d) 212,342
a) 10
b) 11
c) 12
d) 13
advertisement
a) 1024
b) 4096
c) 2048
d) 8192
8192 bit.
advertisement
a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell

d) Memory mapping
user.
advertisement
a) 0
b) 1
c) Both 0 and 1
a) Reprogrammed
b) Restarted
c) Charged
d) Power off
c) It is volatile
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
advertisement
a) 1024
b) 512
c) 2516
d) 256
a) HIGH
b) LOW
a) Power is on
b) Power is off
c) System is down
this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Explanation: 8K = 8 * 1024 = 8192.
advertisement
b) Faulty
c) Probably good

advertisement
a) RAM
b) FPROM
c) EEPROM
d) ROM
a) RAM
b) ROM
c) PROM
d) EPROM
a) RWM
b) MBR
c) MAR
d) ROM
Read Write Memory).
advertisement
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
a) MBR
b) MAR
c) RAM
d) ROM
a) Data buffer
b) Chip select
c) Read and write
d) Memory
respectively.
a) High complexity
b) High resolution

d) High flexibility
advertisement
a) 2
b) 3
c) 4
d) 5
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
operation.
a) ROM
b) EROM
c) PROM
d) RAM
advertisement
a) 32 bit to 64 bit
advertisement

a) Activated
b) Deactivated
c) Unaffected
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
advertisement
6. IC 7489 is of ____________
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
a) Chip select
b) Enable
c) Data input
d) Memory enable
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
a) 1946
b) 1948
c) 1947
d) 1945
advertisement
a) SRAM
b) DRAM
c) EEPROM
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
locations.
a) 1024 * 4
b) 1024 * 8
c) 2048 * 4
d) 2048 * 8
locations.
advertisement
a) 10
b) 9
c) 12
d) 11
locations.
a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional

advertisement
a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
memories.
advertisement
a) Cache
b) Dynamic RAM
c) Static RAM
a) SRAM
b) DRAM
c) Magnetic memory
d) Main Memory
advertisement
d) Has higher speed
a) RAM and ROM
b) CPU and RAM
d) CPU and ROM

a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile
advertisement
a) 10240
b) 15289
c) 16384
d) 17654
bits.

a) 2114
b) 7489
c) 4116
d) 2776
advertisement

a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
a) 3
b) 2
c) 1
d) 4
a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM
advertisement
a) Scratch-pad
b) Buffer
c) Main memory
a) ROM
b) RAM
c) EROM
d) PROM
advertisement
a) ROM
b) RAM
c) EROM
d) PROM
operation.
__________
a) PROM
b) Main Memory
d) Mass memory
12. CD-ROM is a __________
a) Memory register
b) Magnetic memory
a) A bit
b) A record
c) An address
d) A byte
advertisement
a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM
advertisement
d) Data insertion
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
per word.
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2
advertisement
a) 1
b) 2
c) 3
d) 4
a) 4
b) 6
c) 8
d) 12
chips.
a) 2
b) 4
c) 6
d) 8

a single chip.
advertisement
a) Flip-flops
b) Gates
c) Registers
a) RAM
b) ROM
c) PLD
d) PLA
a) High reliability

advertisement
a) 2
b) 3
c) 4
d) 5

a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
advertisement
2. PAL refers to ____________
a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
4. PLA contains ____________
advertisement
a) PLA
b) PAL
c) CPLD
d) SLD
b) AND/OR arrays
(FPGAs).
a) SLD
b) SROM
c) EPROM
d) PLD
advertisement

AND plane
AND plane
advertisement
a) A line
b) A channel
c) A strobe
d) A flip-flop
a) Registered PALs
c) PAL programming

advertisement
a) Documentation
b) Verification

a) 2
b) 3
c) 4
d) 5
advertisement
c) Test the decoder
a) 1 Hz
b) 60 Hz
c) 100 Hz
d) 1000 Hz
advertisement
b) Freeze
advertisement
b) Decoder/display
c) Display register
d) Bit shifter
b) Types and bits

1. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
advertisement
a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
4. 4 to 1 MUX would have ____________
a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
advertisement
b) DPDT switch
c) Rotary switch
d) Linear stepper
advertisement
a) Bidirectional
b) Unidirectional
c) Even parity
a) Enable
b) Disable
c) Saturation
d) High Impedance
(i.e. E’).

advertisement
and Answers.
a) One into many
b) Many into one
c) Distributor
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
advertisement
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answers.
advertisement
Ray Tubes.
advertisement
a) Air
b) Solid
c) Light
d) Water
material.
a) Magnetic field
b) Electric field
d) Gallois field
a) LED
b) LCD
c) OFC
d) OLED
the basis for LCDs.
chemical structure.
advertisement
a) 1950s
b) 1980s
c) 1960s
d) 1970s
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
Cathode Ray Tubes.
a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
a) 8
b) 7
c) 10
d) 9
advertisement

a) 4
b) 8
c) 10
d) 16
advertisement
a) 4
b) 8
c) 12
d) 16
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
a) Yes
b) No
advertisement
a) 2
b) 10
c) 3
d) 4
a) 3
b) 2
c) 8
d) 10
lines.
a) 8
b) 2^8
c) 4
d) 2^4
___________
a) Enable
b) Disable
c) Strobe
d) Clock
an active-low pin.
advertisement
a) No
b) Yes
c) Sometimes
d) Never
a) The higher value
b) The lower value
advertisement
a) 4
b) 5
c) 15
d) 10
from 0 to 9.
advertisement
a) Encoder
b) Display
c) Counter
d) Decoder
a) 4
b) 8
c) 10
d) 2
<= 2n.
a) 10
b) 9
c) 8
d) 3
advertisement
a) 32
b) 64
c) 128
d) 16
c) By using an ALU
d) By using UART
circuits.
a) 2
b) 16
c) 8
d) 4
advertisement
symbol?
2”.
c) CRC
d) Checksum
advertisement
c) CRC
d) Checksum
a) 2
b) 3
c) 4
d) 1
a) Even
b) Odd
d) Undefined
advertisement
b) CRC
d) Checksum
a) 0
b) 1
c) 1001
d) 0011
number of 1’s.
a) Indeterminate
b) 42
c) Even
d) Odd
c) CRC
d) Checksum
advertisement
a) AND
b) NAND
c) EX-OR
d) EX-NOR
advertisement
0101 0011 & 0010 0110 1000
a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
d) 101011 001100001
advertisement
c) With an ALU
d) UART
circuits.
a) BCD code
b) Binary code
c) ASCII code
d) Gray Code

c) Error correction
d) Error Detection
advertisement
a) Binary addition
b) 2’s complement
a) 0011101
b) 0110101
c) 1101001
d) 0101011
a) 101101
b) 001110
c) 110111
d) 111001
↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1
advertisement
Answers.
a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
advertisement
a) a > b
b) a – b
c) a < b
d) a = b
a) 0
b) 1
c) A
d) B
a) 1
b) 2
c) 3
d) 4
a) 1
b) 0
c) A
d) B
advertisement
a) XOR
b) XNOR
c) AND
d) NAND
a) Memory
b) CPU
c) Motherboard
d) Hard drive
b) Size comparator
c) Comparator
a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
advertisement
a) 1
b) 2
c) 3
d) 4
“HIGH” A = B = 1 or “LOW” A = B = 0.
comparison.
advertisement
14. TTL 74LS85 is a _____________

d) 555 timer
advertisement
a) One stable state
b) Two stable state
a) 4
b) 3
c) 2
d) 5
advertisement
a) System rated
b) Set reset
c) Set ready
d) Set Rated
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
a) x and y
b) a and b
c) s and r
d) q and q’
a) 1
b) 0
c) Inverted
d) Don’t cares
advertisement
a) label inputs
b) label outputs
c) label states
d) label tables
labelled.
a) x and y
b) a and b
c) s and r
d) j and k
high and Q’ low.
output.
advertisement
a) Unstable
b) Stable
c) Metastable
d) Bistable
feature?
c) Gate impedance
d) Cross coupling
advertisement
b) Racer
c) Switch debouncer
a) 1
b) 2
c) 3
d) 4
a) Be invalid
b) Change
c) Not change
d) Toggle

advertisement
a) AND or OR gates
d) AND or NOR gates
c) Latches
d) Flip-flops
c) Latches
d) Flip-flops
a) 2
b) 3
c) 4
d) 5
advertisement
a) Flip-flop
b) Latch
c) Strobe
d) Adder
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
a) Set
b) Reset
c) Previous state
d) Current state
advertisement
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
advertisement
a) No change
b) Set
c) Reset
d) Forbidden
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
advertisement
a) Both are same

a) 2
b) 3
c) 4
d) 5
a) 4 AND gates
d) 3 AND gates
d) Invalid State
as Invalid State.
advertisement
a) Racer
c) Only S is active
d) Only R is active
advertisement
a) SET
b) RESET
c) Clear
d) Invalid
_____________
b) NOR latch
c) NAND latch
inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
number of inputs.
advertisement
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
flip-flop.
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
b) Ones catching
advertisement
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
a) Constantly LOW
b) Constantly HIGH

HIGH
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
advertisement
a) 00
b) 11
c) 01
d) 10
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
a) 2
b) 1
c) 4
d) 8
advertisement
Answers.
a) Distant
b) Data
c) Desired
d) Delay
advertisement
a) 1
b) 2
c) 3
d) 4
a) 2
b) 3
c) 4
d) 1
a) S-R
b) J-K
c) T
d) S-K
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
advertisement
a) 0
b) 1
c) Forbidden
d) Toggle

advertisement
edge of the clock
states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
advertisement

b) Q(n+1)=J’Q(n)+KQ'(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
advertisement
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) 3
b) 4
c) 2
d) 5
advertisement
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
advertisement
a) Level enabled
b) Edge triggered
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
advertisement
a) Constantly LOW
b) Constantly HIGH
output.
a) 1 state
b) 0 state
d) forbidden State
advertisement
a) Input
b) Pulser
c) Output
states.
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
c) Lock out state
d) Forbidden State
advertisement
a) High state
b) Low state
c) Toggle state
d) No Change State
a) D type
b) S-R type
c) Latch
d) J-K type
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
a) T flip-flop
b) SR flip-flop
d) D flip-flop
advertisement
a) S-R flip-flop
b) J-K flip-flop
d) D Flip-flop
a) 3
b) 2
c) 4
d) 5
triggering.
12. Flip-flops are ____________
a) Stable devices
b) Astable devices
c) Bistable devices
states.
advertisement
advertisement
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
S=1 & R=0.
a) S and R
b) R input
c) J and K input
d) D input
advertisement
___________
a) 1
b) 0
c) Don’t care
d) Toggle
___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
will be J=1, K=X.
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
a) S
b) R
c) D
d) Both S and R
advertisement
c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K

“Counters”.
advertisement
flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
a) 2
b) 3
c) 4
d) 5
and such like.
a) 5
b) 10
c) 15
d) 20
advertisement
a) SSI counters
d) VLSI counters
them.
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
a) Parallel counter
b) Decade counter
d) VLSI counter
count from 0 to 9.
advertisement
b) Clock frequency
c) Counter modulus
d) Clock count
a) 4
b) 8
c) 16
d) 32
advertisement
a) Each flip-flop

applications
a) Ripple counter
b) Ring counter
c) Modulus counter
occurs?
advertisement
a) 4
b) 8
c) 5
d) 10
a) 0000
b) 1010
c) 1001
d) 1111
a) 2
b) 4
c) 8
d) 16
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
advertisement
a) 1
b) 2
c) 8
d) 15
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) 10
b) 20
c) 100
d) 1000
a) Each flip-flop

advertisement
a) 3
b) 6
c) 8
d) 16
switch ____________
a) HIGH
c) To an open
d) LOW
ICs”.
a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
advertisement
a) 1
b) 4
c) 2
d) 8
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
5. IC 7493 consist of ____________
a) 4 S-R flip-flop
b) 4 J-K flip-flop
d) 4 D flip-flop
advertisement
counter.

a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
advertisement
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
7493 FF.
a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
advertisement

division.
a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12
advertisement
– 1) to 0).
3. UP Counter is ____________
a) 2
b) 4
c) 6
d) 8
advertisement
a) MSB flip-flop
b) LSB flip-flop
d) Latch
a) 000
b) 111
c) 010
d) 101
____________
a) 000
b) 111
c) 101
d) 010
becomes 111.
____________
a) 000
b) 111
c) 101
d) 010
becomes 101.
advertisement
a) 3CB0
b) 3C66
c) 63C0
d) 6300
are toggling

advertisement
advertisement
a) Count up
b) Count down
____________
c) The system clock
a) Synchronous
b) Bean
c) Decade
d) BCD
a) 74134
b) LPM
c) Synchronous
d) AHDL
advertisement
a) 3
b) 8
c) 5
d) 10
a) 20%
b) 50%
c) 10%
d) 80%
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
a) 8
b) 4
c) 16
d) 32
advertisement
a) Ring counter
b) Ripple counter
a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
fundamental mode.
advertisement
a) Each flip-flop
advertisement
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) Each flip-flop
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
advertisement
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
= 1/200ns = 5 MHz.
a) Strobing
b) Feeding
c) Wagging
d) Waving
advertisement
c) It is very fast
c) Stop counting
previous flip-flop.

advertisement
a) Latches
b) Flip-flops
c) UP counter
advertisement
a) Dual counter
b) Multi counter
d) Two Counter
well as downwards.
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
advertisement
a) Starts counting
b) Can be reversed
d) Can be altered
a) 2
b) 3
c) 4
d) 5
required.
a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
a) 8
b) 9
c) 11
d) 15
advertisement
________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Hence, f = 10/8 = 1.25 kHz.

advertisement
Answers.
another.
advertisement
c) CPU
d) Latches
inputs.
a) 2
b) 3
c) 4
d) 5
a) Delay
b) Decrement
c) Data
d) Decay
advertisement
a) Data register
b) Binary register
c) Shift register
d) D – Register
a) 2
b) 3
c) 4
d) 5
advertisement
b) simultaneously
Registers”.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Tristate
b) End around
c) Universal
d) Conversion

advertisement
a) 01110
b) 00001
c) 00101
d) 00110
01110->initial
01011->second
00101->third.
a) 1100
b) 0011
c) 0000
d) 1111
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.

a) 0000
b) 1111
c) 0111
d) 1000
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
sec.
advertisement
(td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
a) Ring shift
b) Clock
c) Johnson
d) Binary
advertisement
a) 1101
b) 0111
c) 0001
d) 1110
1011 | 1101
clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
a) 2
b) 3
c) 4
d) 5
advertisement
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
a) HIGH, LOW, float
b) High-Z, 0, float
d) 1, Low-Z, float
output device
advertisement
b) A ring is faster

manner.
advertisement
input.
a) 1110
b) 0111
c) 1000
d) 1001
Explanation: Given,

111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
a) 1110
b) 0001
c) 1100
d) 1000
are 0001.
a) 10111000
b) 10110111
c) 11110000
d) 11111100
simultaneously.
advertisement
a) 1
b) 3
c) 4
d) 8
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
a) One bit
b) Two bits
c) Four bits
d) Eight bits
them.
advertisement
counters.
advertisement
d) The clock input
out.
a) UART
b) Key matrix
c) Memory chip
advertisement
a) All FFs set to 1
c) Strobe line
d) Multiplexer
advertisement
a) Circulating gate
b) Transceiver
d) Strobed latch
1. Memory is a/an ___________

advertisement
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
required.
information.
a) Data
b) Word
c) Nibble
16-bits or 2-bytes.
advertisement
a) A small display
a) Large memory
b) Small memory
c) Core memory
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
memory.
advertisement
a) NMOS
b) CMOS
c) BJT
a) Floppy disk
d) Control Unit
desired data word.
advertisement
a) EROM
b) RAM
c) PROM
d) EEPROM
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
b) Read Out Memory
c) Read Only Memory
d) Read One Memory
advertisement
a) PROM
b) EPROM
c) CDROM
d) PLA
process.
the user.
advertisement
a) PAL
b) PLA
c) APL
d) PPL
a) PAL
b) PPL
c) PLA
d) APL
a) ISAC
b) ASIC
c) SACC
d) CISF
advertisement

a) EPROM
b) FPGA
d) ROM
advertisement
a) 3
b) 4
c) 5
d) 6
Memory.
advertisement
a) Registers
b) Main Memory
c) RAM
b) Within RAM
c) Within ROM
d) Within CPU
a) RAM
b) ROM
c) Registers
d) Flag
a) Registers
b) Semiconductors
c) Counters
d) PLDs
advertisement
a) Secondary Memory
b) Auxiliary Memory
c) Static Memory

a) Main Memory
b) Secondary Memory
c) Static Memory
d) Volatile Memory
a) Floppy disk
b) Magnetic drum
c) Hard disk
a) 2
b) 3
c) 4
d) 5
advertisement

a) Floppy disk
b) Hard disk
d) RAM
a) Floppy disk
b) Hard disk
advertisement

and Answers.
advertisement
a) 1
b) 2
c) 3
d) 4
a) CCD
d) Floppy-Disk

advertisement
b) Read Only Memory
a) 2
b) 3
c) 4
d) 5
advertisement
to hold the data.
__________

a) PLD
b) LSI
c) VLSI
advertisement

a) Bus collisions
c) Address decoding
d) Bus contention
advertisement
a) Unit cells
b) Storage cells
c) Data cells
d) Binary cells
a) Storage cells
b) Data cells
c) Unit cells
a) Nibble
b) Word
c) Byte
d) Address
a) Letters
b) Binary numbers
d) Gray codes
bits or 2-bytes.
advertisement
a) RAM
b) ROM
c) Storage class
d) Address
or 2-bytes.
a) Nibble
b) Flag
c) Byte
d) Word

a) Control lines
and received.
advertisement
b) Tracks per inch
d) Rotation speed
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
advertisement
d) Erase operation

4. The ROM is a ___________
c) Magnetic circuit
d) Static circuit
not past states.
b) NOR and decoder
d) NAND and decoder
advertisement
a) Memory unit
b) Storage class
c) Data word
d) Address
a) Zip
b) Hard disk
c) Super Disk
d) Jaz
a) Memory unit
b) Storage class
c) Data word
d) Address
advertisement
a) NMOS
b) CMOS
c) BJT
a) 2
b) 3
c) 4
d) 5
advertisement
a) FETs
b) Transistors
c) MOSFETs
d) BJTs
more efficient.
a) 8 bits
b) 12 bits
c) 16 bits
d) 32 bits
advertisement
a) Extended
b) Expanded
c) Base
d) Conventional
a) Address bus
b) System bus
c) Control bus
d) Data bus
a) Platter
b) Read/Write
c) Valve
d) Spindle
advertisement
a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
more efficient.
a) Cluster
b) Read/Write
c) Cylinder
d) Recordable
a) EEPROM
b) Mask ROM
c) EPROM
d) PROM
advertisement
c) RAM and ROM
programmed.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Mask Programming
b) PROM
d) EPROM
a) Photo
b) Negative
c) Mask
d) Virtual image
a) EPROM
b) PROM
a) 8 bits
b) 16 bits
c) 128 bits
d) 64 bits
advertisement
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
MSI/TTL based.
7. IC 74187 is of __________
a) 512 bits
b) 1024 bits
c) 256 bits
d) 68 bits
a) 128, 3
b) 128, 4
c) 256, 3
d) 256, 4
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
advertisement
a) 16
b) 32
c) 64
d) 8
a) TMS 45276
b) TMS 45278
c) TMS 45279
d) TMS 45275
13. TMS 45276 is of __________
a) 32 KB
b) 56 KB
c) 8 bits
d) 4 bytes
a) TMS 45276
b) IC 74188
c) IC 74187
d) IC 74185
organization.
a) Storing Capacity
b) Custom Select
c) Chip Select
d) Custom Storage
advertisement
c) Code conversion
b) Data hold
c) Read cycle time
d) Access time
advertisement
a) ROM
b) EPROM
c) PROM
d) EEPROM

a) 4096
b) 16384
c) 32768
d) 8129
advertisement
of eight bits?
a) Eight
b) Two
c) One
d) Four
c) Command code
advertisement
a) 8 locations
b) 256 locations
c) 65,536 locations
locations = 28.

a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
advertisement
a) 2
b) 3
c) 4
d) 5
a) Polycrystalline
c) Nichrome
d) Silicon dioxide
c) Nichrome
d) Silicon dioxide
advertisement
a) EPROM programmer
c) PROM programmer
d) ROM programmer
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
advertisement
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
rows and 8 columns.
7. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
a) 165,667
b) 245,784
c) 262,144
d) 212,342
a) 10
b) 11
c) 12
d) 13
advertisement
a) 1024
b) 4096
c) 2048
d) 8192
8192 bit.

advertisement
a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell
d) Memory mapping
user.

advertisement
a) 0
b) 1
c) Both 0 and 1
a) Reprogrammed
b) Restarted
c) Charged
d) Power off
c) It is volatile
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
advertisement
a) 1024
b) 512
c) 2516
d) 256
a) HIGH
b) LOW
a) Power is on
b) Power is off
c) System is down
this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Explanation: 8K = 8 * 1024 = 8192.
advertisement
b) Faulty
c) Probably good
advertisement
a) RAM
b) FPROM
c) EEPROM
d) ROM
a) RAM
b) ROM
c) PROM
d) EPROM
a) RWM
b) MBR
c) MAR
d) ROM
Read Write Memory).
advertisement
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
a) MBR
b) MAR
c) RAM
d) ROM
a) Data buffer
b) Chip select
c) Read and write
d) Memory
respectively.
a) High complexity
b) High resolution
d) High flexibility
advertisement
a) 2
b) 3
c) 4
d) 5
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
operation.
a) ROM
b) EROM
c) PROM
d) RAM
advertisement
a) 32 bit to 64 bit
advertisement
a) Activated
b) Deactivated
c) Unaffected
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
advertisement
6. IC 7489 is of ____________
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
a) Chip select
b) Enable
c) Data input
d) Memory enable
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
a) 1946
b) 1948
c) 1947
d) 1945
advertisement
a) SRAM
b) DRAM
c) EEPROM
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
locations.
a) 1024 * 4
b) 1024 * 8
c) 2048 * 4
d) 2048 * 8
locations.
advertisement
a) 10
b) 9
c) 12
d) 11
locations.
a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional
advertisement
a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
memories.
advertisement
a) Cache
b) Dynamic RAM
c) Static RAM
a) SRAM
b) DRAM
c) Magnetic memory
d) Main Memory
advertisement
d) Has higher speed
a) RAM and ROM
b) CPU and RAM
d) CPU and ROM
a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile

advertisement
a) 10240
b) 15289
c) 16384
d) 17654
bits.
a) 2114
b) 7489
c) 4116
d) 2776
advertisement
a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
a) 3
b) 2
c) 1
d) 4
a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM
advertisement
a) Scratch-pad
b) Buffer
c) Main memory
a) ROM
b) RAM
c) EROM
d) PROM
advertisement
a) ROM
b) RAM
c) EROM
d) PROM
operation.
__________
a) PROM
b) Main Memory
d) Mass memory
12. CD-ROM is a __________
a) Memory register
b) Magnetic memory
a) A bit
b) A record
c) An address
d) A byte
advertisement
a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM
advertisement
d) Data insertion
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
per word.
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2
advertisement
a) 1
b) 2
c) 3
d) 4
a) 4
b) 6
c) 8
d) 12
chips.
a) 2
b) 4
c) 6
d) 8
a single chip.
advertisement
a) Flip-flops
b) Gates
c) Registers
a) RAM
b) ROM
c) PLD
d) PLA
a) High reliability
advertisement
a) 2
b) 3
c) 4
d) 5

a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
advertisement
2. PAL refers to ____________
a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
4. PLA contains ____________

advertisement
a) PLA
b) PAL
c) CPLD
d) SLD
b) AND/OR arrays
(FPGAs).
a) SLD
b) SROM
c) EPROM
d) PLD
advertisement
AND plane
AND plane

advertisement
a) A line
b) A channel
c) A strobe
d) A flip-flop
a) Registered PALs
c) PAL programming
advertisement
a) Documentation
b) Verification
a) 2
b) 3
c) 4
d) 5
advertisement
c) Test the decoder
a) 1 Hz
b) 60 Hz
c) 100 Hz
d) 1000 Hz
advertisement
b) Freeze

advertisement
b) Decoder/display
c) Display register
d) Bit shifter
b) Types and bits

1. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
advertisement
a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
4. 4 to 1 MUX would have ____________
a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
advertisement

b) DPDT switch
c) Rotary switch
d) Linear stepper
advertisement
a) Bidirectional
b) Unidirectional
c) Even parity
a) Enable
b) Disable
c) Saturation
d) High Impedance
(i.e. E’).
advertisement
and Answers.

a) One into many
b) Many into one
c) Distributor
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
advertisement

advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answers.
advertisement

Ray Tubes.
advertisement
a) Air
b) Solid
c) Light
d) Water
material.
a) Magnetic field
b) Electric field
d) Gallois field
a) LED
b) LCD
c) OFC
d) OLED
the basis for LCDs.
chemical structure.
advertisement
a) 1950s
b) 1980s
c) 1960s
d) 1970s
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
Cathode Ray Tubes.
a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
a) 8
b) 7
c) 10
d) 9
advertisement

a) 4
b) 8
c) 10
d) 16
advertisement
a) 4
b) 8
c) 12
d) 16
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
a) Yes
b) No
advertisement
a) 2
b) 10
c) 3
d) 4
a) 3
b) 2
c) 8
d) 10
lines.
a) 8
b) 2^8
c) 4
d) 2^4
___________
a) Enable
b) Disable
c) Strobe
d) Clock
an active-low pin.
advertisement
a) No
b) Yes
c) Sometimes
d) Never
a) The higher value
b) The lower value
advertisement
a) 4
b) 5
c) 15
d) 10
from 0 to 9.
advertisement
a) Encoder
b) Display
c) Counter
d) Decoder
a) 4
b) 8
c) 10
d) 2
<= 2n.
a) 10
b) 9
c) 8
d) 3
advertisement
a) 32
b) 64
c) 128
d) 16
c) By using an ALU
d) By using UART
circuits.
a) 2
b) 16
c) 8
d) 4
advertisement
symbol?
2”.
c) CRC
d) Checksum
advertisement
c) CRC
d) Checksum
a) 2
b) 3
c) 4
d) 1
a) Even
b) Odd
d) Undefined
advertisement
b) CRC
d) Checksum

a) 0
b) 1
c) 1001
d) 0011
number of 1’s.
a) Indeterminate
b) 42
c) Even
d) Odd
c) CRC
d) Checksum
advertisement
a) AND
b) NAND
c) EX-OR
d) EX-NOR
advertisement
0101 0011 & 0010 0110 1000
a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
d) 101011 001100001
advertisement
c) With an ALU
d) UART
circuits.
a) BCD code
b) Binary code
c) ASCII code
d) Gray Code
c) Error correction
d) Error Detection
advertisement
a) Binary addition
b) 2’s complement
a) 0011101
b) 0110101
c) 1101001
d) 0101011
a) 101101
b) 001110
c) 110111
d) 111001
↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1
advertisement
Answers.
a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
advertisement
a) a > b
b) a – b
c) a < b
d) a = b
a) 0
b) 1
c) A
d) B
a) 1
b) 2
c) 3
d) 4
a) 1
b) 0
c) A
d) B
advertisement
a) XOR
b) XNOR
c) AND
d) NAND
a) Memory
b) CPU
c) Motherboard
d) Hard drive
b) Size comparator
c) Comparator
a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
advertisement
a) 1
b) 2
c) 3
d) 4
“HIGH” A = B = 1 or “LOW” A = B = 0.
comparison.
advertisement
14. TTL 74LS85 is a _____________
d) 555 timer
advertisement
a) One stable state
b) Two stable state
a) 4
b) 3
c) 2
d) 5
advertisement
a) System rated
b) Set reset
c) Set ready
d) Set Rated
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
a) x and y
b) a and b
c) s and r
d) q and q’
a) 1
b) 0
c) Inverted
d) Don’t cares
advertisement
a) label inputs
b) label outputs
c) label states
d) label tables
labelled.
a) x and y
b) a and b
c) s and r
d) j and k
high and Q’ low.
output.
advertisement
a) Unstable
b) Stable
c) Metastable
d) Bistable
feature?
c) Gate impedance
d) Cross coupling
advertisement
b) Racer
c) Switch debouncer
a) 1
b) 2
c) 3
d) 4
a) Be invalid
b) Change
c) Not change
d) Toggle
advertisement
a) AND or OR gates
d) AND or NOR gates

c) Latches
d) Flip-flops
c) Latches
d) Flip-flops
a) 2
b) 3
c) 4
d) 5
advertisement
a) Flip-flop
b) Latch
c) Strobe
d) Adder
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
a) Set
b) Reset
c) Previous state
d) Current state
advertisement
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
advertisement
a) No change
b) Set
c) Reset
d) Forbidden
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
advertisement
a) Both are same
a) 2
b) 3
c) 4
d) 5
a) 4 AND gates
d) 3 AND gates
d) Invalid State
as Invalid State.
advertisement
a) Racer

c) Only S is active
d) Only R is active
advertisement
a) SET
b) RESET
c) Clear
d) Invalid
_____________
b) NOR latch
c) NAND latch
inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
number of inputs.
advertisement
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
flip-flop.
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
b) Ones catching
advertisement
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
a) Constantly LOW
b) Constantly HIGH
HIGH
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
advertisement
a) 00
b) 11
c) 01
d) 10
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
a) 2
b) 1
c) 4
d) 8
advertisement
Answers.
a) Distant
b) Data
c) Desired
d) Delay
advertisement
a) 1
b) 2
c) 3
d) 4
a) 2
b) 3
c) 4
d) 1
a) S-R
b) J-K
c) T
d) S-K
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
advertisement
a) 0
b) 1
c) Forbidden
d) Toggle
advertisement
edge of the clock
states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1

advertisement
b) Q(n+1)=J’Q(n)+KQ'(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
advertisement
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) 3
b) 4
c) 2
d) 5
advertisement

a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
advertisement
a) Level enabled
b) Edge triggered
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled
d) Level triggered
advertisement
a) Constantly LOW
b) Constantly HIGH

output.
a) 1 state
b) 0 state
d) forbidden State
advertisement
a) Input
b) Pulser
c) Output
states.
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
c) Lock out state
d) Forbidden State

advertisement
a) High state
b) Low state
c) Toggle state
d) No Change State
a) D type
b) S-R type
c) Latch
d) J-K type
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
a) T flip-flop
b) SR flip-flop
d) D flip-flop
advertisement
a) S-R flip-flop
b) J-K flip-flop
d) D Flip-flop
a) 3
b) 2
c) 4
d) 5
triggering.
12. Flip-flops are ____________
a) Stable devices
b) Astable devices
c) Bistable devices
states.
advertisement
advertisement
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
S=1 & R=0.
a) S and R
b) R input
c) J and K input
d) D input
advertisement
___________
a) 1
b) 0
c) Don’t care
d) Toggle
___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
will be J=1, K=X.
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
a) S
b) R
c) D
d) Both S and R
advertisement

c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
“Counters”.
advertisement
flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
a) 2
b) 3
c) 4
d) 5
and such like.
a) 5
b) 10
c) 15
d) 20
advertisement
a) SSI counters
d) VLSI counters
them.
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
a) Parallel counter
b) Decade counter
d) VLSI counter
count from 0 to 9.
advertisement
b) Clock frequency
c) Counter modulus
d) Clock count
a) 4
b) 8
c) 16
d) 32
advertisement
a) Each flip-flop
applications
a) Ripple counter
b) Ring counter
c) Modulus counter
occurs?
advertisement
a) 4
b) 8
c) 5
d) 10
a) 0000
b) 1010
c) 1001
d) 1111

a) 2
b) 4
c) 8
d) 16
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
advertisement
a) 1
b) 2
c) 8
d) 15
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) 10
b) 20
c) 100
d) 1000
a) Each flip-flop
advertisement
a) 3
b) 6
c) 8
d) 16
switch ____________
a) HIGH
c) To an open
d) LOW
ICs”.
a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
advertisement
a) 1
b) 4
c) 2
d) 8
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
5. IC 7493 consist of ____________
a) 4 S-R flip-flop
b) 4 J-K flip-flop
d) 4 D flip-flop
advertisement
counter.
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492

advertisement
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
7493 FF.
a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
advertisement
division.
a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12
advertisement
– 1) to 0).
3. UP Counter is ____________
a) 2
b) 4
c) 6
d) 8
advertisement
a) MSB flip-flop
b) LSB flip-flop
d) Latch
a) 000
b) 111
c) 010
d) 101
____________
a) 000
b) 111
c) 101
d) 010
becomes 111.
____________
a) 000
b) 111
c) 101
d) 010
becomes 101.
advertisement
a) 3CB0
b) 3C66
c) 63C0
d) 6300
are toggling
advertisement

advertisement
a) Count up
b) Count down
____________
c) The system clock
a) Synchronous
b) Bean
c) Decade
d) BCD
a) 74134
b) LPM
c) Synchronous
d) AHDL
advertisement
a) 3
b) 8
c) 5
d) 10
a) 20%
b) 50%
c) 10%
d) 80%
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
a) 8
b) 4
c) 16
d) 32
advertisement
a) Ring counter
b) Ripple counter
a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
fundamental mode.
advertisement

a) Each flip-flop
advertisement
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) Each flip-flop
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
advertisement
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
= 1/200ns = 5 MHz.
a) Strobing
b) Feeding
c) Wagging
d) Waving
advertisement
c) It is very fast
c) Stop counting
previous flip-flop.
advertisement

a) Latches
b) Flip-flops
c) UP counter
advertisement
a) Dual counter
b) Multi counter
d) Two Counter
well as downwards.

a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
advertisement
a) Starts counting
b) Can be reversed
d) Can be altered
a) 2
b) 3
c) 4
d) 5
required.

a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
a) 8
b) 9
c) 11
d) 15
advertisement

________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Hence, f = 10/8 = 1.25 kHz.
advertisement
Answers.

another.
advertisement
c) CPU
d) Latches
inputs.
a) 2
b) 3
c) 4
d) 5
a) Delay
b) Decrement
c) Data
d) Decay
advertisement
a) Data register
b) Binary register
c) Shift register
d) D – Register
a) 2
b) 3
c) 4
d) 5
advertisement
b) simultaneously

Registers”.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Tristate
b) End around
c) Universal
d) Conversion
advertisement
a) 01110
b) 00001
c) 00101
d) 00110
01110->initial
01011->second
00101->third.
a) 1100
b) 0011
c) 0000
d) 1111
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
a) 0000
b) 1111
c) 0111
d) 1000
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
sec.
advertisement
(td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us

a) Ring shift
b) Clock
c) Johnson
d) Binary
advertisement
a) 1101
b) 0111
c) 0001
d) 1110
1011 | 1101

clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
a) 2
b) 3
c) 4
d) 5
advertisement
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
a) HIGH, LOW, float
b) High-Z, 0, float
d) 1, Low-Z, float
output device
advertisement
b) A ring is faster

manner.
advertisement

input.
a) 1110
b) 0111
c) 1000
d) 1001
Explanation: Given,
111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
a) 1110
b) 0001
c) 1100
d) 1000
are 0001.
a) 10111000
b) 10110111
c) 11110000
d) 11111100
simultaneously.
advertisement
a) 1
b) 3
c) 4
d) 8

a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
a) One bit
b) Two bits
c) Four bits
d) Eight bits
them.
advertisement

counters.
advertisement
d) The clock input
out.
a) UART
b) Key matrix
c) Memory chip
advertisement
a) All FFs set to 1
c) Strobe line
d) Multiplexer
advertisement
a) Circulating gate
b) Transceiver
d) Strobed latch
1. Memory is a/an ___________
advertisement
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
required.
information.
a) Data
b) Word
c) Nibble
16-bits or 2-bytes.
advertisement
a) A small display
a) Large memory
b) Small memory
c) Core memory
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
memory.
advertisement
a) NMOS
b) CMOS
c) BJT
a) Floppy disk
d) Control Unit
desired data word.
advertisement

a) EROM
b) RAM
c) PROM
d) EEPROM
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
b) Read Out Memory
c) Read Only Memory
d) Read One Memory

advertisement
a) PROM
b) EPROM
c) CDROM
d) PLA
process.
the user.

advertisement
a) PAL
b) PLA
c) APL
d) PPL
a) PAL
b) PPL
c) PLA
d) APL
a) ISAC
b) ASIC
c) SACC
d) CISF
advertisement
a) EPROM
b) FPGA
d) ROM
advertisement
a) 3
b) 4
c) 5
d) 6
Memory.
advertisement
a) Registers
b) Main Memory
c) RAM
b) Within RAM
c) Within ROM
d) Within CPU
a) RAM
b) ROM
c) Registers
d) Flag
a) Registers
b) Semiconductors
c) Counters
d) PLDs
advertisement
a) Secondary Memory
b) Auxiliary Memory
c) Static Memory
a) Main Memory
b) Secondary Memory
c) Static Memory
d) Volatile Memory
a) Floppy disk
b) Magnetic drum
c) Hard disk
a) 2
b) 3
c) 4
d) 5
advertisement
a) Floppy disk
b) Hard disk
d) RAM
a) Floppy disk
b) Hard disk
advertisement
and Answers.
advertisement
a) 1
b) 2
c) 3
d) 4
a) CCD
d) Floppy-Disk
advertisement
b) Read Only Memory
a) 2
b) 3
c) 4
d) 5
advertisement

to hold the data.
__________
a) PLD
b) LSI
c) VLSI
advertisement
a) Bus collisions
c) Address decoding
d) Bus contention
advertisement
a) Unit cells
b) Storage cells
c) Data cells
d) Binary cells
a) Storage cells
b) Data cells
c) Unit cells
a) Nibble
b) Word
c) Byte
d) Address
a) Letters
b) Binary numbers
d) Gray codes
bits or 2-bytes.
advertisement
a) RAM
b) ROM
c) Storage class
d) Address
or 2-bytes.
a) Nibble
b) Flag
c) Byte
d) Word
a) Control lines
and received.
advertisement
b) Tracks per inch
d) Rotation speed
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
advertisement
d) Erase operation
4. The ROM is a ___________
c) Magnetic circuit
d) Static circuit
not past states.
b) NOR and decoder
d) NAND and decoder
advertisement
a) Memory unit
b) Storage class
c) Data word
d) Address
a) Zip
b) Hard disk
c) Super Disk
d) Jaz
a) Memory unit
b) Storage class
c) Data word
d) Address
advertisement
a) NMOS
b) CMOS
c) BJT
a) 2
b) 3
c) 4
d) 5
advertisement
a) FETs
b) Transistors
c) MOSFETs
d) BJTs
more efficient.
a) 8 bits
b) 12 bits
c) 16 bits
d) 32 bits
advertisement
a) Extended
b) Expanded
c) Base
d) Conventional
a) Address bus
b) System bus
c) Control bus
d) Data bus
a) Platter
b) Read/Write
c) Valve
d) Spindle
advertisement
a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
more efficient.
a) Cluster
b) Read/Write
c) Cylinder
d) Recordable
a) EEPROM
b) Mask ROM
c) EPROM
d) PROM
advertisement
c) RAM and ROM
programmed.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Mask Programming
b) PROM
d) EPROM
a) Photo
b) Negative
c) Mask
d) Virtual image
a) EPROM
b) PROM
a) 8 bits
b) 16 bits
c) 128 bits
d) 64 bits
advertisement
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
MSI/TTL based.
7. IC 74187 is of __________
a) 512 bits
b) 1024 bits
c) 256 bits
d) 68 bits
a) 128, 3
b) 128, 4
c) 256, 3
d) 256, 4
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
advertisement
a) 16
b) 32
c) 64
d) 8
a) TMS 45276
b) TMS 45278
c) TMS 45279
d) TMS 45275
13. TMS 45276 is of __________
a) 32 KB
b) 56 KB
c) 8 bits
d) 4 bytes
a) TMS 45276
b) IC 74188
c) IC 74187
d) IC 74185
organization.
a) Storing Capacity
b) Custom Select
c) Chip Select
d) Custom Storage
advertisement
c) Code conversion
b) Data hold
c) Read cycle time
d) Access time
advertisement

a) ROM
b) EPROM
c) PROM
d) EEPROM
a) 4096
b) 16384
c) 32768
d) 8129
advertisement
of eight bits?
a) Eight
b) Two
c) One
d) Four
c) Command code
advertisement
a) 8 locations
b) 256 locations
c) 65,536 locations
locations = 28.
a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
advertisement
a) 2
b) 3
c) 4
d) 5
a) Polycrystalline
c) Nichrome
d) Silicon dioxide

c) Nichrome
d) Silicon dioxide
advertisement
a) EPROM programmer
c) PROM programmer
d) ROM programmer
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
advertisement
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
rows and 8 columns.
7. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
a) 165,667
b) 245,784
c) 262,144
d) 212,342
a) 10
b) 11
c) 12
d) 13
advertisement
a) 1024
b) 4096
c) 2048
d) 8192
8192 bit.
advertisement
a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell

d) Memory mapping
user.
advertisement
a) 0
b) 1
c) Both 0 and 1
a) Reprogrammed
b) Restarted
c) Charged
d) Power off
c) It is volatile
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
advertisement
a) 1024
b) 512
c) 2516
d) 256
a) HIGH
b) LOW
a) Power is on
b) Power is off
c) System is down
this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Explanation: 8K = 8 * 1024 = 8192.
advertisement
b) Faulty
c) Probably good

advertisement
a) RAM
b) FPROM
c) EEPROM
d) ROM
a) RAM
b) ROM
c) PROM
d) EPROM
a) RWM
b) MBR
c) MAR
d) ROM
Read Write Memory).
advertisement
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
a) MBR
b) MAR
c) RAM
d) ROM
a) Data buffer
b) Chip select
c) Read and write
d) Memory
respectively.
a) High complexity
b) High resolution

d) High flexibility
advertisement
a) 2
b) 3
c) 4
d) 5
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
operation.
a) ROM
b) EROM
c) PROM
d) RAM
advertisement
a) 32 bit to 64 bit
advertisement

a) Activated
b) Deactivated
c) Unaffected
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
advertisement
6. IC 7489 is of ____________
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
a) Chip select
b) Enable
c) Data input
d) Memory enable
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
a) 1946
b) 1948
c) 1947
d) 1945
advertisement
a) SRAM
b) DRAM
c) EEPROM
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
locations.
a) 1024 * 4
b) 1024 * 8
c) 2048 * 4
d) 2048 * 8
locations.
advertisement
a) 10
b) 9
c) 12
d) 11
locations.
a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional

advertisement
a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
memories.
advertisement
a) Cache
b) Dynamic RAM
c) Static RAM
a) SRAM
b) DRAM
c) Magnetic memory
d) Main Memory
advertisement
d) Has higher speed
a) RAM and ROM
b) CPU and RAM
d) CPU and ROM

a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile
advertisement
a) 10240
b) 15289
c) 16384
d) 17654
bits.

a) 2114
b) 7489
c) 4116
d) 2776
advertisement

a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
a) 3
b) 2
c) 1
d) 4
a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM
advertisement
a) Scratch-pad
b) Buffer
c) Main memory
a) ROM
b) RAM
c) EROM
d) PROM
advertisement
a) ROM
b) RAM
c) EROM
d) PROM
operation.
__________
a) PROM
b) Main Memory
d) Mass memory
12. CD-ROM is a __________
a) Memory register
b) Magnetic memory
a) A bit
b) A record
c) An address
d) A byte
advertisement
a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM
advertisement
d) Data insertion
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
per word.
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2
advertisement
a) 1
b) 2
c) 3
d) 4
a) 4
b) 6
c) 8
d) 12
chips.
a) 2
b) 4
c) 6
d) 8

a single chip.
advertisement
a) Flip-flops
b) Gates
c) Registers
a) RAM
b) ROM
c) PLD
d) PLA
a) High reliability

advertisement
a) 2
b) 3
c) 4
d) 5

a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
advertisement
2. PAL refers to ____________
a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
4. PLA contains ____________
advertisement
a) PLA
b) PAL
c) CPLD
d) SLD
b) AND/OR arrays
(FPGAs).
a) SLD
b) SROM
c) EPROM
d) PLD
advertisement

AND plane
AND plane
advertisement
a) A line
b) A channel
c) A strobe
d) A flip-flop
a) Registered PALs
c) PAL programming

advertisement
a) Documentation
b) Verification

a) 2
b) 3
c) 4
d) 5
advertisement
c) Test the decoder
a) 1 Hz
b) 60 Hz
c) 100 Hz
d) 1000 Hz
advertisement
b) Freeze
advertisement
b) Decoder/display
c) Display register
d) Bit shifter
b) Types and bits

Answers – MultivibratorsThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Number System – 1”.
a) MSB
b) LSB
c) Byte
d) Nibble
advertisement
a) Bit
b) Byte
c) Word
d) Nibble
2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10
advertisement
a) (450)10
b) (451)10
c) (421)10
d) (501)10

(421)10.
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
a) 6 * 162 + 13 * 161 + 14 * 160

b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.
advertisement
a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits

» Next - Digital Circuits Questions and Answers – Number System – 2This set of Digital Electronics/Circuits Multiple
Choice Questions & Answers (MCQs) focuses on “Number System – 1”.
a) MSB
b) LSB
c) Byte
d) Nibble
advertisement
a) Bit
b) Byte
c) Word
d) Nibble
2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10
advertisement
a) (450)10
b) (451)10
c) (421)10
d) (501)10

(421)10.
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.
advertisement
a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
» Next - Digital Circuits Questions and Answers – Number System – 2This set of Digital Electronics/Circuits Multiple
Choice Questions & Answers (MCQs) focuses on “Number System – 2”.
1. The given hexadecimal number (1E.53)16 is equivalent to ____________
a) (35.684)8
b) (36.246)8
c) (34.340)8
d) (35.599)8
Explanation: First, the hexadecimal number is converted to it’s equivalent binary form, by writing the binary
equivalent of each digit in form of 4 bits. Then, the binary equivalent bits are grouped in terms of 3 bits and then for
each of the 3-bits, the respective digit is written. Thus, the octal equivalent is obtained.
(1E.53)16 = (0001 1110.0101 0011)2
= (00011110.01010011)2
= (011110.010100110)2
= (011 110.010 100 110)2
= (36.246)8.
advertisement
2. The octal number (651.124)8 is equivalent to ______
a) (1A9.2A)16
b) (1B0.10)16
c) (1A8.A3)16
d) (1B0.B0)16
Explanation: First, the octal number is converted to it’s equivalent binary form, by writing the binary equivalent of
each digit in form of 3 bits. Then, the binary equivalent bits are grouped in terms of 4 bits and then for each of the 4-
bits, the respective digit is written. Thus, the hexadecimal equivalent is obtained.
(651.124)8 = (110 101 001.001 010 100)2
= (110101001.001010100)2
= (0001 1010 1001.0010 1010)2
= (1A9.2A)16.
3. The octal equivalent of the decimal number (417)10 is _____
a) (641)8
b) (619)8
c) (640)8
d) (598)8
Explanation: Octal equivalent of decimal number is obtained by dividing the number by 8 and collecting the
remainders in reverse order.
8 | 417
8 | 52 — 1
8|6–4
So, (417)10 = (641)8.
4. Convert the hexadecimal number (1E2)16 to decimal.
a) 480
b) 483
c) 482
d) 484
(1E2)16 = 1 * 162 + 14 * 161 + 2 * 160 (Since, E = 14)

= 256 + 224 + 2 = (482)10.
5. (170)10 is equivalent to ____________
a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16
Explanation: Hexadecimal equivalent of decimal number is obtained by dividing the number by 16 and collecting the
remainders in reverse order.
16 | 170
16 | 10 – 10
Hence, (170)10 = (AA)16.
advertisement
6. Convert (214)8 into decimal.
a) (140)10
b) (141)10
c) (142)10
d) (130)10
(214)8 = 2 * 8v + 1 * 81 + 4 * 80
= 128 + 8 + 4 = (140)10.
7. Convert (0.345)10 into an octal number.
a) (0.16050)8
b) (0.26050)8
c) (0.19450)8
d) (0.24040)8
Explanation: Converting decimal fraction into octal number is achieved by multiplying the fraction part by 8
everytime and collecting the integer part of the result, unless the result is 1.
0.345*8 = 2.76 2
0.760*8 = 6.08 6
00.08*8 = 0.64 0
0.640*8 = 5.12 5
0.120*8 = 0.96 0
So, (0.345)10 = (0.26050)8.
8. Convert the binary number (01011.1011)2 into decimal.
a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10
(01011)2 = 0 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11
(1011)2 = 1 * 2-1 + 0 * 2-2 + 1 * 2-3 + 1 * 2-4 = 0.6875
So, (01011.1011)2 = (11.6875)10.
9. Octal to binary conversion: (24)8 =?
a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2
Explanation: Each digit of the octal number is expressed in terms of group of 3 bits. Thus, the binary equivalent of
the octal number is obtained.
(24)8 = (010100)2.
advertisement
10. Convert binary to octal: (110110001010)2 =?
a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8
Explanation: The binary equivalent is segregated into groups of 3 bits, starting from left. And then for each group,
the respective digit is written. Thus, the octal equivalent is obtained.
(110110001010)2 = (6612)8.
« Prev - Digital Circuits Questions and Answers – Number System – 1» Next - Digital Circuits Questions and
Answers – Arithmetic Operation This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs)
focuses on “Arithmetic Operation”
1. What is the addition of the binary numbers 11011011010 and 010100101?
a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011
Explanation: The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
advertisement
1
11011011010
+00010100101
_______________________
11101111111
_______________________
2. Perform binary addition: 101101 + 011011 = ?
a) 011010
b) 1010100
c) 101110
d) 1001000
Explanation:The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
111111
101101
+011011
_______________
1001000
_______________
Therefore, the addition of 101101 + 011011 = 1001000.
3. Perform binary subtraction: 101111 – 010101 = ?
a) 100100
b) 010101
c) 011010
d) 011001
Explanation: The rules for Binary Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
101111
-010101
____________
011010
_____________
Therefore, The subtraction of 101111 – 010101 = 011010.
advertisement
4. Binary subtraction of 100101 – 011110 is?
a) 000111
b) 111000
c) 010101
d) 101010
Explanation: The rules for Binary Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
100101
-011110
___________
000111
___________
Therefore, The subtraction of 100101 – 011110 = 000111.
5. Perform multiplication of the binary numbers: 01001 × 01011 = ?
a) 001100011
b) 110011100
c) 010100110
d) 101010111
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
01001
x01011
____________
01001
010010
0000000
01001000
000000000
___________________
001100011
___________________
Therefore, 01001 × 01011 = 001100011.
advertisement
6. 100101 × 0110 = ?
a) 1011001111
b) 0100110011
c) 101111110
d) 0110100101
0*0=0
0*1=0
1*0=0
1*1=1
100101
x 0110
___________
000000
1001010
10010100
000000000
__________________
011011110
___________________
Therefore, 100101 x 0110 = 011011110.
7. On multiplication of (10.10) and (01.01), we get ____________
a) 101.0010
b) 0010.101
c) 011.0010
d) 110.0011
0*0=0
0*1=0
1*0=0
1*1=1
1 0.1 0
x 0 1.0 1
__________
1010
00000
101000
0000000
_______________
0 1 1.0 0 1 0
_________________
Therefore, 10.10 x 01.01 = 011.0010.
8. Divide the binary numbers: 111101 ÷ 1001 and find the remainder.
a) 0010
b) 1010
c) 1100
d) 0111
Explanation: Binary Division is accomplished using long division method.
1001)111101(11
1001
__________
01100
1001
___________
0111
Therefore, the remainder of 111101 ÷ 1001 = 0111.
advertisement
9. Divide the binary number (011010000) by (0101) and find the quotient.
a) 100011
b) 101001
c) 110010
d) 010001
Explanation:
0101)011010000(010111
0000
_____________________
01101
00101
______________
010000
000000
______________________
10000
00101
____________________
010110
000101
____________________
100010
000101
________________________
111010
000101
________________________
10101
00101
________________________
10000
Therefore, the quotient of 011010000 ÷ 1001 = 101001.
10. Binary subtraction of 101101 – 001011 = ?
a) 100010
b) 010110
c) 110101
d) 101100
Explanation: The rules for binary subtraction are:
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
101101
-001011
____________
100010
____________
Therefore, the subtraction of 101101 – 001011 = 100010.

« Prev - Digital Circuits Questions and Answers – Number System – 2» Next - Digital Circuits Questions and
Answers – 1’s, 2’s, 9’s & 10’s Complements – 1This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “1’s, 2’s, 9’s & 10’s Complements – 1”.
1. 1’s complement of 1011101 is ____________
a) 0101110
b) 1001101
c) 0100010
d) 1100101
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the 1’s to 0’s and 0’s to
1’s.
advertisement
Thus, 1’s complement of 1011101 = 0100010.
2. 2’s complement of 11001011 is ____________
a) 01010111
b) 11010100
c) 00110101
d) 11100010
Explanation: 2’s complement of a binary number is obtained by finding the 1’s complement of the number and then
adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.
3. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a) 01001
b) 11010
c) 10101
d) 10100
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds the result.
111
Minuend - 11110
1’s complement of subtrahend - 10101
____________
Carry over - 1 10011
_____________
10100
a) 0111001
b) 1100101
c) 0110110
d) 1000011
-> If the result has a carry, then it is dropped and the result is positive.
_________________
111
Minuend - 1011001
_________________
Answer: 1000011
a) 1101100
b) 011101
c) 11010101
d) 11010111
advertisement
_________________
Minuend - 101001
_________________
Answer: 011101
6. On addition of 28 and 18 using 2’s complement, we get ____________
a) 00101110
b) 0101110
c) 00101111
d) 1001111
Explanation: Steps for Binary Addition Using 2’s complement:
-> The binary equivalent of the two numbers are obtained and added using the rules of binary addition.
advertisement
Augend - 0 011100
Addend - 0 010010
_________________
0 101110
Answer: 0 1 0 1 1 1 0
7. On addition of +38 and -20 using 2’s complement, we get ____________
a) 11110001
b) 100001110
c) 010010
d) 110101011
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the first number.
-> The result is the 2’s complement of the sum obtained.
Augend - 0100110
2’s Complement of Subtrahend: 1101100
_________________
1 0010010
Answer: 0 1 0 0 1 0
8. On addition of -46 and +28 using 2’s complement, we get ____________
a) -10010
b) -00101
c) 01011
d) 0100101
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary
addition is performed.
Augend is 28 and Subtrahend is -46.
Augend - 0 0 1 1 1 0 0 .....(a)
2’s Complement of Subtrahend: 1 0 1 0 0 1 0 .....(b)
_________________
Addiing (a) and (b): 1101110
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.

0010001
+ 1
_________________
0010010
Answer: - 1 0 0 1 0
9. On addition of -33 and -40 using 2’s complement, we get ____________
a) 1001110
b) -110101
c) 0110001
d) -1001001
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary
addition is performed.
Augend is -40 and Subtrahend is -33.
advertisement
Augend - 1 0 1 0 0 0 0 1 .....(a)
2’s Complement of Subtrahend: 1 1 0 1 1 0 0 1 .....(b)
______________________
Addiing (a) and (b): 10 1001000
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.

1001000
+ 1
_________________
1001001
Answer: -1001001
10. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
Minuend - 011101
____________________
Carry over - 1 0 0 0 0 0 1
Answer: 000001 = 1
« Prev - Digital Circuits Questions and Answers – Arithmetic Operation» Next - Digital Circuits Questions and
Answers – 1’s, 2’s, 9’s & 10’s Complements – 2This set of Digital Electronic Circuits Interview Questions and Answers
focuses on “1’s,2’s,9’s & 10’s Complements-2”.
1. If the number of bits in the sum exceeds the number of bits in each added numbers, it results in _________
a) Successor
b) Overflow
c) Underflow
d) Predecessor
Explanation: If the number of bits in the sum exceeds the number of bits in each added numbers, it results in
overflow and is also known as excess-one. In case of any arithmetic operation, if the result has less number of bits
than the operands, then it is known as underflow condition.
advertisement
2. An overflow is a _________
a) Hardware problem
b) Software problem
c) User input problem
d) Input Output Error
Explanation: An overflow is a software problem which occurs when the processor cannot handle the result properly
when it produces an out of the range output.
3. An overflow occurs in _________
a) MSD position
b) LSD position
c) Middle position
d) Signed Bit
Explanation: An overflow occurs at the Most Significant Digit position. It occurs when the processor cannot handle
the result properly when it produces an out of the range output.
4. Logic circuitry is used to detect _________
a) Underflow
b) MSD
c) Overflow
d) LSD
Explanation: To check the overflow logic circuitry is used in each case. Overflow occurs when the processor cannot
handle the result properly when it produces an out of the range output.
5. 1’s complement can be easily obtained by using _________
a) Comparator
b) Inverter
c) Adder
d) Subtractor
Explanation: With the help of inverter the 1’s complement is easily obtained. Since, during the operation of 1’s
complement 1 is converted into 0 and vice-versa and this is well suited for the inverter.
advertisement
6. The advantage of 2’s complement system is that _________
a) Only one arithmetic operation is required
b) Two arithmetic operations are required
c) No arithmetic operations are required
d) Different Arithmetic operations are required

Explanation: The advantage of 2’s complement is that only one arithmetic operation is required for 2’s
complement’s operation and that is only addition. Just by adding a 1 bit to 1’s complement, we get 2’s complement.
7. The 1’s complements requires _________
a) One operation
b) Two operations
c) Three operations
d) Combined Operations
Explanation: Only one operation is required for 1’s complement operation. This includes only inversion of 1’s to 0’s
and 0’s to 1’s.
8. Which one is used for logical manipulations?
a) 2’s complement
b) 9’s complement
c) 1’s complement
d) 10’s complement
Explanation: For logical manipulations, 1’s complement is used, as all logical operations take place with binary
numbers.
9. For arithmetic operations only _________
a) 1’s complement is used
b) 2’s complement
c) 10’s complement
d) 9’s complement
Explanation: Only 2’s complement is used for arithmetic operations, as it is more fast.
advertisement
10. The addition of +19 and +43 results as _________ in 2’s complement system.
a) 11001010
b) 101011010
c) 00101010
d) 0111110
Explanation: The decimal numbers are converted to their respective binary equivalent and then the binary addition
rules are applied.
To practice all areas of Digital Electronic Circuits for Interviews, here is complete set of 1000+ Multiple Choice
« Prev - Digital Circuits Questions and Answers – 1’s, 2’s, 9’s & 10’s Complements – 1» Next - Digital Circuits
Questions and Answers – Binary Coded Decimal(BCD)This set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Binary Coded Decimal(BCD)”.
1. Binary coded decimal is a combination of __________
a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits
Explanation: Binary coded decimal is a combination of 4 binary digits. For example-8421.
advertisement
2. The decimal number 10 is represented in its BCD form as __________
a) 10100000
b) 01010111
c) 00010000
d) 00101011
Explanation: The decimal number 10 is represented in its BCD form as 0001 0000, in accordance to 8421 for each of
the two digits.
3. Add the two BCD numbers: 1001 + 0100 = ?
a) 10101111
b) 01010000
c) 00010011
d) 00101011
Explanation: Firstly, Add the 1001 and 0100. We get 1101 as output but it’s not in BCD form. So, we add 0110 (i.e. 6)
with 1101. As a result we get 10011 and it’s BCD form is 0001 0011.
4. Carry out BCD subtraction for (68) – (61) using 10’s complement method.
a) 00000111
b) 01110000
c) 100000111
d) 011111000
Explanation: First the two numbers are converted into their respective BCD form using 8421 sequence. Then binary
subtraction is carried out.
5. Code is a symbolic representation of __________ information.
a) Continuous
b) Discrete
c) Analog
d) Both continuous and discrete
Explanation: Code is a symbolic representation of discrete information, which may be present in the form of
numbers, letters or physical quantities. Mostly, it is represented using a particular number system like decimal or
binary and such like.
advertisement
6. When numbers, letters or words are represented by a special group of symbols, this process is called
__________
a) Decoding
b) Encoding
c) Digitizing
d) Inverting
Explanation: When numbers, letters or words are represented by a special group of symbols, this process is called
encoding. Encoding in the sense of fetching the codes or words in a computer. It is done to secure the transmission
of information.
7. A three digit decimal number requires ________ for representation in the conventional BCD format.
a) 3 bits
b) 6 bits
c) 12 bits
d) 24 bits
Explanation: The number of bits needed to represent a given decimal number is always greater than the number of
bits required for a straight binary encoding of the same. Hence, a three digit decimal number requires 12 bits for
representation in BCD format.
8. How many bits would be required to encode decimal numbers 0 to 9999 in straight binary codes?
a) 12
b) 14
c) 16
d) 18
Explanation: Total number of decimals to be represented = 10000 = 104 = 2n (where n is the number of bits
required) = 213.29. Therefore, the number of bits required for straight binary encoding = 14.
9. The excess-3 code for 597 is given by __________
a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101
Explanation: The addition of ‘3’ to each digit yields the three new digits ‘8’, ’12’ and ’10’. Hence, the corresponding
four-bit binary equivalents are 100011001010, in accordance to 8421 format.
advertisement
10. The decimal equivalent of the excess-3 number 110010100011.01110101 is _____________
a) 970.42
b) 1253.75
c) 861.75
d) 1132.87
Explanation: The conversion of binary numbers into digits ‘1100’, ‘1010’, ‘0011’, ‘0111’ and ‘0101’ gives ’12’, ‘5’, ‘3’,
‘7’ and ‘5’ respectively. Hence, the decimal number is 970.42.
« Prev - Digital Circuits Questions and Answers – 1’s, 2’s, 9’s & 10’s Complements – 2» Next - Digital Circuits
Questions and Answers – Boolean Logic OperationsThis set of Digital Electronics/Circuits Multiple Choice Questions
& Answers (MCQs) focuses on “Boolean Logic Operations”.
1. In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C & A*(B*C) = (A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.
advertisement
2. The expression for Absorption law is given by _________
a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
Explanation: The expression for Absorption Law is given by: A+AB = A.
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per 1’s Property).
3. According to boolean law: A + 1 = ?
a) 1
b) A
c) 0
d) A’
Explanation: A + 1 = 1, as per 1’s Property.
4. The involution of A is equal to _________
a) A
b) A’
c) 1
d) 0
Explanation: The involution of A means double inversion of A (i.e. A”) and is equal to A.
Proof: ((A)’)’ = A
5. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
Explanation: A(A + B) = AA + AB (By Distributive Property) = A + AB (A.A = A By Commutative Property) = A(1 + B) =

A*1 (1 + B = 1 by 1’s Property) = A.
advertisement
6. DeMorgan’s theorem states that _________
a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.
7. (A + B)(A’ * B’) = ?
a) 1
b) 0
c) AB
d) AB’
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.
8. Complement of the expression A’B + CD’ is _________
a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By DeMorgan’s Theorem) = (A +
B’)(C’ + D).
9. Simplify Y = AB’ + (A’ + B)C.
a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C = (AB’ + C)( AB’ + AB’) = (AB’ + C).1 = (AB’ + C).
advertisement
10. The boolean function A + BC is a reduced form of ____________
a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC (By Commutative Property) = A(1 + C + B) + BC = A

+ BC (1 + B + C =1 By 1’s Property).

« Prev - Digital Circuits Questions and Answers – Binary Coded Decimal(BCD)» Next - Digital Circuits Questions and
Answers – Sum of Products and Products of SumThis set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Sum of Products and Products of Sum”.
1. The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation
Explanation: The logical sum of two or more logical product terms, is called SOP (i.e. sum of product). The logical
product of two or more logical sum terms is called POS (i.e. product of sums).
advertisement
2. The expression Y=AB+BC+AC shows the _________ operation.
a) EX-OR
b) SOP
c) POS
d) NOR
Explanation: The given expression has the operation product as well as the sum of that. So, it shows SOP operation.
POS will be the product of sum terms.
3. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.
a) AND
b) POS
c) SOP
d) NAND
Explanation: The given expression has the operation sum as well as the product of that. So, it shows POS(product of
sum) operation. SOP will be the sum of product terms.
4. A product term containing all K variables of the function in either complemented or uncomplemented form is
called a __________
a) Minterm
b) Maxterm
c) Midterm
d) ∑ term
Explanation: A product term containing all K variables of the function in either complemented or uncomplemented
form is called a minterm. A sum term containing all K variables of the function in either complemented or
uncomplemented form is called a maxterm.
5. According to the property of minterm, how many combination will have value equal to 1 for K input variables?
a) 0
b) 1
c) 2
d) 3
Explanation: The main property of a minterm is that it possesses the value 1 for only one combination of K input
variables and the remaining will have the value 0.
advertisement
6. The canonical sum of product form of the function y(A,B) = A + B is __________
a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’
Explanation: A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB + AB’ + A’B = AB + AB’ + A’B.
7. A variable on its own or in its complemented form is known as a __________
a) Product Term
b) Literal
c) Sum Term
d) Word
Explanation: A literal is a single logic variable or its complement. For example — X, Y, A’, Z, X’ etc.
8. Maxterm is the sum of __________ of the corresponding Minterm with its literal complemented.
a) Terms
b) Words
c) Numbers
d) Nibble
Explanation: Maxterm is the sum of terms of the corresponding Minterm with its literal complemented.
9. Canonical form is a unique way of representing ____________
a) SOP
b) Minterm
c) Boolean Expressions
d) POS
Explanation: Boolean Expressions are represented through a canonical form. An example of canonical form is A’B’C’
+ AB’C + ABC’.
advertisement
10. There are _____________ Minterms for 3 variables (a, b, c).
a) 0
b) 2
c) 8
d) 1
Explanation: Minterm is given by 2n. So, 23 = 8 minterms are required.
11. _____________ expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level
NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS
Explanation: SOP expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND
logic circuits.
advertisement
« Prev - Digital Circuits Questions and Answers – Boolean Logic Operations» Next - Digital Circuits Questions and
Answers – Karnaugh MapThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Karnaugh Map”.
1. A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a matrix of squares.
a) Venn Diagram
b) Cycle Diagram
c) Block diagram
d) Triangular Diagram
Explanation: A Karnaugh map (K-map) is an abstract form of Venn diagram organized as a matrix of squares, where
each square represents a Maxterm or a Minterm.
advertisement
2. There are ______ cells in a 4-variable K-map.
a) 12
b) 16
c) 18
d) 8
Explanation: There are 16 = (24) cells in a 4-variable K-map.
3. The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ = 1.
a) Impact
b) Non Impact
c) Force
d) Complementarity
Explanation: The given expression A +A’ = 1 is based on non-impact unifying theorem.
4. Each product term of a group, w’.x.y’ and w.y, represents the ____________ in that group.
a) Input
b) POS
c) Sum-of-Minterms
d) Sum of Maxterms
Explanation: In a minterm, each variable w, x or y appears once either as the variable itself or as the inverse. So, the
given expression satisfies the property of Sum of Minterm.
5. The prime implicant which has at least one element that is not present in any other implicant is known as
___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement
Explanation: Essential prime implicants are prime implicants that cover an output of the function that no
combination of other prime implicants is able to cover.
advertisement
6. Product-of-Sums expressions can be implemented using ___________
a) 2-level OR-AND logic circuits
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
d) Both 2-level OR-AND and NOR logic circuits
Explanation: Product-of-Sums expressions can be implemented using 2-level OR-AND & NOR logic circuits.
7. Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product term of the
given ___________
a) Function
b) Value
c) Set
d) Word
Explanation: Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product term
of the given function.
8. Don’t care conditions can be used for simplifying Boolean expressions in ___________
a) Registers
b) Terms
c) K-maps
d) Latches
Explanation: Don’t care conditions can be used for simplifying Boolean expressions in K-maps which helps in pairing
with 1/0.
9. It should be kept in mind that don’t care terms should be used along with the terms that are present in
___________
a) Minterms
b) Expressions
c) K-Map
d) Latches
Explanation: It should be kept in mind that don’t care terms should be used along with the terms that are present in
minterms as well as maxterms which reduces the complexity of the boolean expression.
advertisement
10. Using the transformation method you can realize any POS realization of OR-AND with only.
a) XOR
b) NAND
c) AND
d) NOR
Explanation: Using the transformation method we can realize any POS realization of OR-AND with only NOR.
11. There are many situations in logic design in which simplification of logic expression is possible in terms of XOR
and _________________ operations.
a) X-NOR
b) XOR
c) NOR
d) NAND
Explanation: There are many situations in logic design in which simplification of logic expression is possible in terms
of XOR and XNOR operations.
Expression of XOR : AB’ + A’B
Expression of XNOR : AB + A’B’
12. These logic gates are widely used in _______________ design and therefore are available in IC form.
a) Sampling
b) Digital
c) Analog
d) Systems
Explanation: These logic gates(XOR, XNOR, NOR) are widely used in digital design and therefore are available in IC
form as digital circuits deal with data transmission in the form of binary digits.
13. In case of XOR/XNOR simplification we have to look for the following _______________
a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies
Explanation: In case of XOR/XNOR simplification we have to look for the following diagonal and offset adjacencies.
XOR gives output 1 when odd number of 1s are present in input while XNOR gives output 1 when even number of 1s
or all 0s are present in input.
advertisement
14. Entries known as _______________ mapping.
a) Diagonal
b) Straight
c) K
d) Boolean
Explanation: Entries known as diagonal mapping. The diagonal mapping holds true when for any relation, there is a
projection of product on the factor.

« Prev - Digital Circuits Questions and Answers – Sum of Products and Products of Sum» Next - Digital Circuits
Questions and Answers – Quine McCluskey or Tabular Method of Minimization of Logic FunctionsThis set of Digital
Electronic Circuits Questions and Answers for freshers focuses on “Quine-McCluskey or Tabular Method of
Minimization of Logic Functions”.
1. The output of an EX-NOR gate is 1. Which input combination is correct?
a) A = 1, B = 0
b) A = 0, B = 1
c) A = 0, B = 0
d) A = 0, B’ = 1
Explanation: The output of EX-NOR gate is given by AB + A’B’. So, for A = 0 and B = 0 the output will be 1.
advertisement
2. In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND
b) NOR
c) NAND
d) OR
Explanation: In or gate we need at least one bit to be equal to 1 to generate the output as 1 because OR means any
of the condition out of two is equal to 1 which means if at least one input is 1 then it shows output as 1.
3. The time required for a gate or inverter to change its state is called __________
a) Rise time
b) Decay time
c) Propagation time
d) Charging time
Explanation: The time required for a gate or inverter to change its state is called propagation time.
4. What is the minimum number of two input NAND gates used to perform the function of two input OR gates?
a) One
b) Two
c) Three
d) Four
Explanation: Y = A + B. This is the equation of OR gate. We require 3 NAND gates to create OR gate. We can also
write,
1st, 2nd and 3rd NAND operations as: Y = ((NOT A) AND (NOT B))’ = A’’ + B’’ = (A+B).
5. Odd parity of word can be conveniently tested by ___________
a) OR gate
b) AND gate
c) NAND gate
d) XOR gate
Explanation: Odd parity of word can be conveniently tested by XOR gate, since, XOR outputs 1 only when the input
has odd number of 1’s.
advertisement
6. The number of full and half adders are required to add 16-bit number is __________
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders
Explanation: Half adder has two inputs and two outputs whereas Full Adder has 3 inputs and 2 outputs. One half
adder can add the least significant bit of the two numbers whereas full adders are required to add the remaining 15
bits as they all involve adding carries.
7. Which of the following will give the sum of full adders as output?
a) Three point major circuit
b) Three bit parity checker
c) Three bit comparator

d) Three bit counter
Explanation: Counters are used for counting purposes in ascending or descending order. Three bit counter will give
the sum of full adders as output.
8. Which of the following gate is known as coincidence detector?
a) AND gate
b) OR gate
c) NOR gate
d) NAND gate
Explanation: AND gate is known as coincidence detector due to multiplicity behaviour, as it outputs 1 only when all
the inputs are 1.
9. An OR gate can be imagined as ____________
a) Switches connected in series
b) Switches connected in parallel
c) MOS transistor connected in series
d) BJT transistor connected in series
Explanation: OR gate means addition of two inputs, which outputs when any of the input is high. Due to this reason,
it is imagined as switches connected in parallel.
advertisement
10. How many full adders are required to construct an m-bit parallel adder?
a) m/2
b) m
c) m-1
d) m+1
Explanation: We need adder for every bit. So we should need m bit adders. A full adder adds a carry bit to two inputs
and produces an output and a carry. But the most significant bits can use a half adder which differs from the full
adder as in that it has no carry input, so we need m-1 full adders and 1 half adder in m bit parallel adder.
To practice all areas of Digital Electronic Circuits for Freshers, here is complete set of 1000+ Multiple Choice
« Prev - Digital Circuits Questions and Answers – Karnaugh Map» Next - Digital Circuits Questions and Answers –
Logic Gates and Networks – 1This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs)
focuses on “Logic Gates and Networks – 1”.
1. The output of a logic gate is 1 when all the input are at logic 0 as shown below:
INPUT
OUTPUT
0
1
INPUT
OUTPUT
1
0
advertisement
The gate is either _________
a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR. The output of a logic gate
is 1 when all inputs are at logic 0 or all inputs are at logic 1, then it is EX-NOR. (The truth tables for NOR and EX-NOR
Gates are shown in the above table).
2. The code where all successive numbers differ from their preceding number by single bit is __________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Explanation: The code where all successive numbers differ from their preceding number by single bit is gray code. It
is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when
going from one code number to next. BCD Code is one in which decimal digits are represented by a group of 4-bits
each, whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then written in their BCD format.
3. The following switching functions are to be implemented using a decoder:

f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.
4. How many AND gates are required to realize Y = CD + EF + G?
a) 4
b) 5
c) 3
d) 2
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.
advertisement
5. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.
6. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.
7. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal
logic gate?
a) OR
b) AND
c) XOR
d) NAND
Explanation: An Universal Logic Gate is one which can generate any logic function and also the three basic gates:
AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus Universal Logic Gates.
8. A full adder logic circuit will have __________
a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous
stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder circuit, there are only two
inputs bits and two outputs (SUM and CARRY).
advertisement
9. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
Explanation: There are three product terms. So, three AND gates of two inputs are required. As only two input OR
gates are available, so two OR gates are required to get the logical sum of three product terms.
10. Which of the following are known as universal gates?

a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit can be realized
completely by using either of these two gates, and also they can generate the 3 basic gates AND, OR and NOT.
11. The gates required to build a half adder are __________
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the SUM of the
two input bits whereas AND outputs the CARRY of the two input bits.
advertisement
Answers.

« Prev - Digital Circuits Questions and Answers – Quine McCluskey or Tabular Method of Minimization of Logic
Functions» Next - Digital Circuits Questions and Answers – Logic Gates and Networks – 2This set of Digital Electronic
Circuits Interview Questions and Answers for freshers focuses on “Logic Gates and Networks-2”.
1. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
Explanation: A transistor can be used as a switch. That is when base is low collector is high (input zero, output one)
and base is high collector is low (input 1, output 0).
advertisement
2. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16
Explanation: For 4 inputs: 24 = 16 truth table entries are necessary.
3. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
d) All inputs are LOW
Explanation: For AND gate, the output is high only when both inputs are high. That’s why the high output in AND will
occurs only when all the inputs are high. However, in case of OR gate, if atleast one input is high, the output will be
high.
4. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
Explanation: Expression for XOR is: A.(B’)+(A’).B
So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required for constructing a XOR gate.
5. The basic logic gate whose output is the complement of the input is the ___________
a) OR gate
b) AND gate
c) INVERTER gate
d) XOR gate
Explanation: It is also called NOT gate and it simply inverts the input, such that 1 becomes 0 and 0 becomes 1.
advertisement
6. The AND function can be used to ___________ and the OR function can be used to _____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
Explanation: The AND gate and OR gate are used for enabling and disabling respectively because of their multiplicity
and additivity property. The AND gate outputs 1 when all inputs are at logic 1, whereas the OR gate outputs 0 when
all inputs are at logic 0.
7. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
Explanation: The dependency notation “>=1” inside a block stands for OR operation.
8. If we use an AND gate to inhibit a signal from passing one of the inputs must be ___________
a) LOW
b) HIGH
c) Inverted
d) Floating
Explanation: AND gate means A*B and OR gate means A+B and to inhibit means to get low signal, one of the input
must be low. It means (0*1=0 or 1*0=0) we will get low output signal. Thus, AND gate outputs 1 only when all inputs
are at logic level 1 else it outputs 0.
9. Logic gate circuits contain predictable gate functions that open theirs ____________
a) Outputs
b) Inputs
c) Pre-state
d) Impedance state
Explanation: Logic gate circuits contain predictable gate functions that open their inputs because we are free to give
any types of inputs.
advertisement
10. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8
Explanation: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc and remaining pins used
for connections. For a NAND gate two inputs are required and one output is obtained means for NAND gate 3 pin
connections are required. Thus, a 7400IC contains 4 NAND gates with each having 3 pins. Therefore, total 12 pins
dedicated for the NAND operation. Rest 2 pins for power supply.

To practice all areas of Digital Electronic Circuits for interviews, here is complete set of 1000+ Multiple Choice
« Prev - Digital Circuits Questions and Answers – Logic Gates and Networks – 1» Next - Digital Circuits Questions
and Answers – Digital Integrated Circuits – 1This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Digital Integrated Circuits – 1”.
1. Which of the following logic families has the highest maximum clock frequency?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS
Explanation: AS-TTL (Advanced Schottky) has a maximum clock frequency of 105 MHz. S-TTL (Schottky High Speed
TTL) has 100 MHz. Found nothing as HS-TTL. There are H and S separate TTL. HCMOS has 50 MHz clock frequency.
advertisement
2. Why is the fan-out of CMOS gates frequency dependent?
a) Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be
connected to the output of a CMOS gate
b) When the frequency reaches the critical value the gate will only be capable of delivering 70% of the normal output
voltage and consequently the output power will be one-half of normal and this defines the upper operating
frequency
c) The higher number of gates attached to the output the more frequently they will have to be serviced thus
reducing the frequency at which each will be serviced with an input signal
d) The input gates of the FETs are predominantly capacitive and as the signal frequency increases the capacitive
loading also increases thereby limiting the number of loads that may be attached to the output of the driving gate
Explanation: Fan out is the measure of maximum number of inputs that a single logic gate output can drive. Actually
power dissipation in CMOS circuits depends on clock frequency. As the frequency increases Pd also increases so fan-
out depends on frequency.
3. Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to have _______________
a) A greater current/voltage capability than an ordinary logic circuit
b) Greater input current/voltage capability than an ordinary logic circuit
c) A smaller output current/voltage capability than an ordinary logic
d) Greater the input and output current/voltage capability than an ordinary logic circuit
Explanation: Buffer circuits are usually incorporated to isolate the input from the output. Logic circuits that are
designated as buffers, drivers or buffer/drivers are designed to have a greater current/voltage capability than an
ordinary logic circuit.
4. Which of the following will not normally be found on a data sheet?
a) Minimum HIGH level output voltage
b) Maximum LOW level output voltage
c) Minimum LOW level output voltage
d) Maximum HIGH level input current
Explanation: Minimum LOW level output voltage will not normally be found on a data sheet.
5. Which of the following logic families has the shortest propagation delay?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS
Explanation: AS-TTL (Advanced Schottky) has a maximum clock frequency that is 105 MHz. So, the propagation delay
will be given by 1/105 sec which is the lowest one. It is followed by S-TTL and HCMOS in terms of increasing
propagation delay.
advertisement
6. What is the static charge that can be stored by your body as you walk across a carpet?
a) 300 volts
b) 3000 volts
c) 30000 volts
d) Over 30000 volts
Explanation: When a person walks across a carpeted or tile floor electric charge builds up in the body due to the
friction between shoes and floor material. If the friction static is greater the voltage potential develop in the body
will be greater. You start act as a capacitor. This is called Electrostatic discharge. The potential static charge that can
develop from walking on tile floors is greater than 15000 volts while carpeted floors can generate in excess of 30000
volts.
7. What must be done to interface TTL to CMOS?
a) A dropping resistor must be used on the CMOS of 12 V supply to reduce it to 5 V for the TTL
b) As long as the CMOS supply voltage is 5 V they can be interfaced (however, the fan-out of the TTL is limited to five
CMOS gates)
c) A 5 V zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher
output voltages of the CMOS gates
d) A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP will depend on
the number of CMOS gates connected to the node
Explanation: To interface TTL to CMOS a pull-up resistor must be used between the TTL output-CMOS input node
and Vcc. A pull-up resistor is used to avoid the floating state on the input node of the CMOS, thus using a small
amount of current. The value of RP will depend on the number of CMOS gates connected to the node.
8. What causes low-power Schottky TTL to use less power than the 74XX series TTL?
a) The Schottky-clamped transistor
b) A larger value resistor
c) The Schottky-clamped MOSFET
d) A small value resistor
Explanation: A larger value resistor causes low power low-power Schottky TTL to use less power than the 74XX series
TTL.
9. What are the major differences between the 5400 and 7400 series of ICs?
a) The 5400 series are military grade and require tighter supply voltages and temperatures
b) The 5400 series are military grade and allow for a wider range of supply voltages and temperatures
c) The 7400 series are an improvement over the original 5400s
d) The 7400 series was originally developed by Texas Instruments and the 5400 series was brought out by National
Semiconductors after TI’s patents expired as a second supply source
Explanation: The 5400 series are military grade and allow for a wider range of supply voltages and temperatures,
these are the major differences between the 5400 and 7400 series of ICs. Also, the working temperature range of
5400 series is -50 to 125C while that for 7400 is 0 to 70C.
advertisement
10. Which of the following statements apply to CMOS devices?
a) The devices should not be inserted into circuits with the power on
b) All tools, test equipment and metal workbenches should be tied to earth ground
c) The devices should be stored and shipped in antistatic tubes or conductive foam
Explanation: For CMOS devices, all the mentioned statements are applicable. The devices should not be inserted into
circuits with the power on. All tools, test equipment and metal workbenches should be tied to earth ground. Also,
the devices should be stored and shipped in antistatic tubes or conductive foam.
« Prev - Digital Circuits Questions and Answers – Logic Gates and Networks – 2» Next - Digital Circuits Questions
and Answers – Digital Integrated Circuits – 2This set of Digital Electronic/Circuits Questions and Answers for
experienced focuses on “Digital Integrated Circuits-2”.
1. SSI refers to ___________
a) Small Scale Integration

b) Short Scale Integration
c) Small Set Integration
d) Short Set Integration
Explanation: SSI refers to Small Scale Integration.
advertisement
2. Small Scale Integration(SSI) refers to ICs with __________ gates on the same chip.
a) Fewer than 10
b) Greater than 10
c) Equal to 10
d) Greater than 50
Explanation: Small Scale Integration(SSI) refers to ICs with fewer than 10 gates on the same chip.
3. MSI means ___________
a) Merged Scale Integration
b) Main Scale Integration
c) Medium Scale Integration
d) Main Set Integration
Explanation: MSI means Medium Scale Integration.
4. MSI includes _______ gates per chip.
a) 12 to 100
b) 13 to 50
c) greater than 10
d) greater than 100
Explanation: Medium Scale Integration includes 12 to 100 gates per chip.
5. LSI means ________ and refers to ________ gates per chip.

a) Long Scale Integration, more than 10 upto 10000
b) Large Scale Integration, more than 100 upto 5000
c) Large Short Integration, less than 10 and greater than 5000
d) Long Short Integration, more than 10 upto 10000
Explanation: The full form of LSI is Large Scale Integration and refers to more than 100 upto 5000 gates per chip.
6. Integrated circuits are classified as ___________
a) Large, Small and Medium
b) Very Large, Small and Linear
c) Linear and Digital
d) Non-Linear and Digital
Explanation: Integrated circuits are classified as Linear and Digital. Linear operates with continuous and digital refers
to discrete signals.
advertisement
7. According to the IC fabrication process logic families can be divided into two broad categories as
___________
a) RTL and TTL
b) HTL and MOS
c) ECL and DTL
d) Bipolar and MOS
Explanation: According to the IC fabrication process logic families can be divided into two broad categories as:
Bipolar and Metal-oxide semiconductor. The mentioned all others are part of bipolar. Bipolar IC fabrication refers to
TTL logic where MOS refers to CMOS logic.
8. The full form of DIP is ___________
a) Dual-in-Long Package
b) Dual-in-Line Package
c) Double Integrated Package
d) Double-in-Line Package
Explanation: The full form of DIP is Dual-in-Line Package.

9. LCC refers to ___________
a) Longest Chip Carrier
b) Leadless Chip Carrier
c) Leaded Chip Carrier
d) Large Chip Carrier
Explanation: LCC refers to Leadless Chip Carrier.
advertisement
10. PGA refers to ____________
a) Plastic Grid Array
b) Pin Grid Array
c) Pin Greater Array
d) Plastic Greater Array
Explanation: PGA refers to Pin Grid Array.
To practice all areas of Digital Electronic Circuits for Experienced, here is complete set of 1000+ Multiple Choice

« Prev - Digital Circuits Questions and Answers – Digital Integrated Circuits – 1» Next - Digital Circuits Questions
and Answers – Digital Integrated Circuits – 3This set of Digital Electronic/Circuits Interview Questions and Answers
for experienced focuses on “Digital Integrated Circuits – 3”.
1. MOS families includes __________
a) PMOS and NMOS
b) CMOS and NMOS
c) PMOS, NMOS and CMOS
d) EMOS, NMOS and PMOS
Explanation: Metal Oxide Semiconductor families includes PMOS, NMOS and CMOS.
advertisement
2. CMOS refers to __________
a) Continuous Metal Oxide Semiconductor
b) Complementary Metal Oxide Semiconductor
c) Centred Metal Oxide Semiconductor
d) Concrete Metal Oxide Semiconductor
Explanation: CMOS refers to Complementary Metal Oxide Semiconductor.
3. Propagation delay is defined as __________
a) the time taken for the output of a gate to change after the inputs have changed
b) the time taken for the input of a gate to change after the outputs have changed
c) the time taken for the input of a gate to change after the intermediates have changed
d) the time taken for the output of a gate to change after the intermediates have changed
Explanation: Propagation delay is defined as the time taken for the output of a gate to change after the inputs have
changed.
4. Propagation delay times can be divided as __________
a) t(PLH) and t(LPH)
b) t(LPH) and t(PHL)

c) t(PLH) and t(PHL)
d) t(HPL) and t(LPH)
Explanation: Propagation delay times can be divided as: t(PLH) and t(PHL). t(PLH) stands for propagation from low to
high and t(PHL) stands for propagation from high to low.
5. The delay times are measured between the __________ % voltage levels of the input and output waveforms.
a) 50
b) 75
c) 25
d) 100
Explanation: Propagation delay is the time taken by the output to change it’s state when the input changes. The
average of the two propagation delays is given by (t1 + t2)/2, which gives the intermediate value. So, the delay times
are measured between the 50% voltage levels of the input and output waveforms.
advertisement
6. Power Dissipation in DIC is expressed in __________
a) Watts or kilowatts
b) Milliwatts or nanowatts
c) DB
d) Mdb
Explanation: Power Dissipation in DIC is expressed in milliwatts or nanowatts.
7. Fan-in is defined as __________
a) the number of outputs connected to gate without any degradation in the voltage levels
b) the number of inputs connected to gate without any degradation in the voltage levels
c) the number of outputs connected to gate with degradation in the voltage levels
d) the number of inputs connected to gate with degradation in the voltage levels
Explanation: Fan-in is defined as the maximum number of inputs that can be connected to the output of a gate
without any degradation in the voltage levels. For example, an eight-input gate requires one Unit Load per input. It’s
fan-in is 8.
8. The maximum noise voltage that may appear at the input of a logic gate without changing the logical state of its
output is termed as __________
a) Noise Margin
b) Noise Immunity
c) White Noise
d) Signal to Noise Ratio
Explanation: The maximum noise voltage that may appear at the input of a logic gate without changing the logical
state of its output is termed as noise immunity.
9. Depending upon the flow of current from the output of one logic circuit to the input of another the logic families
can be divides into _________ categories.
a) 2
b) 3
c) 4
d) 5
Explanation: Depending upon the flow of current from the output of one logic circuit to the input of another the
logic families can be divides into two categories and they are current sourcing and current sinking. Source means
from where the current originates or exits while Sink means where the current enters or is accepted.
advertisement
10. Fan-in and Fan-out are the characteristics of ___________
a) Registers
b) Logic families
c) Sequential Circuits
d) Combinational Circuits
Explanation: Fan-in and Fan-out are the characteristics of logic families. Fan-in is the measure of maximum number
of inputs that a single gate output can drive or accept. Whereas, Fan-out means the maximum number of inputs that
can be fed by a single output.

To practice all areas of Digital Electronic Circuits for experienced, here is complete set of 1000+ Multiple Choice
and Answers – Register-Transistor Logic(RTL)This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Register-Transistor Logic(RTL)”.
1. All input of NOR as low produces result as __________
a) Low
b) Mid
c) High
d) Floating
Explanation: All input of NOR as low produces the result as high, whereas, rest all conditions produce output as low.
advertisement
2. In RTL NOR gate, the output is at logic 1 only when all the inputs are at __________
a) logic 0
b) logic 1
c) +10V
d) Floating
Explanation: RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only when all the inputs are at
logic 0 and in rest conditions of the input, the output is 0.
3. Resistor–transistor logic (RTL) is a class of digital circuits built using _______ as the input network and _______ as
switching devices.
a) Resistors, bipolar junction transistors (BJTs)
b) Bipolar junction transistors (BJTs), Resistors
c) Capacitors, resistors
d) Resistors, capacitors
Explanation: Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as the input network and
bipolar junction transistors (BJTs) as switching devices.
4. RTL consists of a common emitter stage with a _______ connected between the base and the input voltage
source.
a) collector
b) base resistor
c) capacitor
d) inductor
Explanation: RTL consist of a common emitter stage with a base resistor connected between the base and the input
voltage source. The role of base resistor is to expand the negligible transistor input voltage range (about 0.7 V) to the
logical “1” level (about 3.5 V) by converting the input voltage into a current. Thus, base resistor plays a major role in
biasing of the transistor.
5. The role of the _______ is to convert the collector current into a voltage in RTL.
a) Collector resistor
b) Base resistor
c) Capacitor
d) Inductor
Explanation: The role of the collector resistor is to convert the collector current into a voltage; its resistance is
chosen high enough to saturate the transistor and low enough to obtain low output resistance. Base Resistor is to
provide the necessary biasing to the base of the transistor in order to activate it.
advertisement
6. The limitations of the one transistor RTL NOR gate are overcome by __________
a) Two-transistor RTL implementation
b) Three-transistor RTL implementation
c) Multi-transistor RTL implementation
d) Four-transistor RTL implementation
Explanation: The limitations of the one transistor RTL NOR gate are overcome by the use of multi transistor RTL. It
consists of a set of parallel connected transistor switches driven by the logic inputs.
7. The primary advantage of RTL technology was that __________
a) It results as low power dissipation
b) It uses a minimum number of resistors
c) It uses a minimum number of transistors
d) It operates swiftly
Explanation: The primary advantage of RTL technology was that it uses a minimum number of transistors. It consists
of registers in large amount and it results in as high power dissipation. The resistors act as the input network and the
transistors performs the switching operation.
8. The disadvantage of RTL is that __________
a) It uses a maximum number of resistors
b) It results in high power dissipation
c) High noise creation
d) It uses a minimum number of transistors
Explanation: The disadvantage of RTL is its high power dissipation when the transistor is switched on by current
flowing in the collector and base resistor. This requires that more current be supplied to and heat be removed from
RTL circuits. In contrast, TTL circuits with “totem-pole” output stage minimize both of these requirements.
9. TTL circuits with “totem-pole” output stage minimize __________
a) The power dissipation in RTL
b) The time consumption in RTL
c) The speed of transferring rate in RTL
d) Propagation delay in RTL
Explanation: TTL circuits with “totem-pole” output stage minimize the power dissipation and heating effect in RTL.
advertisement
10. The minimum number of transistors can be used by 2 input AND gate is __________
a) 2
b) 3
c) 4
d) 5
Explanation: The minimum number of transistors can be used by 2 input AND gate is 2 and maximum up to 3.
and Answers – Diode-Transistor Logic(DTL)his set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Diode-Transistor Logic(DTL)”.
1. Diode–transistor logic (DTL) is the direct ancestor of _____________
a) Register-transistor logic
b) Transistor–transistor logic
c) High threshold logic
d) Emitter Coupled Logic
Explanation: Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor–transistor
logic. To overcome the shortcomings of DTL, TTL came into existence.
advertisement
2. In DTL logic gating function is performed by ___________
a) Diode
b) Transistor
c) Inductor
d) Capacitor
Explanation: Diode serves as the input network and the switching operation is performed by the transistor.
3. In DTL amplifying function is performed by ___________
a) Diode
b) Transistor
c) Inductor
d) Capacitor
Explanation: The amplifying and switching function is performed by a transistor and the diode acts an input network
in DTL.
4. How many stages a DTL consist of?
a) 2
b) 3
c) 4
d) 5
Explanation: The DTL circuit shown in the picture consists of three stages: an input diode logic stage, an intermediate
level shifting stage and an output common-emitter amplifier stage.
5. The full form of CTDL is ___________
a) Complemented transistor diode logic
b) Complemented transistor direct logic
c) Complementary transistor diode logic
d) Complementary transistor direct logic
Explanation: The full form of CTDL is Complemented transistor diode logic.

advertisement
6. The DTL propagation delay is relatively ___________
a) Large
b) Small
c) Moderate
d) Negligible
Explanation: Propagation delay refers to the time taken by the output to change it’s state when the input is altered.
When the transistor goes into saturation from all inputs being high charge is stored in the base region. When it
comes out of saturation (one input goes low) this charge has to be removed and will dominate the propagation time
which results as a large propagation delay. Thus, it has small clock frequency.
7. The way to speed up DTL is to add an across intermediate resister is ___________
a) Small “speed-up” capacitor
b) Large “speed-up” capacitor
c) Small “speed-up” transistor
d) Large ” speed-up” transistor
Explanation: One way to speed up DTL is to add a small “speed-up” capacitor across intermediate resister. The
capacitor helps to turn off the transistor by removing the stored base charge; the capacitor also helps to turn on the
transistor by increasing the initial base drive.
8. The process to avoid saturating the switching transistor is performed by ___________
a) Baker clamp
b) James R. Biard
c) Chris Brown
d) Totem-Pole
Explanation: Another way to speed up DTL other than adding a small “speed-up” capacitor across intermediate
resister is to avoid saturating the switching transistor which can be done with a Baker clamp. The name Baker clamp
is given at the name of Richard H. Baker, who described it in his 1956 technical report “Maximum Efficiency
Switching Circuits”.
9. A major advantage of DTL over the earlier resistor–transistor logic is the ___________
a) Increased fan out
b) Increased fan in
c) Decreased fan out

d) Decreased fan in
Explanation: A major advantage over the earlier resistor–transistor logic is the increased fan in. Fan-in is the measure
of the maximum number of inputs that a single gate output can accept.
advertisement
10. To increase fan-out of the gate in DTL ___________
a) An additional capacitor may be used
b) An additional resister may be used
c) An additional transistor and diode may be used
d) Only an additional diode may be used
Explanation: To increase fan-out of the gate in DTL, an additional transistor and diode may be used. Here, the fan out
means the number of maximum input that a single gate output can feed.
11. A disadvantage of DTL is ___________
a) The input transistor to the resister
b) The input resister to the transistor
c) The increased fan-in
d) The increased fan-out
Explanation: A disadvantage of DTL is the input resistor to the transistor and its presence tends to slow the circuit
down. Hence limiting the speed at which the transistor is able to switch states. Thus, the propagation delay
increases.
advertisement
« Prev - Digital Circuits Questions and Answers – Register-Transistor Logic(RTL)» Next - Digital Circuits Questions
and Answers – Transistor Transistor Logic(TTL)This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Digital Circuits Questions and Answers – Transistor Transistor Logic(TTL or T2L)”.
1. Transistor–transistor logic (TTL) is a class of digital circuits built from ____________
a) JFET only
b) Bipolar junction transistors (BJT)
c) Resistors
d) Bipolar junction transistors (BJT) and resistors
Explanation: Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT)
and resistors. However, resistors have a small role to play and both logic gating and amplifying functions are
performed by the transistors.
advertisement
2. TTL is called transistor–transistor logic because both the logic gating function and the amplifying function
are performed by ____________
a) Resistors
b) Bipolar junction transistors
c) One transistor
d) Resistors and transistors respectively

Explanation: TTL is called transistor–transistor logic because both the logic gating function and the amplifying
function are performed by bipolar junction transistors (BJTs).
3. TTL was invented in 1961 by ____________
a) Baker clamp
b) James L. Buie
c) Chris Brown
d) Frank Wanlass
Explanation: TTL was invented in 1961 by James L Buie.
4. The full form of TCTL is ____________
a) Transistor-coupled transistor logic
b) Transistor-capacitor transistor logic
c) Transistor-complemented transistor logic
d) Transistor-complementary transistor logic
Explanation: The full form of TCTL is transistor-coupled transistor logic.
5. The _______ ancestor to the first personal computers.
a) PARAM 1
b) SATYAM 1
c) KENBAK 1
d) MITS Altair
Explanation: The KENBAK 1, ancestor to the first personal computers.
advertisement
6. TTL inputs are the emitters of a ____________
a) Transistor-transistor logic
b) Multiple-emitter transistor
c) Resistor-transistor logic
d) Diode-transistor logic
Explanation: TTL inputs are the emitters of a multiple-emitter transistor.
7. TTL is a ____________
a) Current sinking
b) Current sourcing
c) Voltage sinking
d) Voltage sourcing
Explanation: Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring them to a
logic 0 level. Current Sink means it accepts current coming out from a source.
8. Standard TTL circuits operate with a __ volt power supply.
a) 2
b) 4
c) 5
d) 3
Explanation: Standard TTL circuits operate with a 5-volt power supply.
9. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
a) Less
b) More
c) Equal
d) Very High
Explanation: TTL devices consume substantially more power than equivalent CMOS devices at rest. Thus, CMOS
devices are faster than TTL devices.
advertisement
10. A TTL gate may operate inadvertently as an ____________
a) Digital amplifier
b) Analog amplifier
c) Inverter
d) Regulator
Explanation: A TTL gate may operate inadvertently as an analog amplifier if the input is connected to a slowly
changing input signal that traverses the unspecified region from 0.7V to 3.3V.
11. The speed of ______ circuits is limited by the tendency of common emitter circuits to go into saturation.
a) TTL
b) ECL
c) RTL
d) DTL
Explanation: The speed of TTL circuits is limited by the tendency of common emitter circuits to go into saturation
due to the injection of minority carriers into the collector region. Hence, it functions slowly compared to CMOS
devices.
advertisement
« Prev - Digital Circuits Questions and Answers – Diode-Transistor Logic(DTL)» Next - Digital Circuits Questions and
Answers – Emitter-Coupled Logic(ECL)This set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Emitter-Coupled Logic(ECL)”.
1. The full form of ECL is __________
a) Emitter-collector logic
b) Emitter-complementary logic
c) Emitter-coupled logic
d) Emitter-cored logic
Explanation: The full form of ECL is emitter-coupled logic.
advertisement
2. Which logic is the fastest of all the logic families?
a) TTL
b) ECL
c) HTL
d) DTL
Explanation: ECL is the fastest of all the logic families because of the emitters of many transistors are coupled
together which results in the highest transmission rate.
3. The full form of CML is __________
a) Complementary mode logic
b) Current mode logic
c) Collector mode logic
d) Collector Mixed Logic
Explanation: The full form of CML is Collector Mode Logic.
4. Sometimes ECL can also be named as __________
a) EEL
b) CEL
c) CML
d) CCL
Explanation: ECL (Emitter Coupled Logic) can also be named as CML(Collector Mode Logic).
5. In an ECL the output is taken from __________
a) Emitter
b) Base
c) Collector
d) Junction of emitter and base
Explanation: Though, the emitter and collector of the ECL are coupled together. So, the output will be taken from a
collector.
advertisement
6. The ECL behaves as __________
a) NOT gate
b) NOR gate
c) NAND gate
d) AND gate
Explanation: The ECL behaves as NOR gate because if any of the input voltages go high as compared to the reference
voltage, the output is low and the output is high only when all the input voltages are low.
7. In ECL the fanout capability is __________
a) High
b) Low
c) Zero
d) Sometimes high and sometimes low
Explanation: If the input impedance is high and the output resistance is low; as a result, the transistors change states
quickly, gate delays are low, and the fanout capability is high. Fan-out is the measure of the maximum number of
inputs that a single gate output can accept.
8. ECL’s major disadvantage is that __________
a) It requires more power
b) It’s fanout capability is high
c) It creates more noise

d) It is slow
Explanation: ECL’s major disadvantage is that each gate continuously draws current, which means it requires (and
dissipates) significantly more power than those of other logic families. But ECL logic gates have clock frequency.
Thus, they have a fast operation.
9. The full form of SCFL is __________
a) Source-collector logic
b) Source-coupled logic
c) Source-complementary logic
d) Source Cored Logic
Explanation: The full form of SCFL is source-coupled logic.
advertisement
10. The equivalent of emitter-coupled logic made out of FETs is called __________
a) CML
b) SCFL
c) FECL
d) EFCL
Explanation: The equivalent of emitter-coupled logic made out of FETs is called Source-coupled logic(SCFL). Like ECL,
SCL is also the fastest among the logic families.
11. ECL was invented in _______ by __________
a) 1956, Baker clamp
b) 1976, James R. Biard
c) 1956, Hannon S. Yourke
d) 1976, Yourke
Explanation: ECL was invented in August 1956 at IBM by Hannon S Yourke.
12. At the time of invention, an ECL was called as __________

a) Source-coupled logic
b) Current Mode Logic
c) Current-steering logic
d) Emitter-coupled logic
Explanation: At the time of invention, an ECL was called a current-steering logic because it involved current
switching.
13. The ECL circuits usually operates with __________
a) Negative voltage
b) Positive voltage
c) Grounded voltage
d) High Voltage
Explanation: The ECL circuits usually operate with negative power supplies (positive end of the supply is connected
to ground), in comparison to other logic families in which negative end of the supply is grounded. It is done mainly to
minimize the influence of the power supply variations on the logic levels as ECL is more sensitive to noise on the VCC
and relatively immune to noise on VEE.
advertisement
14. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of __________
a) ECL
b) VECL
c) PECL
d) LECL
Explanation: Low voltage positive emitter coupled logic (LVPECL) is a power optimized version of PECL using a +3.3 V
instead of 5 V supply.
« Prev - Digital Circuits Questions and Answers – Transistor Transistor Logic(TTL)» Next - Digital Circuits Questions
and Answers – Integrated-injection Logic(I^2L)This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Integrated-injection Logic(I2L)”.
1. The full form of IIL is __________
a) Injection integrated logic
b) Integrated inspected logic
c) Integrated injection logic
d) Injection Inspected Logic
Explanation: The full form of IIL is Integrated injection logic. It is made up of multiple bipolar junction transistors and
had a speed comparable to TTl and power consumption equivalent to CMOS.
advertisement
2. Integrated injection logic is a class of digital circuits built with __________
a) Single collector BJT
b) Double emitter BJT
c) Multiple emitter BJT
d) Multiple collector BJT
Explanation: Integrated injection logic is a class of digital circuits built with multiple collector bipolar junction
transistors (BJT).
3. IIL has _____ noise immunity.

a) High
b) Low
c) Neutral
d) Nil
had speed comparable to TTl and power consumption equivalent to CMOS. IIL has high noise immunity because it
operates by current instead of voltage.
4. IIL is sometimes also known as __________
a) Single transistor logic
b) Multiple transistor logic
c) Merged transistor logic
d) Mixed Transistor Logic
had speed comparable to TTl and power consumption equivalent to CMOS. IIL is sometimes also known as merged
transistor logic.
5. Integrated Injection logic cannot be denoted as __________
a) IIL
b) I2L
c) I2L
d) I TWO L
had speed comparable to TTl and power consumption equivalent to CMOS. Integrated Injection logic can be denoted
as IIL, I2L and I2L as well.
advertisement
6. The heart of an I2L circuit is the __________
a) Common collector open emitter inverter
b) Common emitter open collector inverter
c) Open emitter common collector inverter
d) Open Emitter Open Collector Inverter

Explanation: The heart of an I2L circuit is the common emitter open collector inverter. The emitter is connected to
the ground, with the base having an input behaving as either current sink or high impedance floating condition. The
output of an inverter is connected to the collector.
7. In Integrated Injection, logic input is supplied to the __________
a) Emitter
b) Base
c) Collector
d) Collector Emitter
Explanation: In IIL, the input is supplied to the base as either a current sink (low logic level) or as a high impedance
floating condition (high logic level). The output of an inverter is connected to the collector.
8. In Integrated Injection, logic output is received through the __________
a) Emitter
b) Base
c) Collector
d) Base Emitter Junction
Explanation: In Integrated Injection logic output is received through the collector. The output of an inverter is
connected at the collector.
9. When the outputs of two inverters are wired together the result is __________
a) A two-input NOR gate
b) A single-input NOR gate
c) A two-input NAND gate
d) A single-input NAND gate
Explanation: When the outputs of two inverters are wired together then the result is a two-input NOR gate because
the configuration (NOT A) AND (NOT B) is equivalent to NOT (A OR B). In a NOR gate, the output is high only when all
of its input are at logic 0 else, the output is low.
advertisement
10. IIL was commonly used before the advent of CMOS logic by company ___________
a) Samsung
b) Nokia
c) Motorola
d) Apple
Explanation: I2L is relatively simple to construct on an integrated circuit and was commonly used before the advent
of CMOS logic by companies such as Motorola.
11. Which company introduced one of the first consumer-grade digital watches (the Black Watch) which used I2L
technology?
a) Cambridge Consultants Pvt Ltd
b) Sinclair Radionics Ltd
c) National Research and Development Council
d) Westminster
Explanation: Sinclair Radionics Ltd introduced one of the first consumer-grade digital watches (the Black Watch) in
August 1975, which used I2L technology.
advertisement

« Prev - Digital Circuits Questions and Answers – Emitter-Coupled Logic(ECL)» Next - Digital Circuits Questions and
Answers – MOS Digital Integrated CircuitsThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “MOS Digital Integrated Circuits”.
1. The full form of MOS is ___________
a) Metal oxide semiconductor
b) Metal oxygen semiconductor
c) Metallic oxide semiconductor
d) Metallic oxygen semiconductor
Explanation: The full form of MOS is “Metal Oxide Semiconductor”. It is a type of transistor having 3 layers: a metal
conductor, an insulating silicon layer and a semiconductor silicon layer.
advertisement
2. What are the types of MOSFET devices available?
a) P-type enhancement type MOSFET
b) N-type enhancement type MOSFET
c) Depletion type MOSFET
d) All of the mentioned
Explanation: MOSFET are of two types: enhancement and depletion type. Further, these are classified into n-type
and p-type device. The depletion type is switched on without the application of gate bias voltage and the
enhancement type is switched on with the application of gate voltage.
3. Which insulating layer used in the fabrication of MOSFET?
a) Aluminium oxide
b) Silicon Nitride
c) Silicon dioxide
d) Aluminium Nitrate
Explanation: Silicon dioxide is used as an insulating layer in the fabrication of MOSFET. It gives an extremely high
input resistance in the order of 1010 to 1015 Ω for MOSFET.
4. Which of the following plays an important role in improving the device performance of MOSFET?
a) Dielectric constant
b) Threshold voltage
c) Power supply voltage
d) Gate to drain voltage
Explanation: In MOSFET, the threshold voltage is typically 3 to 6V. This large voltage is not compatible with the
supply of 5V which is used in digital ICs. So, for the improvement of the device’s performance the magnitude of
threshold voltage should be reduced.
5. A technique used to reduce the magnitude of threshold voltage of MOSFET is the ___________
a) Use of complementary MOSFET
b) Use of Silicon nitride
c) Using thin film technology
d) Increasing potential of the channel
Explanation: Silicon nitride is sandwiched between two SiO2 layer and provide necessary barrier. The dielectric
constant of Si3N4 is 7.5, whereas that of SiO2 is 4. This increase in overall dielectric constant reduces threshold
voltage.
advertisement
6. What is used to higher the speed of operation in MOSFET fabrication?
a) Ceramic gate
b) Silicon dioxide
c) Silicon nitride
d) Poly silicon gate
Explanation: In conventional metal gate small overlap capacitance is present, which lowers the speed of operation.
With the presence of self aligning property of the poly silicon gate it eliminates this capacitance. Using a process
called ion-implantation, polysilicon, the drain and the source get doped. However, the thin oxide under silicon gate
acting as a mask for the process and thus develops the gate aligning property.
7. Find the sequence of steps involved in fabrication of poly silicon gate MOSFET?
Step 1: Entire wafer surface of a Si3N4 is coated and is etched away with the help of mask to include
source, gate and drain.

Step 2: The contact areas are defined using photolithographic process.
Step 3: Selective etching of Si3N4 and growth of thin oxide.
Step 4: The deposition of poly silicon gate.
Step 5: The growth of thick oxide is called field oxide and P implantation.
Step 6: The metallization and interconnection between substrate and source.
a) 1->5->3->4->2->6
b) 1->3->4->2->5->6
c) 1->5->4->3->2->6
d) 1->4->2->5->3->6
Explanation: These steps are the sequence of steps involved in fabrication of poly silicon gate MOSFET. With the help
of poly silicon gate doping, it highers the speed of operation of the MOSFET.
advertisement
8. Why MOSFET is preferred over BJT in IC components?
a) MOSFET has low packing density
b) MOSFET has medium packing density
c) MOSFET has high packing density
d) MOSFET has no packing density
Explanation: MOSFET is preferred over BJT because of its low packaging density. Thus, more number of MOSFET
memory cells can be accommodated in a particular area as compared to BJT.
9. Critical defects per unit chip area are ________ for a MOS transistor.
a) High
b) Low
c) Neutral
d) Very High
Explanation: Critical defects per unit chip area is low for a MOS transistor because it involves fewer steps in the
fabrication of a MOS transistor. Also, MOSFET has low packaging density.
10. MOS is being used in ___________
a) LSI
b) VLSI
c) MSI
Explanation: Since more transistor and circuitry functions can be achieved on a single chip with MOS technology that
is why MOS is being used in LSI and VLSI. LSI stands for Large Scale Integration and VLSI stands for Very Large Scale
Integration.
advertisement
Answers.
« Prev - Digital Circuits Questions and Answers – Integrated-injection Logic(I^2L)» Next - Digital Circuits Questions
and Answers – Characteristics of CMOSThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Characteristics of CMOS”.
1. The full form of CMOS is ____________
a) Capacitive metal oxide semiconductor
b) Capacitive metallic oxide semiconductor

c) Complementary metal oxide semiconductor
d) Complemented metal oxide semiconductor
Explanation: The full form of CMOS is complementary metal oxide semiconductor. In this type of device, both n-type
and p-type transistors are used in a complementary way.
advertisement
2. The full form of COS-MOS is ____________
a) Complementary symmetry metal oxide semiconductor
b) Complementary systematic metal oxide semiconductor
c) Capacitive symmetry metal oxide semiconductor
d) Complemented systematic metal oxide semiconductor
Explanation: The full form of COS-MOS is complementary systematic metal oxide semiconductor. In this type of
device, both n-type and p-type transistors are used in a complementary way. Usually, the transistors used are
MOSFETs.
3. CMOS is also sometimes referred to as ____________
a) Capacitive metal oxide semiconductor
b) Capacitive symmetry metal oxide semiconductor
c) Complementary symmetry metal oxide semiconductor
d) Complemented symmetry metal oxide semiconductor
Explanation: CMOS is also sometimes referred to as complementary systematic metal oxide–semiconductor (COS-
MOS). In this type of device, both n-type and p-type transistors are used in a complementary way. Usually, the
transistors used are MOSFETs.
4. CMOS technology is used in ____________
a) Inverter
b) Microprocessor
c) Digital logic
d) Both microprocessor and digital logic
Explanation: CMOS technology is used in Microprocessor, Microcontroller, static RAM and other digital logic circuits.
CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters and
highly integrated transceivers for many types of communication.
5. Two important characteristics of CMOS devices are ____________
a) High noise immunity
b) Low static power consumption
c) High resistivity
d) Both high noise immunity and low static power consumption
Explanation: Two important characteristics of CMOS devices are high noise immunity and low static power
consumption. Since one transistor of the pair is always off and the series combination draws significant power only
momentarily during switching between on and off states. Also, the performance of CMOS is not altered with the
presence of noise and thus it has high noise immunity.
advertisement
6. CMOS behaves as a/an ____________
a) Adder
b) Subtractor
c) Inverter
d) Comparator
Explanation: Since, the outputs of the PMOS and NMOS transistors are complementary such that when the input is
low, the output is high and when the input is high, the output is low. Because of this behaviour of input and output,
the CMOS circuit’s output is the inverse of the input. Whereas, adders and subtractors are combinational circuits.
7. An important characteristic of a CMOS circuit is the ____________
a) Noise immunity
b) Duality
c) Symmetricity
d) Noise Margin
Explanation: An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and
NMOS transistors. Due to the presence of two different types of transistors, the device has a complementary
function.
8. CMOS logic dissipates _______ power than NMOS logic circuits.

a) More
b) Less
c) Equal
d) Very High
Explanation: CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when
switching (“dynamic power”). Thus, CMOS has less power consumption and is more efficient.
9. Semiconductors are made of ____________
a) Ge and Si
b) Si and Pb
c) Ge and Pb
d) Pb and Au
Explanation: Semiconductors are made of Silicon (Si) and Germanium (Ge). Semiconductors are devices having
conductivity between conductors and insulators.
advertisement
10. Which chip were the first RTC and CMOS RAM chip to be used in early IBM computers, capable of storing
a total of 64 bytes?
a) The Samsung 146818
b) The Samsung 146819
c) The Motorola 146818
d) The Motorola 146819
Explanation: The Motorola 146818 was the first RTC and CMOS RAM chip to be used in early IBM computers;
capable of storing a total of 64 bytes.
« Prev - Digital Circuits Questions and Answers – MOS Digital Integrated Circuits» Next - Digital Circuits Questions
and Answers – BiCMOS Logic CircuitsThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “BiCMOS Logic Circuits”.
1. BiCMOS is an evolved semiconductor technology that integrates two formerly separate semiconductor
technologies those of the _____________
a) CMOS and FET
b) MOSFET and CMOS
c) BJT and CMOS
d) BJT and MOSFET
Explanation: BiCMOS is an evolved semiconductor technology that integrates two formerly separate semiconductor
technologies those of the BJT and CMOS. CMOS ensures low power dissipation, smaller noise margin and higher
packaging density, while BJT offers high switching speed and improved noise performance.
advertisement
2. We use BJT in BiCMOS because of its _____________
a) High speed
b) High gain
c) Low output resistance
Explanation: Bipolar junction transistors offer high speed, high gain and low output resistance, which are excellent
properties for high-frequency analog amplifiers. It also offers high switching speed and improved noise performance.
3. We use CMOS transistor in BiCMOS because of its _____________

a) High input resistance
b) Simple construction
c) Low power logic gates
Explanation: CMOS ensures low power dissipation, smaller noise margin and higher packaging density. It also offers
high input resistance and is excellent for constructing simple, low-power logic gates.
4. When was BiCMOS technology introduced?
a) 1990
b) 1991
c) 1992
d) 1989
Explanation: BiCMOS technology was introduced in 1990s. BiCMOS is an evolved semiconductor technology that
integrates two formerly separate semiconductor technologies those of the BJT and CMOS. CMOS ensures low power
dissipation, smaller noise margin and higher packaging density, while BJT offers high switching speed and improved
noise performance.
5. On which technology the Pentium is based?
a) MOSFET
b) CMOS
c) BiCMOS
d) BJT
Explanation: The Pentium technology is based on BiCMOS technology because BiCMOS circuits use the
characteristics of each type of transistor most appropriately. CMOS ensures low power dissipation, smaller noise
margin and higher packaging density, while BJT offers high switching speed and improved noise performance.
advertisement
6. The advantage of BiCMOS circuit is that it gives _____________
a) Large fan-out
b) Large fan-in
c) Small fan-in
d) Small fan-out
Explanation: Fan-out is the measure of the maximum number of inputs that a single gate output can feed. BiCMOS
circuits are particularly useful for logic with large fan-out (large capacitive load).
7. How many members a BiCMOS family have?
a) 5
b) 6
c) 7
d) 8
Explanation: BICMOS is a combination of both CMOS and BJT technology. The BiCMOS family has mainly 5 members
and those are ABT logic, ALB logic, ALVT logic, BCT logic and LVT logic.
8. What is LVT logic?
a) Lower threshold voltage
b) Lower supply threshold voltage
c) Lower supply voltage while retaining TTL logic levels
Explanation: LVT stands for Low Voltage BiCMOS Technology which is an integration of less power dissipation and
less noise of CMOS along with the high switching speed and output drive of BJT. LVT logic is nothing but the lower
supply voltage while retaining TTL logic levels.
9. What does ALVT mean?
a) All lower supply voltage while retaining TTL logic levels
b) ABT lower supply voltage while retaining TTL logic levels
c) Advanced version of LVT logic
d) All version of LVT logic
Explanation: ALVT stands for Advanced Low Voltage BiCMOS Technology (ALVT). It is a faster version of LVT family. It
is an integration of less power dissipation and less noise of CMOS along with the high switching speed and output
drive of BJT.
advertisement
10. The full form of PTL is _____________
a) Pull transistor logic
b) Push transistor logic
c) Pass transistor logic
d) Post Transistor Logic
Explanation: The full form of PTL is “pass transistor logic”. It combines different logic families to design an integrated
circuit. Thus, it reduces the number of transistors used by scraping off the unnecessary transistors.
11. CVSL means _____________
a) Complementary Voltage Switch Logic
b) Cascode Voltage Switch Logic
c) Complemented Voltage Switch Logic
d) Cascade Voltage Switch Logic
Explanation: Cascode Voltage Switch Logic (CVSL) refers to a CMOS-type logic family which is designed for certain
advantages. It requires mainly N-channel MOSFET transistors to implement the logic using true and complementary
input signals and also needs two P-channel transistors at the top to pull one of the outputs high.
advertisement

« Prev - Digital Circuits Questions and Answers – Characteristics of CMOS» Next - Digital Circuits Questions and
Answers – Compatibility or InterfacingThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Compatibility or Interfacing”.
1. Compatibility refers to ____________
a) The output of a circuit should match with the input of another circuit
b) The output of a circuit should match with the input of the same circuit
c) The input of a circuit should match with the output of another circuit
d) The input of a circuit should match with the output of same circuit
Explanation: The output(s) of a circuit or a system should match the input(s) of another circuit or system that has
different electrical characteristics. This is referred to as compatibility.
advertisement
2. The method of connecting a driving device to a loading device is known as ___________
a) Compatibility
b) Interface
c) Sourcing
d) Sinking
Explanation: The method of connecting a driving device to a loading device is known as interface. The output(s) of a
circuit or a system should match the input(s) of another circuit or system that has different electrical characteristics.
This is referred to as compatibility.
3. The first CML logic was introduced by General Electric in ___________
a) 1960
b) 1981
c) 1961
d) 1990
Explanation: CML stands for Current Mode Logic. The first CML logic was introduced by General Electric in 1961.
4. Commercial ECL families are not nearly as popular as TTL and CMOS mainly because they ___________
a) Produces too much noise

b) Consume too much power
c) Have high fan-in
d) Have high fan-out
Explanation: Commercial ECL families are not nearly as popular as TTL and CMOS mainly because they consume too
much power. CMOS consumes the least power while TTL provides high speed.
5. The key to propagation delay in bipolar logic family is to prevent the transistors in a gate from ___________
a) Fan-in
b) Fan-out
c) Saturation
d) Cut-off
Explanation: The key to propagation delay in bipolar logic family is to prevent the transistors in a gate from
saturation. In Saturation mode, the transistor is in “ON”mode, where it seems like a short circuit between collector
and emitter.
advertisement
6. Schottky families prevent the saturating using ___________
a) Transistors
b) Schottky transistors
c) Diodes
d) Schottky diodes
Explanation: Schottky families prevent the saturating using Schottky diodes across the base-collector junctions of
transistors. In Saturation mode, the transistor is in “ON”mode, where it seems like a short circuit between collector
and emitter.
7. The basic idea of basic CML circuit came from an ___________
a) Inverter
b) Buffer
c) Transistor
d) Both inverter and buffer
Explanation: CML is Current Mode Logic in which data is transmitted at high speed of Mbps. Since this circuit has
both inverting and non-inverting output. So, It behaves like an inverter/buffer.
8. The full form of MECL is ___________
a) Mono emitter coupled logic
b) Motorola emitter coupled logic
c) Motorola emitter capacitor logic
d) Both mono emitter and motorola coupled logic
Explanation: The full form of MECL is Motorola emitter coupled logic. ECL is a high speed BJT. It uses BJT differential
amplifier with single input and restricted current to avoid the transistor going into saturation and thus turning off
operation.
9. Motorola has offered MECL circuits in ______ logic families.
a) 3
b) 4
c) 5
d) 6
Explanation: Motorola has offered MECL circuits in five logic families: MECL I, MECL II, MECL III, MECL 10000 (MECL
10K) and MECL 10H000 (MECL 10KH). The full form of MECL is Motorola emitter coupled logic. ECL is a high speed
BJT. It uses BJT differential amplifier with single input and restricted current to avoid the transistor going into
saturation and thus turning off operation.
10. The latest entrant to the ECL family is ___________
a) ECL 10K
b) ECL 100K
c) ECL 1000K
d) ECL 10000K
Explanation: The latest entrant to the ECL family is ECL 100K, having 6-digit part numbers. This family offers
functions, in general, different from those offered by 10K series. This family operates with a reduced power supply
voltage -4.5 V, has shorter propagation delay of 0.75 ns, and transition time of 0.7 ns. However, the power
consumption per gate is about 40 mW.
11. All input of NOR as low produces result as ___________
a) Low
b) Mid
c) High
d) High Impedance
Explanation: According to the properties of NOR gate, if all the input of NOR as low produces a result as high. While
if any input of NOR is high, then it produces low output.
advertisement
12. In RTL NOR gate, the output is at logic 1 only when all the inputs are at ___________
a) logic 0
b) logic 1
c) +10v
d) floating
Explanation: RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only when all the inputs are at
logic 0. The output of NOR will be 0 if any of the input is 1.
advertisement
Answers.

« Prev - Digital Circuits Questions and Answers – BiCMOS Logic Circuits» Next - Digital Circuits Questions and
Answers – Introduction of Arithmetic OperationThis set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Introduction of Arithmetic Operation”.
1. The basic building blocks of the arithmetic unit in digital computers are __________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator
Explanation: The basic building blocks of the arithmetic unit in digital computers are adders. Since a parallel adder is
constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the parallel
adder, it is possible to obtain different types of arithmetic operations.
advertisement
2. A digital system consists of _____ types of circuits.
a) 2
b) 3
c) 4
d) 5
Explanation: A digital system consists of two types of circuits and these are a combinational and sequential logic
circuit. Combinational circuits are the ones which do not depend on previous inputs while Sequential circuits depend
on past inputs.
3. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
b) Intermediate values
c) Input values
d) Clock pulses
Explanation: In a combinational circuit, the output at any time depends only on the input values at that time and not
on past or intermediate values.
4. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
c) Both past output and present input
d) Present input values
Explanation: In a sequential circuit, the output at any time depends on the present input values as well as past
output values. It also depends on clock pulses depending on whether it’s synchronous or asynchronous sequential
circuits.
5. Procedure for the design of combinational circuits are:
advertisement
A. From the word description of the problem, identify the inputs and outputs and draw a block diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) B, A, E, C, D
Explanation: Combinational circuits are the ones which do not depend on previous inputs and depends only on the
present values. The given arrangement A, B, E, C, D is the right sequence for the designing of the combinational
circuits.
6. All logic operations can be obtained by means of __________
a) AND and NAND operations
b) OR and NOR operations

c) OR and NOT operations
d) NAND and NOR operations
Explanation: Since the logic gates NOR and NAND are known as universal logic gates, therefore it can be used to
design all the three basic gates AND, OR and NOT. Thus, it means that any operations can be obtained by
implementation of these gates.
7. The design of an ALU is based on __________
a) Sequential logic
b) Combinational logic
c) Multiplexing
d) De-Multiplexing
Explanation: The design of an ALU is based on combinational logic. Because the unit has a regular pattern, it can be
broken into identical stages connected in cascade through carries.
advertisement
8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____
result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry and a possible zero
result.
9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the
result, a zero indication and __________
a) An underflow condition
b) A neutral condition
c) An overflow condition
d) One indication
Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the
sign of the result, a zero indication and an overflow condition.
10. The flag bits in an ALU is defined as ___________
a) The total number of registers
b) The status bit conditions
c) The total number of control lines
Explanation: In an ALU, status bit conditions are sometimes called condition code bits or flag bits. It is so called
because they tend to represent the status of the respect flags after any operation.
advertisement
Answers.
« Prev - Digital Circuits Questions and Answers – Compatibility or Interfacing» Next - Digital Circuits Questions and
Answers – Half Adder & Full AdderThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Half Adder & Full Adder”.
1. In parts of the processor, adders are used to calculate ____________
a) Addresses
b) Table indices
c) Increment and decrement operators
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used
to calculate addresses, table indices, increment and decrement operators, and similar operations.
advertisement
2. Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
Explanation: Total number of inputs in a half adder is two. Since an EXOR gates has 2 inputs and carry is connected
with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR
gives SUM and that of AND gives carry.
3. In which operation carry is obtained?
a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after
1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow 1).
4. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND
B.
5. If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is given by A XOR
B.
advertisement
6. Half-adders have a major limitation in that they cannot __________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage,
meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-
adder can also represent the result A+B=3 as sum and carry both being high.
7. The difference between half adder and full adder is __________
a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference between them, while
both have two outputs SUM and CARRY.
8. If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.
9. If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B) AND C, which
is equivalent to (A AND B) OR (B AND C) OR (C AND A).
advertisement
10. How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half
adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2 EXOR.
« Prev - Digital Circuits Questions and Answers – Introduction of Arithmetic Operation» Next - Digital Circuits
Questions and Answers – Half & Full SubtractorThis set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Half & Full Subtractor”.
1. Half subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of two bits, namely
minuend and subtrahend and produces two outputs, borrow and difference.
advertisement
2. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because carry is taken into
consideration during addition process.
3. How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4
Explanation: There are two outputs required for the implementation of a subtractor. One for the difference and
another for borrow.
4. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In both of the situation
subtractor gives 0 as the output.
5. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
Explanation: The subtractor has two outputs BORROW and DIFFERENCE. Since the difference output of a subtractor
is given by AB’ + BA’ and this is the output of a XOR gate. So, the final difference output is AB’ + BA’.
advertisement
6. Let A and B is the input of a subtractor then the borrow will be ___________
a) A AND B’
b) A’ AND B
c) A OR B
d) A AND B
Explanation: The borrow of a subtractor is received through AND gate whose one input is inverted. On that basis the
borrow will be (A’ AND B).
7. What does minuend and subtrahend denotes in a subtractor?
a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the two inputs of a
subtractor then A is called minuend and B as subtrahend.
8. Full subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend bit and borrow
from the previous stage. However, it also produces 2 outputs BORROW and DIFFERENCE.
9. The full subtractor can be implemented using ___________
a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
Explanation: A full subtractor has 3 input bits and two outputs bits BORROW and DIFFERENCE. The full subtractor can
be implemented using two half subtractors and an OR gate.
advertisement
10. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
Explanation: The difference output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR X.
11. The output of a full subtractor is same as ____________

a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
Explanation: The sum and difference output of a full adder and a full subtractor are same. If A, B and C are the input
of a full adder and a full subtractor then the output will be given by (A XOR B XOR C), respectively.
advertisement
« Prev - Digital Circuits Questions and Answers – Half Adder & Full Adder» Next - Digital Circuits Questions and
Answers – Procedure for the Design of Combinational CircuitsThis set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Procedure for the Design of Combinational Circuits”.
1. The basic building blocks of the arithmetic unit in a digital computers are ____________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator
Explanation: The basic building blocks of the arithmetic unit in a digital computers are adders. Since, a parallel adder
is constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the
parallel adder, it is possible to obtain different types of arithmetic operations.
advertisement
2. A digital system consists of _____ types of circuits.
a) 2
b) 3
c) 4
d) 5
Explanation: A digital system consists of two types of circuits and these are combinational and sequential logic
circuit. Combinational circuits are the ones which do not depend on previous inputs while Sequential circuits depend
on past inputs.
3. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
c) Input values
d) Clock pulses
Explanation: In a combinational circuit, the output at any time depends only on the input values at that time and not
on past or intermediate values.
4. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
c) Both past output and present input
d) Present input values
Explanation: In a sequential circuit, the output at any time depends on the present input values as well as past
output values. It also depends on clock pulses depending whether it’s synchronous or asynchronous sequential
circuits.
5. Procedure for the design of combinational circuits are:

advertisement
A. From the word description of the problem, identify the inputs and outputs and draw a block diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) B, A, E, C, D
Explanation: Combinational circuits are the ones which do not depend on previous inputs and depends only on the
present values. The given arrangement in option c is the right sequence for the designing of the combinational
circuits.
6. All logic operations can be obtained by means of ____________
a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations
Explanation: Since, the logic gates NOR and NAND are known as universal logic gates, therefore it can be used to
design all the three basic gates AND, OR and NOT. Thus, it means that any operations can be obtained by
implementation of these gates.
7. The design of an ALU is based on ____________
a) Sequential logic
b) Combinational logic
c) Multiplexing
d) De-Multiplexing
Explanation: The design of an ALU is based on combinational logic. Because the unit has a regular pattern, it can be
broken into identical stages connected in cascade through carries.
advertisement
8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____
result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry and a possible zero
result.
9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the
result, a zero indication and ___________
a) An underflow condition
b) A neutral condition
c) An overflow condition
d) One indication
Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the
sign of the result, a zero indication and an overflow condition.
10. The flag bits in an ALU is defined as ____________
a) The total number of registers
b) The status bit conditions
c) The total number of control lines
Explanation: In an ALU, status bit conditions are sometimes called condition code bits or flag bits. It is so called
because they tend to represent the status of the respect flags after any operation.
advertisement
Answers.
« Prev - Digital Circuits Questions and Answers – Half & Full Subtractor» Next - Digital Circuits Questions and
Answers – K-Map SimplificationThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs)
focuses on “K-Map Simplification”.
1. Which statement below best describes a Karnaugh map?
a) It is simply a rearranged truth table
b) The Karnaugh map eliminates the need for using NAND and NOR gates
c) Variable complements can be eliminated by using Karnaugh maps
d) A Karnaugh map can be used to replace Boolean rules
Explanation: K-map is simply a rearranged truth table. It is a pictorial representation of truth table having a specific
number of cells or squares, where each cell represents a Maxterm or a Minterm.
advertisement
2. Which of the examples below expresses the commutative law of multiplication?
a) A + B = B + A
b) A • B = B + A
c) A • (B • C) = (A • B) • C
d) A • B = B • A
Explanation: The commutative law of multiplication is (A * B) = (B * A).
The commutative law of addition is (A + B) = (B + A).
3. The Boolean expression Y = (AB)’ is logically equivalent to what single gate?
a) NAND
b) NOR
c) AND
d) OR
Explanation: If A and B are the input for AND gate the output is obtained as AB and after inversion we get (AB)’,
which is the expression of NAND gate. NAND gate produces high output when any of the input is 0 and produces low
output when all inputs are 1.
4. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referred to as
__________________
a) A Karnaugh map
b) DeMorgan’s second theorem
c) The commutative law of addition
d) The associative law of multiplication
Explanation: DeMorgan’s Law: ~(P+Q) <=> (~P).(~Q) Also,
~(P.Q) <=> (~P)+(~Q).
5. The systematic reduction of logic circuits is accomplished by _______________
a) Symbolic reduction
b) TTL logic
c) Using Boolean algebra
d) Using a truth table
Explanation: The systematic reduction of logic circuits is accomplished by using boolean algebra.
advertisement
6. Each “1” entry in a K-map square represents _______________
a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
Explanation: Each “1” entry in a K-map square represents a HIGH for each input truth table condition that produces a
HIGH output. Thus, it represents a minterm.
7. Each “0” entry in a K-map square represents _______________
a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
Explanation: Each “0” entry in a K-map square represents a LOW output for all possible HIGH input conditions. Thus,
it represents Maxterm.
8. Which of the following statements accurately represents the two BEST methods of logic circuit simplification?
a) Actual circuit trial and error evaluation and waveform analysis
b) Karnaugh mapping and circuit waveform analysis
c) Boolean algebra and Karnaugh mapping
d) Boolean algebra and actual circuit trial and error evaluation
Explanation: The two BEST methods of logic circuit simplification are Boolean algebra and Karnaugh mapping.
Boolean Algebra uses the Laws of Boolean Algebra for minimization of Boolean expressions while Karnaugh Map is a
pictorial representation and reduction of the Boolean expression.
9. Looping on a K-map always results in the elimination of __________
a) Variables within the loop that appear only in their complemented form
b) Variables that remain unchanged within the loop
c) Variables within the loop that appear in both complemented and uncomplemented form
d) Variables within the loop that appear only in their uncomplemented form
Explanation: Looping on a K-map always results in the elimination of variables within the loop that appear in both
complemented and uncomplemented form.
advertisement
10. Which of the following expressions is in the sum-of-products form?
a) (A + B)(C + D)
b) (A * B)(C * D)
c) A* B *(CD)
d) A * B + C * D
Explanation: Sum of product means that it is the sum of all product terms. Thus, the number is multiplied first and
then it is added: A * B + C * D.
11. Which of the following is an important feature of the sum-of-products form of expressions?
a) All logic circuits are reduced to nothing more than simple AND and OR operations
b) The delay times are greatly reduced over other forms
c) No signal must pass through more than two gates, not including inverters
d) The maximum number of gates that any signal must pass through is reduced by a factor of two
Explanation: An important feature of the sum-of-products form of expressions in the given option is that all logic
circuits are reduced to nothing more than simple AND and OR operations. Sum Of Product means it is the sum of
product terms containing variables in complemented as well as uncomplemented forms.
12. Which of the following expressions is in the product-of-sums form?
a) (A + B)(C + D)
b) (AB)(CD)
c) AB(CD)
d) AB + CD
Explanation: (A + B)(C + D) represents the product-of-sums form.
advertisement
Answers.
« Prev - Digital Circuits Questions and Answers – Procedure for the Design of Combinational Circuits» Next - Digital
Circuits Questions and Answers – Controlled InverterThis set of Digital Electronics/Circuits Multiple Choice Questions
& Answers (MCQs) focuses on “Controlled Inverter”.
1. Controlled inverter is also known as _____________
a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) Controlled gate
Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well. It is used between output
and a bus so that one can control whether the output is fed to the bus or not.
advertisement
2. Why XOR gate is called an inverter?
a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) It behaves like a AND gate
Explanation: The XOR (Exclusive Or) gate has a true output when the two inputs are different. When one input is
true, the output is the inversion of the other. When one input is false, the output is the non-inversion of the other.
3. Controlled buffers can be useful __________
a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose value should match
the output of one of several components. By placing a controlled buffer between each component output and the
bus, you can control whether that component’s output is fed onto the bus or not.
4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is __________
a) Ex-NOR gate
b) OR gate
c) Ex-OR gate
d) NAND gate
Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are same and EX-NOR is
opposite of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs are LOW. Thus, EX-NOR
produces output for even number of 1’s or all 0s, while EXOR produces output for odd number of 1’s.
5. What is the first thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
Explanation: HDL stands for Hardware Description Language. In order to use a macro function, one needs to have
experience in HDL for representing the structure and behaviour of digital circuits.
advertisement
6. What is the major difference between half-adders and full-adders?
a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number like 0001 and 0011,
then half adder can not be used because if the first bit of both the numbers is 1, then the sum would be 0 and carry
would be 1. But this carry can not be added with the second bits addition of the number. So, half adders are useless.
But in full adders, one more carry input is present, so that, if carry of one stage is present, it can be added with the
next stage as it is done in normal addition. So, therefore, full adders have a carry input capability.
7. The binary subtraction of 0 – 0 = ?
a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
Explanation: The binary subtraction of 0 – 0 = 0. Thus, it’s difference is 0 as well as it’s borrow.
8. How many basic binary subtraction operations are possible?
a) 1
b) 4
c) 3
d) 2
Explanation: 4 basic binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
9. When performing subtraction by addition in the 2’s-complement system is?
a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
d) The minuend and subtrahend are both left in their original form
Explanation: When performing subtraction by addition in the 2’s-complement system, the minuend is left in its
original form and the subtrahend is changed to its 2’s-complement. It is then added to the minuend. If the result has
carry, then it’s dropped and that’s the final answer. Else, if the result has no carry, then the result is again converted
to it’s 2’s complement form and that’s the final answer with a ‘negative’ sign.
advertisement
10. What are the two types of basic adder circuits?
a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
Explanation: There are two types of adder circuits: half-adder and full-adder. Half-Adder has 2 inputs while Full-
Adder has 3 inputs. Whereas, both have two outputs SUM and CARRY.
11. Which of the following is correct for full adders?
a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
Explanation: By using maximum of two half adders we can make a full adder for the first stage of a Parallel Full
adder.
12. The selector inputs to an arithmetic/logic unit (ALU) determine the __________
a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
Explanation: An ALU performs basic arithmetic and logic operations and stores it in the accumulator. Examples of
arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are
comparisons of values such as NOT, AND and OR and any logical operations.
advertisement
Answers.
« Prev - Digital Circuits Questions and Answers – K-Map Simplification» Next - Digital Circuits Questions and
Answers – 4-Bit Parallel Adder/Subtractor – 1This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “4-Bit Parallel Adder/Subtractor – 1”.
1. Controlled inverter is also known as ____________
a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) Controlled gate
Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well. It is used between output
and a bus so that one can control whether the output is fed to the bus or not.
advertisement
2. Why XOR gate is called an inverter?
a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) It behaves like a AND gate
Explanation: The XOR (Exclusive Or) gate has a true output when the two inputs are different. When one input is
true, the output is the inversion of the other. When one input is false, the output is the non-inversion of the other.
3. Controlled buffers can be useful ____________
a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose value should match
the output of one of several components. By placing a controlled buffer between each component output and the
bus, you can control whether that component’s output is fed onto the bus or not.
4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is ____________
a) Ex-NOR gate
b) OR gate
c) Ex-OR gate
d) NAND gate
Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are same and EX-NOR is
opposite of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs are LOW. Thus, EX-NOR
produces output for even number of 1’s or all 0s, while EXOR produces output for odd number of 1’s.
5. What is the first thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
Explanation: HDL stands for Hardware Description Language. In order to use a macro function, one needs to have
experience in HDL for representing the structure and behaviour of digital circuits.
advertisement
6. What is the major difference between half-adders and full-adders?
a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number like 0001 and 0011,
then half adder can not be used because if the first bit of both the numbers is 1, then the sum would be 0 and carry
would be 1. But this carry can not be added with the second bits addition of the number. So, half adders are useless.
But in full adders, one more carry input is present, so that, if carry of one stage is present, it can be added with the
next stage as it is done in normal addition. So, therefore, full adders have a carry input capability.
7. The binary subtraction of 0 – 0 =?
a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
Explanation: The binary subtraction of 0 – 0 = 0. Thus, it’s difference is 0 as well as it’s borrow.
8. How many basic binary subtraction operations are possible?
a) 1
b) 4
c) 3
d) 2
Explanation: 4 basic binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
9. When performing subtraction by addition in the 2’s-complement system ____________
a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
d) The minuend and subtrahend are both left in their original form
Explanation: When performing subtraction by addition in the 2’s-complement system, the minuend is left in its
original form and the subtrahend is changed to its 2’s-complement. It is then added to the minuend. If the result has
carry, then it’s dropped and that’s the final answer. Else, if the result has no carry, then the result is again converted
to it’s 2’s complement form and that’s the final answer with a ‘negative’ sign.
advertisement
10. What are the two types of basic adder circuits?
a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
Explanation: There are two types of adder circuits: half-adder and full-adder. Half-Adder has 2 inputs while Full-
Adder has 3 inputs. Whereas, both have two outputs SUM and CARRY.
11. Which of the following is correct for full adders?
a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder

Explanation: By using maximum of two half adders we can make a full adder for the first stage of a Parallel Full
adder.
12. The selector inputs to an arithmetic/logic unit (ALU) determine the ____________
a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
Explanation: An ALU performs basic arithmetic and logic operations and stores it in the accumulator. Examples of
arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are
comparisons of values such as NOT, AND and OR and any logical operations.
advertisement
Answers.
« Prev - Digital Circuits Questions and Answers – Controlled Inverter» Next - Digital Circuits Questions and Answers
– 4-Bit Parallel Adder/Subtractor – 2This set of Digital Electronic/Circuits Test focuses on “4-Bit Parallel
Adder/Subtractor – 2”.
1. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is ___________
a) The same as if the carry-in is tied LOW since the least significant carry-in is ignored
b) That carry-out will always be HIGH
c) A one will be added to the final result
d) The carry-out is ignored
Explanation: For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, one will be added to the final
result as a result because carry-in gives output as 1.
advertisement
2. Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which ___________
a) Determine sign and magnitude
b) Reduce propagation delay
c) Add a 1 to complemented inputs
d) Increase ripple delay
Explanation: A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead adder improves
speed by reducing the amount of time required to determine carry bits. It reduces the propagation delay by making
the hardware more complex. The ripple carry design is converted in such a way that carry over a group of bits of the
adder becomes 2-level logic.
3. One way to make a four-bit adder to perform subtraction is by ___________
a) Inverting the output
b) Inverting the carry-in
c) Inverting the B inputs
d) Grounding the B inputs
Explanation: A adder is a digital circuit which adds bits along with a carry bit from a previous stage, thus producing 2
outputs SUM and CARRY. Since, a four bit adder has four A, four B and a carry at the input end. So, for subtraction to
be performed, all the Bs terminal should be inverted.
4. What distinguishes the look-ahead-carry adder?
a) It is slower than the ripple-carry adder
b) It is easier to implement logically than a full adder

c) It is faster than a ripple-carry adder
d) It requires advance knowledge of the final answer
Explanation: It is faster than ripple carry adder as it reduces the propagation delay by converting the ripple carry in
such a way that the carry over a group of bits of the adder becomes 2-level logic.
5. Carry lookahead logic uses the concepts of ___________
a) Inverting the inputs
b) Complementing the outputs
c) Generating and propagating carries
d) Ripple factor
Explanation: Look Ahead Carry Adder is a type of digital circuit which reduces the propagation delay. Carry
lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry
lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the
concepts can be used more generally than this.
advertisement
6. What is one disadvantage of the ripple-carry adder?
a) The interconnections are more complex
b) More stages are required to a full adder
c) It is slow due to propagation time
Explanation: The main disadvantage in using this type of adders is that the time delay increases as for each adder to
add the carry should be generated in the previous adder, and for that to add the carry from the one before is
required. However, this disadvantage is taken care of in Carry Look Ahead adder in which the ripple carry is
converted in such a way that the carry over a group of bits of the adder becomes 2-level logic.
7. The carry propagation delay in 4-bit full-adder circuits ___________
a) Is cumulative for each stage and limits the speed at which arithmetic operations are performed
b) Is normally not a consideration because the delays are usually in the nanosecond range
c) Decreases in direct ratio to the total number of full-adder stages

d) Increases in direct ratio to the total number of full-adder stages but is not a factor in limiting the speed of
arithmetic operations
Explanation: A full adder is a digital circuit with 3 inputs and two outputs SUM and CARRY. The carry propagation
delay in 4-bit full-adder circuits is cumulative for each stage and limits the speed at which arithmetic operations are
performed.
8. What is Manchester carry chain?
a) Is a chain of controlled inverter
b) Variation of a carry-lookahead adder
c) Variation of a full-adder
d) Variation of a ripple carry adder
Explanation: The Manchester carry chain is a variation of the carry-lookahead adder that uses shared logic to lower
the transistor count. However, the carry generating logic depends on the logic to generate the carries in the past.
9. The main disadvantage of Manchester carry chain is ___________
a) Ripple factor
b) Propagation delay
c) Capacitive load
d) Both propagation delay and capacitive load
Explanation: Propagation delay is the measure of time taken by the output to go to the next state when the input is
altered. One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs,
together with the resistance of the transistors causes the propagation delay to increase much more quickly than a
regular carry lookahead.
advertisement
10. The summing outputs of a half or full-adder are designated by which Greek symbol?
a) Omega
b) Theta
c) Lambda
d) Sigma
Explanation: The summing outputs of a half or full-adder are designated by “sigma” which is a Greek symbol. This
same symbol is used to signify the Minterms in case of an SOP expression.
11. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
a) To decrease the cost
b) To make it smaller
c) To slow down the circuit
d) To speed up the circuit
Explanation: A Carry Look Ahead (CLA) Adder is a type of adder that reduce the propagation delay. A fast Carry Look
Ahead Adder is more fast than a normal CLA. Since, it is easy to implement and can be implemented on any types of
chip and have the capability to reduce propagation delay, which helps in increasing the speed of 7483 4-bit full-
adder.
To practice all areas of Digital Electronic Circuits for various tests, here is complete set of 1000+ Multiple Choice
advertisement
« Prev - Digital Circuits Questions and Answers – 4-Bit Parallel Adder/Subtractor – 1» Next - Digital Circuits
Questions and Answers – Fast Adder & Serial Adder – 1This set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on “Fast Adder & Serial Adder – 1”.
1. The inverter can be produced with how many NAND gates?
a) 2
b) 1
c) 3
d) 4
Explanation: The inverter can be produced with the help of single NAND gate, because we can send a single input
twice through the same NAND gate together, thus producing the inverted version of the input as output. It works as
an inverter.
advertisement
2. One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second
positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the leading edge of the first pulse.
Which statement describes the output’s relation with the inputs?
a) The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s between the pulses
b) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s between the pulses
c) The exclusive-OR output is a 15 s pulse followed by a 40 s pulse
d) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse
Explanation: When both the input pulses are high or low X-OR output is low. But when one of the input is high and
another is low or vice-versa, output is high. In this problem for the first 20uS one input is high and another is low. So,
obviously output is a high. for next 15uS both the input is high so output is low and for remaining 40uS(75-20-15)
first input is still high and second one is low so output is high.
3. How many NOT gates are required to implement the Boolean expression: X = AB’C + A’BC?
a) 2
b) 3
c) 4
d) 5
Explanation: Since in the given expression two inputs are complemented. So, we require two NOT gate at the input.
A NOT gate is a basic gate which accepts a single input and produces a single output, which is the inverted version of
the input.
4. The carry look ahead adder is based on the principle of looking at the lower order bits of ________ and ________
if a high order carry is generated.
a) Addend, minuend
b) Minuend, subtrahend
c) Addend, minuend
d) Augend, addend
Explanation: The carry look ahead adder is based on the principle of looking at the lower order bits of the augend
and addend if a high order carry is generated. A carry look ahead adder is a type of adder which reduces the
propagation delay.
5. What are carry generate combinations?
a) If all the input are same then a carry is generated
b) If all of the output are independent of the inputs
c) If all of the input are dependent on the output
d) If all of the output are dependent on the input
Explanation: If the input is either 0, 0, 0 or 0, 0, 1 then the output will be 0 (i.e. independent of input) and if the input
is either 1, 1, 0 or 1, 1, 1 then the output is 1 (i.e independent of input). Such situation is known as carry generate
combinations.
advertisement
6. In serial addition, the addition is carried out __________
a) 3 bit per second
b) Byte by byte
c) Bit by bit
d) All bits at the same time
Explanation: In serial addition, the addition is carried out bit by bit.
7. How many shift registers are used in a 4 bit serial adder?
a) 4
b) 3
c) 2
d) 5
Explanation: There are two shift registers are used in a 4-bit serial adder, which is used to store the numbers to be
added serially. Serial addition takes place bit by bit.
8. A D flip-flop is used in a 4-bit serial adder, why?
a) It is used to invert the input of the full adder
b) It is used to store the output of the full adder
c) It is used to store the carry output of the full adder
d) It is used to store the sum output of the full adder
Explanation: The D flip-flop, i.e. carry flip-flop, is used to store the carry output of the full adder so that it can be
added to the next significant position of the numbers in the registers.
9. What is ripple carry adder?
a) The carry output of the lower order stage is connected to the carry input of the next higher order stage
b) The carry input of the lower order stage is connected to the carry output of the next higher order stage
c) The carry output of the higher order stage is connected to the carry input of the next lower order stage
d) The carry input of the higher order stage is connected to the carry output of the lower order stage
Explanation: When the carry output of the lower order stage is connected to the carry input of the next higher order
stage, such types of connection is called ripple carry adder in a 4-bit binary parallel adder.
advertisement
10. If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be
__________
a) 0
b) 1
c) Floating
d) High Impedance
Explanation: If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be
1. Because on subtracting 0 and 1, one borrow is taken and it proceeds till the next step (i.e 0 – 1 – 1 = 0, borrow =
1).
« Prev - Digital Circuits Questions and Answers – 4-Bit Parallel Adder/Subtractor – 2» Next - Digital Circuits
Questions and Answers – Fast Adder & Serial Adder – 2This set of Digital Electronic/Circuits Quiz focuses on “Fast
Adder & Serial Adder – 2”.
1. A serial subtractor can be obtained by converting the serial adder by using the _____________
a) 1’s complement system
b) 2’s complement system
c) 10’s complement
d) 9’s complement
Explanation: A serial subtractor can be obtained by converting the serial adder by using the 2’s complement system.
9’s complement and 10’s complement are used for decimal numbers while adders deal with binary numbers.
advertisement
2. The hexadecimal number (4B)16 is transmitted as an 8-bit word in parallel. What is the time required for
this transmission if the clock frequency is 2.25 MHz?
a) 444 ns
b) 444 s
c) 3.55 s
d) 3.55 ms
Explanation: Because the clock pulse of 4-bit transmits the data of 8-bit word in parallel mode and this transmission
is done at 2.25 MHz frequency. We know that: f=1/t and we can find the time required for this transmission by the
clock pulse.
Therefore, time = (1/2.25) = 0.4444 us = 444.44 ns ~ 444ns.
3. Internally, a computer’s binary data are always transmitted on parallel channels which is commonly referred to as
the __________
a) Parallel bus
b) Serial bus
c) Data bus
d) Memory bus
Explanation: A process consists of 3 types of buses: Control Bus, Data Bus and Address Bus. A computer’s data is
always in the binary form which is stored in the bus that transmits the data on any channels. It doesn’t matter that
it’s in parallel or serial.
4. What is the frequency of a clock waveform if the period of that waveform is 1.25sec?
a) 8 kHz
b) 0.8 kHz
c) 0.8 MHz
d) 8 MHz
Explanation: By using the formula of frequency, we can find the frequency of clock waveform. Time period(t) of the
waveform is = 1.25microseconds
f=1/t
Where ‘t’ is the time taken by the clock waveform;
f=(1/1.25)
so, f=0.8 MHz.
5. Why is parallel data transmission preferred over serial data transmission for most applications?
a) It is much slower
b) It is cheaper
c) More people use it
d) It is much faster
Explanation: Parallel data transmission preferred over serial data transmission for most applications because it is
much faster as bits are transmitted simultaneously, whereas in serial data transmission, bits are transmitted one by
one.
advertisement
6. With surface-mount technology (SMT), the devices should __________
a) Utilize transistor outline connections
b) Mount directly
c) Have parallel connecting pins
d) Require holes and pads
Explanation: Surface-mount technology (SMT) is a method for producing electronic circuits in which the components
are mounted or placed directly onto the surface of printed circuit boards (PCBs). An electronic device so made is
called a surface-mount device (SMD). In the industry, it has largely replaced the through-hole technology
construction method of fitting components with wire leads into holes in the circuit board. Both technologies can be
used on the same board for components not suited to surface mounting such as large transformers and heat-sinked
power semiconductors.
7. In most applications, transistor switches used in place of relays?
a) They consume less power
b) They are faster
c) They are quieter and smaller
Explanation: Transistors are of less consuming power, faster, quieter, smaller and its implementation is too easy. So,
in most applications transistor switches are more preferred. And also, transistors can be current-controlled or
voltage-controlled depending on our choice.
8. What can a relay provide between the triggering source and the output that semiconductor switching devices
cannot?
a) Total isolation
b) Faster
c) Higher current rating
d) Total isolation and higher current rating
Explanation: A relay provides total isolation and higher current rating between the triggering source and the output
that semiconductor switching devices cannot provide. This is why relays are used to drive high watt appliances at
offices or other buildings.
9. The serial format for transmitting binary information uses __________
a) A single conductor
b) Multiple conductors
c) Infrared technology
d) Fiber-optic
Explanation: A conductor accepts the whole data and arranges it in a serial manner, which is transmitted as binary
information. In serial transmission, data is transmitted bit by bit while in parallel transmission data is transmitted
simultaneously.
advertisement
10. Serial communication can be sped up by __________
a) Using silver or gold conductors instead of copper
b) Using high-speed clock signals
c) Adjusting the duty cycle of the binary information
d) Using silver or gold conductors instead of copper and high-speed clock signals
Explanation: For any serial data transmission there is required of continuously data supply and if the input supply
(i.e. high speed clock signals) in a high amount the speed of serial communication can be increased. In serial
communication, data is transmitted bit by bit. So the use of high speed clock pulses would make the process faster.
To practice all areas of Digital Electronic Circuits for quizzes, here is complete set of 1000+ Multiple Choice Questions
and Answers.
« Prev - Digital Circuits Questions and Answers – Fast Adder & Serial Adder – 1» Next - Digital Circuits Questions
and Answers – BCD AdderThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs)
focuses on “BCD Adder”.
1. The decimal number system represents the decimal number in the form of ____________
a) Hexadecimal
b) Binary coded
c) Octal
d) Decimal
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit
is represented by a fixed number of bits, usually four or eight. Hexadecimal and Octal are number systems having
base 16 and 8 respectively.
advertisement
2. 29 input circuit will have total of ____________
a) 32 entries
b) 128 entries
c) 256 entries
d) 512 entries
Explanation: 29 input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.
3. BCD adder can be constructed with 3 IC packages each of ____________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
is represented by a fixed number of bits, usually four or eight. BCD adder can be constructed with 3 IC packages.
Each of 4-bit adders is an MSI(Medium scale Integration) function and 3 gates for the correction logic need one SSI
(Small Scale Integration) package.
4. The output sum of two decimal digits can be represented in ____________
a) Gray Code
b) Excess-3
c) BCD
d) Hexadecimal
Explanation: The output sum of two decimal digits can be represented in BCD(Binary-coded decimal). Binary-coded
decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed
number of bits, usually four or eight.
5. The addition of two decimal digits in BCD can be done through ____________
a) BCD adder
b) Full adder
c) Ripple carry adder
d) Carry look ahead
Explanation: The addition of two decimal digits in BCD can be done through BCD adder. Every input inserted, in
addition by the user converted into binary and then proceed for the addition. Whereas, Full Adder, Ripple Carry
Adder and Carry Look Adder are for the addition of binary bits.
advertisement
6. 3 bits full adder contains ____________
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
Explanation: 3 bits full adder contains 23 = 8 combinational inputs.
7. The simplified expression of full adder carry is ____________
a) c = xy+xz+yz
b) c = xy+xz
c) c = xy+yz
d) c = x+y+z
Explanation: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM and CARRY. The
simplified expression of full adder carry is c = xy+xz+yz.
8. Complement of F’ gives back __________
a) F’
b) F
c) FF
d) FF’
Explanation: Complement means inversion. So, complement of F’ gives back F, as per the Law of Involution.
9. Decimal digit in BCD can be represented by ____________
a) 1 input line
b) 2 input lines
c) 3 input lines
d) 4 input lines
is represented by a fixed number of bits, usually four or eight. Decimal digit in BCD can be represented by 4 input
lines. Since it is constructed with 4-bits.
advertisement
10. The number of logic gates and the way of their interconnections can be classified as ____________
a) Logical network
b) System network
c) Circuit network
d) Gate network
Explanation: The number of different levels of logic gates is represented in a fashion which is known as a logical
network.
« Prev - Digital Circuits Questions and Answers – Fast Adder & Serial Adder – 2» Next - Digital Circuits Questions
and Answers – Combinational CircuitsThis set of Digital Electronics/Circuits Multiple Choice Questions & Answers
(MCQs) focuses on “Combinational Circuits”.
1. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?
a) a
b) b
c) c
d) d
Explanation: SOP means Sum Of Products form which represents the sum of product terms having variables in
complemented as well as in uncomplemented form. Here, the diagram of d contains the OR gate followed by the
AND gates, so it is in SOP form.
advertisement
2. Which of the following logic expressions represents the logic diagram shown?
a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
Explanation: 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.
3. The device shown here is most likely a ________

a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
Explanation: The given diagram is demultiplexer, because it takes single input & gives many outputs. A demultiplexer
is a combinational circuit that takes a single output and latches it to multiple outputs depending on the select lines.
4. What type of logic circuit is represented by the figure shown below?
a) XOR
b) XNOR
c) AND
d) XAND
Explanation: After solving the circuit we get (A’B’)+AB as output, which is XNOR operation. Thus, it will produce 1
when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.
5. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?
a) d
b) a
c) c
d) b
Explanation: When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P
001
010
100
1 1 1.
Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.
advertisement
6. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate
d) One 4-input NAND gate, one inverter
Explanation: For decoding any number output must be high for that code and this is possible in One 4-input NAND
gate, one inverter option only. A decoder is a combinational circuit that converts binary data to n-coded data upto
2n outputs.
7. What is the indication of a short to ground in the output of a driving gate?
a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates
c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state
Explanation: Short to ground in the output of a driving gate indicates of a signal loss to all load gates. This results in
information being disrupted and loss of data.
8. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the
status of the Y’ outputs?
a) All are HIGH
b) All are LOW
c) All but Y0 are LOW
d) All but Y0 are HIGH
Explanation: In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0 and rest all are HIGH.
9. The carry propagation can be expressed as ________

a) Cp = AB
b) Cp = A + B
c) All but Y0 are LOW
d) All but Y0 are HIGH
Explanation: This happens in parallel adders (where we try to add numbers in parallel via more than one adders). A
carry propagation occurs when carry from one adder needs to be forwarded to other adder and that second adder is
holding the computation (addition) because carry from first adder has not come yet. So, there is a slight delay for
second adder and this is known as carry propagation.
advertisement
10. 3 bits full adder contains ________
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
Explanation: Full Adder is a combinational circuit with 3 input bits and 2 output bits CARRY and SUM. Three bits full
adder requires 23 = 8 combinational circuits.

« Prev - Digital Circuits Questions and Answers – BCD Adder» Next - Digital Circuits Questions and Answers –
Multiplexers (Data Selectors) – 1This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs)
focuses on “Multiplexers (Data Selectors) – 1”.
1. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line, depending on the active select lines.
advertisement
2. Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the
binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer
Explanation: Data Selector is another name of Multiplexer. A multiplexer (or MUX) is a device that selects one of
several analog or digital input signals and forwards the selected input into a single line, depending on the active
select lines.
3. It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital
multiplexer with the proficiency of large number of ___________
a) Inputs
b) Outputs
c) Selection lines
d) Enable lines
Explanation: It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the
digital multiplexer with the proficiency of large number of inputs.
4. Which is the major functioning responsibility of the multiplexing combinational circuit?
a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) Encoding of binary information
Explanation: The major functioning responsibility of the multiplexing combinational circuit is generation of selected
path between multiple sources and a single destination because it makes the circuit too flexible. A multiplexer (or
MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a
single line, depending on the active select lines.
5. What is the function of an enable input on a multiplexer chip?
a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
Explanation: Enable input is used to active the chip, when enable is high the chip works (ACTIVE), when enable is low
the chip does not work (MEMORY). However, Enable can be Active-High or Active-Low, indicating it is active either
when it is connected to VCC or GND respectively.
advertisement
6. One multiplexer can take the place of ___________
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line, depending on the active select lines. Since many operational behaviour
can be performed by using a multiplexer. Whereas, a combinational circuit is a combination of many logic gates
which makes the circuit more complex.
7. A digital multiplexer is a combinational circuit that selects ___________
a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one

c) Many decimal inputs and transmits the selected information
d) Many decimal outputs and accepts the selected information
Explanation: A digital multiplexer is a combinational circuit that selects one digital information from several sources
and transmits the selected information on a single output line depending on the status of the select lines. That is
why it is also known as a data selector.
8. In a multiplexer, the selection of a particular input line is controlled by ___________
a) Data controller
b) Selected lines
c) Logic gates
d) Both data controller and selected lines
Explanation: The selection of a particular input line is controlled by a set of selected lines in a multiplexer, which
helps to select a particular input from several sources.
9. If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) 2n
Explanation: If the number of n selected input lines is equal to 2^m then it requires m select lines to select one of m
select lines.
advertisement
10. How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Explanation: 2n input lines, n control lines and 1 output line available for MUX. Here, 8 input lines mean 23 inputs.
So, 3 control lines are possible. Depending on the status of the select lines, the input is selected and fed to the
output.
11. A basic multiplexer principle can be demonstrated through the use of a ___________
b) DPDT switch
c) Rotary switch
d) Linear stepper
Explanation: A basic multiplexer principle can be demonstrated through the use of a rotary switch. Since its
behaviour is similar to the multiplexer. There are around 10 digits out of which one is selected one at a time and fed
to the output.
12. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3
b) 4
c) 2
d) 5
Explanation: There are two NOT gates required for the construction of 4-to-1 multiplexer. x0, x1, x2 and x3 are the
inputs and C1 and C0 are the select lines and M is the output.
The diagram of a 4-to-1 multiplexer is shown below:
13. In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is ___________
a) X0
b) X1
c) X2
d) X3
Explanation: The output will be X1, because c1 = 0 and c0 = 1 results into 1 which further results as X1. And rest of
the AND gates gives output as 0.
advertisement
14. The enable input is also known as ___________
a) Select input
b) Decoded input
c) Strobe
d) Sink
Explanation: The enable input is also known as strobe which is used to cascade two or more multiplexer ICs to
construct a multiplexer with a larger number of inputs. Enable input activates the multiplexer to operate.
« Prev - Digital Circuits Questions and Answers – Combinational Circuits» Next - Digital Circuits Questions and
Answers – Multiplexers (Data Selectors) – 2This set of Digital Electronic/Circuits MCQs focuses on “Multiplexers(Data
Selectors) – 2”.
1. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
advertisement
a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
4. 4 to 1 MUX would have ____________
a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
advertisement
b) DPDT switch
c) Rotary switch
d) Linear stepper

advertisement
a) Bidirectional
b) Unidirectional
c) Even parity
a) Enable
b) Disable
c) Saturation
d) High Impedance
(i.e. E’).
advertisement
and Answers.
a) One into many
b) Many into one
c) Distributor
advertisement
c) AC to DC
a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3
a) Y0
b) Y1
c) Y2
d) Y3
a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
advertisement
advertisement
c) AC to DC

a) 2
b) 3
c) 4
d) 5
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
advertisement
a) Y0
b) Y1
c) Y2
d) Y3

a) 2
b) 3
c) 4
d) 5
since 23 = 8.
a) 2
b) 6
c) 8
d) 5
8.
advertisement
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answers.
advertisement
Ray Tubes.
advertisement
a) Air
b) Solid
c) Light
d) Water
material.
a) Magnetic field
b) Electric field
d) Gallois field
a) LED
b) LCD
c) OFC
d) OLED
the basis for LCDs.
chemical structure.
advertisement

a) 1950s
b) 1980s
c) 1960s
d) 1970s
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
Cathode Ray Tubes.
a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
a) 8
b) 7
c) 10
d) 9
advertisement
a) 4
b) 8
c) 10
d) 16
advertisement
a) 4
b) 8
c) 12
d) 16
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
a) Yes
b) No

advertisement
a) 2
b) 10
c) 3
d) 4
a) 3
b) 2
c) 8
d) 10
lines.
a) 8
b) 2^8
c) 4
d) 2^4
___________
a) Enable
b) Disable
c) Strobe
d) Clock
an active-low pin.
advertisement
a) No
b) Yes
c) Sometimes
d) Never
a) The higher value
b) The lower value
advertisement
a) 4
b) 5
c) 15
d) 10
from 0 to 9.
advertisement
a) Encoder
b) Display
c) Counter
d) Decoder
a) 4
b) 8
c) 10
d) 2
<= 2n.
a) 10
b) 9
c) 8
d) 3
advertisement
a) 32
b) 64
c) 128
d) 16
c) By using an ALU
d) By using UART
circuits.
a) 2
b) 16
c) 8
d) 4
advertisement
symbol?
2”.
c) CRC
d) Checksum
advertisement
c) CRC
d) Checksum
a) 2
b) 3
c) 4
d) 1
a) Even
b) Odd
d) Undefined
advertisement
b) CRC
d) Checksum
a) 0
b) 1
c) 1001
d) 0011
number of 1’s.
a) Indeterminate
b) 42
c) Even
d) Odd
c) CRC
d) Checksum
advertisement
a) AND
b) NAND
c) EX-OR
d) EX-NOR

advertisement
0101 0011 & 0010 0110 1000
a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
d) 101011 001100001
advertisement
c) With an ALU
d) UART
circuits.
a) BCD code
b) Binary code
c) ASCII code
d) Gray Code
c) Error correction
d) Error Detection
advertisement
a) Binary addition
b) 2’s complement
a) 0011101
b) 0110101
c) 1101001
d) 0101011
a) 101101
b) 001110
c) 110111
d) 111001
↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1
advertisement
Answers.

a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
advertisement
a) a > b
b) a – b
c) a < b
d) a = b
a) 0
b) 1
c) A
d) B
a) 1
b) 2
c) 3
d) 4
a) 1
b) 0
c) A
d) B
advertisement
a) XOR
b) XNOR
c) AND
d) NAND
a) Memory
b) CPU
c) Motherboard
d) Hard drive
b) Size comparator
c) Comparator
a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
advertisement
a) 1
b) 2
c) 3
d) 4
“HIGH” A = B = 1 or “LOW” A = B = 0.
comparison.
advertisement
14. TTL 74LS85 is a _____________

d) 555 timer
advertisement

a) One stable state
b) Two stable state
a) 4
b) 3
c) 2
d) 5
advertisement
a) System rated
b) Set reset
c) Set ready
d) Set Rated
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
a) x and y
b) a and b
c) s and r
d) q and q’
a) 1
b) 0
c) Inverted
d) Don’t cares
advertisement
a) label inputs
b) label outputs
c) label states
d) label tables
labelled.
a) x and y
b) a and b
c) s and r
d) j and k
high and Q’ low.

output.
advertisement
a) Unstable
b) Stable
c) Metastable
d) Bistable
feature?
c) Gate impedance
d) Cross coupling
advertisement
b) Racer
c) Switch debouncer
a) 1
b) 2
c) 3
d) 4
a) Be invalid
b) Change
c) Not change
d) Toggle
advertisement
a) AND or OR gates
d) AND or NOR gates
c) Latches
d) Flip-flops

c) Latches
d) Flip-flops
a) 2
b) 3
c) 4
d) 5
advertisement
a) Flip-flop
b) Latch
c) Strobe
d) Adder
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
a) Set
b) Reset
c) Previous state
d) Current state
advertisement

a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
advertisement
a) No change
b) Set
c) Reset
d) Forbidden
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
advertisement
a) Both are same
a) 2
b) 3
c) 4
d) 5
a) 4 AND gates
d) 3 AND gates
d) Invalid State
as Invalid State.
advertisement
a) Racer
c) Only S is active
d) Only R is active
advertisement
a) SET
b) RESET
c) Clear
d) Invalid
_____________
b) NOR latch
c) NAND latch

inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
number of inputs.
advertisement
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
flip-flop.
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
b) Ones catching
advertisement
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
a) Constantly LOW
b) Constantly HIGH
HIGH
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
advertisement
a) 00
b) 11
c) 01
d) 10
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
a) 2
b) 1
c) 4
d) 8
advertisement

Answers.
a) Distant
b) Data
c) Desired
d) Delay
advertisement
a) 1
b) 2
c) 3
d) 4
a) 2
b) 3
c) 4
d) 1
a) S-R
b) J-K
c) T
d) S-K
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
advertisement
a) 0
b) 1
c) Forbidden
d) Toggle
advertisement

edge of the clock
states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
advertisement

b) Q(n+1)=J’Q(n)+KQ'(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
advertisement
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
a) 3
b) 4
c) 2
d) 5
advertisement
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
advertisement
a) Level enabled
b) Edge triggered
d) Level triggered
a) Level enabled
d) Level triggered
a) Level enabled

d) Level triggered
a) Level enabled
d) Level triggered
advertisement
a) Constantly LOW
b) Constantly HIGH
output.
a) 1 state
b) 0 state
d) forbidden State
advertisement
a) Input
b) Pulser
c) Output
states.
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
c) Lock out state
d) Forbidden State
advertisement
a) High state
b) Low state
c) Toggle state
d) No Change State
a) D type
b) S-R type
c) Latch
d) J-K type
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
a) T flip-flop
b) SR flip-flop
d) D flip-flop
advertisement
a) S-R flip-flop
b) J-K flip-flop
d) D Flip-flop
a) 3
b) 2
c) 4
d) 5
triggering.
12. Flip-flops are ____________
a) Stable devices
b) Astable devices
c) Bistable devices
states.
advertisement
advertisement
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
S=1 & R=0.
a) S and R
b) R input
c) J and K input
d) D input
advertisement
___________
a) 1
b) 0
c) Don’t care
d) Toggle
___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
will be J=1, K=X.
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
a) S
b) R
c) D
d) Both S and R
advertisement
c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
“Counters”.
advertisement
flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
a) 2
b) 3
c) 4
d) 5
and such like.
a) 5
b) 10
c) 15
d) 20
advertisement
a) SSI counters
d) VLSI counters
them.
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
a) Parallel counter
b) Decade counter
d) VLSI counter
count from 0 to 9.
advertisement

b) Clock frequency
c) Counter modulus
d) Clock count
a) 4
b) 8
c) 16
d) 32
advertisement
a) Each flip-flop
applications
a) Ripple counter
b) Ring counter
c) Modulus counter
occurs?

advertisement
a) 4
b) 8
c) 5
d) 10
a) 0000
b) 1010
c) 1001
d) 1111
a) 2
b) 4
c) 8
d) 16
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
advertisement
a) 1
b) 2
c) 8
d) 15
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) 10
b) 20
c) 100
d) 1000
a) Each flip-flop
advertisement
a) 3
b) 6
c) 8
d) 16
switch ____________
a) HIGH
c) To an open
d) LOW
ICs”.
a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
advertisement
a) 1
b) 4
c) 2
d) 8
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
5. IC 7493 consist of ____________
a) 4 S-R flip-flop
b) 4 J-K flip-flop
d) 4 D flip-flop
advertisement

counter.
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
advertisement
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
7493 FF.
a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
advertisement
division.
a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12

advertisement
– 1) to 0).
3. UP Counter is ____________

a) 2
b) 4
c) 6
d) 8
advertisement
a) MSB flip-flop
b) LSB flip-flop
d) Latch
a) 000
b) 111
c) 010
d) 101
____________
a) 000
b) 111
c) 101
d) 010
becomes 111.
____________
a) 000
b) 111
c) 101
d) 010
becomes 101.
advertisement
a) 3CB0
b) 3C66
c) 63C0
d) 6300
are toggling
advertisement
advertisement
a) Count up
b) Count down
____________
c) The system clock
a) Synchronous
b) Bean
c) Decade
d) BCD
a) 74134
b) LPM
c) Synchronous
d) AHDL
advertisement
a) 3
b) 8
c) 5
d) 10
a) 20%
b) 50%
c) 10%
d) 80%
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
a) 8
b) 4
c) 16
d) 32
advertisement
a) Ring counter
b) Ripple counter

a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
fundamental mode.
advertisement

a) Each flip-flop
advertisement
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
a) Each flip-flop

a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
advertisement
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
= 1/200ns = 5 MHz.
a) Strobing
b) Feeding
c) Wagging
d) Waving
advertisement
c) It is very fast
c) Stop counting
previous flip-flop.
advertisement
a) Latches
b) Flip-flops
c) UP counter

advertisement
a) Dual counter
b) Multi counter
d) Two Counter
well as downwards.
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
advertisement
a) Starts counting
b) Can be reversed
d) Can be altered
a) 2
b) 3
c) 4
d) 5
required.
a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
a) 8
b) 9
c) 11
d) 15
advertisement
________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Hence, f = 10/8 = 1.25 kHz.
advertisement
Answers.
another.
advertisement
c) CPU
d) Latches
inputs.
a) 2
b) 3
c) 4
d) 5
a) Delay
b) Decrement
c) Data
d) Decay
advertisement
a) Data register
b) Binary register
c) Shift register
d) D – Register
a) 2
b) 3
c) 4
d) 5
advertisement
b) simultaneously

Registers”.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Tristate
b) End around
c) Universal
d) Conversion
advertisement
a) 01110
b) 00001
c) 00101
d) 00110
01110->initial
01011->second
00101->third.
a) 1100
b) 0011
c) 0000
d) 1111
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
a) 0000
b) 1111
c) 0111
d) 1000
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
sec.
advertisement
(td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
a) Ring shift
b) Clock
c) Johnson
d) Binary
advertisement
a) 1101
b) 0111
c) 0001
d) 1110
1011 | 1101
clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
a) 2
b) 3
c) 4
d) 5
advertisement
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms

a) HIGH, LOW, float
b) High-Z, 0, float
d) 1, Low-Z, float
output device
advertisement
b) A ring is faster
manner.
advertisement
input.
a) 1110
b) 0111
c) 1000
d) 1001
Explanation: Given,
111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
a) 1110
b) 0001
c) 1100
d) 1000
are 0001.
a) 10111000
b) 10110111
c) 11110000
d) 11111100

simultaneously.
advertisement
a) 1
b) 3
c) 4
d) 8
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
a) One bit
b) Two bits
c) Four bits
d) Eight bits
them.
advertisement

counters.
advertisement
d) The clock input

out.
a) UART
b) Key matrix
c) Memory chip
advertisement
a) All FFs set to 1

c) Strobe line
d) Multiplexer
advertisement
a) Circulating gate
b) Transceiver
d) Strobed latch
1. Memory is a/an ___________
advertisement
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
required.
information.
a) Data
b) Word
c) Nibble
16-bits or 2-bytes.
advertisement
a) A small display
a) Large memory
b) Small memory
c) Core memory
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
memory.
advertisement
a) NMOS
b) CMOS
c) BJT

a) Floppy disk
d) Control Unit
desired data word.
advertisement
a) EROM
b) RAM
c) PROM
d) EEPROM
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
b) Read Out Memory
c) Read Only Memory
d) Read One Memory
advertisement
a) PROM
b) EPROM
c) CDROM
d) PLA
process.
the user.
advertisement
a) PAL
b) PLA
c) APL
d) PPL
a) PAL
b) PPL
c) PLA
d) APL
a) ISAC
b) ASIC
c) SACC
d) CISF
advertisement
a) EPROM
b) FPGA
d) ROM

advertisement
a) 3
b) 4
c) 5
d) 6
Memory.
advertisement
a) Registers
b) Main Memory
c) RAM
b) Within RAM
c) Within ROM
d) Within CPU
a) RAM
b) ROM
c) Registers
d) Flag
a) Registers
b) Semiconductors
c) Counters
d) PLDs
advertisement
a) Secondary Memory
b) Auxiliary Memory
c) Static Memory
a) Main Memory
b) Secondary Memory
c) Static Memory
d) Volatile Memory
a) Floppy disk
b) Magnetic drum
c) Hard disk
a) 2
b) 3
c) 4
d) 5
advertisement
a) Floppy disk
b) Hard disk
d) RAM
a) Floppy disk
b) Hard disk
advertisement
and Answers.

advertisement
a) 1
b) 2
c) 3
d) 4
a) CCD
d) Floppy-Disk
advertisement
b) Read Only Memory
a) 2
b) 3
c) 4
d) 5
advertisement
to hold the data.
__________
a) PLD
b) LSI
c) VLSI
advertisement

a) Bus collisions
c) Address decoding
d) Bus contention
advertisement
a) Unit cells
b) Storage cells
c) Data cells
d) Binary cells
a) Storage cells
b) Data cells
c) Unit cells
a) Nibble
b) Word
c) Byte
d) Address
a) Letters
b) Binary numbers
d) Gray codes
bits or 2-bytes.
advertisement
a) RAM
b) ROM
c) Storage class
d) Address
or 2-bytes.
a) Nibble
b) Flag
c) Byte
d) Word
a) Control lines
and received.
advertisement
b) Tracks per inch

d) Rotation speed
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
advertisement

d) Erase operation
4. The ROM is a ___________
c) Magnetic circuit
d) Static circuit
not past states.
b) NOR and decoder
d) NAND and decoder
advertisement
a) Memory unit
b) Storage class
c) Data word
d) Address
a) Zip
b) Hard disk
c) Super Disk
d) Jaz
a) Memory unit
b) Storage class
c) Data word
d) Address
advertisement
a) NMOS
b) CMOS
c) BJT
a) 2
b) 3
c) 4
d) 5
advertisement
a) FETs
b) Transistors
c) MOSFETs
d) BJTs
more efficient.
a) 8 bits
b) 12 bits
c) 16 bits
d) 32 bits
advertisement
a) Extended
b) Expanded
c) Base
d) Conventional
a) Address bus
b) System bus
c) Control bus
d) Data bus
a) Platter
b) Read/Write
c) Valve
d) Spindle
advertisement
a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
more efficient.
a) Cluster
b) Read/Write
c) Cylinder
d) Recordable
a) EEPROM
b) Mask ROM
c) EPROM
d) PROM
advertisement
c) RAM and ROM
programmed.
a) 2
b) 3
c) 4
d) 5
advertisement
a) Mask Programming
b) PROM
d) EPROM
a) Photo
b) Negative
c) Mask
d) Virtual image
a) EPROM
b) PROM
a) 8 bits
b) 16 bits
c) 128 bits
d) 64 bits
advertisement
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
MSI/TTL based.
7. IC 74187 is of __________
a) 512 bits
b) 1024 bits
c) 256 bits
d) 68 bits
a) 128, 3
b) 128, 4
c) 256, 3
d) 256, 4
a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186

a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
advertisement
a) 16
b) 32
c) 64
d) 8
a) TMS 45276
b) TMS 45278
c) TMS 45279
d) TMS 45275
13. TMS 45276 is of __________
a) 32 KB
b) 56 KB
c) 8 bits
d) 4 bytes
a) TMS 45276
b) IC 74188
c) IC 74187
d) IC 74185
organization.
a) Storing Capacity
b) Custom Select
c) Chip Select
d) Custom Storage
advertisement
c) Code conversion
b) Data hold
c) Read cycle time
d) Access time
advertisement
a) ROM
b) EPROM
c) PROM
d) EEPROM
a) 4096
b) 16384
c) 32768
d) 8129
advertisement
of eight bits?
a) Eight
b) Two
c) One
d) Four
c) Command code
advertisement
a) 8 locations
b) 256 locations
c) 65,536 locations
locations = 28.
a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
advertisement
a) 2
b) 3
c) 4
d) 5
a) Polycrystalline
c) Nichrome
d) Silicon dioxide
c) Nichrome
d) Silicon dioxide
advertisement
a) EPROM programmer
c) PROM programmer
d) ROM programmer
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
advertisement
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
rows and 8 columns.
7. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
a) 165,667
b) 245,784
c) 262,144
d) 212,342
a) 10
b) 11
c) 12
d) 13
advertisement
a) 1024
b) 4096
c) 2048
d) 8192
8192 bit.

advertisement
a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell
d) Memory mapping
user.
advertisement
a) 0
b) 1
c) Both 0 and 1
a) Reprogrammed
b) Restarted
c) Charged
d) Power off
c) It is volatile
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
advertisement
a) 1024
b) 512
c) 2516
d) 256
a) HIGH
b) LOW
a) Power is on
b) Power is off
c) System is down
this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Explanation: 8K = 8 * 1024 = 8192.
advertisement
b) Faulty
c) Probably good
advertisement
a) RAM
b) FPROM
c) EEPROM
d) ROM
a) RAM
b) ROM
c) PROM
d) EPROM
a) RWM
b) MBR
c) MAR
d) ROM
Read Write Memory).
advertisement
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
a) MBR
b) MAR
c) RAM
d) ROM
a) Data buffer
b) Chip select
c) Read and write
d) Memory
respectively.
a) High complexity
b) High resolution

d) High flexibility
advertisement
a) 2
b) 3
c) 4
d) 5
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
operation.
a) ROM
b) EROM
c) PROM
d) RAM
advertisement
a) 32 bit to 64 bit
advertisement

a) Activated
b) Deactivated
c) Unaffected
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
advertisement
6. IC 7489 is of ____________
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
a) Chip select
b) Enable
c) Data input
d) Memory enable
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
a) 1946
b) 1948
c) 1947
d) 1945
advertisement
a) SRAM
b) DRAM
c) EEPROM
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
locations.
a) 1024 * 4
b) 1024 * 8
c) 2048 * 4
d) 2048 * 8
locations.
advertisement
a) 10
b) 9
c) 12
d) 11
locations.
a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional

advertisement
a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
memories.
advertisement
a) Cache
b) Dynamic RAM
c) Static RAM
a) SRAM
b) DRAM
c) Magnetic memory
d) Main Memory
advertisement
d) Has higher speed
a) RAM and ROM
b) CPU and RAM
d) CPU and ROM

a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile
advertisement
a) 10240
b) 15289
c) 16384
d) 17654
bits.

a) 2114
b) 7489
c) 4116
d) 2776
advertisement

a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
a) 3
b) 2
c) 1
d) 4
a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM
advertisement
a) Scratch-pad
b) Buffer
c) Main memory
a) ROM
b) RAM
c) EROM
d) PROM
advertisement
a) ROM
b) RAM
c) EROM
d) PROM
operation.
__________
a) PROM
b) Main Memory
d) Mass memory
12. CD-ROM is a __________
a) Memory register
b) Magnetic memory
a) A bit
b) A record
c) An address
d) A byte
advertisement
a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM
advertisement
d) Data insertion
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
per word.
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2
advertisement
a) 1
b) 2
c) 3
d) 4
a) 4
b) 6
c) 8
d) 12
chips.
a) 2
b) 4
c) 6
d) 8

a single chip.
advertisement
a) Flip-flops
b) Gates
c) Registers
a) RAM
b) ROM
c) PLD
d) PLA
a) High reliability

advertisement
a) 2
b) 3
c) 4
d) 5

a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
advertisement
2. PAL refers to ____________
a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
4. PLA contains ____________
advertisement
a) PLA
b) PAL
c) CPLD
d) SLD
b) AND/OR arrays
(FPGAs).
a) SLD
b) SROM
c) EPROM
d) PLD
advertisement

AND plane
AND plane
advertisement
a) A line
b) A channel
c) A strobe
d) A flip-flop
a) Registered PALs
c) PAL programming
Q1. The binary number 10101 is equivalent to decimal number …………..
1. 19
2. 12
3. 27
4. 21
Answer : 4
Q2. The universal gate is ………………
1. NAND gate
2. OR gate
3. AND gate
4. None of the above
Answer : 1
Q3. The inverter is ……………
1. NOT gate
2. OR gate
3. AND gate
Answer : 1
Q4. The inputs of a NAND gate are connected together. The resulting circuit is ………….
1. OR gate
2. AND gate
3. NOT gate
Answer : 3
Q5. The NOR gate is OR gate followed by ………………
1. AND gate
2. NAND gate
3. NOT gate
Answer : 3
Q6. The NAND gate is AND gate followed by …………………
1. NOT gate
2. OR gate
3. AND gate
Answer : 1
Q7. Digital circuit can be made by the repeated use of ………………
1. OR gates
2. NOT gates
3. NAND gates
Answer : 3
Q8. The only function of NOT gate is to ……………..
1. Stop signal
2. Invert input signal
3. Act as a universal gate
Answer : 2
Q9. When an input signal 1 is applied to a NOT gate, the output is
………………
1. 0
2. 1
3. Either 0 & 1
Answer : 1
Q10. In Boolean algebra, the bar sign (-) indicates ………………..
1. OR operation
2. AND operation
3. NOT operation
Answer : 3
Q11. The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value of n is …….
1. 8
2. 9
3. 10
4. 11
Answer : 3
Explanation:
(5/2N-1)1000 = 5 or N = 10
Q12. 2’s complement of binary number 0101 is ………..
1. 1011
2. 1111
3. 1101
4. 1110
Answer : 1
Explanation: 1’s complement of 0101 is 1010 and 2’s complement is 1010+1 = 1011.
Q13. An OR gate has 4 inputs. One input is high and the other three are low. The output is …….
1. Low
2. High
3. alternately high and low
4. may be high or low depending on relative magnitude of inputs
Answer : 2
Explanation: In OR any input high means high output.
Q14. Decimal number 10 is equal to binary number ……………
1. 1110
2. 1010
3. 1001
4. 1000
Answer : 2
Explanation: 1010 = 8 + 2 = 10 in decimal.

Q15. Both OR and AND gates can have only two inputs.
1. True
2. False
Answer : 2
Explanation: Any number of inputs are possible.
Q16. A device which converts BCD to seven segments is called ……..
1. Encoder
2. Decoder
3. Multiplexer
4. None of these
Answer : 2
Explanation: Decoder converts binary/BCD to alphanumeric.
Q17. In 2’s complement representation the number 11100101 represents the decimal number ……………
1. +37
2. -31
3. +27
4. -27
Answer : 4
Explanation:
A = 11100101. Therefore Ā = 00011010 and A’ = Ā + 1 = 00011011 = 16 + 8 + 2 + 1 = 27. Therefore A = -27.
Q18. A decade counter skips ………..
1. binary states 1000 to 1111
4. binary states 1111 to higher
Answer : 3
Explanation: A decade counter counts from 0 to 9. It has 4 flip-flops. The states skipped are 10 to 15 or 1010 to 1111.
Q19. BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment decoder/driver. The segments which
will lit up are ………….
1. a, b, d
2. a, b, c
3. all
4. a, b, g, c, d
Answer : 3
Explanation: 1000 equals decimal 8 Therefore all segments will lit up.
Q20. A ring counter with 5 flip flops will have ………. states.
1. 5
2. 10
3. 32
4. Infinite
Answer : 1
Q21. For the gate in the given figure the output will be ………..
1. 0
2. 1
3. A
4. Ā
Answer : 4
Explanation: If A = 0, Y = 1 and A = 1, Y = 0 Therefore Y = Ā.
Q22. In the expression A + BC, the total number of minterms will be ………
1. 2
2. 3
3. 4
4. 5
Answer : 4
Q23. The circuit in the given figure is a ………… gate.
1. positive logic OR gate
2. negative logic OR gate
3. negative logic AND gate
4. positive logic AND gate

Answer : 2
Explanation: Since V(1) is lower state than V(0) it is a negative logic circuit. Since diodes are in parallel, it is an OR
gate.
Q24. Which of the following is non-saturating?
1. TTL
2. CMOS
3. ECL
4. Both 1 and 2
Answer : 3
Q25. The number of digits in octal system is ………
1. 8
2. 7
3. 9
4. 10
Answer : 1
Explanation: The octal system has 8 digits 0 to 7.
Q16.
Answer : 2
Explanation:
Q26. The access time of a word in 4 MB main memory is 100 ms. The access time of a word in a 32 kb data cache
memory is 10 ns. The average data cache bit ratio is 0.95. The efficiency of memory access time is ………
1. 9.5 ns
2. 14.5 ns
3. 20 ns
4. 95 ns
Answer : 2
Explanation: Access time = 0.95 x 10 + 0.05 x 100.
Q27. The expression Y = pM (0, 1, 3, 4) is …………..
1. POS
2. SOP
3. Hybrid
4. none of these
Answer : 1
Explanation: This is a product of sums expression.
Q28. An 8 bit DAC has a full scale output of 2 mA and full scale error of ± 0.5%. If input is 10000000 the range of
outputs is ………….
1. 994 to 1014 μA
2. 990 to 1020 μA
3. 800 to 1200 μA
4. none of the above
Answer : 1
Explanation:
Q29. Decimal 43 in hexadecimal and BCD number system is respectively……. and ……..
1. B2 and 01000011
2. 2B and 01000011
3. 2B and 00110100
4. B2 and 01000100
Answer : 2
Explanation:
Q30. The circuit of the given figure realizes the function …………
Answer : 1
Explanation:
Q31. An AND gate has two inputs A and B and one inhibit input 3, Output is 1 if
1. A = 1, B = 1, S = 1
2. A = 1, B = 1, S = 0
3. A = 1, B = 0, S = 1
4. A = 1, B = 0, S = 0
Answer: 2
Explanation: All AND inputs must be 1 and inhibit 0 for output to be 1.
Q32. The greatest negative number which can be stored is 8 bit computer using 2’s complement arithmetic is ……..
1. -256
2. -128
3. -255
4. -127
Answer: 2
Explanation: The largest negative number is 1000 0000 = -128.
Q33. A JK flip flop has tpd= 12 ns. The largest modulus of a ripple counter using these flip flops and operating at 10
MHz is ……..
1. 16
2. 64
3. 128
4. 256
Answer: 4
Explanation:
Q34. The basic storage element in a digital system is ………….
1. flipflop
2. counter
3. multiplexer
4. encoder
Answer : 1
Explanation: Storing can be done only in memory and flip-flop is a memory element.
Q35. In a ripple counter,
1. whenever a flipflop sets to 1, the next higher FF toggles
2. whenever a flipflop sets to 0, the next higher FF remains unchanged
3. whenever a flipflop sets to 1, the next higher FF faces race condition

Answer : 1
Explanation: In a ripple counter the effect ripples through the counter.
Q36. A 12 bit ADC is used to convert analog voltage of 0 to 10 V into digital. The resolution is ……….
1. 2.44 mV
2. 24.4 mV
3. 1.2 V
4. none of these
Answer : 1
Explanation:
Q37. For the truth table of the given figure Y = ………….
1. A + B + C
2. Ā +BC
3. Ā
4. B¯
Answer : 4
Explanation:
Q38. A full adder can be made out of …………
1. two half adders
2. two half adders and a OR gate
3. two half adders and a NOT gate
4. three half adders
Answer : 2
Q39. If the functions w, x, y, z are as follows
1. w = z x = z
2. w = z, x = y
3. w = y
4. w = y = z
Answer : 1
Q40. The output of a half adder is ……….
1. Sum
2. Sum and Carry
3. Carry
4. none of these
Answer: 2
Q41. Minimum number of 2-input NAND gates required to implement the function F = (x + y) (Z + W) is ………..
1. 3
2. 4
3. 5
4. 6
Answer : 2
Explanation:
Q42. Which device has one input and many outputs?
1. Multiplexer
2. Demultiplexer
3. Counter
4. Flip flop
Answer: 2
Explanation: Demultiplexer takes data from one line and directs it to any of its N output depending on the status of
its select lines.
Q43. A carry look ahead adder is frequently used for addition because
1. it costs less
2. it is faster
3. it is more accurate
4. uses fewer gates
Answer: 2
Explanation:
Q27.
Answer : 1
Explanation: In look ahead carry adder the carry is directly derived from the gates when original inputs are being
added. Hence the addition is fast. This process requires more gates and is costly.
Q44. The counter in the given figure is ………….
1. Mod 3
2. Mod 6
3. Mod 8
4. Mod 7
Answer : 2
Explanation: When counter is 110 the counter resets. Hence mod 6.

Q45. In register index addressing mode the effective address is given by ……..
1. index register value
2. sum of the index register value and the operand
3. operand
4. difference of the index register value and the operand
Answer : 2
Explanation:
4 = 22, in up scaling digit will be shifted by two bit in right direction.
Q46. 7BF16 = ____ 2
1. 0111 1011 1110
2. 0111 1011 1111
3. 0111 1011 0111
4. 0111 1011 0011
Answer : 2
Explanation:
7BF16 = 7 x 162 + 11 x 161 + 15 x 160 = 1983 in decimal = 0111 1011 1111 in binary.
Q47. For the minterm designation Y = ∑ m (1, 3, 5, 7) the complete expression is …………..
Answer : 2
Explanation:
Q48. Zero suppression is not used in actual practice.
1. True
2. False
Answer: 2
Explanation: Zero suppression is commonly used.

Q49. A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then
conversion time is ………..
1. 8 μ sec
2. 10 μ sec
3. 2 μ sec
4. 5 μ sec
Answer : 1
Explanation:
Q50. The hexadecimal number (3E8)16 is equal to decimal number ………
1. 1000
2. 982
3. 768
4. 323
Answer : 1
Explanation: 3 x 162 + 14 x 161 + 8 = 1000
Which of the Following represents Commutative Law? *
1/1
A+B=B+A
A + (B + C) = (A + B) + C
A(B + C) = AB + AC
None of the Above
Simplify the equation given below using Boolean Algebra *
0/2
Captionless Image
Option 1
Option 2
Option 3
Correct answer
Option 3
Simplify the equation given below using Boolean Law ? *
2/2
Captionless Image
Which of the Following represents NOR as OR *
0/2
Option 1
Option 2
Option 3
None of the above
Correct answer
Option 2
Universal Gates are *
0/1
Ex-OR and EX-NOR
NAND and NOR
All the above
None of the Above
Correct answer
NAND and NOR
Identify the IC Number? *
0/2
Captionless Image
IC 7400
IC 7402
IC 7408
IC 7432
Correct answer
IC 7402
Which of the Following is the Truth table for Demorgan's 2nd Theorem? *
2/2
Option 1
Option 2
Option 3
None of the above
What is the Logic for the given truth Table? *
2/2
Captionless Image
When Both the inputs are high, output is high
When any one input is high, output is high
When any one input is low, output is low
When any one input is low, output is high
To which Gate does this Truth Table Belong? *
2/2
Captionless Image
OR Gate
EX-OR Gate
NAND Gate
EX-NOR Gate
Why NAND and NOR are called as Universal Gate ? *
0/1
They are Universally Accepted over the Globe
Using them any Digital Circuit can be Implemented
They are the Basic Building block of any Digital Circuit
All the Above
Correct answer
Using them any Digital Circuit can be Implemented

Simplify the equation given below using Boolean Law? *
0/2
Captionless Image
AB
A+B
Correct answer
To implement using NAND gate, what will be the equation? *
0/2
Captionless Image
Option 1
Option 2
Option 3
None of the Above
Correct answer
Option 3
What is the Equation for the Gate given below? *
0/1
Captionless Image
Option 1
Option 2
Option 3
Option 4
Correct answer
Option 4
What is the IC number for the given equation? *
0/2
Captionless Image
IC 7400
IC 7402
IC 7486
IC 7432
Correct answer
IC 7400
Demorgan's First Theorem States that *
1/1
Complement of Product is Equivalent to Sum of Individual Complements
Product of Individual Complement is Equal to Complement of Sums
Complement of Sums is equal to Complement of Products
All the above
What is the Output Z? *
0/3
Captionless Image
Option 1
Option 2
Option 3
Option 4
Correct answer
Option 4
Identify the IC Number? *
0/1
Captionless Image
IC 7432
IC 74266
IC 7404
IC 7402
Correct answer
IC 74266
What is the Output Equation? *
0/3
Captionless Image
Option 1
Option 2
Option 3
Option 4
Correct answer
Option 2
Which of the Following represents NAND as OR? *
0/2
Option 1
Option 2
Option 3
None of the Above
Correct answer
Option 3
Which one of the following is True ? *
0/1
A+A = A
A+1 = A
Option 3
A+0 = 0
All the Above
Correct answer
A+A = A
Msbtenews.com
22320 Digital Techniques Mcq Test Papers

De Morgan‟s 2nd Theorem states that Complement of sum is equal to product of their
individual complements
(a) True
(b) False Answer
Reason: De Morgan‟s 2nd Theorem states that Complement of product is equal to sum of
their individual complement
In a ring counter if the output of any stage is 1, then its remainder is 1?

(a) True
(b) False Answer
Reason: In ring counter if the output of any stage is 1, then its reminder is 0
The Ring counters transfers the same output throughout the circuit
(a) True Answer
(b) False
Memory required electrical power to keep information stored is called non-volatile memory
(a) True
(b) False
Reason: Memory that will keep storing its information without the need of electrical power is
called nonvolatile memory.
ROMs, EPROM, magnetic memories are examples of Volatile memory?

(a) True
(b) False Answer
Reason: All RAMs are Volatile memory
Volatile memory is used for temporary storage?

(a) True Answer
(b) False
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are
equal to logic level “1”
(a) True Answer
(b) False
EPROM stands for Electrically Erasable Programmable Read-Only Memory.

(a) True
(b) False Answer
Reason: EPROM stands for Erasable Programmable ReadOnly Memory
EPROM is a modern version of PROM.
(a) True Answer
(b) False
Fan-in is a term that defines the maximum number of digital inputs that a single logic gate
can accept.
(a) True Answer
(b) False
Fan-out is a term that defines the maximum number of digital inputs that the output of a
single logic gate can feed.
(a) True Answer
(b) False
In synchronous counter Decoding errors are present?

(a) True
(b) False Answer
Reason: In synchronous counter Decoding errors are not present
Linearity is defined as the relation between the digital input and analog output should be
linear?
(a) True Answer
(b) False
An encoder is a device or circuit that converts information from one format or code to
another, for the purpose of standardization, speed or compression?
(a) True Answer
(b) False
Power Dissipation is the amount of power dissipated in an IC

(a) True Answer
(b) False
Basic gates of ECL

(a) OR/NOR Answer
(b) NOT
(c) Ex-OR
(d) NAND
Propagation delay of TTL

(a) 2
(b) 4
(c) 8
(d) 10 Answer
Fan out of TTL
(a) 5
(b) 10 Answer
(c) 15
(d) 20
Power Dissipation of TTL

(a) 5 mW
(b) 10mW Answer
(c) 15mW
(d) 20mW
Power Dissipation of CMOS

(a) 0.75 mW
(b) 0.95mW
(c) 1.01mW Answer
(d) 1.25mW
Noise Immunity of CMOS

(a) 5V Answer
(b) 10V
(c) 15V
(d) 20V
Noise Immunity of ECL

(a) 0.25V Answer
(b) 0.50V
(c) 0.75V
(d) 1V
State the necessity of multiplexer

(a) For simplifying logic design
(b) It reduces the number of wires required to pass data from source to destination.
(c) For minimizing the hardware circuit
(d) Reduces the cost as sending many signals separately is expensive and requires more
wires to send.
(e) All of the above Answer
How many flip flops are required for a Mod-6 counter?

(a) 2
(b) 3 Answer
(c) 4
(d) 5
_______is used to erase the content of EPROM?
(a) electrical signal.
(b) Magnetic signal
(c) Ultraviolet Light
(d) Both (b) & (c) Answer
For more Msbte Mcq test papers visit msbtenews.com

MeritNotes.com
Digital Electronics Questions and Answers Pdf
Question: 1
Which of the following is not an analog device?

(A) Audio microphone
(B) Light switch
(C) Current flow in a circuit
(D) Thermocouple
Ans: B
Light switch
Question: 2
Which of the following gates has the exact inverse output of

the OR gate for all possible input combinations?
(A) AND
(B) NOT
(C) NOR
(D) NAND
Ans: C
NOR
Question: 3
Full adder is used to

(A) 2 bit addition
(B) 3 bit addition
(C) 4 bit addition
(D) 6 bit addition
Ans: B
3 bit addition
Question: 4
Which format requires fewer conductors?

(A) Perpendicular
(B) Parallel
(C) Serial
(D) Both are the same
Ans: C
Serial
Question: 5
The systematic reduction of logic circuits is accomplished by

(A) Using a truth table
(B) TTL logic
(C) Symbolic reduction
(D) Using Boolean algebra
Ans: D
Using Boolean algebra

Q1. The binary number 10101 is equivalent to decimal number …………..
1. 19
2. 12
3. 27
4. 21
Answer : 4
1. NAND gate
2. OR gate
3. AND gate
Answer : 1
1. NOT gate
2. OR gate
3. AND gate
Answer : 1
Q4. The inputs of a NAND gate are connected together. The resulting circuit is
………….
1. OR gate
2. AND gate
3. NOT gate
Answer : 3
1. AND gate
2. NAND gate
3. NOT gate
Answer : 3
1. NOT gate
2. OR gate
3. AND gate
Answer : 1
1. OR gates
2. NOT gates
3. NAND gates
Answer : 3
1. Stop signal
Answer : 2
Q9. When an input signal 1 is applied to a NOT gate, the output is ………………
1. 0
2. 1
3. Either 0 & 1
Answer : 1
1. OR operation
2. AND operation
3. NOT operation
Answer : 3
Q11. The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value
of n is …….
1. 8
2. 9
3. 10
4. 11
Answer : 3
Explanation:
(5/2N-1)1000 = 5 or N = 10
1. 1011
2. 1111
3. 1101
4. 1110
Answer : 1
Explanation: 1’s complement of 0101 is 1010 and 2’s complement is 1010+1 = 1011.
Q13. An OR gate has 4 inputs. One input is high and the other three are low. The
output is …….
1. Low
2. High
Answer : 2
1. 1110
2. 1010
3. 1001
4. 1000
Answer : 2
1. True
2. False
Answer : 2
Q16. A device which converts BCD to seven segments is called ……..
1. Encoder
2. Decoder
3. Multiplexer
4. None of these
Answer : 2
Q17. In 2’s complement representation the number 11100101 represents the decimal
number ……………
1. +37
2. -31
3. +27
4. -27
Answer : 4
Explanation:
A = 11100101. Therefore Ā = 00011010 and A’ = Ā + 1 = 00011011 = 16 + 8 + 2 + 1 = 27. Therefore

A = -27.

Answer : 3
Explanation: A decade counter counts from 0 to 9. It has 4 flip-flops. The states skipped are 10
to 15 or 1010 to 1111.
Q19. BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment
decoder/driver. The segments which will lit up are ………….
1. a, b, d
2. a, b, c
3. all
4. a, b, g, c, d
Answer : 3
1. 5
2. 10
3. 32
4. Infinite
Answer : 1
1. 0
2. 1
3. A
4. Ā
Answer : 4
Q22. In the expression A + BC, the total number of minterms will be ………
1. 2
2. 3
3. 4
4. 5
Answer : 4

Answer : 2
Explanation: Since V(1) is lower state than V(0) it is a negative logic circuit. Since diodes are in
parallel, it is an OR gate.
1. TTL
2. CMOS
3. ECL
4. Both 1 and 2
Answer : 3
1. 8
2. 7
3. 9
4. 10
Answer : 1
Q16.
Answer : 2
Explanation:
Q26. The access time of a word in 4 MB main memory is 100 ms. The access time of a
word in a 32 kb data cache memory is 10 ns. The average data cache bit ratio is 0.95.
The efficiency of memory access time is ………
1. 9.5 ns
2. 14.5 ns
3. 20 ns
4. 95 ns
Answer : 2
1. POS
2. SOP
3. Hybrid
4. none of these
Answer : 1
Q28. An 8 bit DAC has a full scale output of 2 mA and full scale error of ± 0.5%. If
input is 10000000 the range of outputs is ………….
1. 994 to 1014 μA
2. 990 to 1020 μA
3. 800 to 1200 μA
Answer : 1
Explanation:
Q29. Decimal 43 in hexadecimal and BCD number system is respectively……. and
……..
1. B2 and 01000011
2. 2B and 01000011
3. 2B and 00110100
4. B2 and 01000100
Answer : 2
Explanation:
Answer : 1
Explanation:
Q31. An AND gate has two inputs A and B and one inhibit input 3, Output is 1 if
1. A = 1, B = 1, S = 1
2. A = 1, B = 1, S = 0
3. A = 1, B = 0, S = 1
4. A = 1, B = 0, S = 0
Answer: 2
Q32. The greatest negative number which can be stored is 8 bit computer using 2’s
complement arithmetic is ……..
1. -256
2. -128
3. -255
4. -127
Answer: 2
Q33. A JK flip flop has tpd= 12 ns. The largest modulus of a ripple counter using these
flip flops and operating at 10 MHz is ……..
1. 16
2. 64
3. 128
4. 256
Answer: 4
Explanation:
1. flipflop
2. counter
3. multiplexer
4. encoder
Answer : 1
Explanation: Storing can be done only in memory and flip-flop is a memory element.

2. whenever a flipflop sets to 0, the next higher FF remains unchanged
Answer : 1
Q36. A 12 bit ADC is used to convert analog voltage of 0 to 10 V into digital. The
resolution is ……….
1. 2.44 mV
2. 24.4 mV
3. 1.2 V
4. none of these
Answer : 1
Explanation:
1. A + B + C
2. Ā +BC
3. Ā
4. B¯
Answer : 4
Explanation:
1. two half adders

Answer : 2
1. w = z x = z
2. w = z, x = y
3. w = y
4. w = y = z
Answer : 1
1. Sum
2. Sum and Carry
3. Carry
4. none of these
Answer: 2
Q41. Minimum number of 2-input NAND gates required to implement the function F
= (x + y) (Z + W) is ………..
1. 3
2. 4
3. 5
4. 6
Answer : 2
Explanation:
1. Multiplexer
2. Demultiplexer
3. Counter
4. Flip flop
Answer: 2
Explanation: Demultiplexer takes data from one line and directs it to any of its N output
depending on the status of its select lines.
Q43. A carry look ahead adder is frequently used for addition because
1. it costs less
2. it is faster
4. uses fewer gates
Answer: 2
Explanation:
Q27.
Answer : 1
Explanation: In look ahead carry adder the carry is directly derived from the gates when original
inputs are being added. Hence the addition is fast. This process requires more gates and is costly.

1. Mod 3
2. Mod 6
3. Mod 8
4. Mod 7
Answer : 2
Q45. In register index addressing mode the effective address is given by ……..

3. operand
Answer : 2
Explanation:
Q46. 7BF16 = __________ 2
1. 0111 1011 1110

2. 0111 1011 1111
3. 0111 1011 0111
4. 0111 1011 0011
Answer : 2
Explanation:
7BF16 = 7 x 162 + 11 x 161 + 15 x 160 = 1983 in decimal = 0111 1011 1111 in binary.
Q47. For the minterm designation Y = ∑ m (1, 3, 5, 7) the complete expression is

…………..
Answer : 2
Explanation:
1. True
2. False
Answer: 2
Q49. A counter type A/D converter contains a 4 bit binary ladder and a counter
driven by a 2 MHz clock. Then conversion time is ………..
1. 8 μ sec
2. 10 μ sec
3. 2 μ sec
4. 5 μ sec
Answer : 1
Explanation:
Q50. The hexadecimal number (3E8)16 is equal to decimal number ………
1. 1000
2. 982
3. 768
4. 323
Answer : 1
Explanation: 3 x 162 + 14 x 161 + 8 = 1000
Q51. The number of distinct Boolean expression of 4 variables is …….
1. 16
2. 256
3. 1024
4. 65536
Answer : 4
Explanation:
Q52. For the K map in the given figure the simplified Boolean expression is ……
Answer : 1
Explanation:
Q53. A memory system of size 16 k bytes is to be designed using memory chips which
have 12 address lines and 4 data lines each. The number of such chips required to
design the memory system is ……….
1. 2
2. 4
3. 8
4. 18
Answer : 3
Explanation:
(16×1024×8)/(4096×4) = 8
Q54. In a 7 segment display, LEDs b and c lit up. The decimal number displayed is
……….
1. 9
2. 7
3. 3
4. 1
Answer : 1
Q55. In a BCD to 7 segment decoder the minimum and maximum number of outputs
active at any time is ….
1. 2 and 7
2. 3 and 7
3. 1 and 6
4. 3 and 6
Answer: 1
Explanation:
Minimum number of outputs when input is decimal 1 and maximum number of outputs when
input is decimal 8.
Q56. A three state switch has three outputs. These are …….. , …….. , ……….
1. low, low and high

2. low, high, high
3. low. floating, low
4. low, high, floating
Answer: 4
Q57. Maxterm designation for A + B + C is ……….
1. M0
2. M1
3. M3
4. M4
Answer: 1
Explanation: A + B + C = 000 = M0
Q58. 1’s complement of 11100110 is ……………….
1. 00011001
2. 10000001
3. 00011010
4. 00000000
Answer: 1
Explanation: By replacing 1 by 0 and 0 by 1.
1. Any number with an exponent of zero is equal to:

A.zero
B. one
C. that number
D.ten
Answer: Option B
Explanation:
No answer description available for this question. Let us discuss.

Workspace
Report errors
View Answer Discuss in Forum Workspace Report
2. In the decimal numbering system, what is the MSD?

A.The middle digit of a stream of numbers
B. The digit to the right of the decimal point
C. The last digit on the right
D.The digit with the most weight
Answer: Option D
Explanation:

Workspace
Report errors
3. Which of the following statements does NOT describe an advantage of digital technology?
A.The values may vary over a continuous range.
B. The circuits are less affected by noise.
C. The operation can be programmed.
D.Information storage is easy.
Answer: Option A
Explanation:

Workspace
Report errors
4. The generic array logic (GAL) device is ________.

A.one-time programmable
B. reprogrammable
C. a CMOS device
D.reprogrammable and a CMOS device
Answer: Option B
Explanation:

Workspace
Report errors
5. The range of voltages between VL(max) and VH(min) are ________.

A.unknown
B. unnecessary
C. unacceptable
D.between 2 V and 5 V
Answer: Option C
Explanation:
What are the symbols used to represent digits in the binary number system?
A.0,1
B. 0,1,2
C. 0 through 8
D.1,2
Answer: Option A
Explanation:

Workspace
Report errors
8. A full subtracter circuit requires ________.

A.two inputs and two outputs
B. two inputs and three outputs
C. three inputs and one output
D.three inputs and two outputs
Answer: Option D
Explanation:

Workspace
Report errors
9. The output of an AND gate is LOW ________.

A.all the time
B. when any input is LOW
C. when any input is HIGH
D.when all inputs are HIGH
Answer: Option B
Explanation:

Workspace
Report errors
10. Give the decimal value of binary 10010.

A.610
B. 910
C. 1810
D.2010
Answer: Option C
Explanation:
Parallel format means that:
A.each digital signal has its own conductor.
B. several digital signals are sent on each conductor.
C. both binary and hexadecimal can be used.
D.no clock is needed.
Answer: Option A
Explanation:

Workspace
Report errors
12. A decoder converts ________.

A.noncoded information into coded form
B. coded information into noncoded form
C. HIGHs to LOWs
D.LOWs to HIGHs
Answer: Option B
Explanation:

Workspace
Report errors
13. A DAC changes ________.

A.an analog signal into digital data
B. digital data into an analog signal
C. digital data into an amplified signal
D.none of the above
Answer: Option B
Explanation:

Workspace
Report errors
14. The output of a NOT gate is HIGH when ________.

A.the input is LOW
B. the input is HIGH
C. the input changes from LOW to HIGH
D.voltage is removed from the gate
Answer: Option A
Explanation:

Workspace
Report errors

15. The output of an OR gate is LOW when ________.
A.all inputs are LOW
B. any input is LOW
C. any input is HIGH
D.all inputs are HIGH
Answer: Option A
16. Which of the following is not an analog device?
A.Thermocouple
B. Current flow in a circuit
C. Light switch
D.Audio microphone
Answer: Option C
Explanation:

Workspace
Report errors
17. A demultiplexer has ________.

A.one data input and a number of selection inputs, and they have several outputs
B. one input and one output
C. several inputs and several outputs
D.several inputs and one output
Answer: Option A
Explanation:

Workspace
Report errors
18. A flip-flop has ________.

A.one stable state
B. no stable states
C. two stable states
D.none of the above
Answer: Option C
Explanation:

Workspace
Report errors
19. Digital signals transmitted on a single conductor (and a ground) must be transmitted in:
A.slow speed.
B. parallel.
C. analog.
D.serial.
Answer: Option D
Explanation:

Workspace
Report errors
20. In a certain digital waveform, the period is four times the pulse width. The duty cycle is ________.
A.0%
B. 25%
C. 50%
D.100%
Answer: Option B
In positive logic, ________.

A.a HIGH = 1, a LOW = 0
B. a LOW = 1, a HIGH = 0
C. only HIGHs are present
D.only LOWs are present
Answer: Option A
Explanation:

Workspace
Report errors
22. Convert the fractional binary number 0000.1010 to decimal.

A.0.625
B. 0.50
C. 0.55
D.0.10
Answer: Option A
Explanation:

Workspace
Report errors
23. Digital representations of numerical values of quantities may BEST be described as having
characteristics:
A.that are difficult to interpret because they are continuously changing.
B. that vary constantly over a continuous range of values.
C. that vary in constant and direct proportion to the values they represent.
D.that vary in discrete steps in proportion to the values they represent.
Answer: Option D
Explanation:

Workspace
Report errors
24. A common instrument used in troubleshooting a digital circuit is a(n) ________.

A.logic probe
B. oscilloscope
C. pulser
D.all of the above
Answer: Option D
Explanation:

Workspace
Report errors
25. The parallel transmission of digital data:

A.is much slower than the serial transmission of data.
B. requires only one signal line between sender and receiver.
C. requires as many signal lines between sender and receiver as there are data bits.
D.is less expensive than the serial method of data transmission.
Answer: Option C
Explanation:
If a 3-input NOR gate has eight input possibilities, how many of those
possibilities will result in a HIGH output?
A.1
B. 2
C. 7
D.8
Answer: Option A
Explanation:

Workspace
Report errors
3. If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output
is HIGH, the gate is a(n):
A.AND
B. NAND
C. NOR
D.OR
Answer: Option B
Explanation:

Workspace
Report errors
4. A device used to display one or more digital signals so that they can be compared to expected timing
diagrams for the signals is a:
A.DMM
B. spectrum analyzer
C. logic analyzer
D.frequency counter
Answer: Option C
Explanation:

Workspace
Report errors
5. When used with an IC, what does the term "QUAD" indicate?
A.2 circuits
B. 4 circuits
C. 6 circuits
D.8 circuits
Answer: Option B
The output of an OR gate with three inputs, A, B, and C, is LOW when ________.
A.A = 0, B = 0, C = 0
B. A = 0, B = 0, C = 1
C. A = 0, B = 1, C = 1
D.all of the above
Answer: Option A
Explanation:

Workspace
Report errors
7. Which of the following logical operations is represented by the + sign in Boolean algebra?
A.inversion
B. AND
C. OR
D.complementation
Answer: Option C
Explanation:

Workspace
Report errors
8. Output will be a LOW for any case when one or more inputs are zero for a(n):
A.OR gate
B. NOT gate
C. AND gate
D.NOR gate
Answer: Option C
Explanation:

Workspace
Report errors
9. How many pins does the 4049 IC have?

A.14
B. 16
C. 18
D.20
Answer: Option B
Explanation:

Workspace
Report errors
10. Which of the following choices meets the minimum requirement needed to create specialized
waveforms that are used in digital control and sequencing circuits?
A.basic gates, a clock oscillator, and a repetitive waveform generator
B. basic gates, a clock oscillator, and a Johnson shift counter
C. basic gates, a clock oscillator, and a DeMorgan pulse generator
D.basic gates, a clock oscillator, a repetitive waveform generator, and a Johnson shift counter
Answer: Option A
Explanation:
TTL operates from a ________.

A.9-volt supply
B. 3-volt supply
C. 12-volt supply
D.5-volt supply
Answer: Option D
Explanation:

Workspace
Report errors
12. The output of a NOR gate is HIGH if ________.

A.all inputs are HIGH
B. any input is HIGH
C. any input is LOW
D.all inputs are LOW
Answer: Option D
Explanation:

Workspace
Report errors
13. The switching speed of CMOS is now ________.

A.competitive with TTL
B. three times that of TTL
C. slower than TTL
D.twice that of TTL
Answer: Option A
Explanation:

Workspace
Report errors
14. The format used to present the logic output for the various combinations of logic inputs to a gate is
called a(n):
A.Boolean constant
B. Boolean variable
C. truth table
D.input logic function
Answer: Option C
Explanation:

Workspace
Report errors
15. The power dissipation, PD, of a logic gate is the product of the ________.
A.dc supply voltage and the peak current
B. dc supply voltage and the average supply current
C. ac supply voltage and the peak current
D.ac supply voltage and the average supply current
Answer: Option B
Explanation:

Workspace
Report errors
A logic probe is again applied to the pins of a 7421 IC with the

following results. Is there a problem with the circuit and if so, what
is the problem?
A.Pin 6 should be ON.

B. Pin 8 should be ON.
C. Pin 8 should be pulsing.
D.no problem
Answer: Option D
Explanation:

Workspace
Report errors
17. If a 3-input AND gate has eight input possibilities, how many of those possibilities will result in a HIGH
output?
A.1
B. 2
C. 7
D.8
Answer: Option A
Explanation:

Workspace
Report errors
18. The Boolean expression for a 3-input AND gate is ________.

A.X = AB
B. X = ABC
C. X = A + B + C
D.X = AB + C
Answer: Option B
Explanation:

Workspace
Report errors
19. A CMOS IC operating from a 3-volt supply will consume ________.

A.less power than a TTL IC
B. more power than a TTL IC
C. the same power as a TTL IC
D.no power at all
Answer: Option A
Explanation:

Workspace
Report errors
20. What does the small bubble on the output of the NAND gate logic symbol mean?
A.open collector output
B. tristate
C. The output is inverted.
D.none of the above
Answer: Option C
What are the pin numbers of the outputs of the gates in a 7432 IC?
A.3, 6, 10, and 13
B. 1, 4, 10, and 13
C. 3, 6, 8, and 11
D.1, 4, 8, and 11
Answer: Option C
Explanation:

Workspace
Report errors
22. The output of a NOT gate is HIGH when ________.

A.the input is LOW
B. the input is HIGH
C. power is applied to the gate's IC
D.power is removed from the gate's IC
Answer: Option A
Explanation:

Workspace
Report errors
23. If the input to a NOT gate is A and the output is X, then ________.
A.X = A
B.
C. X = 0
D.none of the above
Answer: Option B
Explanation:

Workspace
Report errors

24. A logic probe is used to test the pins of a 7411 IC with the following results. Is there a problem with the
chip and if so, what is the problem?
A.Pin 6 should be ON.

B. Pin 6 should be pulsing.
C. Pin 8 should be ON.
D.no problem
Answer: Option B
Explanation:

Workspace
Report errors
25. How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate to go
HIGH?
A.any one of the inputs
B. any two of the inputs
C. any three of the inputs
D.all four inputs
Answer: Option D
Explanation:
Determine the values of A, B, C, and D that make the sum term equal to zero.
A.A = 1, B = 0, C = 0, D = 0
B. A = 1, B = 0, C = 1, D = 0
C. A = 0, B = 1, C = 0, D = 0
D.A = 1, B = 0, C = 1, D = 1
Answer: Option B
Explanation:

Workspace
Report errors
3. Which of the following expressions is in the sum-of-products (SOP) form?

A.(A + B)(C + D)
B. (A)B(CD)
C. AB(CD)
D.AB + CD
Answer: Option D
Explanation:

Workspace
Report errors
4. Derive the Boolean expression for the logic circuit shown below:
A.
B.
C.
D.
Answer: Option A
Explanation:

Workspace
Report errors
5. From the truth table below, determine the standard SOP expression.
A.
B.
C.
D.
Answer: Option D
One of De Morgan's theorems states that . Simply stated, this means that logically there is no
difference between:
A.a NOR and an AND gate with inverted inputs
B. a NAND and an OR gate with inverted inputs
C. an AND and a NOR gate with inverted inputs
D.a NOR and a NAND gate with inverted inputs
Answer: Option A
Explanation:

Workspace
Report errors
7. The commutative law of Boolean addition states that A + B = A × B.

A.True
B. False
Answer: Option B
Explanation:

Workspace
Report errors
8. Applying DeMorgan's theorem to the expression , we get ________.

A.
B.
C.
D.
Answer: Option A
Explanation:

Workspace
Report errors

9. The systematic reduction of logic circuits is accomplished by:
A.using Boolean algebra
B. symbolic reduction
C. TTL logic
D.using a truth table
Answer: Option A
Explanation:

Workspace
Report errors
10. Which output expression might indicate a product-of-sums circuit construction?

A.
B.
C.
D.
Answer: Option D
An AND gate with schematic "bubbles" on its inputs performs the same function as a(n)________ gate.
A.NOT
B. OR
C. NOR
D.NAND
Answer: Option C
Explanation:

Workspace
Report errors
12. For the SOP expression , how many 1s are in the truth table's output column?
A.1
B. 2
C. 3
D.5
Answer: Option C
Explanation:

Workspace
Report errors
13. A truth table for the SOP expression has how many input combinations?
A.1
B. 2
C. 4
D.8
Answer: Option D
Explanation:

Workspace
Report errors
14. How many gates would be required to implement the following Boolean expression before
simplification? XY + X(X + Z) + Y(X + Z)
A.1
B. 2
C. 4
D.5
Answer: Option D
Explanation:

Workspace
Report errors
15. Determine the values of A, B, C, and D that make the product term equal to 1.
A.A = 0, B = 1, C = 0, D = 1
B. A = 0, B = 0, C = 0, D = 1
C. A = 1, B = 1, C = 1, D = 1
D.A = 0, B = 0, C = 1, D = 0
Answer: Option A
What is the primary motivation for using Boolean algebra to simplify logic expressions?
A.It may make it easier to understand the overall function of the circuit.
B. It may reduce the number of gates.
C. It may reduce the number of inputs required.
D.all of the above
Answer: Option D
Explanation:

Workspace
Report errors
17. How many gates would be required to implement the following Boolean expression after simplification?
XY + X(X + Z) + Y(X + Z)
A.1
B. 2
C. 4
D.5
Answer: Option B
Explanation:

Workspace
Report errors
18. AC + ABC = AC
A.True
B. False
Answer: Option A
Explanation:

Workspace
Report errors
19. When are the inputs to a NAND gate, according to De Morgan's theorem, the output expression
could be:
A.X = A + B
B.
C. X = (A)(B)
D.
Answer: Option A
Explanation:

Workspace
Report errors
20. Which Boolean algebra property allows us to group operands in an expression in any order without
affecting the results of the operation [for example, A + B = B + A]?
A.associative
B. commutative
C. Boolean
D.distributive
Answer: Option B
Applying DeMorgan's theorem to the expression , we get ________

A.
B.
C.
D.
Answer: Option A
Explanation:

Workspace
Report errors
22. When grouping cells within a K-map, the cells must be combined in groups of ________.
A.2s
B. 1, 2, 4, 8, etc.
C. 4s
D.3s
Answer: Option B
Explanation:

Workspace
Report errors
23. Use Boolean algebra to find the most simplified SOP expression
for F = ABD + CD + ACD + ABC + ABCD.
A.F = ABD + ABC + CD
B. F = CD + AD
C. F = BC + AB
D.F = AC + AD
Answer: Option A
Explanation:

Workspace
Report errors
24. Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such
as a BCD-to-decimal converter. These result in ________terms in the K-map and can be treated as either
________ or ________, in order to ________ the resulting term.
A.don't care, 1s, 0s, simplify
B. spurious, ANDs, ORs, eliminate
C. duplicate, 1s, 0s, verify
D.spurious, 1s, 0s, simplify
Answer: Option A
Explanation:

Workspace
Report errors
25. The NAND or NOR gates are referred to as "universal" gates because either:
A.can be found in almost all digital circuits
B. can be used to build all the other types of gates
C. are used in all countries of the world
D.were the first gates to be integrated
Answer: Option B
Explanation:
Which of the figures shown below represents the exclusive-NOR gate?
A.a
B. b
C. c
D.d
Answer: Option B
Explanation:

Workspace
Report errors

3. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?
A.a
B. b
C. c
D.d
Answer: Option D
Explanation:

Workspace
Report errors
4. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW.
What is the status of the Y output?
A.LOW
B. HIGH
C. Don't Care
D.Cannot be determined
Answer: Option A
Explanation:

Workspace
Report errors
5. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH.
What is the status of the Y output?
A.LOW
B. HIGH
C. Don't Care
D.Cannot be determined
Answer: Option A
Convert BCD 0001 0010 0110 to binary.

A.1111110
B. 1111101
C. 1111000
D.1111111
Answer: Option A
Explanation:

Workspace
Report errors
7. A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be
the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?
A.
B.
C.
D.
Answer: Option A
Explanation:

Workspace
Report errors
8. Convert BCD 0001 0111 to binary.

A.10101
B. 10010
C. 10001
D.11000
Answer: Option C
Explanation:

Workspace
Report errors

9. Which of the figures in figure (a to d) is equivalent to figure (e)?
A.a
B. b
C. c
D.d
Answer: Option B
Explanation:

Workspace
Report errors
10. How many data select lines are required for selecting eight inputs?
A.1
B. 2
C. 3
D.4
Answer: Option C
Explanation:
The simplest equation which implements the K-map shown below is:
A.
B.
C.
D.
Answer: Option A
Explanation:

Workspace
Report errors
12. How many 1-of-16 decoders are required for decoding a 7-bit binary number?
A.5
B. 6
C. 7
D.8
Answer: Option D
Explanation:

Workspace
Report errors
13. Which of the following logic expressions represents the logic diagram shown?
A.
B.
C.
D.
Answer: Option D
Explanation:

Workspace
Report errors
14. The implementation of simplified sum-of-products expressions may be easily implemented into actual
logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select
the response for the blank space that will BEST make the statement true.)
A.AND/OR
B. NAND
C. NOR
D.OR/AND
Answer: Option B
For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH.
What is the status of the outputs?
A.All are HIGH.
B. All are LOW.
C. All but are LOW.
D.All but are HIGH.
Answer: Option A
Explanation:

Workspace
Report errors
17. Which of the following combinations cannot be combined into K-map groups?
A.Corners in the same row
B. Corners in the same column
C. Diagonal corners
D.Overlapping combinations
Answer: Option C
Explanation:

Workspace
Report errors
18. As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have
taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic
nature. Of the possible faults listed, select the one that most probably is causing the problem.
A.A defective IC chip that is drawing excessive current from the power supply
B. A solar bridge between the inputs on the first IC chip on the board
C. An open input on the first IC chip on the board
D.A defective output IC chip that has an internal open to Vcc
Answer: Option C
Explanation:

Workspace
Report errors
19. Which gate is best used as a basic comparator?

A.NOR
B. OR
C. Exclusive-OR
D.AND
Answer: Option C
Explanation:

Workspace
Report errors
20. The device shown here is most likely a ________.
A.comparator
B. multiplexer
C. demultiplexer
D.parity generator
Answer: Option C
Explanation:
Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

A.The logic level at the D input is transferred to Q on NGT of CLK.
B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
C. The Q output is ALWAYS identical to the D input when CLK = PGT.
D.The Q output is ALWAYS identical to the D input.
Answer: Option A
Explanation:

Workspace
Report errors
3. Propagation delay time, tPLH, is measured from the ________.

A.triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
C. preset input to the LOW-to-HIGH transition of the output
D.clear input to the HIGH-to-LOW transition of the output
Answer: Option A
Explanation:

Workspace
Report errors

A.J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D.J = 1, K = 1
Answer: Option D
Explanation:

Workspace
Report errors

A.1
B. 2
C. 4
D.8
Answer: Option C
Explanation:

Workspace
Report errors
6. How many flip-flops are required to produce a divide-by-128 device?

A.1
B. 4
C. 6
D.7
Answer: Option D
Explanation:
Which is not an Altera primitive port identifier?
A.clk
B. ena
C. clr
D.prn
Answer: Option C
Explanation:

Workspace
Report errors
8. The timing network that sets the output frequency of a 555 astable circuit contains ________.
A.three external resistors are used
B. two external resistors and an external capacitor are used
C. an external resistor and two external capacitors are used
D.no external resistor or capacitor is required
Answer: Option B
Explanation:

Workspace
Report errors
9. What is the difference between the enable input of the 7475 and the clock input of the 7474?
A.The 7475 is edge-triggered.
B. The 7474 is edge-triggered.
Answer: Option B
Explanation:

Workspace
Report errors

10. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called
________.
A.parity error checking
B. ones catching
C. digital discrimination
D.digital filtering
Answer: Option B
Explanation:

Workspace
Report errors
11. What is another name for a one-shot?

A.Monostable
B. Multivibrator
C. Bistable
D.Astable
Answer: Option A
Explanation:

Workspace
Report errors
12. On a master-slave flip-flop, when is the master enabled?

A.when the gate is LOW
B. when the gate is HIGH
C. both of the above
D.neither of the above
Answer: Option B
One example of the use of an S-R flip-flop is as a(n):

A.racer
B. astable oscillator
C. binary storage register
D.transition pulse generator
Answer: Option C
Explanation:

Workspace
Report errors
14. What is the difference between the 7476 and the 74LS76?
A.the 7476 is master-slave, the 74LS76 is master-slave
B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
C. the 7476 is edge-triggered, the 74LS76 is master-slave
D.the 7476 is master-slave, the 74LS76 is edge-triggered
Answer: Option D
Explanation:

Workspace
Report errors

A.The output toggles if one of the inputs is held HIGH.
B. Only one of the inputs can be HIGH at a time.
C. The output complement follows the input when enabled.
D.Q output follows the input D when the enable is HIGH.
Answer: Option D
Explanation:

Workspace
Report errors
16. With regard to a D latch, ________.

A.the Q output follows the D input when EN is LOW
B. the Q output is opposite the D input when EN is LOW
C. the Q output follows the D input when EN is HIGH
D.the Q output is HIGH regardless of EN's input state
Answer: Option C
Explanation:

Workspace
Report errors
17. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
A.It can't be done.
B. Invert the Q outputs.
C. Invert the S-R inputs.
Answer: Option C
Explanation:

Workspace
Report errors

A.when the Q output is opposite the input
B. when the Q output follows the input
C. when you can see through the IC packaging
Answer: Option B
Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as
shown below. Determine if the circuit is functioning properly, and if not, what
might be wrong.
A.The circuit is functioning properly.
B. Q2 is incorrect; the flip-flop is probably bad.
C. The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to
D.
reset.
Answer: Option B
Explanation:

Workspace
Report errors
20. A 555 operating as a monostable multivibrator has an R1 of 1 M . Determine C1 for a pulse width of 2
s.
A.1.8 F
B. 18 F
C. 18 pF
D.18 nF
Answer: Option A
Explanation:

Workspace
Report errors
21. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is
read during the entire time the clock pulse is at a LOW level.
A.True
B. False
Answer: Option B
Explanation:

Workspace
Report errors

A.The output toggles if one of the inputs is held HIGH.
B. Q output follows the input D when the enable is HIGH.
C. Only one of the inputs can be HIGH at a time.
D.The output complement follows the input when enabled.
Answer: Option B
Explanation:

Workspace
Report errors
23. A J-K flip-flop is in a "no change" condition when ________.

A.J = 1, K = 1
B. J = 1, K = 0
C. J = 0, K = 1
D.J = 0, K = 0
Answer: Option D
Explanation:

Workspace
Report errors
24. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
A.clock is LOW
B. slave is transferring
C. flip-flop is reset
D.clock is HIGH
Answer: Option D
In a Gray code, each number is 3 greater than the binary representation of that number.
A.True
B. False
Answer: Option B
Explanation:

Workspace
Report errors
3. Use the weighting factors to convert the following BCD numbers to binary.
0101 0011 0010 0110 1000

A.01010011 001001101000
B. 11010100 100001100000
C. 110101 100001100
D.101011 001100001
Answer: Option C
Explanation:

Workspace
Report errors
A.encoder
B. display
C. counter
D.decoder
Answer: Option D
Explanation:

Workspace
Report errors
5. From the following list of input conditions, determine the state of the five output leads on a 74148 octal-
to-binary encoder.
I0 = 1 I3 = 1 I6 = 1
I1 = 1 I4 = 0 I7 = 1
I2 = 1 I5 = 1 EI = 0
A.GS = L, A0 = L, A1 = L, A2 = H, EO = H
B. GS = L, A0 = H, A1 = L, A2 = L, EO = H
C. GS = L, A0 = L, A1 = H, A2 = L, EO = H
D.GS = L, A0 = H, A1 = H, A2 = L, EO = H
Answer: Option D
What is the function of an enable input on a multiplexer chip?
A.to apply Vcc
B. to connect ground
C. to active the entire chip
D.to active one half of the chip
Answer: Option C
Explanation:

Workspace
Report errors
7. The expansion inputs to a comparator are used for expansion to a(n):

A.4-bit system
B. 8-bit system
C. BCD system
D.counter system
Answer: Option B
Explanation:

Workspace
Report errors
8. What do the mathematical symbols A < b and A > B mean?

A.A < B means A is greater than B. A > B means A is less than B.
B. A > B means A is less than B. A < B means A is greater than B.
C. A < B means A is less than B. A > B means A is greater than B.
Answer: Option C
Explanation:

Workspace
Report errors
9. A basic multiplexer principle can be demonstrated through the use of a:

A.single-pole relay
B. DPDT switch
C. rotary switch
D.linear stepper
Answer: Option C
Explanation:

Workspace
Report errors

A.4
B. 8
C. 10
D.16
Answer: Option C
Explanation:
A principle regarding most IC decoders is that when the correct input is present, the related output will
switch:
A.active-HIGH
B. to a high impedance
C. to an open
D.active-LOW
Answer: Option D
Explanation:

Workspace
Report errors
A.flasher circuit control signal
B. a LOW on all gate enable inputs
C. input from a hexadecimal counter
D.a HIGH on all gate enable circuits
Answer: Option B
Explanation:

Workspace
Report errors
13. One multiplexer can take the place of:

A.several SSI logic gates
B. combinational logic circuits
C. several Ex-NOR gates
D.several SSI logic gates or combinational logic circuits
Answer: Option D
Explanation:

Workspace
Report errors
14. How many exclusive-NOR gates would be required for an 8-bit comparator circuit?
A.4
B. 6
C. 8
D.10
Answer: Option C
Explanation:

Workspace
Report errors
A.4
B. 8
C. 10
D.1
Answer: Option A
Explanation:
A BCD decoder will have how many rows in its truth table?
A.10
B. 9
C. 8
D.3
Answer: Option A
Explanation:

Workspace
Report errors
A.16
B. 32
C. 64
D.128
Answer: Option C
Explanation:

Workspace
Report errors

A.decimal-to-hexadecimal
B. single input, multiple outputs
C. ac to dc
D.odd parity to even parity
Answer: Option B
Explanation:

Workspace
Report errors
19. The inputs/outputs of an analog multiplexer/demultiplexer are:

A.bidirectional
B. unidirectional
C. even parity
D.binary-coded decimal
Answer: Option A
Explanation:

Workspace
Report errors
20. Why can a CMOS IC be used as both a multiplexer and a demultiplexer?

A.It cannot be used as both.
B. CMOS uses bidirectional switches.
Answer: Option B
A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is a(n):
A.Ex-NOR gate
B. OR gate
C. Ex-OR gate
D.NAND gate
Answer: Option A
Explanation:

Workspace
Report errors
3. A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n):
A.Ex-NOR gate
B. OR gate
C. Ex-OR gate
D.NAND gate
Answer: Option C
Identify the type of gate below from the equation

A.Ex-NOR gate
B. OR gate
C. Ex-OR gate
D.NAND gate
Answer: Option C
Explanation:

Workspace
Report errors
5. How is odd parity generated differently from even parity?

A.The first output is inverted.
B. The last output is inverted.
Answer: Option B
Parity systems are defined as either________ or ________ and will add an extra
________ to the digital information being transmitted.
A.positive, negative, byte
B. odd, even, bit
C. upper, lower, digit
D.on, off, decimal
Answer: Option B
Explanation:

Workspace
Report errors
7. Which type of gate can be used to add two bits?

A.Ex-OR
B. Ex-NOR
C. Ex-NAND
D.NOR
Answer: Option A
Explanation:

Workspace
Report errors
8. Why is an exclusive-NOR gate also called an equality gate?

A.The output is false if the inputs are equal.
B. The output is true if the inputs are opposite.
C. The output is true if the inputs are equal.
Answer: Option C
Explanation:

Workspace
Report errors
9. Show from the truth table how an exclusive-OR gate can be used to invert the data on one input if the
other input is a special control function.
A.Using A as the control, when A = 0, X is the same as B. When A = 1, X is the same as B.
B. Using A as the control, when A = 0, X is the same as B. When A = 1, X is the inverse of B.
C. Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the same as B.
D.Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the inverse of B.
Answer: Option B
Explanation:

Workspace
Report errors
10. Determine odd parity for each of the following data words:
1011101 11110111 1001101
A.P = 1, P = 1, P = 0
B. P = 0, P = 0, P = 0
C. P = 1, P = 1, P = 1
D.P = 0, P = 0, P = 1
Answer: Option D
The Ex-NOR is sometimes called the ________.

A.parity gate
B. equality gate
C. inverted OR
D.parity gate or the equality gate
Answer: Option B
Explanation:
Convert the following decimal number to 8-bit binary.

187
A.101110112
B. 110111012
C. 101111012
D.101111002
Answer: Option A
Explanation:

Workspace
Report errors
3. Convert binary 111111110010 to hexadecimal.

A.EE216
B. FF216
C. 2FE16
D.FD216
Answer: Option B
Explanation:

Workspace
Report errors
4. Convert the following binary number to decimal.

010112
A.11
B. 35
C. 15
D.10
Answer: Option A
Explanation:

Workspace
Report errors
5. Convert the binary number 1001.00102 to decimal.

A.90.125
B. 9.125
C. 125
D.12.5
Answer: Option B
Explanation:
Decode the following ASCII message.
10100111010100101010110001001011001
01000001001000100000110100101000100
A.STUDYHARD
B. STUDY HARD
C. stydyhard
D.study hard
Answer: Option B
Explanation:

Workspace
Report errors
7. The voltages in digital electronics are continuously variable.

A.True
B. False
Answer: Option B
Explanation:
One hex digit is sometimes referred to as a(n):

A.byte
B. nibble
C. grouping
D.instruction
Answer: Option B
Explanation:

Workspace
Report errors
9. Which of the following is the most widely used alphanumeric code for computer input and output?
A.Gray
B. ASCII
C. Parity
D.EBCDIC
Answer: Option B
Explanation:

Workspace
Report errors
10. If a typical PC uses a 20-bit address code, how much memory can the CPU address?
A.20 MB
B. 10 MB
C. 1 MB
D.580 MB
Answer: Option C
Explanation:

Workspace
Report errors
11. Convert 59.7210 to BCD.

A.111011
B. 01011001.01110010
C. 1110.11
D.0101100101110010
Answer: Option B
Explanation:

Workspace
Report errors
12. Convert 8B3F16 to binary.

A.35647
B. 011010
C. 1011001111100011
D.1000101100111111
Answer: Option D
Explanation:

Workspace
Report errors
13. Which is typically the longest: bit, byte, nibble, word?

A.Bit
B. Byte
C. Nibble
D.Word
Answer: Option D
Explanation:

Workspace
Report errors
14. Assign the proper odd parity bit to the code 111001.
A.1111011
B. 1111001
C. 0111111
D.0011111
Answer: Option B
Convert decimal 64 to binary.

A.01010010
B. 01000000
C. 00110110
D.01001000
Answer: Option B
Explanation:

Workspace
Report errors
16. Convert hexadecimal value C1 to binary.

A.11000001
B. 1000111
C. 111000100
D.111000001
Answer: Option A
Explanation:

Workspace
Report errors
17. Convert the following octal number to decimal.

178
A.51
B. 82
C. 57
D.15
Answer: Option D
Explanation:

Workspace
Report errors
18. Convert the following binary number to octal.

0101111002
A.1728
B. 2728
C. 1748
D.2748
Answer: Option D
Explanation:

Workspace
Report errors
19. How many binary digits are required to count to 10010?

A.7
B. 2
C. 3
D.100
Answer: Option A
Explanation:

Workspace
Report errors
20. The BCD number for decimal 347 is ________.

A.1100 1011 1000
B. 0011 0100 0111
C. 0011 0100 0001
D.1100 1011 0110
Answer: Option B
Explanation:

Workspace
Report errors
21. The binary number for octal 458 is ________.

A.100010
B. 100101
C. 110101
D.100100
Answer: Option B
The sum of 11101 + 10111 equals ________.
A.110011
B. 100001
C. 110100
D.100100
Answer: Option C
Explanation:

Workspace
Report errors
23. Convert the following binary number to decimal.

100110102
A.154
B. 155
C. 153
D.157
Answer: Option A
Explanation:

Workspace
Report errors
24. The decimal number 188 is equal to the binary number ________.
A.10111100
B. 0111000
C. 1100011
D.1111000
Answer: Option A
Explanation:

Workspace
Report errors
25. Convert the following binary number to octal.

0011010112
A.1538
B. 3518
C. 2538
D.3528
Answer: Option A
Explanation:

Workspace
Report errors
26. How many bits are in an ASCII character?

A.16
B. 8
C. 7
D.4
Answer: Option C
Explanation:

Workspace
Report errors
27. A binary number's value changes most drastically when the ________ is changed.
A.MSB
B. frequency
C. LSB
D.duty cycle
Answer: Option A
Explanation:

Workspace
Report errors

28. Convert decimal 213 to binary.
A.11001101
B. 11010101
C. 01111001
D.11100011
Answer: Option B
Explanation:
The decimal number for octal 748 is ________.
A.74
B. 60
C. 22
D.62
Answer: Option B
Explanation:

Workspace
Report errors
30. The sum of the two BCD numbers, 0011 + 0011, is ________.
A.0110
B. 0111
C. 0011
D.1100
Answer: Option A
Explanation:

Workspace
Report errors
31. Convert binary 01001110 to decimal.

A.4E
B. 78
C. 76
D.116
Answer: Option B
Explanation:

Workspace
Report errors
32. Which is not a word size?

A.64
B. 28
C. 16
D.8
Answer: Option B
Explanation:

Workspace
Report errors
33. The octal numbering system:

A.simplifies tasks
B. groups binary numbers in groups of 4
C. saves time
D.simplifies tasks and saves time
Answer: Option D
Explanation:

Workspace
Report errors

34. The binary number 1110 is equal to the decimal number ________.
A.3
B. 1
C. 7
D.14
Answer: Option D
Explanation:

Workspace
Report errors
35. Convert the following octal number to binary.

768
A.1101112
B. 1111102
C. 1111002
D.1001112
Q1. The binary number 10101 is equivalent to decimal number
…………..
1. 19
2. 12
3. 27
4. 21
Answer : 4
1. NAND gate
2. OR gate
3. AND gate
Answer : 1
1. NOT gate
2. OR gate
3. AND gate
Answer : 1
Q4. The inputs of a NAND gate are connected together. The

resulting circuit is ………….
1. OR gate
2. AND gate
3. NOT gate
Answer : 3
1. AND gate
2. NAND gate
3. NOT gate
Answer : 3
1. NOT gate
2. OR gate
3. AND gate
Answer : 1
1. OR gates
2. NOT gates
3. NAND gates
Answer : 3
1. Stop signal
Answer : 2
Q9. When an input signal 1 is applied to a NOT gate, the output is

………………
1. 0
2. 1
3. Either 0 & 1
Answer : 1
1. OR operation
2. AND operation
3. NOT operation
Answer : 3
Q11. The resolution of an n bit DAC with a maximum input of 5 V
is 5 mV. The value of n is …….
1. 8
2. 9
3. 10
4. 11
Answer : 3
Explanation:
(5/2N-1)1000 = 5 or N = 10
1. 1011
2. 1111
3. 1101
4. 1110
Answer : 1
Explanation: 1’s complement of 0101 is 1010 and 2’s complement is

1010+1 = 1011.
Q13. An OR gate has 4 inputs. One input is high and the other
three are low. The output is …….
1. Low
2. High
Answer : 2
1. 1110
2. 1010
3. 1001
4. 1000
Answer : 2
1. True
2. False
Answer : 2
Q16. A device which converts BCD to seven segments is called

……..
1. Encoder
2. Decoder
3. Multiplexer
4. None of these
Answer : 2
Q17. In 2’s complement representation the number 11100101

represents the decimal number ……………
1. +37
2. -31
3. +27
4. -27
Answer : 4
Explanation:
A = 11100101. Therefore Ā = 00011010 and A’ = Ā + 1 = 00011011 = 16 + 8

+ 2 + 1 = 27. Therefore A = -27.

Answer : 3
Explanation: A decade counter counts from 0 to 9. It has 4 flip-flops. The
states skipped are 10 to 15 or 1010 to 1111.
Q19. BCD input 1000 is fed to a 7 segment display through a BCD

to 7 segment decoder/driver. The segments which will lit up are
………….
1. a, b, d
2. a, b, c
3. all
4. a, b, g, c, d
Answer : 3
1. 5
2. 10
3. 32
4. Infinite
Answer : 1
1. 0
2. 1
3. A
4. Ā
Answer : 4

Q22. In the expression A + BC, the total number of minterms will
be ………
1. 2
2. 3
3. 4
4. 5
Answer : 4

Answer : 2
Explanation: Since V(1) is lower state than V(0) it is a negative logic

circuit. Since diodes are in parallel, it is an OR gate.
1. TTL
2. CMOS
3. ECL
4. Both 1 and 2
Answer : 3
1. 8
2. 7
3. 9
4. 10
Answer : 1
Q16.
Answer : 2
Explanation:
Q26. The access time of a word in 4 MB main memory is 100 ms.

The access time of a word in a 32 kb data cache memory is 10 ns.
The average data cache bit ratio is 0.95. The efficiency of
memory access time is ………
1. 9.5 ns
2. 14.5 ns
3. 20 ns
4. 95 ns
Answer : 2
1. POS
2. SOP
3. Hybrid
4. none of these
Answer : 1

Q28. An 8 bit DAC has a full scale output of 2 mA and full scale
error of ± 0.5%. If input is 10000000 the range of outputs is
………….
1. 994 to 1014 μA
2. 990 to 1020 μA
3. 800 to 1200 μA
Answer : 1
Explanation:
Q29. Decimal 43 in hexadecimal and BCD number system is

respectively……. and ……..
1. B2 and 01000011
2. 2B and 01000011
3. 2B and 00110100
4. B2 and 01000100
Answer : 2
Explanation:
Answer : 1
Explanation:
Q31. An AND gate has two inputs A and B and one inhibit input 3,
Output is 1 if
1. A = 1, B = 1, S = 1
2. A = 1, B = 1, S = 0
3. A = 1, B = 0, S = 1
4. A = 1, B = 0, S = 0
Answer: 2
Q32. The greatest negative number which can be stored is 8 bit

computer using 2’s complement arithmetic is ……..
1. -256
2. -128
3. -255
4. -127
Answer: 2
Q33. A JK flip flop has tpd= 12 ns. The largest modulus of a ripple
counter using these flip flops and operating at 10 MHz is ……..
1. 16
2. 64
3. 128
4. 256
Answer: 4
Explanation:
1. flipflop
2. counter
3. multiplexer
4. encoder
Answer : 1
Explanation: Storing can be done only in memory and flip-flop is a

memory element.

2. whenever a flipflop sets to 0, the next higher FF remains
unchanged
4. whenever a flipflop sets to 0, the next higher FF faces race
condition
Answer : 1
Q36. A 12 bit ADC is used to convert analog voltage of 0 to 10 V

into digital. The resolution is ……….
1. 2.44 mV
2. 24.4 mV
3. 1.2 V
4. none of these
Answer : 1
Explanation:

1. A+B+C
2. Ā +BC
3. Ā
4. B¯
Answer : 4
Explanation:
1. two half adders

Answer : 2

1. w=zx=z
2. w = z, x = y
3. w=y
4. w=y=z
Answer : 1
1. Sum
2. Sum and Carry
3. Carry
4. none of these
Answer: 2
Q41. Minimum number of 2-input NAND gates required to

implement the function F = (x + y) (Z + W) is ………..
1. 3
2. 4
3. 5
4. 6
Answer : 2
Explanation:
1. Multiplexer
2. Demultiplexer
3. Counter
4. Flip flop
Answer: 2
Explanation: Demultiplexer takes data from one line and directs it to any
of its N output depending on the status of its select lines.
Q43. A carry look ahead adder is frequently used for addition

because
1. it costs less
2. it is faster
4. uses fewer gates
Answer: 2
Explanation:
Q27.
Answer : 1
Explanation: In look ahead carry adder the carry is directly derived from
the gates when original inputs are being added. Hence the addition is fast.
This process requires more gates and is costly.

1. Mod 3
2. Mod 6
3. Mod 8
4. Mod 7
Answer : 2
Q45. In register index addressing mode the effective address is

given by ……..

3. operand
Answer : 2
Explanation:
Q46. 7BF16 = __________ 2
1. 0111 1011 1110

2. 0111 1011 1111
3. 0111 1011 0111
4. 0111 1011 0011
Answer : 2
Explanation:
7BF16 = 7 x 162 + 11 x 161 + 15 x 160 = 1983 in decimal = 0111 1011 1111 in

binary.
Q47. For the minterm designation Y = ∑ m (1, 3, 5, 7) the

complete expression is …………..
Answer : 2
Explanation:
1. True
2. False
Answer: 2
Q49. A counter type A/D converter contains a 4 bit binary ladder

and a counter driven by a 2 MHz clock. Then conversion time is
………..
1. 8 μ sec
2. 10 μ sec
3. 2 μ sec
4. 5 μ sec
Answer : 1
Explanation:
Q50. The hexadecimal number (3E8)16 is equal to decimal

number ………
1. 1000
2. 982
3. 768
4. 323
Answer : 1
Explanation: 3 x 162 + 14 x 161 + 8 = 1000
Q51. The number of distinct Boolean expression of 4 variables is

…….
1. 16
2. 256
3. 1024
4. 65536
Answer : 4
Explanation:
Q52. For the K map in the given figure the simplified Boolean
expression is ……
Answer : 1
Explanation:
Q53. A memory system of size 16 k bytes is to be designed using
memory chips which have 12 address lines and 4 data lines each.
The number of such chips required to design the memory system
is ……….
1. 2
2. 4
3. 8
4. 18
Answer : 3
Explanation:
(16×1024×8)/(4096×4) = 8
Q54. In a 7 segment display, LEDs b and c lit up. The decimal

number displayed is ……….
1. 9
2. 7
3. 3
4. 1
Answer : 1
Q55. In a BCD to 7 segment decoder the minimum and maximum

number of outputs active at any time is ….
1. 2 and 7
2. 3 and 7
3. 1 and 6
4. 3 and 6
Answer: 1
Explanation:
Minimum number of outputs when input is decimal 1 and maximum

number of outputs when input is decimal 8.
Q56. A three state switch has three outputs. These are …….. ,
…….. , ……….
1. low, low and high

2. low, high, high
3. low. floating, low
4. low, high, floating
Answer: 4
Q57. Maxterm designation for A + B + C is ……….
1. M0
2. M1
3. M3
4. M4
Answer: 1
Explanation: A + B + C = 000 = M0
Q58. 1’s complement of 11100110 is ……………….
1. 00011001
2. 10000001
3. 00011010
4. 00000000
Answer: 1
Explanation: By replacing 1 by 0 and 0 by 1.

Q.1 The
NAND gate output will be low if the two inputs
are
(A) 00
(B) 01
(C) 10
(D) 11
ANS: D
THE NAND GATE OUTPUT WILL BE LOW IF THE TWO
INPUTS ARE 11 (THE TRUTH TABLE OF NAND GATE IS
SHOWN IN TABLE.1.1)
X(Input) Y(Input) F(Output)

0 0 1
0 1 1
1 0 1
1 1 0
Table 1.1 Truth Table for NAND Gate

Q.2 What
is the binary equivalent of the decimal number
368
(A) 101110000
(B) 110110000
(C) 111010000
(D) 111100000
ANS: A
THE
BINARY EQUIVALENT OF THE DECIMAL NUMBER
368 IS 101110000
(CONVERSION FROM DECIMAL NUMBER TO
BINARY NUMBER IS GIVEN IN TABLE 1.2)
2 368
2 184 — 0
92
2 — 0
46
2 — 0
23
2 — 0
11
2 — 1
5
2 — 1
2
2 — 1
1
2 — 0
0
— 1
Table 1.2 Conversion from Decimal number to Binary number
Q.3
Q3.The decimal equivalent of hex number 1A53 is
(A) 6793 (B) 6739
(C) 6973 (D) 6379
ANS: B
THE DECIMAL EQUIVALENT OF HEX NUMBER
1A53 IS 6739
(CONVERSION
FROM HEX NUMBER TO DECIMAL NUMBER IS
GIVEN BELOW)
1 A 5 3Hexadecimal
16³ 16² 16¹ 16° Weights
(1A53)16 = (1X16³) + (10 X 16²) + (5 X 16¹) + (3 X 16º)
= 4096 + 2560 + 80 + 3
= 6739
Q.4 (734)8 = ( )16
(A) C 1 D (B) D C 1
(C) 1 C D (D) 1 D C
ANS:
D
(734)8 = (1 D C)16
0001 | 1101 | 1100
1 D
Q.5 The number of control lines for a 8 – to – 1 multiplexer is
(A) 2 (B) 3
(C) 4 (D) 5
ANS: B
The number of control lines for an 8 to 1 Multiplexer is 3
(The control signals are used to steer any one of the 8 inputs to the
output)
Q.6 How many Flip-Flops are required for mod–16 counter?
(A) 5 (B) 6
(C) 3 (D) 4
ANS: D
The number of flip-flops is required for Mod-16 Counter is 4.
(For Mod-m Counter, we need N
flip-flops where N is chosen to be the smallest number for which 2N is greater
than or equal to m. In this case 24
greater than or equal to 1)
Q.7
EPROM contents can be erased by exposing
it to
(A)
Ultraviolet rays. (B) Infrared rays.
(C) Burst of microwaves. (D) Intense heat radiations.
ANS: A
EPROM contents can be erased by exposing it to Ultraviolet rays
(The Ultraviolet light passes
through a window in the IC package to the EPROM chip where it releases stored
charges. Thus the stored contents are
erased).
Q.8 The hexadecimal number ‘A0’ has the decimal value equivalent to
(A) 80 (B) 256
(C) 100 (D) 160
ANS: D
The hexadecimal number
‘A0’ has the decimal value equivalent to 160
( A 0
161 160 = 10X161 + 0X160 = 160
Q.1
Q.9 The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either
(A)
a NAND or an EX-OR (B) an OR or an EX-NOR
(C) an
AND or an EX-OR (D) a NOR or an EX-NOR
ANS: D
The output of a logic gate is 1 when all inputs are at logic 0. The
gate is either a NOR or an EX-NOR .
Q.14
Data can be changed from special code to temporal code by using
(A)
Shift registers (B) counters
(C) Combinational circuits (D) A/D converters.
ANS: A
Data can be changed from special code to temporal
code by using Shift Registers.
(A Register in which data gets shifted towards left or right when clock pulses
are applied is known as a Shift Register.)
Q.15
A ring counter consisting of five Flip-Flops will have
(A)
5 states (B) 10
states
(C) 32 states (D) Infinite states.
ANS: A
A RING COUNTER CONSISTING OF FIVE
FLIP-FLOPS WILL HAVE 5 STATES.
Q.16
The speed of conversion is maximum in
(A)
Successive-approximation A/D converter.
(B)
Parallel-comparative A/D converter.
(C)
Counter ramp A/D converter.
(D)
Dual-slope A/D converter.
ANS: B
The speed of conversion is maximum in Parallel-comparator A/D
converter
(Speed of
conversion is maximum because the comparisons of the input voltage are carried
out simultaneously.)
Q.17
The 2’s complement of the number 1101101 is
(A) 0101110 (B) 0111110
(C) 0110010 (D) 0010011
ANS: D
The 2’s complement of the number 1101101 is 0010011 (1’s complement of
the number 1101101 is 0010010
2’s complement of the number
1101101is 0010010 + 1 =0010011)
Q.18
The correction to be applied
in decimal adder to the generated sum is
(A) 00101 (B) 00110
(C) 01101 (D) 01010
ANS: B
The correction to be applied in decimal
adder to the generated sum is 00110.
When the four
bit sum is more than 9 then the sum is invalid. In such cases, add
+6(i.e. 0110) to the four bit sum to
skip the six invalid states. If a carry is generated when adding 6, add the
carry to the next four bit group .
Q.19
When simplified with Boolean Algebra (x + y)(x + z) simplifies to
(A)
x (B) x + x(y + z)
(C) x(1 + yz) (D) x + yz
ANS: D
When simplified with Boolean Algebra (x + y)(x + z) simplifies to x +
yz [(x + y) (x + z)] = xx + xz + xy + yz
= x + xz + xy + yz ( xx = x)
= x(1+z) + xy + yz = x + xy +
yz { (1+z) = 1}
= x(1 + y) + yz = x + yz { (1+y) = 1}]
Q.20
The gates required to build a half adder are
(A)
EX-OR gate and NOR gate (B) EX-OR gate and OR gate
(C) EX-OR
gate and AND gate (D) Four NAND gates.
ANS: C
The gates required to build a half adder are EX-OR gate and AND gate
Q.21 The code where
all successive numbers
differ from their
preceding number by single bit is
(A)
Binary code. (B) BCD.
(C) Excess – 3. (D) Gray.
ANS: D
The code where all successive numbers
differ from their preceding number by single bit is Gray Code.
(It is an unweighted code. The most
important characteristic of this code is that only a single bit change occurs
when going from one code number to next.)
Q.22 Which of the following is the

fastest logic
(A)
TTL (B) ECL
(C) CMOS (D) LSI
ANS: B
ECL is the fastest logic family of all
logic families.
(High speeds
are possible in ECL because the transistors are used in difference amplifier configuration, in which
they are
never driven into saturation and thereby the storage time is eliminated.
Q.23 If the input to T-flipflop is 100 Hz signal, the final output of the
three T-flipflops in cascade is
(A) 1000 Hz (B) 500 Hz
(C) 333 Hz (D) 12.5 Hz.
ANS: D
If the input to T-flip-flop is 100 Hz signal,
the final output
of the three
T- flip-flops in cascade is 12.5 Hz
Q.24 Which of the memory is volatile memory

(A)
ROM (B) RAM
(C) PROM (D) EEPROM
ANS: B
RAM is a volatile memory (Volatile
memory means the contents of the RAM get erased as soon as the power
goes off.)
Q.25 -8 is equal to signed binary number
(A) 10001000 (B) 00001000
(C) 10000000 (D) 11000000
ANS: A
– 8 is equal to signed binary number 10001000
Q.26
DeMorgan’s first theorem shows the equivalence of
(A) OR gate and Exclusive OR gate.
(B)
NOR gate and Bubbled AND gate.
(C) NOR gate and NAND gate.
(D) NAND gate and NOT gate
ANS: B
DeMorgan’s first theorem shows
the equivalence of NOR gate and Bubbled AND gate
Q.27
The digital logic family which has the lowest propagation delay time is
(A)
ECL (B) TTL
(C) CMOS (D) PMOS
ANS: A
The digital logic family which has the lowest propagation delay time
is ECL
(Lowest
propagation delay time is possible in ECL because the transistors are used in
difference amplifier configuration, in which they are never driven into
saturation and thereby the storage time is eliminated).
Q.28
The device which changes from serial data to parallel data is
(A) COUNTER (B) MULTIPLEXER
(C) DEMULTIPLEXER (D) FLIP-FLOP
ANS: C
The device which changes from serial data to parallel data is
demultiplexer.
(A demultiplexer takes in data
from one line and directs it to any of its N outputs depending on the status of
the select inputs.)
Q.29
A device which converts BCD to Seven Segment is called
(A)
Encoder (B) Decoder
(C) Multiplexer (D) Demultiplexer
Ans: B
device which converts BCD to Seven
Segment is called DECODER.
decoder coverts binary words into alphanumeric
characters.)
Q.30
In a JK Flip-Flop, toggle means
(A) Set Q = 1 and Q = 0.
(B)
Set Q = 0 and Q = 1.
(C) Change the output to the
opposite state.
(D) No change in output.
ANS: C
In a JK Flip-Flop, toggle means Change the output to the opposite
state.
Q.31 The access time of ROM using bipolar transistors is about

(A)
1 sec (B) 1 msec
(C) 1 µsec (D) 1 nsec.
ANS: C
THE ACCESS TIME OF ROM USING BIPOLAR
TRANSISTORS IS ABOUT 1 M SEC.
Q.32
The A/D converter
whose conversion time is independent of the number
of bits is
(A) Dual slope (B) Counter type
(C) Parallel conversion (D) Successive approximation.
ANS: C
The A/D converter whose conversion time is independent of the Number
of bits is Parallel conversion.
(This type uses an array of comparators connected in parallel and
comparators compare the input voltage at a particular ratio of the reference
voltage).
Q.3When signed numbers are used in binary arithmetic, then which one of
the following notations would have unique representation for zero.
(A) Sign-magnitude. (B) 1’s complement.
(C) 2’s complement. (D) 9’s complement.
ANS: A
Q.38 A 4-bit synchronous counter uses flip-flops with propagation delay
times of 15 ns each. The maximum possible time required for change of state
will be
(A) 15 ns. (B) 30 ns.
(C) 45 ns. (D) 60 ns.
ANS: A
15 NS BECAUSE IN SYNCHRONOUS COUNTER ALL
THE FLIP-FLOPS CHANGE STATE
AT THE SAME TIME.
Q.39 Words having 8-bits are to be stored into computer memory. The number
of lines required for writing into memory are
(A) 1. (B) 2.
(C) 4. (D) 8.
ANS: D
Because 8-bit words required 8
bit data lines.
Q.40 In successive-approximation A/D converter, offset
voltage equal to D/A converter’s
output. This is done to
(A) Improve the speed of operation.
(B)
Reduce the maximum quantization error.
(C)
Increase the number of bits at the
output.
(D)
Increase the range of input voltage that can be converted.
ANS: B
Q.41
The decimal equivalent of Binary number 11010 is
(A) 26. (B) 36.
(C) 16. (D) 23.
ANS: A
11010 = 1 X 24 + 1 X 2 3 + 0 X 22 + 1 X 21 = 26
1 LSB
is added to the 2
Q.42
1’s complement representation of decimal number
of -17 by using
8 bit representation is
(A) 1110 1110 (B) 1101 1101
(C) 1100 1100 (D) 0001 0001
ANS: A
(17)10
= (10001)2
In 8 bit = 00010001
1’s Complement = 11101110
Q.43 The excess 3 code of decimal number 26

is
(A) 0100 1001 (B) 01011001
(C) 1000 1001 (D) 01001101
ANS: B
(26)10
in BCD is ( 00100110 ) BCD
Add 011 to each BCD 01011001 for excess – 3
Q.44 How many AND gates are required to realize Y = CD+EF+G

(A) 4 (B) 5
(C) 3 (D) 2
ANS: D
To realize Y = CD + EF + G
Two AND gates are required (for CD & EF).
Q.45 How many select lines will a 16 to 1 multiplexer will have
(A) 4 (B) 3
(C) 5 (D) 1
ANS: A
In 16 to 1 MUX four select
lines will be required to select 16 ( 24 ) inputs.
Q.46 How many flip flops are required to construct a decade counter
(A) 10 (B) 3
(C) 4 (D) 2
ANS: C
Decade counter counts 10 states from 0 to 9 ( i.e. from 0000 to 1001 )Thus four FlipFlop’s are
required.
Q.47 Which TTL logic gate is used for wired

ANDing
(A)
Open collector output (B) Totem Pole
(C) Tri state output (D) ECL gates
ANS: A
Open collector output.
Q.48 CMOS circuits consume power
(A) Equal to TTL (B) Less than TTL
(C) Twice of TTL (D) Thrice of TTL
ANS: B
As in CMOS one device is ON & one is Always OFF so power
consumption is low.
Q.49
In a RAM, information can be stored
(A)
By the user, number of times.
(B)
By the user, only once.
(C)
By the manufacturer, a number of times.
(D)
By the manufacturer only once.
ANS: A
RAM is used by the user, number of times.
Q.52 The chief reason
why digital computers
use complemented subtraction is that it
(A)
Simplifies the circuitry.
(B)
Is a very simple process.
(C)
Can handle negative numbers easily.
(D)
Avoids direct subtraction
ANS:
C
Using complement method negative numbers can also be subtracted.
Q.53
In a positive logic system, logic state 1 corresponds to
(A)
positive voltage (B) higher voltage level
(C) zero voltage level (D) lower
voltage level
ANS: B
We decide two
voltages levels for positive digital logic. Higher voltage represents logic 1
& a lower voltage represents logic 0.
Q.54 The commercially available 8-input multiplexer integrated circuit in the TTL family
is
(A) 7495. (B) 74153.
(C) 74154. (D) 74151.
ANS: B
MUX integrated circuit in TTL is 74153.
Q.55 CMOS circuits are extensively used for ON-chip
computers mainly because
of their extremely
(A)
low power dissipation. (B) high noise immunity.
(C) large packing density. (D) low cost.
ANS: C
BECAUSE CMOS CIRCUITS HAVE LARGE PACKING
DENSITY.
Q.56
The MSI chip 7474 is
(A)
Dual edge triggered JK flip-flop (TTL).
(B)
Dual edge triggered D flip-flop (CMOS).
(C)
Dual edge triggered D flip-flop (TTL).
(D)
Dual edge triggered JK flip-flop (CMOS).
ANS: C
MSI chip 7474 dual edge triggered D Flip-Flop.
Q.57
Which of the following memories stores the most number of bits
(A) a 5M´ 8 memory. (B) a
1M ´ 16 memory.
(C) a 5M ´ 4 memory. (D) a
1M ´12 memory.
ANS:
A
5Mx8 = 5 x 220 x 8 = 40M (max)
Q.58
The process of entering data into a ROM is called
(A)
burning in the ROM (B) programming the ROM
(C) changing the ROM (D) charging the ROM
ANS: B
The process of entering data into ROM is known as programming the ROM.
Q.59
When the set of input data to an even parity generator is 0111, the output will be
(A) 1 (B) 0
(C) Unpredictable (D) Depends on the previous input
ANS:
B
In even parity generator if
number of 1 is odd then output will be zero.
Q.60
The number 140 in octal is equivalent
to
(A) (96)10 . (B) (86)10 .
(C) (90)10 . (D) none of these.
ANS: A
(140)8 = (96)10
1 x 82 + 4 x 8 + 0x 1 = 64
+ 32 = 96
Q.61
The NOR gate output will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11
ANS: B, C, OR D
O/P is low if any of the I/P is high
Q.62
Which of the following is the fastest
logic?
(A) ECL (B) TTL
(C) CMOS (D) LSI
ANS: A
Q.63
How many flip-flops are
required to construct mod 30 counter
(A) 5 (B) 6
(C) 4 (D) 8
ANS:
A
Mod – 30 counter +/- needs 5 Flip-Flop as 30 < 25 Mod – N counter counts total ‘ N ‘ number of
states.
To count ‘N’ distinguished states we need
minimum n FlipFlop’s as [N = 2n] For eg. Mod
8 counter requires 3 Flip-Flop’s (8 = 23)
Q.64 How many address bits are required to represent a 32 K memory
(A)
10 bits. (B) 12 bits.
(C) 14 bits. (D) 16 bits.
ANS:
D
32K = 25 x 210 = 215,
Thus 15 address bits are required, Only 16 bits can address it.
Q.65 The number of control lines for 16 to 1 multiplexer is
(A) 2. (B) 4.
(C) 3. (D) 5.
ANS:
B
As 16 = 24, 4 Select lines are
required.
Q.66 Which of following requires refreshing?
(A)
SRAM. (B) DRAM.
(C) ROM. (D) EPROM.

ANS: B
Q.67 Shifting a register
content to left by one bit position
is equivalent to
(A)
division by two. (B) addition by two.
(C) multiplication by two. (D) subtraction by two.
ANS:C
Q.68
For JK flip flop with J=1, K=0, the output
after clock pulse will be
(A) 0. (B) 1.
(C) high impedance. (D) no change.
ANS: B
Q.69
Convert decimal 153 to octal.
Equivalent in octal will be
(A) (231)8 . (B) (331)8 .
(C) (431)8 . (D) none of these.
ANS: A
Q.70
The decimal equivalent of (1100)2 is
(A) 12 (B) 16
(C) 18 (D) 20
ANS: A
(1100)2 = (12)10
Q.71
The binary equivalent of (FA)16 is
(A) 1010 1111 (B) 1111 1010
(C) 10110011 (D) none
of these
ANS: B
(FA)16 = (11111010)10
Q.72
The output of SR flip flop when S=1, R=0 is
(A) 1 (B) 0
(C) No change (D) High impedance
ANS: A
As for the SR flip-flop S=set input R=reset input ,when S=1, R=0,
Flip-flop will be set.
Q.73
The number of flip flops contained in IC 7490 is
(A) 2. (B) 3.
(C) 4. (D) 10.
ANS: A
Q.74
The number of control lines for 32 to 1 multiplexer is
(A) 4. (B) 5.
(C) 16. (D) 6.
ANS: B
The number of control lines for 32 (25)
and to select one input among them total 5 select lines are required.
Q.75
How many two-input
AND and OR gates are required to realize Y=CD+EF+G
(A) 2,2. (B) 2,3.
(C) 3,3. (D) none
of these.
ANS: A
Y=CD+EF+G
Number of two input AND gates=2
Number of two input OR gates = 2
One OR gate to OR CD and EF and next to OR of G & output of first
OR gate.
Q.76
Which of following can not be accessed
randomly
(A)
DRAM. (B) SRAM.
(C) ROM. (D) Magnetic tape.
ANS: D
Magnetic tape can only be accessed sequentially.
Q.77
The excess-3 code of decimal 7 is represented by
(A) 1100. (B) 1001.
(C) 1011. (D) 1010.
ANS: D
An excess 3 code is always equal to the binary code +3
Q.78
When an input signal A=11001
is applied to a NOT gate serially, its output signal is
(A) 00111. (B) 00110.
(C) 10101. (D) 11001.
ANS: B
As A=11001 is serially applied to a NOT gate, first input applied will
be LSB 00110.
Q.79
The result of adding hexadecimal number A6 to 3A is
(A)
DD. (B) E0.
(C) F0. (D) EF.
ANS: B
Q.80
A universal logic gate is one, which can be used to generate any logic
function. Which of the following is a universal logic gate?
(A) OR (B) AND
(C) XOR (D) NAND
ANS: D
NAND can generate any logic function.
Q.81
The logic 0 level of a CMOS logic device is approximately
(A)
1.2 volts (B) 0.4 volts
(C) 5 volts (D) 0 volts
ANS: D
CMOS logic low level is 0 volts approx.
Q.82
Karnaugh map is used for the purpose
of
(A)
Reducing the electronic circuits used.
(B)
To map the given Boolean logic function.
(C)
To minimize the terms in a Boolean expression.
(D)
To maximize the terms of a given a Boolean expression.
ANS: C
Q.83
A full adder logic circuit will have
(A)
Two inputs and one output.
(B)
Three inputs and three outputs.
(C)
Two inputs and two outputs.
(D)
Three inputs and two outputs.
ANS:
D
A full adder
circuit will add two bits and it will also accounts the carry input generated
in the previous stage. Thus three inputs and two outputs (Sum and Carry) are
there.
Q.84
An eight stage ripple counter uses a flip-flop with propagation delay
of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the
input signal which can be used for proper operation of the counter is approximately
(A) 1 MHz. (B) 500 MHz.
(C) 2 MHz. (D) 4 MHz.
ANS: A
Maximum time taken for all

flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must
be less than 1/650ns = 1.5 MHz.
Q.85
The output of a JK flipflop with asynchronous preset and clear inputs
is ‘1’. The output can be changed to ‘0’ with one of the following conditions.
(A) By applying J = 0, K = 0 and
using a clock.
(B)
By applying J = 1, K = 0 and using the
clock.
(C)
By applying J = 1, K = 1 and using the
clock.
(D)
By applying a synchronous preset input.
ANS: C
Preset state of JK Flip-Flop =1
With J=1 K=1 and the clock next
state will be complement of the present state.
Q.86
The information in ROM is stored
(A)
By the user any number of times.
(B)
By the manufacturer during fabrication of the device.
(C)
By the user using ultraviolet light.
(D)
By the user once and only once.
ANS: B
Q.87
The conversation speed of an analog to digital converter is maximum
with the following technique.
(A) Dual slope AD converter.
(B)
Serial comparator AD converter.
(C)
Successive approximation AD converter.
(D)
Parallel comparator AD converter.
ANS: D
Q.88
A weighted resistor
digital to analog converter using N bits requires a total of
(A) N precision resistors. (B) 2N precision resistors.
(C) N + 1 precision resistors. (D) N – 1 precision resistors.
ANS: A
Q.89
The 2’s complement of the number 1101110 is
(A) 0010001. (B) 0010001.
(C) 0010010. (D) None.
ANS: C
1’s complement of 1101110 is = 0010001
Thus 2’s complement of 1101110 is = 0010001 + 1 = 0010010
Q.90
The decimal equivalent of Binary number 10101 is
(A) 21 (B) 31
(C) 26 (D) 28
ANS:
A
1×24 + 0x23 +1×22 +0x21 + 1×20
= 16 + 0 + 4 + 0 + 1 = 21.
Q.91
How many two input AND gates and two input OR gates
are required to realize
Y = BD+CE+AB
(A) 1, 1 (B) 4, 2
(C) 3, 2 (D) 2, 3
ANS: A
There are three product terms, so three AND gates of two inputs are
required.
As only two input OR gates are
available, so two OR gates are required to get the logical sum of three product
terms.
Q.92
How many select lines will a 32:1 multiplexer will have
(A) 5. (B) 8.
(C) 9. (D) 11.
ANS: A
For 32 inputs, 5 select lines will be required, as 25 = 32.
Q.93
How many address bits are required to represent 4K memory
(A)
5 bits. (B) 12 bits.
(C) 8 bits. (D) 10 bits.
ANS: B
For representing 4K
memory, 12 address bits are required as
4K = 22 x
210 = 212 (1K = 1024 = 210)
Q.94
For JK flipflop J = 0, K=1, the output after clock pulse will be
(A)
1. (B) no change.
(C) 0. (D) high impedance.
ANS: C
J=0, K=1, these inputs will reset the flip-flop after the clock pulse.
So whatever be the previous output, the next state will be 0.
Q.95
Which of following are known as universal gates
(A)
NAND & NOR. (B) AND & OR.
(C) XOR & OR. (D) None.
ANS: A
NAND & NOR are known as universal gates, because any digital
circuit can be realized completely by using either of these two gates.
Q.96
Which of the following memories
stores the most number of bits
(A) 64K ´ 8 memory. (B) 1M
´ 8 memory.
(C) 32M
´ 8 memory. (D) 64 ´ 6 memory.
ANS: C
32M x 8 stores most number of bits
25 x 220 = 225 (1M = 220 = 1K x 1K = 210 x 210)
Q.97
Which of following consume minimum
power
(A)
TTL. (B) CMOS.
(C) DTL. (D) RTL.
ANS: B
CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS
transistors are connected in complimentary mode, such that one device
is ON & one is OFF.
DTM oral questions
1. which are the basic logic gates
2. Which are universal Gates
3. what is equation of XOR gate
4. what is equation of ex nor Gate
5. why n a n d Gate is called Universal Gate
6. what is equation of of half adder outputs sum and carry
7. which are output of half subtractor
8. what is equation of sum in full adder
9. how many select lines are used in 8 is to 1 multiplexer
10. Explain working of multiplexer is difference between multiplexer
and demultiplexer
11. How many select lines are required for 32 is to 1 mux list the
types of flip flops
12. which are outputs of SR flip flop
13. what will happen when s equal to R equal to 1
14. what is race around condition
15. why t flip flop is called as toggle flip flop
16. what are the applications of D flip flop and T flip flop
17. list types of shift registers what is function of EU and BIU
18. which are the general purpose registers
19. list the the segment registers
20. List the memory segments in 8086 memory
21. what is the size of instruction queue in 8086
22.how many bits are there in flag register
23.Which flags are affected after arithmetic instructions
24. what is the size of data bus in 8086
25. what is the size of address bus in 8086
26.how physical address is generated in microprocessor 8086
27. which is the instruction for 8 bit addition
28. suggest instruction for 16 bit addition
29.tell the instruction for 8 bit multiplication
30. which instruction is used for 16 bit multiplication
31. where the result of 16 bit multiplication is stored
32.what are the output of 16 by 8 division
33.where the outputs are stored after 32 by 16 bit division?
34. which is k e y instruction for sum of series
35. which is the instruction for finding largest number and
smallest number in an array.
36.what is difference between jmp and jnz
37.tell any five string instructions
Chapter 1
Introduction to Digital Techniques
Hours
16 Marks
1.1 Basics of Digital Techniques
Modern digital computers, mobile communication systems, Internet etc.

have become part and parcel of society nowadays. This has become possible
basically due to Integrated Circuits (ICs). The operation of computers,
communications systems etc. is based on digital techniques.
1.1.1 Digital Signal and Digital Systems

The signals which are continuous and can have any value in a limited
range are called analog signals. A sample analog signal is shown in figure 1.1.
Figure 1.1: Sample analog signal

Electronic circuits used for processing analog signals are called as analog
circuits and the systems build for this kind of operation are called as analog
systems. One of the examples of analog system is electronic amplifier.
On the other hand, the signals which are discrete and can have only two
discrete levels or values are called digital signals. A sample digital signal is
shown in figure 1.2.
Figure 1.2: Sample digital signal

The two levels in a digital signal can be represented using the terms
HIGH and LOW. HIGH level can also be represented as ON or value ‘1’.
Similarly, LOW level can be represented as OFF or value ‘0’.
Electronic circuits used for processing digital signals are called as digital
circuits and the systems build for this kind of operation are called as digital
systems. One of the examples of digital system is electronic calculator.
1-1
1.1.2 Positive and Negative Logic
In digital systems there are two states – one for representing value ‘1’ and
other for representing value ‘0’ (as a binary variable can have value either 0 or
1). These states are represented by two different voltage levels (or sometimes
current levels).
If logic state ‘1’ is represented by a higher voltage level (or current level)
and logic state ‘0’ is represented by a lower voltage level (or current level), it is
called as positive logic system. E.g. If 0V and +5V are the two voltage levels
and +5V is used for representing ‘1’ and 0V is used for representing ‘0’, this is a
positive logic system.
5V
HIGH
3.5 V
1V
LOW
0V
Figure 1.3: Positive Logic
If logic state ‘0’ is represented by a higher voltage level (or current level)
and logic state ‘1’ is represented by a lower voltage level (or current level), it is
called as negative logic system. E.g. If 0V and +5V are the two voltage levels
and +5V is used for representing ‘0’ and 0V is used for representing ‘1’, this is a
negative logic system.
5V
LOW
3.5 V
1V
HIGH
0V
Figure 1.4: Negative Logic
1.1.3 Advantages of Digital Systems

- In digital systems devices generally operate in one of the two states only
i.e. ON and OFF. It results in simple operations.
- There are only few basic operations those can be learnt easily.
- Large number of ICs is available.
- Effect of fluctuations and noise is less.
- Digital systems have capability of memory.
- Digital systems can be easily controlled through computer software.
- They are less expensive.
- They are more reliable.
- They are easy to design.
1-2
- They have higher accuracy.
1.1.4 Disadvantages of Digital Systems

- Even if digital system has so many advantages, real world is analog. All
the real world signals (like velocity, acceleration, temperature, light,
sound, electric and magnetic field etc.) are analog.
- The real world analog signals need to be digitized.
- If a single piece of digital data is missed, large block of data may change
completely.
- Digital communication requires more bandwidth than analog
communication.
- Digital systems are prone to sampling errors.
1.1.5 Applications of Digital Systems

- Digital Audio
- Digital Photography
- Audio and speech processing
- Image processing
- Biomedical signal processing
- Archaeology
- Cell phones
- Fingerprint Processing
- Face detection
- Rolling display
- Industrial automation
1.2 Logic Families
For producing different types of digital integrated circuits (ICs) different

circuit configurations or approaches are used. Each such fundamental approach
is called logic family. Different logic functions may be fabricated in the form of
IC with same approach. i.e. Same logic family may have different logic
functions. All the ICs in same logic family have same characteristics. That’s why
digital ICs belonging to same logic family are compatible with each other.
1.2.1 Characteristics of logic families

(or Characteristics of digital ICs)
There is variety of logic families. Selection of a logic family for an
application depends on its characteristics. For a real-time application immediate
response is required. In such application logic family with high speed of
operation should be selected.
Important characteristics of logic families are,
- Speed of operation
- Power dissipation
- Figure of merit
- Current and voltage parameters
- Fan-out
- Fan-in
1-3
- Noise immunity
- Power supply requirements
- Operating temperature
1.2.1.1 Speed of operation

It is desirable that a digital IC should have high speed of operation. Speed
of operation of a circuit is specified in terms of propagation delay time (i.e. lesser
the propagation delay time → higher the speed of operation).
There are two delay times.
𝑡𝑝𝐻𝐿 → Delay time when output goes from HIGH state to LOW state
𝑡𝑝𝐿𝐻 → Delay time when output goes from LOW state to HIGH state
Propagation delay time is computed as the average of these two delay
times as,
𝑡𝑝𝐻𝐿 + 𝑡𝑝𝐿𝐻
𝑡𝑝 =
2
The two delay times are computed by finding the time difference 50%
voltage levels of input and output waveforms as shown in figure 1.5.
Figure 1.5: Computation of tpLH and tpHL

The propagation delay between input and output must be as low as
possible.
1.2.1.2 Power Dissipation

For operation of every electronic circuit, certain amount of electric power
is required. Out of supplied power, some power gets dissipated in electronic
circuits. This is due to wastage of power across electronic components. i.e.
Power dissipation is nothing but wastage of power across electronic
components or devices within a circuit. Power dissipation of a circuit is
expressed in terms of milliwatt (mW).
If power dissipation for a circuit is less, the circuit requires less power to
be supplied to it. So, power dissipation should be as less as possible
1.2.1.3 Figure of Merit

It is always desirable for an electronic circuit to have less power
dissipation (for reducing power requirements). But when power dissipation is
reduced in an electronic circuit, its speed of operation also gets reduced (In other
words, propagation delay gets increased).
As per above discussion, there is a trade-off between power dissipation
and speed of operation (which is denoted in terms of propagation delay). So,
instead of the two parameters speed of operation and power dissipation, a single
parameter called figure of merit is used for comparison of logic families. Figure
of merit is a product of propagation delay and power dissipation.
𝐹𝑖𝑔𝑢𝑟𝑒𝑜𝑓𝑚𝑒𝑟𝑖𝑡 = 𝑝𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛𝑑𝑒𝑙𝑎𝑦 × 𝑝𝑜𝑤𝑒𝑟𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛
Figure of merit is measured in terms of Pico-Joules (𝑛𝑠 × 𝑚𝑊 = 𝑝𝐽)
1.2.1.4 Current and Voltage Parameters

1-4
These parameters define minimum and maximum limits of current and
voltage for input and output of a logic family.
VIH (HIGH level Input Voltage) : It is the minimum input voltage
corresponding to logic ‘1’ state.
VIL (LOW level Input Voltage) : It is the maximum input voltage
VOH (HIGH level Output Voltage) : It is the minimum output voltage
VOL (LOW level Output Voltage) : It is the maximum output voltage
IIH (HIGH level Input Current) : It is the minimum input current
IIL (LOW level Input Current) : It is the maximum input current
IOH (HIGH level Output Current) : It is the minimum output current
This current is also called as
source current.
IOL (LOW level Output Current) : It is the maximum output current
This current is also called as sink
current.
Figure 1.6: A gate driving N gates

1.2.1.5 Fan–out
Generally, output of one logic gate feeds input to several other gates.
Practically, it is not possible to drive unlimited number of logic gates from
output of a single logic gate.
Fan–out is the maximum number of similar gates that can be driven by a
logic gate. As shown in figure 1.6, if the driver gate is capable of driving at the
most N gates, fan–out of the driver gate is N.
If we try to drive more than N gates, current supply required to drive the
gates may become lesser than the minimum requirement (in case of HIGH
state) or current sink by the driver gate may become greater than its sink
capacity (in case of LOW state).
𝐼 𝐼
Fan–out can be computed as minimum of the ratios 𝐼𝑂𝐻 and 𝐼𝑂𝐿as,
𝐼𝐻 𝐼𝐿
𝐼𝑂𝐻 𝐼𝑂𝐿
𝐹𝑎𝑛 − 𝑜𝑢𝑡 = 𝑚𝑖𝑛 { , }
𝐼𝐼𝐻 𝐼𝐼𝐿
1.2.1.6 Fan–in
Fan–in is the number of inputs to a gate. For a two-input gate, fan–in is 2
and for a 3-input gate, fan–in is 3 and so on.
1.2.1.7 Noise Immunity
1-5
Unwanted signal is called as noise. Stray electric or magnetic fields may
induce noise in the input to the digital circuits. Due to noise, input voltage may
drop below VIH or may rise above VIL. Both the circumstances will result in
undesired operations of the digital circuit.
Every circuit should have ability to tolerate the noise signal. This ability
of tolerating noise signal is called as noise immunity. Measure of noise
immunity is called as noise margin. The noise margin at logic ‘1’ state and
logic ‘0’ state are computed as,
Logic ‘1’ state noise margin: ∆1 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻
Logic ‘0’ state noise margin: ∆0 = 𝑉𝑂𝐿 − 𝑉𝐼𝐿
1.2.1.8 Power Supply Requirements

Every electronic circuit requires certain supply voltage to operate. The
required supply voltage and power should be as less as possible.
1.2.1.9 Operating Temperature

Operating temperature is range of temperature in which an IC functions
properly. An IC is selected for a specific application depending on its operating
temperature. Generally the range of operating temperature is within −550 𝐶 to
+1250 𝐶.
1.2.2 Classification of Logic Families

Entire range of digital ICs is fabricated using either bipolar devices or
MOS devices or a combination of the two.
Different logic families falling in the first category are called bipolar
families. These families include diode logic (DL), resistor–transistor logic (RTL),
diode–transistor logic (DTL), transistor–transistor logic (TTL), emitter–coupled
logic (ECL), also known as current mode logic (CML), and integrated injection
logic (I2L).
The logic families that use MOS devices are known as MOS families.
These families include PMOS family (using P-channel MOSFETs), the NMOS
family (using N-channel MOSFETs) and the CMOS family (using both N- and P-
channel devices).
The Bi-MOS logic family uses both bipolar and MOS devices.
1-6
Logic Families
Bi-MOS Logic
Bipolar Families MOS Families
Family
Resistor
Diode Logic (DL) Transistor Logic PMOS Family NMOS Family
(RTL)
Transistor
Diode Transistor
Transistor CMOS Family
Logic (DTL)
Logic (TTL)
Emitter Integrated
Coupled Logic Injection Logic
(ECL) (I2L)
Figure 1.7: Classification of Logic Families

Logic families that are currently in widespread use include TTL, CMOS,
ECL, NMOS and Bi-CMOS.
1.2.2.1 Transistor–Transistor Logic (TTL) Family

Transistor is the basic element of this logic family. Transistor operates in
either cut-off region or saturation region. TTL Family has number of subfamilies
including standard TTL, low-power TTL, high-power TTL, low-power Schottky
TTL, Schottky TTL, advanced low-power Schottky TTL, fast TTL etc. The ICs
belonging to TTL family are designated as,
74 or 54 : Standard TTL
74L or 54L : Low-power TTL
74H or 54H : High-power TTL
74LS or 54LS : Low-power Schottky TTL
74S or 54S : Schottky TTL
74ALS or 54ALS : Advanced Low-power Schottky TTL
74F or 54F : Fast TTL
Characteristic parameters and features of the standard TTL family of
devices include the following:
VIL=0.8 V
VIH=2 V
IIH=40 µA
IIL=1.6 mA
VOH=2.4 V
VOL=0.4 V
IOH=400 µA
IOL=16 mA
1-7
propagation delay
= 22ns (max.) for LOW-to-HIGH transition at the output
= 15ns (max.) for HIGH- to-LOW output transition
worst-case noise margin=0.4V
fan-out=10
operating temperature range
=0°C to 70°C (74- series)
=−55°C to +125°C (54-series)
speed–power product=100pJ
1.2.2.2 Emitter–Coupled Logic (ECL) Family

Currently, popular sub-families of ECL include MECL-III (also called the
MC 1600 series), the MECL-10K series, the MECL-10H series and the MECL-
10E series.
Characteristic parameters and features of the MECL-III family of devices
include the following:
gate propagation delay=1ns
output edge speed =1ns
(indicative of the rise and fall time of output transition)
power dissipation per gate=50mW
speed–power product=60pJ
input voltage=0–VEE (VEE is the negative supply voltage)
negative power supply range (for VCC=0)=−5.1V to −5.3 V
continuous output source current (max.)=40mA
surge output source current (max.) = 80mA
operating temperature range=−30°C to +85°C.
1.2.2.3 Complementary Metal Oxide Semiconductor (CMOS) Family

This logic family uses both P-channel and N-channel MOSFETs. Popular
CMOS sub-families include 4000A, 4000B, 4000UB, 54/74C, 54/74HC,
54/74/HCT, 54/74AC and 54/74ACT families (The 54/74 sub-families are pin-
compatible with 54/74 TTL series logic functions).
Characteristic features of 4000B and 4000UB CMOS devices are as
follows:
VIH (buffered devices)
=3.5V (for VDD=5V)
=7.0 V (for VDD =10 V)
=11.0V (for VDD =15V)
VIH (unbuffered devices)
=4.0V (for VDD = 5V)
=8.0 V (for VDD =10V)
=12.5V (for VDD =15V)
IIH=1.0µA
IIL=1.0µA
IOH =0.2mA (for VDD =5V)
=0.5mA (for VDD =10V)
IOL =0.52mA (for VDD =5V)
=1.3mA (for VDD = 10V)
1-8
VIL (buffered devices) =1.5V (for VDD =5V)
=3.0V (for VDD = 10V)
=4.0V (for VDD = 15V)
VIL (unbuffered devices) =1.0V (for VDD =5V)
=2.0V (for VDD = 10V)
=2.5V (for VDD =15V)
VOH =4.95V (for VDD =5V)
=9.95V (for VDD =10V)
=14.95V (for VDD =15V)
VOL=0.05V
VDD =3– 15V
propagation delay (buffered devices) =150ns (for VDD =5V)
=65ns (for VDD =10V)
propagation delay (unbuffered devices) =60ns (for VDD =5V)
noise margin (buffered devices) =1.0V (for VDD =5V)
=2.0V (for VDD =10V)
=2.5V (for VDD = 15V)
noise margin (unbuffered devices) =0.5V (for VDD =5V)
=1.0V(for VDD =10V)
=1.5V(for VDD =15V)
Output transition time (for VDD =5Vand CL=50pF)
=100ns (buffered devices)
=50–100ns (for unbuffered devices)
power dissipation per gate (for f =100kHz)=0.1mW
speed–power product (for f =100kHz)=5pJ
1.3 Number System
Number system is one of the most important and basic topic in digital
electronics. It is important to understand a number system as it helps in
understanding how data is represented before processing it in digital system.
Important characteristics of number systems are:
- Independent digits used (radix or base).
- Place value of different digits.
- Maximum numbers that can be represented using given number of
digits.
In a number system there is an ordered set of symbols (digits) with rules

defined for performing arithmetic operations like addition, subtraction,
multiplication etc.
(𝑁)𝑏 = 𝑑𝑛−1 𝑑𝑛−2 … 𝑑𝑖 … 𝑑2 𝑑1 𝑑0 . 𝑑−1 𝑑−2 … 𝑑−𝑓 … 𝑑−𝑚+1 𝑑−𝑚
Integer part Radix Point Fractional part
1-9
Where,
N → A number
b → Base or radix of the number system
n → Number of digits in Integer part
m → Number of digits in Fractional part
𝑑𝑛−1 → Most Significant Digit (MSD)
𝑑−𝑚 → Least Significant Digit (LSD)
Each digit (i.e. 𝑑𝑖 and 𝑑−𝑓 ) must be within the range from 0 to b–1
including the boundaries.
1.3.1 Decimal Number System

Base of decimal number system is 10. It is also called as radix-10 number
system. In this number system, 10 independent digits are used. They are:
0 1 2 3 4 5 6 7 8 9
All the numbers are represented using these digits only. One can
represent whole numbers as well as fractional numbers (requires additional
period symbol. i,e, ‘.’) using these digits. Some examples are given below.
149 39754 22361803 11
23.67333 100.001 .75 10.50
The place values of different digits in a decimal number are 10 0, 101, 102,
103 and so on. Value (also called as magnitude) of a decimal number can be
expressed as sum of multiplication of each digit by its place value. An example is
shown below.
(39754)10 = 4 × 100 + 5 × 101 + 7 × 102 + 9 × 103 + 3 × 104
4 × 1 + 5 × 10 + 7 × 100 + 9 × 1000 + 3 × 10000
4 + 50 + 700 + 9000 + 30000
𝐷𝑒𝑐𝑖𝑚𝑎𝑙𝑣𝑎𝑙𝑢𝑒39754
For fractional part, place values of different digits are 10-1, 10-2, 10-3, 10-4
and so on. An example is shown below.
(10.50)10 = 1 × 101 + 0 × 100 + 5 × 10−1 + 0 × 10−2
1 × 10 + 0 × 1 + 5 × 0.1 + 0 × 0.01
10 + 0 + 0.5 + 0
𝐷𝑒𝑐𝑖𝑚𝑎𝑙𝑣𝑎𝑙𝑢𝑒10.5
1.3.2 Binary Number System

Base of binary number system is 2. It is also called as radix-2 number
system. In this number system, 2 independent digits are used.
They are:
0 1
All the numbers are represented using these digits only. Generally, a
digit in binary number system is called as bit (i.e. binary digit). One can
110 0 101110 1
1-10
101.1010 1.001 .100 1110.10
The place values of different digits in a binary number are 2 0, 21, 22, 23
and so on. Value (also called as magnitude) of a binary number can be expressed
as sum of multiplication of each bit by its place value. An example is shown
below.
(10110)2 = 0 × 20 + 1 × 21 + 1 × 22 + 0 × 23 + 1 × 24
0 × 1 + 1 × 2 + 1 × 4 + 0 × 8 + 1 × 16
0 + 2 + 4 + 0 + 16
For fractional part, place values of different bits are 2-1, 2-2, 2-3, 2-4 and so
on. An example is shown below.
(10.01)2 = 1 × 21 + 0 × 20 + 0 × 2−1 + 1 × 2−2
1 × 2 + 0 × 1 + 0 × 0.5 + 1 × 0.25
2 + 0 + 0 + 0.25
Some important units in binary number system along with their
meanings are shown in table 1.1.
Table 1.1: Units in Binary number system

Unit Meaning
Bit Single binary digit (0 or 1)
Nibble Group of 4 bits
Byte Group of 8 bits
Word Number of bits that can be processed by a computer at a time. It may
vary from one computer to another. Generally it equals to 1 byte, 2
bytes, 4 bytes or even larger.
Advantages of Binary Number System

Binary number system is simplest possible number system.
Logic operations are backbone of any digital computer. Logic operations
are nothing but operations that deal with TRUE (‘1’) and FALSE (‘0’). So, in
digital computers, binary number system is most prominently used number
system.
As data is represented using 0’s and 1’s, basic electronic devices used in
implementation of hardware can easily handle the data (by considering OFF for
‘0’ and ON for ‘1’).
As data is represented using 0’s and 1’s, circuits required for performing
arithmetic operations like addition, subtraction etc can be easily designed.
1.3.3 Octal Number System

Base of octal number system is 8. It is also called as radix-8 number
system. In this number system, 8 independent digits are used. They are:
0 1 2 3 4 5 6 7
1-11
146 32754 22361203 11
23.67333 100.001 .75 10.50
The place values of different digits in a decimal number are 8 0, 81, 82, 83
and so on. Value (also called as magnitude) of a octalal number can be expressed
as sum of multiplication of each digit by its place value. An example is shown
below.
(32754)8 = 4 × 80 + 5 × 81 + 7 × 82 + 2 × 83 + 3 × 84
4 × 1 + 5 × 8 + 7 × 64 + 2 × 512 + 3 × 4096
4 + 40 + 448 + 1024 + 12288
For fractional part, place values of different digits are 8 -1, 8-2, 8-3, 8-4 and
so on. An example is shown below.
(10.50)8 = 1 × 81 + 0 × 80 + 5 × 8−1 + 0 × 8−2
1 × 8 + 0 × 1 + 5 × 0.125 + 0 × 0.0625
8 + 0 + 0.625 + 0
1.3.4 Hexadecimal Number System

Base of hexadecimal number system is 16. It is also called as radix-16
number system. In this number system, 16 independent digits are used. They
are:
0 1 2 3 4 5 6 7 8 9 A B C D E F
Values of additional digits are,
Digit Value Digit Value
A 10 B 11
C 12 D 13
E 14 F 15
149 F1AB 22C 1D3
23.67333 1E.001 .A5 10.50
The place values of different digits in a decimal number are 160, 161, 162,
163 and so on. Value (also called as magnitude) of a hexadecimal number can be
expressed as sum of multiplication of each digit by its place value. An example is
shown below.
(𝐹1𝐴𝐵)16 = 𝐵 × 160 + 𝐴 × 161 + 1 × 162 + 𝐹 × 163
11 × 1 + 10 × 16 + 1 × 256 + 15 × 4096
11 + 160 + 256 + 61440
For fractional part, place values of different digits are 16 -1, 16-2, 16-3, 16-4
and so on. An example is shown below.
(10.50)16 = 1 × 161 + 0 × 160 + 5 × 16−1 + 0 × 16−2
1 × 16 + 0 × 1 + 5 × 0.0625 + 0 × 0.00390625
1-12
16 + 0 + 0.3125 + 0
Advantages of Hexadecimal Number System

As already discussed previously, binary number system is used for
representing data in digital computers. Hexadecimal number system, on the
other hand, provides compact way of representing large binary numbers. A
value 250 can be represented in binary number system as 11111001. This is a
big number. It can be represented in very compact form in hexadecimal number
system as F9.
Due to compact representation of large binary numbers they can be easily
understood and handled.
1.3.5 Conversion of Number Systems

A number represented using one number system can be converted into its
equivalent number in any other number system. i.e. a number can be easily
converted from one number system to another. The original number and the
output of conversion are equivalent of each other. Processes used for converting
a number from one number system to another number system are discussed
below.
1.3.5.1 Binary to Decimal conversion

Decimal equivalent of a binary number can be found by adding sum of
multiplication of each bit by its place value.
Example 1:
(111010)2 = 1 × 25 + 1 × 24 + 1 × 23 + 0 × 22 + 1 × 21 + 0 × 20
1 × 32 + 1 × 16 + 1 × 8 + 0 × 4 + 1 × 2 + 0 × 1
32 + 16 + 8 + 0 + 2 + 0
(58)10
Example 2:
(1101.01)2 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 + 0 × 2−1 + 1 × 2−2
1 × 8 + 1 × 4 + 0 × 2 + 1 × 1 + 0 × 0.5 + 1 × 0.25
8 + 4 + 0 + 1 + 0 + 0.25
(13.25)10
1.3.5.2 Octal to Decimal conversion

Decimal equivalent of octal number can be found by adding sum of
multiplication of each bit by its place value.
Example 1:
(6251)8 = 6 × 83 + 2 × 82 + 5 × 81 + 1 × 80
6 × 512 + 2 × 64 + 5 × 8 + 1 × 1
3072 + 128 + 40 + 1
(3241)10
Example 2:
(37.40)8 = 3 × 81 + 7 × 80 + 4 × 8−1 + 0 × 8−2
3 × 8 + 7 × 1 + 4 × 0.125 + 0 × 0.0625
24 + 7 + 0.5 + 0
1-13
(31.5)10
1.3.5.3 Hexadecimal to Decimal conversion

Decimal equivalent of a hexadecimal number can be found by adding sum
of multiplication of each bit by its place value.
Example 1:
(20𝐴𝐵)16 = 20 × 163 + 0 × 162 + 𝐴 × 161 + 𝐵 × 160
20 × 4096 + 0 × 256 + 10 × 16 + 11 × 1
81920 + 0 + 160 + 11
(82091)10
Example 2:
(𝐷𝐶. 61)16 = 𝐷 × 161 + 𝐶 × 160 + 6 × 16−1 + 1 × 16−2
13 × 16 + 12 × 1 + 6 × 0.0625 + 1 × 0.00390625
208 + 12 + 0.375 + 0.00390625
(220.37890625)10
1.3.5.4 Decimal to Binary conversion

While converting Decimal number into its binary equivalent, the
conversion process for integer part and fraction part are different. So, these
parts must be separated first.
For integer part, decimal number is successively divided by 2 (which is
base or radix of binary number system) until the quotient becomes zero and the
remainders are recorded in each step. The number formed by writing
remainders in reverse order is the binary equivalent of integer part.
For fractional part, it is successively multiplied by 2 (which is base or
radix of binary number system) until result of multiplication is 0 and the carries
are recorded in each step. The number formed by writing carries in forward
order is the binary equivalent of fractional part. If we are not getting the result
of multiplication as zero after multiple iterations, we may stop the process after
getting desired number of bits.
Example 1:
(293.52)10 = (? )2
As a first step, the number should be separated in integer part and
fractional parts as,
(293.52)10 = (293)10 + (0.52)10
Converting the integer part (293)10 :

Divisor Dividend Remainder
2 293 --
2 146 1
2 73 0
2 36 1
2 18 0
2 9 0
1-14
2 4 1
2 2 0
2 1 0
-- 0 1
(293)10 = (100100101)2
Converting the fractional part (0.52)10 :
Fraction Multiplier Result Carry
.52 2 .04 1
.04 2 .08 0
.08 2 .16 0
.16 2 .32 0
.32 2 .64 0
.64 2 .28 1
.28 2 .56 0
.56 2 .12 1
. .
. .
. .
(0.52)10 = (. 10000101)2
Therefore,
(293.52)10 = (100100101.10000101)2
Example 2:
(63.25)10 = (? )2
(63.25)10 = (63)10 + (0.25)10
2 63 --
2 31 1
2 15 1
2 7 1
2 3 1
2 1 1
-- 0 1
(63)10 = (111111)2
.25 2 .5 0
.5 2 .0 1
(0.25)10 = (. 01)2
Therefore,
1-15
(63.25)10 = (111111.01)2
1.3.5.5 Decimal to Octal conversion

While converting Decimal number into its octal equivalent, the conversion
process for integer part and fraction part are different. So, these parts must be
separated first.
base or radix of octal number system) until the quotient becomes zero and the
remainders are recorded in each step. The number formed by writing
remainders in reverse order is the octal equivalent of integer part.
radix of octal number system) until result of multiplication is 0 and the carries
are recorded in each step. The number formed by writing carries in forward
order is the octal equivalent of fractional part. If we are not getting the result of
multiplication as zero after multiple iterations, we may stop the process after
getting desired number of octal digits.
Example 1:
(293.52)10 = (? )8
(293.52)10 = (293)10 + (0.52)10
8 293 --
8 36 5
8 4 4
-- 0 4
(293)10 = (445)2
.52 8 .16 4
.16 8 .28 1
.28 8 .24 2
.24 8 .92 1
.92 8 .36 7
.36 8 .88 2
.88 8 .04 7
.04 8 .32 0
. .
. .
(0.52)10 = (. 41217270)2
Therefore,
(293.52)10 = (445.41217270)2
Example 2:
(63.25)10 = (? )8
1-16
(63.25)10 = (63)10 + (0.25)10
8 63 --
8 7 7
-- 0 7
(63)10 = (77)8
.25 8 .0 2
(0.25)10 = (. 2)8
Therefore,
(63.25)10 = (77.2)8
1.3.5.6 Decimal to Hexadecimal conversion

While converting Decimal number into its hexadecimal equivalent, the
conversion process for integer part and fraction part are different. So, these
parts must be separated first.
base or radix of hexadecimal number system) until the quotient becomes zero
and the remainders are recorded in each step. The number formed by writing
remainders in reverse order is the hexadecimal equivalent of integer part.
radix of hexadecimal number system) until result of multiplication is 0 and the
carries are recorded in each step. The number formed by writing carries in
forward order is the hexadecimal equivalent of fractional part. If we are not
getting the result of multiplication as zero after multiple iterations, we may stop
the process after getting desired number of octal digits.
Example 1:
(293.52)10 = (? )16
(293.52)10 = (293)10 + (0.52)10

16 293 --
16 18 5
1-17
16 1 2
-- 0 1
(293)10 = (125)16
.52 16 .32 8
.32 16 .12 5
.12 16 .92 1
.92 16 .72 14(E)
.72 16 .52 11(B)
.52 16 .32 8
.32 16 .12 5
Results will be repeated
(0.52)10 = (. 851𝐸𝐵)16
Therefore,
(293.52)10 = (125.851𝐸𝐵)16
Example 2:
(63.25)10 = (? )16
(63.25)10 = (63)10 + (0.25)10
16 63 --
16 3 15(F)
-- 0 3
(63)10 = (3𝐹)16
.25 16 .0 4
(0.25)10 = (. 4)16
Therefore,
(63.25)10 = (3𝐹. 4)16
1.3.5.7 Octal to Binary and Binary to Octal conversion

While converting octal number into its binary equivalent, each octal digit
is replaced by its three-bit binary equivalent. The binary equivalents of all
independent octal digits are shown in table 1.2.
Table 1.2: Octal Digits and their binary equivalents
Octal Digit Binary equivalent
1-18
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Example 1:
(273.52)8 = (? )2
Each octal digit is replaced by its three-bit binary equivalent.
2 7 3 . 5 2
Therefore, 010 111 011 . 101 010 (273.52)8 =
(010111011.101010)2
Example 2:
(63.25)8 = (? )2
Each octal digit is replaced by its three-bit binary equivalent.
6 3 . 2 5
Therefore, 110 011 . 010 101 (63.25)8 =
(110011.010101)2
For converting a binary number into octal number both the integer part
and the fractional part of the binary number are split into groups of three bits
starting from radix point (in binary number system it may be called as binary
point). If the outermost groups are not complete (i.e. of three bits), then
sufficient number of 0’s are added to make them complete (on left side of
leftmost group and on right side of rightmost group). Then each group is
replaced by its octal equivalent as shown in table 1.2.
Example 1:
(1010101.0101)2 = (? )8
The binary number is split into groups of three bits from binary point.
1 010 101 . 010 1
Here the first group and the
last group are incomplete. For completing them 0’s are added on left side of first
group and on right side of last group.
001 010 101 . 010 100
Then octal equivalent of each
group of bits is written.
001 010 101 . 010 100
1 2 5 . 2 4
Therefore, (1010101.0101)2 =
(125.24)8
Example 2:
(11010.01)2 = (? )8
1-19
The binary number is split into groups of three bits from binary point.
11 010 . 01
Here the first group and the last group
are incomplete. For completing them 0’s are added on left side of first group and
on right side of last group.
011 010 . 010
Then octal equivalent of each group
of bits is written.
011 010 . 010
3 2 . 2
Therefore, (11010.01)2 = (32.2)8
1.3.5.8 Hexadecimal to Binary and Binary to Hexadecimal conversion

While converting hexadecimal number into its binary equivalent, each
hexadecimal digit is replaced by its four-bit binary equivalent. The binary
equivalents of all independent hexadecimal digits are shown in table 1.3.
Table 1.3: hexadecimal Digits and their binary equivalents
Hexadecimal Binary equivalent
Digit
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
A 1 0 1 0
B 1 0 1 1
C 1 1 0 0
D 1 1 0 1
E 1 1 1 0
F 1 1 1 1
Example 1:
(273. 𝐴2)16 = (? )2
Each hexadecimal digit is replaced by its four-bit binary equivalent.
2 7 3 . A 2
Therefore, 0010 0111 0011 . 1010 0010 (273. 𝐴2)16 =
(001001110011.10100010)2
Example 2:
(𝐸𝐵. 25)16 = (? )2
1-20
Each hexadecimal digit is replaced by its four-bit binary equivalent.
E B . 2 5
Therefore, 1110 1011 . 0010 0101 (𝐸𝐵. 25)16 =
(11101011.00100101)2
For converting a binary number into hexadecimal number both the
integer part and the fractional part of the binary number are split into groups of
four bits starting from radix point (in binary number system it may be called as
binary point). If the outermost groups are not complete (i.e. of four bits), then
sufficient number of 0’s are added to make them complete (on left side of
leftmost group and on right side of rightmost group). Then each group is
replaced by its octal equivalent as shown in table 1.3.
Example 1:
(100101101.01011)2 = (? )16
The binary number is split into groups of four bits from binary point.
1 0010 1101 . 0101 1
Here the first group and the
last group are incomplete. For completing them 0’s are added on left side of first
group and on right side of last group.
0001 0010 1101 . 0101 1000
Then hexadecimal
equivalent of each group of bits is written.
0001 0010 1101 . 0101 1000
1 2 D . 5 8
Therefore,
(100101101.01011)2 = (12𝐷. 58)16
Example 2:
(11010.01)2 = (? )16
The binary number is split into groups of four bits from binary point.
1 1010 . 01
Here the first group and the last group
are incomplete. For completing them 0’s are added on left side of first group and
on right side of last group.
0001 1010 . 0100
Then octal equivalent of each group
of bits is written.
0001 1010 . 0100
1 A . 4
Therefore, (11010.01)2 = (1𝐴. 4)16
1.3.5.9 Hexadecimal to Octal and Octal to Hexadecimal conversion

For converting hexadecimal number into its octal equivalent, two
methods exist. In the first method, the hexadecimal number is first converted
into its binary equivalent and then this binary number is converted into octal
number system. In the second method, the hexadecimal number is first
1-21
converted into its decimal equivalent and then this decimal number is converted
into octal number system. The first method is easier than the second.
Example 1:
(1𝐴. 4)16 = (? )8
The hexadecimal number is first converted into its binary equivalent.
1 A . 4
0001 1010 . 0100
(1𝐴. 4)16 = (00011010.0100)2
Then the binary number is converted into its octal equivalent
00 011 010 . 010 0
000 011 010 . 010 000
0 3 2 . 2 0
Therefore,(1𝐴. 4)16 = (032.20)8 = (32.2)8

Example 2:
(12𝐷. 58)16 = (? )8
The hexadecimal number is first converted into its binary equivalent.
1 2 D . 5 8
0001 0010 1101 . 0101 1000
(12𝐷. 58)16 = (000100101101.01011000)2
Then the binary number is converted into its octal equivalent
000 100 101 101 . 010 110 00
000 100 101 101 . 010 110 000
0 4 5 5 . 2 6 0
Therefore, (12𝐷. 58)16 = (0455.260)8 = (455.26)8
For converting octal number into its hexadecimal equivalent, two

methods exist. In the first method, the octal number is first converted into its
binary equivalent and then this binary number is converted into hexadecimal
number system. In the second method, the octal number is first converted into
its decimal equivalent and then this decimal number is converted into
hexadecimal number system. The first method is easier than the second.
Example 1:
(56.03)8 = (? )16
The octal number is first converted into its binary equivalent.
5 6 . 0 3
101 110 . 000 011
(56.03)8 = (101110.000011)2
Then the binary number is converted into its hexadecimal equivalent
1-22
10 1110 . 0000 11
0010 1110 . 0000 1100
2 E . 0 C
Therefore,(56.03)8 = (2𝐸. 0𝐶)16

Example 2:
(237.41)8 = (? )16
The octal number is first converted into its binary equivalent.
2 3 7 . 4 1
010 011 111 . 100 001
(237.41)8 = (010011111.100001)2
Then the binary number is converted into its hexadecimal equivalent
0 1001 1111 . 1000 01
0000 1001 1111 . 1000 0100
0 9 F . 8 4
Therefore,(237.41)8 = (09𝐹. 84)16 = (9𝐹. 84)16
1.3.6 Number Representation in Binary

Positive and negative decimal numbers can be represented in binary by
using one of the formats discussed below. Generally, while using these
representations, number of bits used for representing the number
should be multiple of 8.
1.3.6.1 Sign-Bit Magnitude Representation

In this representation, MSB (Most Significant Bit) is used for
representing sign. ‘0’ is used for representing positive sign whereas ‘1’ is used for
representing negative sign. Remaining bits are used for representing magnitude
of the number.
In eight-bit representation, MSB is used as sign bit and remaining seven
bits are used for representing magnitude.
Example 1:
(−53)10 = (10110101)𝑠𝑖𝑔𝑛−𝑏𝑖𝑡𝑚𝑎𝑔𝑛𝑖𝑡𝑢𝑑𝑒
Example 2:
(+53)10 = (00110101)𝑠𝑖𝑔𝑛−𝑏𝑖𝑡𝑚𝑎𝑔𝑛𝑖𝑡𝑢𝑑𝑒
Example 3:
(+33)10 = (00010001)𝑠𝑖𝑔𝑛−𝑏𝑖𝑡𝑚𝑎𝑔𝑛𝑖𝑡𝑢𝑑𝑒
Using sign-bit magnitude binary representation, when eight bits are
used; numbers in the range –127 to +127 can be represented. In an n-bit
representation, range of numbers those can be represented using sign-bit
magnitude format are −(2𝑛−1 − 1) to +(2𝑛−1 − 1).
This is the simplest method of representing signed numbers.
1.3.6.2 One’s (1’s) Complement Representation
1-23
In this representation, positive decimal numbers are represented same as
that of sign-bit magnitude method. But negative numbers are represented in a
different way.
For representing negative numbers, following steps are performed.
1. Represent the number with positive sign.
2. Find its 1’s complement. (By replacing each ‘0’ with ‘1’ and vice a
versa. i.e. by inverting all the bits we get 1’s complement).
Output of step 2 is 1’s complement representation of the negative number.
Example 1:
(+53)10 = (00110101)1′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 2:
(+33)10 = (00010001)1′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 3:
(−53)10 = (? )1′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
In step 1, +53 is represented as,

(+53)10 = (00110101)
Then, its 1’s complement is found as
00110101
11001010
Therefore,
(−53)10 = (11001010)1′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 4:
(−33)10 = (? )1′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡

(+33)10 = (00010001)
Then, its 1’s complement is found as
00010001
11101110
Therefore,
(−33)10 = (11101110)1′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Using 1’s complement binary representation, when eight bits are used;
numbers in the range –127 to +127 can be represented. In an n-bit
representation, range of numbers those can be represented using 1’s
complement representation are −(2𝑛−1 − 1) to +(2𝑛−1 − 1).
1.3.6.3 Two’s (2’s) Complement Representation

In this representation, a positive number is represented same as that of
sign-bit magnitude method. A negative number is represented by computing 2’s
complement of binary equivalent of its magnitude. (2’s complement of a binary
number is computed by adding 1 in its 1’s complement).
For representing negative numbers, following steps are performed.
1. Represent the number with positive sign.
2. Find its 2’s complement. (By adding 1 in its 1’s complement).
Output of step 2 is 2’s complement representation of the negative number.
1-24
Example 1:
(+53)10 = (00110101)2′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 2:
(+33)10 = (00010001)2′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 3:
(−53)10 = (? )2′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡

(+53)10 = (00110101)
Then, for finding its 2’s complement, first its 1’s complement is found as
00110101
11001010
Then by adding 1 in the result we get 2’s complement as,
11001010
+ 1
--------------------
11001011
Therefore,
(−53)10 = (11001011)2′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 4:
(−33)10 = (? )2′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡

(+33)10 = (00010001)
Then, for finding its 2’s complement, first its 1’s complement is found as
00010001
11101110
11101110
+ 1
--------------------
11101111
Therefore,
(−33)10 = (11101111)2′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Using 2’s complement binary representation, when eight bits are used;
numbers in the range –128 to +127 can be represented. In an n-bit
representation, range of numbers those can be represented using 1’s
complement representation are −(2𝑛−1 ) to +(2𝑛−1 − 1).
This is the most popular method of representing signed numbers. It is
become popular due to two reasons.
1. It is easy to generate 2’s complement of a binary number.
2. Arithmetic operations in 2’s complement method are easy.
Beyond Curriculum Point 1: Floating point numbers
1-25
Generally, floating point numbers are expressed in the following form.
𝑁 = 𝑚 × 𝑏𝑒
Here m is called significand or mantissa, e is called exponent and b is
base. Some examples are shown below.
0.000005312 = 5.312 × 10−6
531200 = 5.312 × 10+5
𝐵2𝐵. 2𝐶 = 𝐵. 2𝐵2𝐶 × 16+2
0.0031𝐹 = 3.1𝐹 × 16−3
11001.0110 = 0.110010110 × 2+5 = 0.110010110𝑒 + 0101
0.000110110 = 0.110110 × 2−3 = 0.110110𝑒 − 0011
The most commonly used format for representing floating point numbers
is IEEE-754 standard. This standard defines two basic formats as single
precision and double precision.
In single precision format, 8 bits are used for representing exponent and
24 bits are used for representing. Within 8 bits of exponent one bit is used for
representing sign of exponent and remaining 7 bits are used for representing
magnitude of exponent. So value of exponent can range from –127 to +127. (from
2−127 to 2+127 . i.e. from 10−38 to 10+38 ). From 24 bits reserved for mantissa, one
bit is used as sign bit and remaining 23 bits are used for representing
magnitude of mantissa.
In double precision format, 11 bits are used for representing exponent and
53 bits are used for representing. Within 11 bits of exponent one bit is used for
representing sign of exponent and remaining 10 bits are used for representing
magnitude of exponent. So value of exponent can range from –1024 to +1024.
(from 2−1024 to 2+1024. i.e. from 10−308 to 10+308). From 53 bits reserved for
mantissa, one bit is used as sign bit and remaining 52 bits are used for
representing magnitude of mantissa.
1.3.7 Binary Arithmetic

Up to this point, we have studied various methods of data representation.
Now, it is important to study data manipulation. We can perform two types of
operations on binary data – arithmetic operations and logic operations.
Arithmetic operations include addition, subtraction, multiplication and division.
These operations are discussed here. Various logic operation like AND, OR,
NOT are discussed in chapter 2.
1.3.7.1 Binary Addition

Basic rules for performing binary addition are given below in table 1.4.
Table 1.4: Rules for binary addition
A B A+B
0 0 0
0 1 1
1 0 1
1 1 0 with carry 1
1-26
Some examples of performing binary addition are given below.
Example 1:
(1001110)2 + (11110)2 = (? )2
1 0 0 1 1 1 0
+ 1 1 1 1 0
C 1 1 1 1
1 1 0 1 1 0 0
(1001110)2 + (11110)2 = (1101100)2

Example 2:
(11000111)2 + (11110000)2 = (? )2
1 1 0 0 0 1 1 1
+ 1 1 1 1 0 0 0 0
C 1 1
1 1 0 1 1 0 1 1 1
(11000111)2 + (11110000)2 = (110110111)2
1.3.7.2 Binary Subtraction

Basic rules for performing binary subtraction are given below in table 1.5.
Table 1.5: Rules for binary subtraction
A B A–B
0 0 0
0 1 1 with borrow 1
1 0 1
1 1 0
Some examples of performing binary subtraction are given below.
Example 1:
(1001110)2 − (11110)2 = (? )2
1 0 0 1 1 1 0
– 1 1 1 1 0
B 1 1
0 1 1 1 1 0 0
(1001110)2 + (11110)2 = (111100)2
Example 2:
(11110000)2 − (11000111)2 = (? )2
1 1 1 1 0 0 0 0
– 1 1 0 0 0 1 1 1
B 1 1 1 1
0 0 1 0 1 0 0 1
(11110000)2 − (11000111)2 = (101001)2
1-27
1.3.7.3 Binary Multiplication
Basic rules for performing binary multiplication are given in table 1.6.
Table 1.6: Rules for binary multiplication
A B AXB
0 0 0
0 1 0
1 0 0
1 1 1
Some examples of performing binary multiplication are given below.
Example 1:
(1001110)2 × (110)2 = (? )2
1 0 0 1 1 1 0
X 1 1 0
0 0 0 0 0 0 0
+ 1 0 0 1 1 1 0 X
+ 1 0 0 1 1 1 0 X X
1 1 1
1 1 1 0 1 0 1 0 0
(1001110)2 × (110)2 = (111010100)2

Example 2:
(11110000)2 × (1010)2 = (? )2
1 1 1 1 0 0 0 0
X 1 0 1 0
0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 X
0 0 0 0 0 0 0 0 X X
1 1 1 1 0 0 0 0 X X X
1 1 1 1
1 0 0 1 0 1 1 0 0 0 0 0
(11110000)2 − (1010)2 = (100101100000)2
1.3.7.4 Binary Division

Binary division is performed similar to decimal division. Some examples
of performing binary division are given below.
Example 1:
(11110000)2 ÷ (1010)2 = (? )2
Q 0 0 0 1 1 0 0 0
1 0 1 0 1 1 1 1 0 0 0 0
- 1 0 1 0
0 1 0 1 0
- 1 0 1 0
R 0 0 0 0 0 0 0
1-28
(11110000)2 − (1010)2 = (11000)2
Example 2:
(1001111)2 ÷ (110)2 = (? )2
Q 0 0 0 1 1 0 1
1 1 0 1 0 0 1 1 1 1
- 1 1 0
1 1
0 0 1 1 1
- 1 1 0
0 0 1 1 1
- 1 1 0
R 0 0 1
(1001111)2 ÷ (110)2 = (1101)2 𝑤𝑖𝑡ℎ𝑟𝑒𝑚𝑎𝑖𝑛𝑑𝑒𝑟(001)2
1.3.8 One’s complement Arithmetic

Arithmetic operations discussed in 1.3.7 deals with unsigned binary
numbers only. For signed numbers, the arithmetic operations depend on the
way how they are represented. When signed numbers are represented using
one’s complement representation, we have to perform addition or subtraction by
using the steps discussed below.
As these rules deal with signed numbers, we can represent any
subtraction operation in terms of addition as shown in following examples.
𝐴 − 𝐵 = 𝐴 + (−𝐵)
−𝐴 − 𝐵 = (−𝐴) + (−𝐵)
−𝐴 − (−𝐵) = (−𝐴) + 𝐵
Following are the steps for performing 1’s complement addition
(subtraction also – First subtraction should be represented as addition).
1. Represent both the numbers using 1’s complement representation.
2. Perform simple binary addition.
3. If carry is generated out of MSBs, add it to LSB of the result.
4. If MSB is 0, result is positive. Find equivalent of result.
5. If MSB is 1, result is negative. Find 1’s complement of result and then its
equivalent.
Some examples are shown below.
Example 1:
(83)10 + (39)10 = (? )10
Step 1: 1’s complement representation of numbers
(83)10 = 01010011
(39)10 = 00100111
Step 2: Simple Binary addition

1-29
0 1 0 1 0 0 1 1
+ 0 0 1 0 0 1 1 1
1 1 1
0 1 1 1 1 0 1 0
Step 4: As MSB is 0, result is positive and it is,
01111010 = (122)10
∴ (83)10 + (39)10 = (122)10
Example 2:
(−83)10 + (39)10 = (? )10
(−83)10 =?
(83)10 = 01010011
01010011
10101100
(−83)10 = 10101100
(39)10 = 00100111
1 0 1 0 1 1 0 0
+ 0 0 1 0 0 1 1 1
1 1 1
1 1 0 1 0 0 1 1
Step 5: As MSB is 1, result is negative,
11010011
00101100
∴ 𝑅𝑒𝑠𝑢𝑙𝑡𝑖𝑠(−44)10
∴ (−83)10 + (39)10 = (−44)10
Example 3:
(83)10 − (39)10 = (? )10
The above subtraction can be represented in terms of addition as,
(83)10 + (−39)10 = (? )10
(83)10 = 01010011
(−39)10 =?
(39)10 = 00100111
00100111
11011000
(−39)10 = 11011000
0 1 0 1 0 0 1 1
+ 1 1 0 1 1 0 0 0
1-30
1 1 1
1 0 0 1 0 1 0 1 1
Step 3: Carry generated out of MSB is added to LSB of result.
0 0 1 0 1 0 1 1
+ 1
1 1
0 0 1 0 1 1 0 0
00101100 = (+44)10
∴ (83)10 − (39)10 = (+44)10
Example 4:
(−83)10 − (39)10 = (? )10
(−83)10 + (−39)10 = (? )10
Step 1: 2’s complement representation of numbers(−83)10 =?
(83)10 = 01010011
01010011
10101100
(−83)10 = 10101100
(−39)10 =?
(39)10 = 00100111
00100111
11011000
(−39)10 = 11011000
1 0 1 0 1 1 0 0
+ 1 1 0 1 1 0 0 0
1 1 1 1 1
1 1 0 0 0 0 1 0 0
Step 3: Carry generated out of MSB is added to LSB of the result.
1 0 0 0 0 1 0 0
+ 1
1 0 0 0 0 1 0 1
10000101
01111010
∴ (−83)10 − (39)10 = (−122)10
1-31
1.3.9 Two’s complement Arithmetic
Arithmetic operations discussed in 1.3.7 deals with unsigned binary
numbers only. For signed numbers, the arithmetic operations depend on the
way how they are represented. When signed numbers are represented using
two’s complement representation, we have to perform addition or subtraction by
using the steps discussed below.
As these rules deal with signed numbers, we can represent any
subtraction operation in terms of addition as shown in following examples.
𝐴 − 𝐵 = 𝐴 + (−𝐵)
−𝐴 − 𝐵 = (−𝐴) + (−𝐵)
−𝐴 − (−𝐵) = (−𝐴) + 𝐵
Following are the steps for performing 2’s complement addition
(subtraction also – First subtraction should be represented as addition).
1. Represent both the numbers using 2’s complement representation.
3. If any carry is generated out of MSBs, ignore it.
4. If MSB is 0, result is positive. Find equivalent of result.
5. If MSB is 1, result is negative. Find 2’s complement of result and then its
equivalent.

Example 1:
(83)10 + (39)10 = (? )10
(83)10 = 01010011
(39)10 = 00100111
0 1 0 1 0 0 1 1
+ 0 0 1 0 0 1 1 1
1 1 1
0 1 1 1 1 0 1 0
01111010 = (122)10
∴ (83)10 + (39)10 = (122)10
Example 2:
(−83)10 + (39)10 = (? )10
(−83)10 =?
(83)10 = 01010011
01010011
10101100
10101100
1-32
+ 1
--------------------
10101101
(−83)10 = 10101101
(39)10 = 00100111
1 0 1 0 1 1 0 1
+ 0 0 1 0 0 1 1 1
1 1 1 1 1
1 1 0 1 0 1 0 0
11010100
00101011
00101011
+ 1
--------------------
00101100
∴ (−83)10 + (39)10 = (−44)10
Example 3:
(83)10 − (39)10 = (? )10
(83)10 + (−39)10 = (? )10
(83)10 = 01010011
(−39)10 =?
(39)10 = 00100111
00100111
11011000
11011000
+ 1
--------------------
11011001
(−39)10 = 11011001
0 1 0 1 0 0 1 1
1-33
+ 1 1 0 1 1 0 0 1
1 1 1 1 1
1 0 0 1 0 1 1 0 0
Step 3: Carry generated out of MSB is ignored.
00101100 = (+44)10
∴ (83)10 − (39)10 = (+44)10
Example 4:
(−83)10 − (39)10 = (? )10
(−83)10 + (−39)10 = (? )10
Step 1: 2’s complement representation of numbers(−83)10 =?
(83)10 = 01010011
01010011
10101100
10101100
+ 1
--------------------
10101101
(−83)10 = 10101101
(−39)10 =?
(39)10 = 00100111
00100111
11011000
11011000
+ 1
--------------------
11011001
(−39)10 = 11011001
1 0 1 0 1 1 0 1
+ 1 1 0 1 1 0 0 1
1 1 1 1 1 1
1 1 0 0 0 0 1 1 0
Step 3: Carry generated out of MSB is ignored.
10000110
01111001
1-34
01111001
+ 1
--------------------
01111010
∴ (−83)10 − (39)10 = (−122)10
1.3.10 Binary Coded Decimal (BCD) Code

Each decimal digit is represented by a four-bit code. The BCD codes of all
the decimal digits 0 through 9 are shown below.
Table 1.7: BCD Codes
Decimal Digit BCD Code
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Some examples of BCD code representation are shown below. Also their
binary equivalents are shown.
Example Decimal Number BCD Code Binary equivalent
1 14 00010100 1110
2 83 10000011 01010011
3 122 000100100010 01111010
4 39 00111001 00100111
5 293.52 001010010011.01010010 100100101.10000101
6 13.25 00010011.00100101 1101.01
From above examples, it can be easily observed that more number of bits
is required for representing a number using BCD code as compared to simple
binary equivalent. This is disadvantage of BCD code. BCD arithmetic is also
somewhat critical. But even then, BCD code is convenient and useful code for
input and output operations.
Decimal to BCD conversion and BCD to Decimal conversion are very easy
as only the table 1.7 is used for doing the conversion.
BCD is also known as 8-4-2-1 code as the bits in the code have weights as
8, 4, 2 and 1.
Beyond Curriculum Point 2: Additional BCD Codes
1-35
The basic BCD code is 8421 BCD code. There are some more weighted
BCD codes as 4221 BCD code and 5421 BCD code. Obviously, 4, 2, 2, 1 in 4221
BCD code and 5, 4, 2, 1 in 5421 BCD code are weights of respective bits. Table
1.8 shows how decimal digits from 0 through 9 are represented using these BCD
codes.
Table 1.8: Other BCD Codes
Decimal Digit 4221 BCD 5421 BCD
Code Code
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 0
3 0 0 1 1 0 0 1 1
4 1 0 0 0 0 1 0 0
5 0 1 1 1 1 0 0 0
6 1 1 0 0 1 0 0 1
7 1 1 0 1 1 0 1 0
8 1 1 1 0 1 0 1 1
9 1 1 1 1 1 1 0 0
Beyond Curriculum Point 3: Excess–3 Code

Excess-3 code is one more important BCD code. It is very much useful in
performing BCD arithmetic. Table 1.9 shows how decimal digits from 0 through
9 are represented using Excess–3 codes.
Table 1.8: Excess–3 Code
Decimal Digit Excess-3 Code
0 0 0 1 1
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
6 1 0 0 1
7 1 0 1 0
8 1 0 1 1
9 1 1 0 0
1.3.11 BCD Arithmetic

Method of performing BCD arithmetic is different from binary arithmetic.
There are different rules for doing so.
1.3.11.1 BCD Addition

There are various methods for performing BCD addition. One of them is
discussed below.
Rules for performing BCD addition are,
1. Represent both the decimal numbers in their BCD codes.
1-36
3. If any digit (4 bits) in the result contains invalid BCD code or a carry
is generated out of a digit (4 bits), add 0110 to each such digit (4 bits).

Example 1:
(83)10 + (39)10 = (? )10
Step 1: BCD code representation of numbers
(83)10 = 10000011
(39)10 = 00111001
1 0 0 0 0 0 1 1
+ 0 0 1 1 1 0 0 1
1 1
1 0 1 1 1 1 0 0
Step 3: As both digits of result contain invalid BCD codes,
1 0 1 1 1 1 0 0
+ 0 1 1 0 0 1 1 0
1 1 1 1 1 1
1 0 0 1 0 0 0 1 0
(000100100010)𝐵𝐶𝐷 = (122)10
∴ (83)10 + (39)10 = (122)10
Example 2:
(29)10 + (58)10 = (? )10
(29)10 = 00101001
(58)10 = 01011000
0 0 1 0 1 0 0 1
+ 0 1 0 1 1 0 0 0
1 1 1 1
1 0 0 0 0 0 0 1
Step 3: As carry is generated from least significant digit to next
digit 0110 is added to lest significant digit,
1 0 0 0 0 0 0 1
+ 0 1 1 0
1 0 0 0 0 1 1 1
(10000111)𝐵𝐶𝐷 = (87)10
∴ (29)10 + (58)10 = (87)10
Example 3:
1-37
(637)10 + (463)10 = (? )10
(637)10 = 011000110111
(463)10 = 010001100011
0 1 1 0 0 0 1 1 0 1 1 1
+ 0 1 0 0 0 1 1 0 0 0 1 1
1 1 1 1 1 1
1 0 1 0 1 0 0 1 1 0 1 0
Step 3: As least significant digit and most significant digit are
invalid, 0110 is added to both these digits.
1 0 1 0 1 0 0 1 1 0 1 0
+ 0 1 1 0 0 1 1 0
1 1 1 1 1 1 1
1 0 0 0 0 1 0 1 0 0 0 0 0
As result contains invalid digit, 0110 is added to that digit.
1 0 0 0 0 1 0 1 0 0 0 0 0
+ 0 1 1 0
1 1 1
1 0 0 0 1 0 0 0 0 0 0 0 0
(0001000100000000)𝐵𝐶𝐷 = (1100)10
∴ (637)10 + (463)10 = (1100)10
Example 4:
1001 + 1101 =?
Step 1: The above numbers are represented in binary
representation. First number is binary equivalent of (9)10 and second number is
binary equivalent of (13)10 . BCD code representation of these numbers is,
(9)10 = 1001
(13)10 = 00010011
1 0 0 1
+ 0 0 0 1 0 0 1 1
1 1
0 0 0 1 1 1 0 0
Step 3: As least significant digit is invalid, 0110 is added to that
digit.
0 0 0 1 1 1 0 0
+ 0 1 1 0
1 1 1
0 0 1 0 0 0 1 0
1-38
(00100010)𝐵𝐶𝐷 = (22)10
∴ (1001)2 + (1101)2 = (22)10 = (10110)2
1.3.11.2 BCD Subtraction

There are various methods for performing BCD subtraction. One of them
is discussed below.
Rules for performing BCD subtraction are (By considering subtraction as
A – B ),
1. Represent A in BCD code.
2. Represent 9’s complement of B in BCD code.
3. Perform BCD addition.
4. If carry is generated out of MSB, result is positive. To get correct result,
carry is added to result.
5. If carry is not generated, result is negative and it is in 9’s complement
form.

Example 1:
(45)10 − (27)10 = (? )10
Step 1: BCD code representation of A
(45)10 = 01000101
Step 2: 9’s complement of B is,
(27)10 = (72)9′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
BCD code is
72 = 01110010
Step 3: BCD addition
0 1 0 0 0 1 0 1
+ 0 1 1 1 0 0 1 0
1 0 1 1 0 1 1 1
As most significant digit of result contain invalid BCD code,
1 0 1 1 0 1 1 1
+ 0 1 1 0
1 1
1 0 0 0 1 0 1 1 1
Step 4: As carry is generated out of MSB, it is added to result.
(Result is positive)
0 0 0 1 0 1 1 1
+ 1
1 1 1
0 0 0 1 1 0 0 0
(00011000)𝐵𝐶𝐷 = (+18)10
1-39
∴ (45)10 − (27)10 = (+18)10
Example 2:
(45)10 − (83)10 = (? )10
Step 1: BCD code representation of A
(45)10 = 01000101
Step 2: 9’s complement of B is,
(83)10 = (16)9′ 𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
BCD code is
16 = 00010110
Step 3: BCD addition
0 1 0 0 0 1 0 1
+ 0 0 0 1 0 1 1 0
1
0 1 0 1 1 0 1 1
As least significant digit of result contain invalid BCD code,
0 1 0 1 1 0 1 1
+ 0 1 1 0
1 1 1 1
0 1 1 0 0 0 0 1
Step 5: As carry is not generated out of MSB, result is negative and
it is in 9’s complement form
(01100001)𝐵𝐶𝐷 = (61)10
But as result is in 9’s complement form, true result is
∴ (45)10 − (83)10 = (−38)10
1-40
Chapter 2
Logic Gates
08 Hours
18 Marks
2.1 Logic Gates
Logic gates are electronic circuits. For implementing various logic

expressions (a.k.a. Boolean expressions), logic gates can be used. The logic gate
is the most basic building block of combinational logic. Logic gate performs a
logical operation on one or more logical inputs and produce a single logical
output. Before studying logic gates one should know the things discussed here.
Truth table for a logic system lists all possible combinations of input
variables and corresponding output generated by the logic system. Output of a
logic system can be found from the logic expression (i.e. Boolean expression) of
that logic system.
When the number of input binary variables is only one, then there are
only two possible inputs, i.e. ‘0’ and ‘1’. If the number of inputs is two, there can
be four possible input combinations, i.e. 00, 01, 10 and 11. Similarly, for three
input binary variables, the number of possible input combinations becomes
eight, i.e. 000, 001, 010, 011, 100, 101, 110 and 111.
In general, if a logic circuit has n binary inputs, its truth table will have
2 possible input combinations (i.e. truth table contains 2n rows).
n
Figure 2.1 shows a sample 2–input logic system and table 2.2 shows a
sample truth table for a 2–input logic system.
A Logic
System Y
B
Figure 2.1: A sample 2–input logic system
Table 2.1: A sample Truth Table

Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
1-1
2.1.1 Basic Gates
Logic gate is the most basic building block of any digital system (even for
computers). Each basic logic gate is a piece of hardware or an electronic circuit
that can be used to implement some basic logic expression. For implementing
various laws of Boolean algebra, basic gates can be used. Basic gates perform
basic logical operations on the logical inputs.
There are three basic logic gates, namely the OR gate, the AND gate and
the NOT gate.
2.1.1.1 OR gate
The OR gate performs logical OR operation on two or more inputs
(generally referred as logic variables). The OR gate has two or more inputs and
a single output. Output of an OR gate is LOW if all the inputs are LOW. In all
other cases, output of OR gate is HIGH.
The OR operation on two independent logical variables A and B can be
represented by following logic expression (sometimes also called logical
equation).
𝑌 =𝐴+𝐵
It is read as Y is equal to A OR B. The logic expression shown above is
logic expression for 2–input OR gate. Logical symbol for 2 – input OR gate is
A
Y=A+B
B
Figure 2.2: Logical symbol for 2 – input OR gate

Truth table for 2 – input OR gate is shown in table 2.2.
Table 2.2: Truth table for 2 – input OR gate
i/p o/p
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Figure 2.3: IC pin configuration for IC 7432

1-2
The TTL IC used for 2 – input OR gate is 7432. It is a quad 2 – input OR
gate. i.e. There are four 2 – input OR gates in the IC. Pin configuration of IC
7432 is shown in figure 2.3.
The logic expression or logical equation for 3 – input OR gate is shown

below.
𝑌 =𝐴+𝐵+𝐶
Logical symbol for 3 – input OR gate is shown in figure 2.4.
A
B Y=A+B+C
C
Figure 2.4: Logical symbol for 3 – input OR gate

Truth table for 3 – input OR gate is shown in table 2.3.
Table 2.3: Truth table for 3 – input OR gate
i/p o/p
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
The TTL IC used for 3 – input OR gate is 744075. It is a triple 3 – input
OR gate. i.e. There are three 3 – input OR gates in the IC.
2.1.1.2 AND gate

The AND gate performs logical AND operation on two or more inputs
(generally referred as logic variables). The AND gate has two or more inputs
and a single output. Output of an AND gate is HIGH if all the inputs are HIGH.
In all other cases, output of AND gate is LOW.
The AND operation on two independent logical variables A and B can be
equation).
𝑌 = 𝐴. 𝐵
It is read as Y is equal to A AND B. The logic expression shown above is
logic expression for 2–input AND gate. Logical symbol for 2 – input AND gate is
1-3
A
Y=A.B
B
Figure 2.5: Logical symbol for 2 – input AND gate

Truth table for 2 – input AND gate is shown in table 2.4.
Table 2.4: Truth table for 2 – input AND gate
i/p o/p
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
The TTL IC used for 2 – input AND gate is 7408. It is a quad 2 – input
AND gate. i.e. There are four 2 – input AND gates in the IC. Pin configuration of
IC 7408 is shown in figure 2.6.
Figure 2.6: IC pin configuration for 7408
The logic expression or logical equation for 3 – input AND gate is shown
below.
𝑌 = 𝐴. 𝐵. 𝐶
Logical symbol for 3 – input AND gate is shown in figure 2.7.
A
B Y=A.B.C
C
Figure 2.7: Logical symbol for 3 – input AND gate

Truth table for 3 – input AND gate is shown in table 2.5.
1-4
Table 2.5: Truth table for 3 – input AND gate
i/p o/p
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
The TTL IC used for 3 – input AND gate is 7411. It is a triple 3 – input
AND gate. i.e. There are three 3 – input AND gates in the IC.
2.1.1.3 NOT gate

The NOT gate performs logical NOT (i.e. negation) operation on an input
(generally referred as logic variable). The NOT gate has a single input and a
single output. Output of an AND gate is complement of its input. If input is
LOW, output is HIGH and if input is HIGH, output is LOW.
The NOT operation on a logical variable X can be represented by
following logic expression (sometimes also called logical equation).
𝑌 = 𝑋̅
or
𝑌 = 𝑋′
It is read as Y is equal to NOT X. Logical symbol for NOT gate is shown in
figure 2.8.
X 𝑌 = 𝑋̅
Figure 2.8: Logical symbol for NOT gate

Truth table for NOT gate is shown in table 2.6.
Table 2.6: Truth table NOT gate
i/p o/p
X Y
0 1
1 0
The TTL IC used for NOT gate is 7404. It is a hex inverter. i.e. There
are six NOT gates in the IC. Pin configuration of IC 7404 is shown in figure 2.9.
1-5
Figure 2.9: IC pin configuration of 7404
2.1.2 Universal Gates

In addition to basic gates, other logic gates like NAND and NOR gates are
also used in designing digital circuits. The NAND gate and NOR gate are called
universal gates because using any one type of those gates any logic expression
can be realized. Implementation of any logic expression is economical if it is
done using any one type of universal gates (as compared to implementation
using basic gates). The basic reason behind this is the easier fabrication of these
gates.
2.1.2.1 NAND gate

NAND stands for NOT AND. The name suggests that it is a combination
of AND gate followed by a NOT gate as shown in figure 2.10.
A
Y
B
Figure 2.10: NAND gate as a combination of AND and NOT gates

The NAND gate has two or more inputs and a single output. Output of an
NAND gate is LOW if all the inputs are HIGH. In all other cases, output of
NAND gate is HIGH.
The NAND operation on two independent logical variables A and B can be
equation).
𝑌 = ̅̅̅̅̅
𝐴. 𝐵
The logic expression shown above is logic expression for 2–input NAND
gate. Logical symbol for 2 – input NAND gate is shown in figure 2.11.
A
̅̅̅̅̅
𝑌 = 𝐴. 𝐵
B
Figure 2.11: Logical symbol for 2 – input NAND gate
1-6
Truth table for 2 – input NAND gate is shown in table 2.7. It can be
obtained by negating the output of AND gate.
Table 2.7: Truth table for 2 – input NAND gate
i/p o/p
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
The TTL IC used for 2 – input NAND gate is 7400. It is a quad 2 – input
NAND gate. i.e. There are four 2 – input NAND gates in the IC. Pin
configuration of IC 7400 is shown in figure 2.12.
Figure 2.12: IC pin configuration of 7400

The logic expression or logical equation for 3 – input NAND gate is shown
below.
𝑌 = ̅̅̅̅̅̅̅̅̅̅̅
(𝐴. 𝐵. 𝐶)
Logical symbol for 3 – input NAND gate is shown in figure 2.13.
A
B 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅
(𝐴. 𝐵. 𝐶)
C
Figure 2.13: Logical symbol for 3 – input NAND gate

Table 2.8: Truth table for 3 – input NAND gate
i/p o/p
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
1-7
Truth table for 3 – input NAND gate is shown in table 2.8. The TTL IC
used for 3 – input NAND gate is 7410. It is a triple 3 – input NAND gate. i.e.
There are three 3 – input NAND gates in the IC.
2.1.2.2 NOR gate

NOR stands for NOT OR. The name suggests that it is a combination of
OR gate followed by a NOT gate as shown in figure 2.14.
A
Y
B
Figure 2.14: NOR gate as a combination of OR and NOT gates

The NOR gate has two or more inputs and a single output. Output of an
NOR gate is HIGH if all the inputs are LOW. In all other cases, output of NOR
gate is LOW.
The NOR operation on two independent logical variables A and B can be
equation).
𝑌 = ̅̅̅̅̅̅̅̅
𝐴+𝐵
The logic expression shown above is logic expression for 2–input NOR
gate. Logical symbol for 2 – input NOR gate is shown in figure 2.15.
A
𝑌 = ̅̅̅̅̅̅̅̅
𝐴+𝐵
B
Figure 2.15: Logical symbol for 2 – input NOR gate

Truth table for 2 – input NOR gate is shown in table 2.9. It can be
obtained by negating the output of OR gate.
Table 2.9: Truth table for 2 – input NOR gate
i/p o/p
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
The TTL IC used for 2 – input NOR gate is 7402. It is a quad 2 – input NOR
gate. i.e. There are four 2 – input NOR gates in the IC. Pin configuration for IC
7402 is shown in figure 2.16.
1-8
The logic expression or logical equation for 3 – input NOR gate is shown
below.
𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵 + 𝐶)
Logical symbol for 3 – input NOR gate is shown in figure 2.17.
A
B 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵 + 𝐶)
C
Figure 2.17: Logical symbol for 3 – input NOR gate

Truth table for 3 – input NOR gate is shown in table 2.10.
Table 2.10: Truth table for 3 – input NOR gate
i/p o/p
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
The TTL IC used for 3 – input NOR gate is 7427. It is a triple 3 – input
NOR gate. i.e. There are three 3 – input NOR gates in the IC.
2.1.3 Derived Gates

The gates those are derived from basic gates are called as derived gates.
Sometimes NAND gate and NOR gate are also referred as derived gates (as they
are derived from basic gates). Two more derived gates are Ex-OR gate and Ex-
NOR gate.
2.1.3.1 Ex-OR gate (XOR gate)

The Ex-OR stands for Exclusive OR. It is used for performing OR
operation exclusively. Ex-OR gate has two inputs and a single output. (We may
design multiple input Ex-OR gates. But they are not readily available). Output
1-9
of Ex-OR gate is HIGH if odd number of inputs is HIGH. If even number of
inputs is HIGH, output is LOW.
The logic expression (sometimes also called logical equation) of 2 – input
Ex-OR gate is shown below.
𝑌 = 𝐴 ⊕ 𝐵 = 𝐴̅𝐵 + 𝐴𝐵̅
It is read as Y is equal to A Ex-OR B. Logical symbol for 2 – input Ex-OR
gate is shown in figure 2.18.
A
𝑌 =𝐴⊕𝐵
B
Figure 2.18: Logical symbol for 2 – input Ex-OR gate

Table 2.11: Truth table for 2 – input Ex-OR gate
i/p o/p
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Truth table for 2 – input Ex-OR gate is shown in table 2.11. The TTL IC
used for 2 – input Ex-OR gate is 7486. It is a quad 2 – input XOR gate. i.e. There
are four 2 – input XOR gates in the IC. Pin configuration for IC 7486 is shown in
figure 2.19.
We may design multiple-input Ex-OR gates. In multiple input Ex-OR

gates output is HIGH if odd number of inputs have HIGH value. In all other
cases, output is LOW.
2.1.3.2 Ex-NOR gate

The Ex-NOR stands for Exclusive NOR. It means NOT of Ex-OR. Ex-
NOR gate has two inputs and a single output. (We may design multiple input
Ex-NOR gates. But they are not readily available). Output of Ex-NOR gate is
HIGH if even number of inputs is HIGH. If odd number of inputs is LOW,
output is LOW.
The logic expression (sometimes also called logical equation) of 2 – input
Ex-NOR gate is shown below.
1-10
𝑌 = ̅̅̅̅̅̅̅̅̅̅̅
(𝐴 ⊕ 𝐵) = 𝐴𝐵 + 𝐴̅𝐵̅
It is read as Y is equal to A Ex-NOR B. Logical symbol for 2 – input Ex-
NOR gate is shown in figure 2.20.
A
𝑌 =𝐴⊕𝐵
B
Figure 2.20: Logical symbol for 2 – input Ex-NOR gate

Truth table for 2 – input Ex-NOR gate is shown in table 2.12.
Table 2.12: Truth table for 2 – input Ex-NOR gate
i/p o/p
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
The TTL IC used for 2 – input Ex-NOR gate is 747266. It is a quad 2 –
input XNOR gate. i.e. There are four 2 – input XNOR gates in the IC. Pin
configuration for IC 747266 is shown in figure 2.21.
2.1.4 Deriving gates from universal gates

The NAND gate and NOR gate are called universal gates because using
any one type of those gates any logic expression can be realized. We can also
derive all the gates using any one type of universal gates.
2.1.4.1 Deriving NOT gate
A 𝑌 = 𝐴̅
Figure 2.22: NOT gate using NAND gate
1-11
A 𝑌 = 𝐴̅
Figure 2.23: NOT gate using NOR gate
2.1.4.2 Deriving AND gate
A
𝑌 = 𝐴. 𝐵
B
Figure 2.24: AND gate using NAND gates only
𝑌 = 𝐴. 𝐵
Figure 2.25: AND gate using NOR gates only

2.1.4.3 Deriving OR gate
𝑌 =𝐴+𝐵
Figure 2.26: OR gate using NAND gates only
1-12
A
𝑌 =𝐴+𝐵
B
Figure 2.27: OR gate using NOR gates only
2.1.4.4 Deriving NOR gate using NAND gates
𝑌 = ̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵)
Figure 2.28: NOR gate using NAND gates only
2.1.4.5 Deriving NAND gate using NOR gates
𝑌 = ̅̅̅̅̅̅̅̅
(𝐴. 𝐵)
Figure 2.29: NAND gate using NOR gates only
2.1.5 Construction of logic circuits using universal gates

Using any one type of universal gates any logic expression can be
realized.
Example 1: Construct a logic circuit using NAND gates only for following
expression
𝑋 = 𝐴. (𝐵 + 𝐶)
1-13
A
𝑋 = 𝐴. (𝐵 + 𝐶)
Example 2: Construct a logic circuit using NOR gates only for following
expression
𝑋 = 𝐴. (𝐵 + 𝐶)
𝑋 = 𝐴. (𝐵 + 𝐶)
Figure 2.27: OR gate using NOR gates only
Questions:
1. Draw symbol, logical equation and truth table of 3 i/p AND gate and 3
i/p OR gate. [4M]
2. Draw pin configuration of TTL ICs used for AND gate and NAND gate.
[4M]
1-14
3. Draw logical symbol, truth table and logical expression of EX-OR gate.
[2M]
4. Draw symbol and truth table for EX-NOR gate. [2M]
5. Draw logical symbol, truth table and logical expression for NAND and
NOR gate. [4M]
6. Draw logical symbol, expression, truth table and IC pin configuration for 2
input NOR gate. [4M]
7. Draw the pin configuration with the internal schematic of IC 7400. [2M]
8. Draw symbol, logical equation, truth table and TTL IC used for 2 i/p EX-
OR and NOR gate. [4M]
9. Draw logic symbol and truth table of NOR gate. [2M]
10. Draw AND gate using NAND gates only and NOR gates only. [2M]
11. Implement AND, OR, NOT and NOR gate using NAND gates only. [4M]
12. Draw logical symbol, truth table and logical expression of NAND gate and
AND gate. [4M]
13. What is universal gate? Construct a logic circuit using NAND gates only
for following expression. [4M]
𝑋 = 𝐴 ∙ (𝐵 + 𝐶)
14. What are universal gates? Draw logical circuits of basic gates using
universal gates. [4M]
15. Define universal gate and design basic gates using NAND as universal
gate. [4M]
16. What is universal gate? Construct any two basic gates using NOR gate.
[4M]
17. Implement OR and AND gates by using NAND gates only. [4M]
2.2 Boolean laws
Boolean algebra is mathematics of logic. It is one of the most basic tool for
simplifying Boolean laws. Logic variables are denoted by capital letters (e.g. A,
B, C, …). If value of 𝐴 = 0, then 𝐴̅ = 1 and if value of 𝐴 = 1, then 𝐴̅ = 0. Two
Boolean expressions are said to be equal if and only if the truth tables of them
are identical.
Fundamental laws of Boolean algebra are shown below.

𝐴+0=𝐴 𝐴. 0 = 0
𝐴+1=1 𝐴. 1 = 𝐴
𝐴+𝐴=𝐴 𝐴. 𝐴 = 𝐴
𝐴 + 𝐴̅ = 1 𝐴. 𝐴̅ = 0
𝐴̿ = 𝐴
Commutative laws are shown below.

𝐴+𝐵 =𝐵+𝐴
𝐴. 𝐵 = 𝐵. 𝐴
Associative laws are shown below.

(𝐴 + 𝐵) + 𝐶 = 𝐴 + (𝐵 + 𝐶)
1-15
(𝐴. 𝐵). 𝐶 = 𝐴. (𝐵. 𝐶)
Distributive laws are shown below.

𝐴. (𝐵 + 𝐶) = 𝐴. 𝐵 + 𝐴. 𝐶
𝐴 + 𝐵. 𝐶 = (𝐴 + 𝐵). (𝐴 + 𝐶)
Some more important laws are shown below.

𝐴. 𝐵 + 𝐴. 𝐵̅ = 𝐴
(𝐴 + 𝐵). (𝐴 + 𝐵̅ ) = 𝐴
(𝐴 + 𝐵̅ ). 𝐵 = 𝐴. 𝐵
𝐴. 𝐵̅ + 𝐵 = 𝐴 + 𝐵
𝐴 + 𝐴. 𝐵 = 𝐴
𝐴. (𝐴 + 𝐵) = 𝐴
De-Morgan’s theorems are shown below.

̅̅̅̅̅̅̅̅̅̅̅
𝐴. 𝐵 … 𝑁 = 𝐴̅ + 𝐵̅ + ⋯ + 𝑁̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵 + ⋯ + 𝑁 = 𝐴̅. 𝐵̅ … 𝑁
̅
De-Morgan’s first theorem states that complement of product of

variables is equal to the sum of complements of the variables.
De-Morgan’s second theorem states that complement of sum of
variables is equal to the product of complements of the variables.
Duality property states that all Boolean expressions remain valid when
following steps are performed.
Step 1: Interchange OR operator (+) and AND operator (.)
Step 2: Replace all 1’s by 0’s and all 0’s by 1’s.
e.g. As 𝐴 + 0 = 𝐴, its dual is 𝐴. 1 = 𝐴
As (𝐴 + 𝐵̅ ). 𝐵 = 𝐴. 𝐵, its dual is 𝐴. 𝐵̅ + 𝐵 = 𝐴 + 𝐵
̅̅̅̅̅̅̅̅̅̅̅
As 𝐴. 𝐵 … 𝑁 = 𝐴̅ + 𝐵̅ + ⋯ + 𝑁 ̅, its dual is 𝐴̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
+ 𝐵 + ⋯ + 𝑁 = 𝐴̅. 𝐵̅ … 𝑁
̅
2.2.1 Proofs of Boolean laws
Any Boolean law or theorem or expression can be proved in two ways
- Using truth table
- Matching L.H.S. with R.H.S. by simplification
2.2.1.1 Proofs of Boolean laws using truth table

When proof is done with the help of truth tables, by comparing L.H.S. and
R.H.S. in the truth table, law/ theorem/ expression can be proven.
Example 1:
Prove that 𝐴. (𝐵 + 𝐶) = 𝐴. 𝐵 + 𝐴. 𝐶
Proof:
1 2 3 4 5 6 7 8
A B C (B+C) A.(B+C) A.B A.C A.B+A.C
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
1-16
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
By comparing column number 5 and column number 8, it is proven that

𝐴. (𝐵 + 𝐶) = 𝐴. 𝐵 + 𝐴. 𝐶
Example 2:
Prove that 𝐴 + 𝐵. 𝐶 = (𝐴 + 𝐵). (𝐴 + 𝐶)
Proof:
1 2 3 4 5 6 7 8
A B C B.C A+B.C A+B A+C (A+B).(A+C)
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1

𝐴 + 𝐵. 𝐶 = (𝐴 + 𝐵). (𝐴 + 𝐶)
Example 3:
Prove De-Morgan’s first theorem.
De-Morgan’s first theorem states that complement of product of
variables is equal to the sum of complements of the variables.
i.e. ̅̅̅̅̅̅̅̅̅̅̅
𝐴. 𝐵 … 𝑁 = 𝐴̅ + 𝐵̅ + ⋯ + 𝑁
̅
Proof:
Let’s try to prove the De-Morgan’s first theorem for three variables
as,
̅̅̅̅̅̅̅̅
𝐴. 𝐵. 𝐶 = 𝐴̅ + 𝐵̅ + 𝐶̅
1 2 3 4 5 6 7 8 9
𝐴 𝐵 𝐶 𝐴. 𝐵. 𝐶 ̅̅̅̅̅̅̅̅
𝐴. 𝐵. 𝐶 𝐴̅ 𝐵̅ 𝐶̅ 𝐴 + 𝐵̅ + 𝐶̅
̅
0 0 0 0 1 1 1 1 1
0 0 1 0 1 1 1 0 1
0 1 0 0 1 1 0 1 1
0 1 1 0 1 1 0 0 1
1 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 1
1 1 0 0 1 0 0 1 1
1-17
1 1 1 1 0 0 0 0 0

̅̅̅̅̅̅̅̅
𝐴. 𝐵. 𝐶 = 𝐴̅ + 𝐵̅ + 𝐶̅
2.2.1.2 Proofs of Boolean laws using simplification method

When proof is done with the help of simplification, L.H.S. and R.H.S. are
simplified using basic Boolean laws. Then by matching L.H.S. and R.H.S, law/
theorem/ expression can be proven.
Example 1:
Prove that
𝑌̅𝑍̅ + 𝑊
̅ 𝑋̅𝑍̅ + 𝑊
̅ 𝑋𝑌 ̅𝑍 + 𝑊𝑌𝑍̅ = 𝑍̅
Proof:
By using law
L.H.S. = 𝑍̅ . (𝑌̅ + 𝑊
̅ 𝑋̅ + 𝑊̅ 𝑋𝑌 + 𝑊𝑌)
= 𝑍̅ . (𝑌̅ + 𝑊𝑌 + 𝑊 ̅ 𝑋̅ + 𝑊𝑌
̅̅̅̅̅ 𝑋)
= 𝑍. ((𝑌 + 𝑊𝑌) + ( 𝑊 𝑋 + ̅̅̅̅̅
̅ ̅ ̅ ̅ 𝑊𝑌𝑋))
= 𝑍̅ . ((𝑊 + 𝑌̅) + 𝑊̅ . (𝑋̅ + 𝑋𝑌)) 𝐴. 𝐵̅ + 𝐵 = 𝐴 + 𝐵
∴ 𝑊. 𝑌 + 𝑌̅ = 𝑊 + 𝑌̅
= 𝑍̅. ((𝑊 + 𝑌̅) + 𝑊
̅ . (𝑋̅ + 𝑌)) 𝐴. 𝐵̅ + 𝐵 = 𝐴 + 𝐵
∴ 𝑋. 𝑌 + 𝑋̅ = 𝑌 + 𝑋̅
= 𝑍̅. (𝑊 + 𝑌̅ + 𝑊 ̅ . 𝑋̅ + 𝑊
̅ . 𝑌)
= 𝑍̅. (𝑊 + 𝑊̅ . 𝑌 + 𝑌̅ + 𝑊 ̅ . 𝑋̅) By rearranging terms using
commutative law
= 𝑍̅. (𝑊 + 𝑌 + 𝑌̅ + 𝑊
̅ . 𝑋̅) 𝐴. 𝐵̅ + 𝐵 = 𝐴 + 𝐵
̅.𝑌 + 𝑊 = 𝑌 + 𝑊
∴𝑊
= 𝑍̅. (𝑊 + (𝑌 + 𝑌̅) + 𝑊 ̅ . 𝑋̅)
= 𝑍̅. (𝑊 + 1 + 𝑊 ̅ . 𝑋̅) 𝐴 + 𝐴̅ = 1
∴ 𝑌 + 𝑌̅ = 1
= 𝑍̅. (1 + 𝑊 + 𝑊 ̅ . 𝑋̅)
= 𝑍̅. (1) 1+𝐴=1
∴ 1+𝑊+𝑊 ̅ . 𝑋̅ = 1
= 𝑍̅ 𝐴. 1 = 𝐴
∴ 𝑍̅. 1 = 𝑍̅
= R.H.S. Hence proved
Questions:
1. State De-Morgan’s theorem. [2M]
2. State and prove De Morgan’s theorem. [4M]
3. State commutative law. [2M]
4. List different Boolean laws. Also write duality theorem. [4M]
5. State associative law and distributive law of Boolean algebra. [4M]
6. State any four Boolean laws. [2M]
7. State duality theorem and prove it. [4M]
2.3 Simplification of Boolean expressions using Boolean laws

1-18
When logic circuit is constructed (or realized) for a complex Boolean
expression, it may require more number of logic gates. If the complex Boolean
expression is simplified and then realized (or constructed), less number of logic
gates are used. This is why there is need of simplification of Boolean
expressions.
Boolean expressions may be simplified using one of the following methods
- Using Boolean laws
- Karnaugh map method
- Quine-McCluskey method
Here discussion is done on how the Boolean expressions are simplified

using Boolean laws. The discussion about Karnaugh map (K-map) method is
done in chapter 3 and Quine-McCluskey method is out of the scope of
curriculum of this subject.
A complex Boolean expression may be simplified by applying set of basic

Boolean laws discussed in 2.2. Some examples are given below.
Example 1:
Simplify 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅
𝐴𝐵 + 𝐴̅ + 𝐴𝐵
By using law
Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅
𝐴𝐵 + 𝐴̅ + 𝐴𝐵
= ̿̿̿̿
𝐴𝐵 . 𝐴̿. ̅̅̅̅
𝐴𝐵 By applying De-Morgan’s law
= 𝐴. 𝐵. 𝐴. ̅̅̅̅
𝐴𝐵 𝐴̿ = 𝐴
∴ ̿̿̿̿
𝐴𝐵 = 𝐴𝐵
̅̅̅̅
= 𝐴. 𝐴. 𝐵. 𝐴𝐵
̅̅̅̅
= 𝐴. 𝐵. 𝐴𝐵 𝐴. 𝐴 = 𝐴
= 𝐴. 𝐵. (𝐴̅ + 𝐵̅ ) By applying De-Morgan’s law
= 𝐴. 𝐵. 𝐴̅ + 𝐴. 𝐵. 𝐵̅
= 𝐴. 𝐴̅. 𝐵 + 𝐴. 𝐵. 𝐵̅
= 0. 𝐵 + 𝐴. 0 As, 𝐴. 𝐴̅ = 0
= 0+0 As, 𝐴. 0 = 0
=0 As, 0 + 0 = 0
Therefore, 𝑌 = 0
Example 2:
̅ + 𝐴𝐵)(𝐴 + 𝐵̅)(𝐴̅𝐵)
Simplify 𝑌 = (𝐴 + 𝐵
By using law
Y ̅ + 𝐴𝐵)(𝐴 + 𝐵
= (𝐴 + 𝐵 ̅ 𝐵)
̅ )(𝐴
= (𝐴 + 𝐴𝐵 + 𝐵̅ )(𝐴 + 𝐵̅ )(𝐴̅𝐵)
= (𝐴 + 𝐴 + 𝐵̅ )(𝐴 + 𝐵̅ )(𝐴̅𝐵 ) 𝐴. 𝐵̅ + 𝐵 = 𝐴 + 𝐵
∴ 𝐴. 𝐵 + 𝐵̅ = 𝐴 + 𝐵̅
= (𝐴 + 𝐵̅ )(𝐴 + 𝐵̅ )(𝐴̅𝐵 ) 𝐴+𝐴=𝐴
= (𝐴 + 𝐵̅ )(𝐴̅𝐵 ) 𝐴+𝐴=𝐴
∴ (𝐴 + 𝐵 (𝐴 + 𝐵̅ ) = (𝐴 + 𝐵̅ )
̅ ).
1-19
= 𝐴𝐴̅𝐵 + 𝐵̅ 𝐴̅𝐵 By distributive law
= 0. 𝐵 + 𝐵̅ 𝐴̅𝐵 𝐴. 𝐴̅ = 0
= 0. 𝐵 + 0. 𝐴̅ 𝐵. 𝐵̅ = 0
= 0+0 0. 𝐴 = 0
=0
Therefore, 𝑌 = 0
Example 3:
̅ )(𝐴̅ + 𝐵)
Simplify 𝑌 = (𝐴 + 𝐵)(𝐴 + 𝐵
By using law
̅̅̅ ̅̅̅
Y = (𝐴 + 𝐵) (𝐴 + 𝐵) (𝐴 + 𝐵)
= (𝐴. 𝐴 + 𝐴. 𝐵̅ + 𝐵. 𝐴 + 𝐵. 𝐵̅ )(𝐴̅ + 𝐵) By using distributive law

= (𝐴 + 𝐴. 𝐵̅ + 𝐵. 𝐴 + 0)(𝐴̅ + 𝐵) 𝐴. 𝐴 = 𝐴 and 𝐵. 𝐵̅ = 0
= (𝐴 + 𝐴. 𝐵̅ + 𝐵. 𝐴)(𝐴̅ + 𝐵) 𝐴+0=𝐴
= (𝐴 + 𝐴. (𝐵̅ + 𝐵))(𝐴̅ + 𝐵) By taking A common
= (𝐴 + 𝐴. 0)(𝐴̅ + 𝐵) 𝐵 + 𝐵̅ = 0
= (𝐴 + 0)(𝐴̅ + 𝐵) 𝐴. 0 = 0
= 𝐴. (𝐴̅ + 𝐵) 𝐴+0=𝐴
= 𝐴. 𝐴̅ + 𝐴. 𝐵 By using distributive law
= 0 + 𝐴. 𝐵 𝐴. 𝐴̅ = 0
= 𝐴. 𝐵 𝐴+0=𝐴
Therefore, 𝑌 = 𝐴. 𝐵
2.4 Construction of logic circuits
As already discussed previously, any Boolean expression can be realized

(or constructed or implemented or drawn) using logic gates. Before realizing a
Boolean expression, it should be simplified so that requirement of number of
gates may be reduced. Simplification of given Boolean expression can be
minimized (or simplified) using various methods. Here the simplification is done
using basic Boolean laws.
Example 1:
Draw logical circuit for following Boolean expression using basic gates
𝑌 = 𝐴̅𝐵 + 𝐵𝐶
The expression given above is already in reduced (or simplified or

minimized) form. So, further simplification is not possible.
Logical Circuit:
1-20
𝐴 𝐴̅ 𝐵 𝐶
𝑌 = 𝐴̅𝐵 + 𝐵𝐶
Example 2:
Simplify following expression and draw logic gate diagram.
̅̅̅̅ + ̅̅̅̅̅̅̅̅
𝑌 = (𝐴𝐵 𝐴 + 𝐵 )𝐴. 𝐵̅
By using law
Y ̅̅̅̅ + ̅̅̅̅̅̅̅̅
= (𝐴𝐵 𝐴 + 𝐵 )𝐴. 𝐵̅
= (𝐴̅ + 𝐵̅ + 𝐴̅. 𝐵̅ )𝐴. 𝐵̅ By using De-Morgan’s theorem
= (𝐴̅ + 𝐵̅ (1 + 𝐴̅))𝐴. 𝐵̅ By taking common
= (𝐴̅ + 𝐵̅ . 1)𝐴. 𝐵̅ 1+𝐴=1
= (𝐴̅ + 𝐵̅ )𝐴. 𝐵̅ 𝐴. 1 = 𝐴
= 𝐴̅. 𝐴. 𝐵̅ + 𝐵̅ . 𝐴. 𝐵̅ By using distributive law
= 0. 𝐵̅ + 𝐵̅ . 𝐴 𝐴. 𝐴̅ = 0 and 𝐴. 𝐴 = 𝐴
= 0 + 𝐴. 𝐵̅ 0. 𝐴 = 0
= 𝐴. 𝐵̅ 0+𝐴 = 𝐴
Therefore, 𝑌 = 𝐴. 𝐵̅
Logic gate diagram:
𝐵 𝐵̅ 𝐴
𝑌 = 𝐴. 𝐵̅
Questions:
1. Prove that 𝑌̅𝑍̅ + 𝑊̅ 𝑋̅𝑍̅ + 𝑊̅ 𝑋𝑌 ̅𝑍 + 𝑊𝑌𝑍̅ = 𝑍̅ [4M]
2. Prove [4M]
a. 𝐴 + 𝐴̅𝐵 + 𝐴𝐵̅ = 𝐴 + 𝐵
b. 𝐴𝐵 + 𝐴̅𝐵 + 𝐴̅𝐵̅ = 𝐴̅ + 𝐵
3. Reduce the following expression and implement using logic gates. [4M]
𝑌 = 𝐴𝐵 + 𝐴𝐵𝐶 + 𝐴𝐵(𝐸 + 𝐹)
4. Simplify the following Boolean expressions using Boolean laws. [4M]
a. 𝑌 = 𝐴(𝐴̅ + 𝐶)(𝐴̅𝐵 + 𝐶̅ )
b. 𝑌 = 𝐵𝐶̅ 𝐷̅ + 𝐴̅𝐵𝐷 + 𝐴𝐵𝐷 + 𝐵𝐶𝐷 ̅ + 𝐵̅ 𝐶𝐷 + 𝐴̅𝐵̅ 𝐶̅ 𝐷 + 𝐴𝐵̅ 𝐶̅ 𝐷
5. Simplify following expression and draw logic gate diagram. [4M]
̅̅̅̅ + 𝐴
𝑌 = (𝐴𝐵 ̅̅̅̅̅̅̅̅
+ 𝐵 )𝐴. 𝐵̅
1-21
6. Simplify following Boolean expressions. [4M]
a. 𝑌 = 𝐴𝐵 + 𝐴𝐵𝐶 + 𝐴̅𝐵 + 𝐴𝐵 ̅̅̅̅𝐶
̅ ̅
b. 𝑌 = (𝐴 + 𝐵)(𝐴 + 𝐵 )(𝐴 + 𝐵)
7. Draw logical circuit for following Boolean expressions using basic gates.
[4M]
a. 𝑌 = 𝐴̅𝐵 + 𝐵𝐶
b. 𝑌 = (𝐴 ̅̅̅̅̅̅̅̅
+ 𝐵)
8. Simplify the following expressions. [4M]
a. 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ + 𝐴̅ + 𝐴𝐵
𝐴𝐵
b. 𝑌 = (𝐴 + 𝐵̅ + 𝐴𝐵)(𝐴 + 𝐵̅ )(𝐴̅𝐵)
1-22
Chapter 3
Combinational Logic Circuits
12 Hours
24 Marks
3.1 Standard representation for logical functions
Boolean expressions / logic expressions / logical functions are expressed in

terms of logical variables. Logical variables can have value either ‘0’ or ‘1’. The
logical functions can be represented in one of the following forms.
- Sum of Products form (SOP form)
- Product of Sums form (POS form)
3.1.1 Sum of Products (SOP) form

In this form, Boolean expression is defined by sum of product terms.
Various AND terms are ORed together. Each AND term may be a single
variable or a product of multiple variables (each variable may be either in
complemented or un-complemented form).
Example 1:
𝑌 = 𝐴𝐶 + 𝐴̅𝐵𝐶 + 𝐵
Here, Y is represented in SOP form with three terms. First AND term
contains two variables, second contains three variables and third contains a
single variable.
Example 2:
We can obtain sum of products expression from a truth table by
considering the input combinations those produce logic ‘1’ output as shown
below.
Table 3.1: Example Truth table
i/p o/p
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
First logic ‘1’ output in the truth table is for A=0, B=0 and C=1. This is
possible when 𝐴̅, 𝐵̅ and C are ANDed. So, first term is 𝐴̅. 𝐵̅ . 𝐶 and other terms can
be obtained similarly to get the expression for the truth table 3.1 in sum of
products form as,
3-1
𝑌 = 𝐴̅. 𝐵̅ . 𝐶 + 𝐴̅. 𝐵. 𝐶̅ + 𝐴̅. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶̅
As this expression is a function of three variables, it can be expressed as
𝑓(𝐴, 𝐵, 𝐶). It cans also be represented as 𝑌(𝐴, 𝐵, 𝐶).
𝑌 = 𝑓(𝐴, 𝐵, 𝐶) = 𝐴̅. 𝐵̅ . 𝐶 + 𝐴̅. 𝐵. 𝐶̅ + 𝐴̅. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶̅
Both the examples shown above are in sum of products form. But in first
example, even though the expression is function of three variables, first term is
containing only two variables whereas third term is containing only one
variable.
𝑌 = 𝐴. 𝐶 + 𝐴̅. 𝐵. 𝐶 + 𝐵
We may write each such incomplete term of the above expression in
expanded form as,
𝐴. 𝐶 = 𝐴. 𝐶. (𝐵 + 𝐵̅ ) = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶
𝐵 = 𝐵. (𝐴 + 𝐴̅) = 𝐴. 𝐵 + 𝐴̅. 𝐵 = 𝐴. 𝐵. (𝐶 + 𝐶̅ ) + 𝐴̅. 𝐵. (𝐶 + 𝐶̅ )
= 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶̅ + 𝐴̅. 𝐵. 𝐶 + 𝐴̅. 𝐵. 𝐶̅
Therefore, the expanded sum of product expression can be written as,
𝑌 = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐴̅. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶̅ + 𝐴̅. 𝐵. 𝐶 + 𝐴̅. 𝐵. 𝐶̅
𝑌 = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐴̅. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶̅ + 𝐴̅. 𝐵. 𝐶̅
Expanded form of Boolean expression in which each term contains all the
Boolean variables in it is called as canonical form. It is also called as
standard sum of products form.
Example 1:
Convert following Boolean expression into standard SOP form.
𝐴𝐶̅ + 𝐵𝐷
The above expression is a function of four variables A, B, C and D.
As each term is not containing all the variables, it is not standard SOP. The
terms can be expanded to make it standard SOP as,
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴. 𝐶̅ + 𝐵. 𝐷
= 𝐴. (𝐵 + 𝐵̅ ). 𝐶̅ + 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅ + 𝐴. 𝐵̅ . 𝐶̅ + 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅ . (𝐷 + 𝐷̅ ) + 𝐴. 𝐵̅ . 𝐶̅ . (𝐷 + 𝐷 ̅ ) + 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅ . 𝐷 + 𝐴. 𝐵. 𝐶̅ . 𝐷̅ + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷 + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷̅ + 𝐵. 𝐷
̅ ̅ ̅ ̅ ̅ ̅
= 𝐴. 𝐵. 𝐶 . 𝐷 + 𝐴. 𝐵. 𝐶 . 𝐷 + 𝐴. 𝐵 . 𝐶 . 𝐷 + 𝐴. 𝐵 . 𝐶 . 𝐷 ̅ ̅ + (𝐴 + 𝐴̅). 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅ . 𝐷 + 𝐴. 𝐵. 𝐶̅ . 𝐷̅ + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷 + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷̅ + 𝐴. 𝐵. 𝐷 + 𝐴. 𝐵. 𝐷̅
̅
= 𝐴. 𝐵. 𝐶 . 𝐷 + 𝐴. 𝐵. 𝐶 . 𝐷̅ ̅
̅ + 𝐴. 𝐵̅ . 𝐶 . 𝐷 + 𝐴. 𝐵̅ . 𝐶 . 𝐷̅ ̅
̅ + 𝐴. 𝐵. (𝐶 + 𝐶 ). 𝐷
+ 𝐴. 𝐵. (𝐶 + 𝐶 ). 𝐷 ̅ ̅
= 𝐴. 𝐵. 𝐶̅ . 𝐷 + 𝐴. 𝐵. 𝐶̅ . 𝐷̅ + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷 + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷̅ + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶̅ . 𝐷
̅
+ 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶 . 𝐷 ̅ ̅
As, 𝐴 + 𝐴 = 𝐴
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴. 𝐵. 𝐶̅ . 𝐷 + 𝐴. 𝐵. 𝐶̅ . 𝐷̅ + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷 + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷̅ + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷 ̅
Example 2:
Standardize following Boolean expression.
𝑌 = 𝐴𝐶 + 𝐵̅ 𝐶
3-2
The above expression is a function of three variables A, B and C. As
each term is not containing all the variables, it is not standard SOP. The terms
can be expanded to make it standard SOP as,
𝑌(𝐴, 𝐵, 𝐶) = 𝐴. 𝐶 + 𝐵̅ . 𝐶
= 𝐴. (𝐵 + 𝐵̅ ). 𝐶 + 𝐵̅ . 𝐶
= 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐵̅ . 𝐶
= 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + (𝐴 + 𝐴̅). 𝐵̅ . 𝐶
= 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐴̅. 𝐵̅ . 𝐶
As, 𝐴 + 𝐴 = 𝐴
𝑌(𝐴, 𝐵, 𝐶) = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐴̅. 𝐵̅ . 𝐶
Single term in standard sum of products is called as minterm. Each

expression can be represented using minterms. Some examples are shown
below.
Example 1:
𝑌 = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐴̅. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶̅ + 𝐴̅. 𝐵. 𝐶̅
As the above expression in standard sum of products, all terms in it are
minterms. They are,
𝐴. 𝐵. 𝐶 𝐴. 𝐵̅ . 𝐶 𝐴̅. 𝐵. 𝐶
m7 m5 m3
111 101 011
𝐴. 𝐵. 𝐶̅ 𝐴̅. 𝐵. 𝐶̅
m6 m2
110 010
Therefore the expression can be represented as,
𝑌(𝐴, 𝐵, 𝐶) = ∑ 𝑚(2,3,5,6,7)
Example 2:
𝑌 = 𝐴. 𝐵. 𝐶̅ . 𝐷 + 𝐴. 𝐵. 𝐶̅ . 𝐷
̅ + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷 + 𝐴. 𝐵̅ . 𝐶̅ . 𝐷
̅ + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷
̅
As the above expression in standard sum of products, all terms in it are
minterms. They are,
𝐴. 𝐵. 𝐶̅ . 𝐷 𝐴. 𝐵. 𝐶̅ . 𝐷
̅ 𝐴. 𝐵̅ . 𝐶̅ . 𝐷
m13 m12 m9
1101 1100 1001
𝐴. 𝐵̅ . 𝐶̅ . 𝐷
̅ 𝐴. 𝐵. 𝐶. 𝐷 ̅
𝐴. 𝐵. 𝐶. 𝐷
m8 m15 m14
1000 1111 1110
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(8,9,12,13,14,15)
3.1.2 Product of Sums (POS) form

In this form, Boolean expression is defined by product of sum terms.
Various OR terms are ANDed together. Each OR term may be a single variable
3-3
or a sum of multiple variables (each variable may be either in complemented or
un-complemented form).
Example 1:
𝑌 = (𝐴 + 𝐶). (𝐵̅ + 𝐶). 𝐴
Here, Y is represented in POS form with three terms. First OR term
contains two variables, second contains two variables and third contains a single
variable.
Example 2:
We can obtain product of sums expression from a truth table by
considering the input combinations those produce logic ‘0’ output as shown
below.
Table 3.2: Example Truth table
i/p o/p
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
First logic ‘0’ output in the truth table is for A=0, B=0 and C=0. This is
possible when 𝐴, 𝐵 and C are ORed. So, first term is (𝐴 + 𝐵 + 𝐶) and other terms
can be obtained similarly to get the expression for the truth table 3.2 in product
of sums form as,
𝑌 = (𝐴 + 𝐵 + 𝐶). (𝐴̅ + 𝐵 + 𝐶). (𝐴̅ + 𝐵 + 𝐶̅ ). (𝐴̅ + 𝐵̅ + 𝐶̅ )
As this expression is a function of three variables, it can be expressed as
𝑓(𝐴, 𝐵, 𝐶). It cans also be represented as 𝑌(𝐴, 𝐵, 𝐶).
𝑌 = 𝑓(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵 + 𝐶). (𝐴̅ + 𝐵 + 𝐶). (𝐴̅ + 𝐵 + 𝐶̅ ). (𝐴̅ + 𝐵̅ + 𝐶̅ )
Both the examples shown above are in product of sums form. But in first
example, even though the expression is function of three variables, first term is
containing only two variables, second term is also containing only two variables
and third term is containing only one variable.
𝑌 = (𝐴 + 𝐶). (𝐵̅ + 𝐶). 𝐴
We may write each such incomplete term of the above expression in
expanded form as,
(𝐴 + 𝐶) = (𝐴 + 𝐵. 𝐵̅ + 𝐶) = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵̅ + 𝐶)
(𝐵̅ + 𝐶) = (𝐴. 𝐴̅ + 𝐵̅ + 𝐶) = (𝐴 + 𝐵̅ + 𝐶). (𝐴̅ + 𝐵̅ + 𝐶)
𝐴 = (𝐴 + 𝐵. 𝐵̅ ) = (𝐴 + 𝐵). (𝐴 + 𝐵̅ ) = (𝐴 + 𝐵 + 𝐶. 𝐶̅ ). (𝐴 + 𝐵̅ + 𝐶. 𝐶̅ )
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴 + 𝐵̅ + 𝐶). (𝐴 + 𝐵̅ + 𝐶̅ )
3-4
Therefore, the expanded sum of product expression can be written as,
𝑌 = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵̅ + 𝐶). (𝐴 + 𝐵̅ + 𝐶). (𝐴̅ + 𝐵̅ + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴
+ 𝐵̅ + 𝐶). (𝐴 + 𝐵̅ + 𝐶̅ )
𝑌 = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵̅ + 𝐶). (𝐴̅ + 𝐵̅ + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴 + 𝐵̅ + 𝐶̅ )
Expanded form of Boolean expression in which each term contains all the
Boolean variables in it is called as canonical form. It is also called as
standard product of sums form.
Example 1:
Convert following Boolean expression into standard POS form.
(𝐴 + 𝐶̅ ). (𝐵 + 𝐷)
The above expression is a function of four variables A, B, C and D.
As each term is not containing all the variables, it is not standard POS. The
terms can be expanded to make it standard POS as,
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = (𝐴 + 𝐶̅ ). (𝐵 + 𝐷)
= (𝐴 + 𝐵. 𝐵̅ + 𝐶̅ ). (𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶̅ ). (𝐴 + 𝐵̅ + 𝐶̅ ). (𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶̅ + 𝐷. 𝐷 ̅ ). (𝐴 + 𝐵̅ + 𝐶̅ + 𝐷. 𝐷 ̅ ). (𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶̅ + 𝐷). (𝐴 + 𝐵 + 𝐶̅ + 𝐷 ̅ ). (𝐴 + 𝐵̅ + 𝐶̅ + 𝐷). (𝐴 + 𝐵̅ + 𝐶̅
̅
+ 𝐷). (𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶̅ + 𝐷). (𝐴 + 𝐵 + 𝐶̅ + 𝐷 ̅ ). (𝐴 + 𝐵̅ + 𝐶̅ + 𝐷). (𝐴 + 𝐵̅ + 𝐶̅
̅ ̅
+ 𝐷). (𝐴. 𝐴 + 𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶̅ + 𝐷
̅ ̅ ). (𝐴 + 𝐵̅ + 𝐶̅ + 𝐷). (𝐴 + 𝐵̅ + 𝐶̅
+𝐷̅ ). (𝐴 + 𝐵 + 𝐷). (𝐴̅ + 𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶̅ + 𝐷
̅ ̅ ). (𝐴 + 𝐵̅ + 𝐶̅ + 𝐷). (𝐴 + 𝐵̅ + 𝐶̅
+𝐷̅ ). (𝐴 + 𝐵 + 𝐶. 𝐶̅ + 𝐷). (𝐴̅ + 𝐵 + 𝐶. 𝐶̅ + 𝐷)
= (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶̅ + 𝐷
̅ ̅ ). (𝐴 + 𝐵̅ + 𝐶̅ + 𝐷). (𝐴 + 𝐵̅ + 𝐶̅
+𝐷̅ ). (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶̅ + 𝐷). (𝐴̅ + 𝐵 + 𝐶
+ 𝐷). (𝐴̅ + 𝐵 + 𝐶̅ + 𝐷)
As, 𝐴. 𝐴 = 𝐴
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = (𝐴 + 𝐵 + 𝐶̅ + 𝐷). (𝐴 + 𝐵 + 𝐶̅ + 𝐷 ̅ ). (𝐴 + 𝐵̅ + 𝐶̅ + 𝐷). (𝐴 + 𝐵̅ + 𝐶̅
+𝐷̅ ). (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴̅ + 𝐵 + 𝐶 + 𝐷). (𝐴̅ + 𝐵 + 𝐶̅ + 𝐷)
Example 2:
Standardize following Boolean expression.
𝑌 = (𝐴 + 𝐵)(𝐴̅ + 𝐶)
The above expression is a function of three variables A, B and C. As
each term is not containing all the variables, it is not standard POS. The terms
can be expanded to make it standard POS as,
𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵). (𝐴̅ + 𝐶)
= (𝐴 + 𝐵 + 𝐶. 𝐶̅ ). (𝐴̅ + 𝐶)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴̅ + 𝐶)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴̅ + 𝐵. 𝐵̅ + 𝐶)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴̅ + 𝐵 + 𝐶). (𝐴̅ + 𝐵̅ + 𝐶)
As, 𝐴 + 𝐴 = 𝐴
𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴̅ + 𝐵 + 𝐶). (𝐴̅ + 𝐵̅ + 𝐶)
3-5
Single term in standard product of sumss is called as maxterm. Each
expression can be represented using maxterms. Some examples are shown
below.
Example 1:
𝑌 = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵̅ + 𝐶). (𝐴̅ + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴̅ + 𝐵 + 𝐶̅ )
As the above expression in standard product of sums form, all terms in it
are maxterms. They are,
𝐴+𝐵+𝐶 𝐴 + 𝐵̅ + 𝐶 𝐴̅ + 𝐵 + 𝐶
M0 M2 M4
0 0 0 0 1 0 1 0 0
𝐴 + 𝐵 + 𝐶̅ 𝐴̅ + 𝐵 + 𝐶̅
M1 M5
0 0 1 1 0 1
𝑌(𝐴, 𝐵, 𝐶) = ∏ 𝑀(0,1,2,4,5)
Example 2:
𝑌 = (𝐴 + 𝐵 + 𝐶̅ + 𝐷). (𝐴 + 𝐵 + 𝐶̅ + 𝐷
̅ ). (𝐴 + 𝐵̅ + 𝐶̅ + 𝐷)
As the above expression in standard product of sums form, all terms in it

are maxterms. They are,
𝐴 + 𝐵 + 𝐶̅ + 𝐷 𝐴 + 𝐵 + 𝐶̅ + 𝐷
̅ 𝐴 + 𝐵̅ + 𝐶̅ + 𝐷
M2 M3 M6
0 0 1 0 0 0 1 1 0 1 1 0
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = ∏ 𝑀(2,3,6)
3.2 Karnaugh Map
In the last chapter, we have simplified Boolean expression using Boolean

laws. That was algebraic simplification method. In that method, it is hard to
guess whether the simplified expression is in its simplest form or not (i.e.
whether simplification is to be continued or not).This drawback has been
overcome in Karnaugh map simplification.
Karnaugh map (also called K-map) is graphical representation of a logic
system. It can be drawn from minterm or maxterm Boolean expressions.
Number of cells in a K-map depends on number of variables in the Boolean
expression. Karnaugh map of a Boolean expression with n variables contain 2n
cells (squares). Each cell in the K-map corresponds with one input combination.
Each row and each column of K-map is assigned by 0s and 1s.
A two-variable K-map can be drawn with various possibilities. Two
possibilities are shown in figure 3.1. In these notes we will use pattern shown in
figure 3.1a.
3-6
B A
0 1 0 1
A 0 0 1 B 0 0 2
1 2 3 1 1 3
a. b.
Figure 3.1: Two ways of representing a 2-variable K-map
As discussed previously, each square (or cell) in K-map corresponds to one
input combination. In figure 3.1a, cell 0 corresponds to input combination ‘00’
(i.e. 𝐴̅. 𝐵̅), cell 1 corresponds to input combination ‘01’ (i.e. 𝐴̅. 𝐵), cell 2
corresponds to input combination ‘10’ (i.e. 𝐴. 𝐵̅) and cell 3 corresponds to input
combination ‘11’ (i.e. 𝐴. 𝐵).
A three-variable K-map can be drawn with various possibilities. Four
figure 3.2a.
BC AB
00 01 11 10 00 01 11 10
A 0 0 1 3 2 C 0 0 2 6 4
1 4 5 7 6 1 1 3 7 5
a. b.
C A
0 1 0 1
AB 00 0 1 BC 00 0 4
01 2 3 01 1 5
11 6 7 11 3 7
10 4 5 10 2 6
c. d.
Figure 3.2: Four ways of representing a 3-variable K-map
A four-variable K-map can be drawn with various possibilities. Two

figure 3.3a.
3-7
CD AB
00 01 11 10 00 01 11 10
AB 00 0 1 3 2 CD 00 0 4 12 8
01 4 5 7 6 01 1 5 13 9
11 12 13 15 14 11 3 7 15 11
10 8 9 11 10 10 2 6 14 10
a. b.
Figure 3.3: Two ways of representing a 4-variable K-map
We can represent any expression which is in standard SOP (minterms)

form or standard POS (maxterms) form in a K-map.
3.2.1 Representation SOP on K-map

If the given Boolean expression is not in standard SOP form, it should be
first converted to standard SOP form. Then its minterms are written. For each
minterm in the expression, ‘1’ is written in the corresponding cell in the K-map
and the remaining cells are marked as ‘0’.
Example 1:
Represent following Boolean expression by K-map.
𝑌 = 𝐵𝐶 + 𝐴̅𝐵̅ 𝐶̅ + 𝐴𝐵𝐶̅
The above expression is in SOP form. It is a function of three
variables A, B and C. As each term is not containing all the variables, it is not in
standard SOP form. So, converting it into standard SOP form,
𝑌(𝐴, 𝐵, 𝐶) = 𝐵. 𝐶 + 𝐴̅. 𝐵̅ . 𝐶̅ + 𝐴. 𝐵. 𝐶̅
= (𝐴 + 𝐴̅). 𝐵. 𝐶 + 𝐴̅. 𝐵̅ . 𝐶̅ + 𝐴. 𝐵. 𝐶̅
𝑌(𝐴, 𝐵, 𝐶) = 𝐴. 𝐵. 𝐶 + 𝐴̅. 𝐵. 𝐶 + 𝐴̅. 𝐵̅ . 𝐶̅ + 𝐴. 𝐵. 𝐶̅
111 011 000 110
m7 m3 m0 m6
𝑌(𝐴, 𝐵, 𝐶) = ∑ 𝑚(0,3,6,7)
The above minterms can be represented in K-map. All the present terms
are marked as ‘1’ and remaining cells are marked as ‘0’. As the function is of
three variables, a three-variable K-map is used for representation.
BC
00 01 11 10
A 0 0 1 1 0 3 1 2 0
1 4 0 5 0 7 1 6 1
Example 2:
Represent following expression using K-map.
𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0,1,2,5,13,15)
The above minterms can be represented in K-map. All the present
terms are marked as ‘1’ and remaining cells are marked as ‘0’. As the function is
of four-variables, a four-variable K-map is used for representation.
3-8
CD
00 01 11 10
AB 00 0 1 1 1 3 0 2 1
01 4 0 5 1 7 0 6 0
11 12 0 13 1 15 1 14 0
10 8 0 9 0 11 0 10 0
Example 3:
𝑌 = ∑ 𝑚(0,1,3)
The above minterms can be represented in K-map. All the present
of two-variables, a two-variable K-map is used for representation.
B
0 1
A 0 0 1 1 1
1 2 0 3 1
3.2.2 Representation POS on K-map

If the given Boolean expression is not in standard POS form, it should be
first converted to standard POS form. Then its maxterms are written. For each
maxterm in the expression, ‘0’ is written in the corresponding cell in the K-map
and the remaining cells are marked as ‘1’.
Example 1:
Represent following Boolean expression by K-map.
𝑌 = (𝐴 + 𝐵) + (𝐴̅ + 𝐵̅ + 𝐶̅ ) + (𝐴 + 𝐵 + 𝐶̅ )
The above expression is in POS form. It is a function of three
variables A, B and C. As each term is not containing all the variables, it is not in
standard POS form. So, converting it into standard POS form,
𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵) + (𝐴̅ + 𝐵̅ + 𝐶̅ ) + (𝐴 + 𝐵 + 𝐶̅ )
= (𝐴 + 𝐵 + 𝐶. 𝐶̅ ) + (𝐴̅ + 𝐵̅ + 𝐶̅ ) + (𝐴 + 𝐵 + 𝐶̅ )
= (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶̅ ) + (𝐴̅ + 𝐵̅ + 𝐶̅ ) + (𝐴 + 𝐵 + 𝐶̅ )
𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶̅ ) + (𝐴̅ + 𝐵̅ + 𝐶̅ )
0 0 0 0 0 1 1 1 1
M0 M1 M7
𝑌(𝐴, 𝐵, 𝐶) = ∏ 𝑀(0,1,7)
The above maxterms can be represented in K-map. All the present terms
are marked as ‘0’ and remaining cells are marked as ‘1’. As the function is of
three variables, a three-variable K-map is used for representation.
BC
00 01 11 10
A 0 0 0 1 0 3 1 2 1
1 4 1 5 1 7 0 6 1
3-9
Example 2:
𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∏ 𝑀(1,3,5,7,9,11,13,15)
The above maxterms can be represented in K-map. All the present
of four-variables, a four-variable K-map is used for representation.
CD
00 01 11 10
AB 00 0 1 1 0 3 0 2 1
01 4 1 5 0 7 0 6 1
11 12 1 13 0 15 0 14 1
10 8 1 9 0 11 0 10 1
Example 3:
𝑌 = ∏ 𝑀(0,2)
The above maxterms can be represented in K-map. All the present
of two-variables, a two-variable K-map is used for representation.
B
0 1
A 0 0 0 1 1
1 2 0 3 1
3.2.3 Grouping of adjacent cells

K-maps are used for simplification of Boolean expressions. The
simplification is based on grouping of the terms in adjacent cells. Important
aspects of grouping are discussed below.
- Number of cells in a group must always be a power of 2. (i.e. 1, 2, 4, 8,
16 etc.)
- Two cells are said to be adjacent if they differ in only one variable.
Four cells are said to be adjacent if they differ in two variables. Eight
cells are said to be adjacent if they differ in three variables and so on.
- If K-map is represented for a SOP, grouping is done for adjacent 1’s
and if K-map is represented for a POS, grouping is done for adjacent
0’s.
- While grouping, each cell containing ‘1’ in case of SOP (‘0’ in case of
POS) must be considered at least once.
- We should try to make minimum number of groups (i.e. each group of
maximum possible size).
- ‘Don’t care entries’ may be considered in any group.
3-10
Chapter 4
Sequential Logic Circuits
14 Hours
28Marks
4.1Introduction to Sequential Logic Circuit
Logic circuits discussed previously were combinational circuits. In those

circuits output depends only on the current input combination. But in sequential
logic circuits, output of circuit depends on current input as well as past
input or past output. For achieving this, sequential logic circuits contain
memory element for storing past input or past output.
Questions:
1. Give any four differences between combinational (or combinatorial) and
sequential logic circuit. [4M]
2. Differentiate between combinational logic and sequential logic system.
[4M]
4.2.1One-bit memory cell

Memory element just discussed above, stores data (generally one bit data
is stored per element). Snapshot of a memory is called a state. One-bit memory
cell is bi-stable. It means, it has two stable internal states. Flip-flop is common
implementation of bi-stable. Therefore flip flop is also referred as basic memory
cell.
One bit memory cell stores one bit data as 0 or 1. It can be implemented
using transistors, NAND gates or NOR gates.
Figure 4.1: One-bit memory cell using NAND gates
Table 4.1: Truth Table for One-bit memory cell (NAND implementation)
Input Output
S R
0 0 Race
(both 1)
0 1 0 1
1 0 1 0
1 1
4-1
Figure 4.2: One-bit memory cell using NOR gates
Table 4.2: Truth Table for One-bit memory cell (NOR implementation)
Input Output
S R
0 0
0 1 0 1
1 0 1 0
1 1 Race (both 0)
The above one-bit memory cell is also referred as SR flip flop or RS flip
flop. S input (Set) is used for setting the flip flop (i.e. to get output as 1). R input
(Reset) is used for resetting the flip flop (i.e. to get output as 0).
Questions:
3. Draw 1-bit memory cell using NAND gate. [2M]
4. Draw 1-bit memory cell using NOR gate. [2M]
5. Why a flip-flop is called a basic memory cell? [2M]
4.2.2Clock signal and Triggering Methods

Clock signal is a digital signal. Which is generally fed to every sequential
circuit. A sample clock signal is drawn below.
Level 1 (HIGH)
Positive Negative
Edge Edge
Level 0 (LOW)
Figure 4.3: Clock signal

Clock signal is a digital signal which has only two levels as level 0 and
level 1. Level 0 is also referred as LOW, FALSE, negative or OFFlevel. Level
1 is also referred as HIGH, TRUE, positive or ONlevel. The edge which
changes the level from level 0 to level 1 is referred as positive edge,rising
edge, leading edge or LOW-to-HIGH edge. The edge which changes the level
from level 1 to level 0 is referred as negative edge,falling edge, trailing edge
orHIGH-to-LOW edge.
4-2
Triggering is the process of activating the circuit for generating the
output. Triggering can be broadly classified in two categories as,
- Level triggering
- Edge triggering
In level triggering, the circuit is triggered at a level. There are two

types of level triggering. If circuit gets triggered at level 1 (i.e. Circuit generates
output at level 1 of clock signal), it is called level 1 triggering,HIGH level
triggering or positive level triggering. If circuit gets triggered at level 0 (i.e.
Circuit generates output at level 0 of clock signal), it is called level 0
triggering,LOW level triggering or negative level triggering.
In edge triggering, the circuit is triggered on an edge. There are two
types of edge triggering. If circuit gets triggered on positive edge (i.e. Circuit
generates output on rising edging of clock signal), it is called positive edge
triggering or rising edge triggering. If circuit gets triggered on negative
edge (i.e. Circuit generates output on falling edge of clock signal), it is called
negative edge triggering or falling edge triggering.
Questions:
1. Draw clock signal. Explain various triggering methods. [4M]
2. Name the types of triggering that can be used for clocking a flip flop. [2M]
3. Explain positive edge triggering and negative edge triggering. [4M]
4. Enlist triggering methods and explain one of them. [4M]
5. Describe different types of triggering methods for a flip-flop. [4M]
6. Explain the types of triggering methods. [4M]
4.3 Flip flops
Logic gate was the most basic building block of a combinational circuit. In
sequential circuit, flip-flop is the most basic building block.Flip flop is a bi-stable
circuit. It means, it has two stable internal states. Both the output states and
are stable. Circuit remains in a particular output state indefinitely until
something is done to change it.
Various types of flip-flops are
- SR Flip flop
- JK Flip flop
- T Flip flop
- D Flip flop
4.3.1SR Flip Flop or RS Flip Flop

Implementation of a SR flip flop using NAND gates is shown in figure 4.4.
Symbol of SR flip flop is shown in figure 4.5.
4-3
Figure 4.4: Implementation of SR Flip Flop using NAND gates
SR
Flip Flop
Figure 4.5: Symbol of SR Flip Flop
When S=0 and R=0

As S is 0 and R is 0, after inversion one input of both NAND gates is 1. So
outputs of these NAND gates are inversion of other inputs. So output of upper
NAND gate remains (as inversion of ) and output of lower NAND gate
remains (as inversion of ). So output remains unchanged.
When S=0 and R=1

As R is 1, after inversion one input of lower NAND gate is 0 which results
in generating output 1 for the lower NAND gate. i.e. becomes 1. As S is 0,
after inversion one input of upper NAND gate is 1. Other input of this NAND
gate is also 1 (as is 1). So the output of upper NAND gate i.e. becomes 0.
Both the outputs remain stable as 0 and 1.i.e. flip flop is reset.
When S=1 and R=0

As S is 1,after inversion one input of upper NAND gate is 0 which results
in generating output 1 for the upper NAND gate. i.e. becomes 1. As R is 0, after
inversion one input of lower NAND gate is 1. Other input of this NAND gate is
also 1 (as is 1). So the output of lower NAND gate i.e. becomes 0. Both the
outputs remain stable as 1 and 0.i.e. flip flop is set.
When S=1 and R=1

As S is 1 R is 1, after inversion one input of both NAND gates is 0. So
both the NAND gates try to generate output as 1, which is race between and
. This is forbidden state.
Truth table of SR flip flop is shown below.
4-4
Table 4.3: Truth Table for SR Flip Flop
Input Output
S R
0 0
0 1 0
1 0 1
1 1 Forbidden
4.3.1.1 Clocked SR Flip Flop

As discussed in 4.2.2, clock is fed to every sequential circuit. So, a
clocked SR flip flop can be implemented using NAND gates as shown below.
1
3
4
2
Figure 4.6: Implementation of clocked SR Flip Flop
Symbol of clocked SR flip flop is shown below. It is positive triggered SR

flip flop.
SR
Flip Flop
Figure 4.7: Symbol of clocked SR Flip Flop
When Clk=0, S=X and R= X

Output of NAND gates 1 and 2 are always 1 regardless of value of S and
R. As one input of NAND gates 3 and 4 are always 1, outputs of these NAND
gates are inversion of other inputs. So output of NAND gate 3 remains (as
inversion of ) and output of NAND gate 4 remains (as inversion of ). So
output remains unchanged regardless of values of S and R. i.e. Flip flop is not
triggered.
When Clk=1
As one input of NAND gates 1 and 2 are always 1, outputs of these NAND
gates are inversion of other inputs. i.e. Circuit responds to values of S and R.
Here NAND gates 1 and 2 work as NOT gates.
4-5
When Clk=1, S=0 and R=0
As both S and R are 0, output of NAND gates 1 and2becomes 1. So, one
input of NAND gates 3 and 4 are always 1, outputs of these NAND gates are
inversion of other inputs. So output of NAND gate 3 remains (as inversion of
) and output of NAND gate 4 remains (as inversion of ). So output remains
unchanged.

As R is 1, output of NAND gate 2 is0. As one input of NAND gate 4 is 0,
its output is 1. Therefore becomes 1. As S is 0, output of NAND gate 1 becomes
1. So both the inputs of NAND gate 3 are 1, resulting in output as 0. Therefore
becomes 0. Both the outputs remain stable as 0 and 1. i.e. flip flop is reset.

As S is 1, output of NAND gate 1 is 0. As one input of NAND gate 3 is 0,
its output is 1. Therefore becomes 1. As R is 0, output of NAND gate 2
becomes 1. So both the inputs of NAND gate 4 are 1, resulting in output as 0.
Therefore becomes 0. Both the outputs remain stable as 1 and 0. i.e. flip flop is
set.

As S is 1, output of NAND gate 1 is 0. As one input of NAND gate 3 is 0,
its output is 1. Therefore becomes 1. As R is 1, output of NAND gate 2 is 0. As
one input of NAND gate 4 is 0, its output is 1. Therefore becomes 1. Here both
and tries to become 1. That there is a race between and . This is
forbidden state.
Truth table of clocked (positive level triggered) SR flip flop is shown

below.
Table 4.3: Truth Table for clocked SR Flip Flop
Input Output
Clk S R
0 X X No change
1 0 0
1 0 1 0
1 1 0 1
1 1 1 Forbidden
4.3.1.2Clocked SR Flip Flop with Preset and Clear inputs

Flip flops generally have two additional inputs as Preset and Clear.
Preset input is used to preset the flip flop to 1. i.e. to 1.Whereas clear input is
used to clear the flip flop to 0. i.e. to 0. Both the Preset and Clear inputs are
active low (i.e. active when low). Aclocked SR flip flop with preset and
clear inputs can be implemented using NAND gates as shown below.
4-6
1 3
2 4
Figure 4.8: Implementation of clocked SR Flip Flop with Preset & Clear
Symbol of clocked SR flip flop with Preset and Clear inputs is shown
below.
SR
Flip Flop
Figure 4.9: Symbol of clocked SR Flip Flop with Preset & Clear
When Pr=0, Cr=0, Clk=X, S=X and R= X

As Pr is 0, one of the input of NAND gate 3 becomes 0. So output of
NAND gate 3 becomes 1. i.e. becomes 1 regardless of all other inputs. As Cr is
0, one of the input of NAND gate 4 becomes 0. So output of NAND gate 4
becomes 1. i.e. becomes 1 regardless of all other inputs. This should never
happen. So this input combination is not allowed.
As Pr is 0, one of the input of NAND gate 3 becomes 0. So output of
NAND gate 3 becomes 1. i.e. becomes 1 regardless of all other inputs. So flip
flop is preset. Here becomes 0.
As Cr is 0, one of the input of NAND gate 4 becomes 0. So output of
NAND gate 4 becomes 1. i.e. becomes 1 regardless of all other inputs. Here
becomes 0. So flip flop is clear.
When Pr=1, Cr=1
For the values of Pr and Cr as 1, flip flop works same as normal clocked
SR flip flop which is already discussed in 4.3.1.1.
4-7
Truth table of clocked (positive level triggered) SR flip flop with Preset
and Clear inputs is shown below.
Table 4.4: Truth Table for clocked SR Flip Flop with Pr& Cr
Input Output
Pr Cr Clk S R
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 Forbidden
4.3.1.3 SR Flip Flop with different triggering methods

For flip flop to be triggered it should be clocked. Various types of SR flip
flops on the basis of triggering methods are
- Positive level triggered SR flip flop
- Negative level triggered SR flip flop
- Positive edge triggered SR flip flop
- Negative edge triggered SR flip flop
Symbols and truth tables of these flip flops are given below.
SR
Flip Flop
Figure 4.10: Symbol of Positive level triggered SR Flip Flop
Table 4.5: Truth Table for Positive level triggered SR Flip Flop
Input Output
Clk S R
0 X X No change
1 0 0
1 0 1 0
1 1 0 1
1 1 1 Forbidden
4-8
SR
Flip Flop
Figure 4.11: Symbol of Negative level triggered SR Flip Flop
Table 4.6: Truth Table for Negative level triggered SR Flip Flop
Input Output
Clk S R
1 X X No change
0 0 0
0 0 1 0
0 1 0 1
0 1 1 Forbidden
SR
Flip Flop
Figure 4.12: Symbol of Positive edge triggered SR Flip Flop
Table 4.7: Truth Table for Positive edge triggered SR Flip Flop
Input Output
Clk S R
Other X X No change
 0 0
 0 1 0
 1 0 1
 1 1 Forbidden
4-9
SR
Flip Flop
Figure 4.13: Symbol of Negative edge triggered SR Flip Flop
Table 4.8: Truth Table for Negative edge triggered SR Flip Flop
Input Output
Clk S R
Other X X No change
 0 0
 0 1 0
 1 0 1
 1 1 Forbidden
4.3.2JK Flip Flop

As seen in above discussion, in all versions of SR flip flops there is one
forbidden input combination. This is the main drawback of SR flip flop. This
limitation of SR flip flop is overcome in JK flip flop. Implementation of JK flip
flop is shown below. This implementation is of positive level triggered JK flip
flop with preset and clear inputs.
1 3
2 4
Figure 4.14: Implementation of clocked JK Flip Flop with Preset & Clear
Symbol of JK flip flop is shown below.
4-10
JK
Flip Flop
Figure 4.15: Symbol of clocked JK Flip Flop with Preset & Clear
Preset input, Clear input and Clock input work same as that of SR flip
flop. So they are not discussed here.
When J=0 and K=0

As J and K are 0, one input of NAND gates 1 and 2 are 0. So outputs of
these NAND gates is 1. S is 0 and R is 0, after inversion one input of both
NAND gates is 1. As preset and clear are also 1, two inputs of NAND gates 3
and 4 are 1. So outputs of these NAND gates are inversion of remaining input.
So output of NAND gate 3 remains (as inversion of ) and output of NAND
gate 4 remains (as inversion of ). So output remains unchanged.
When J=0 and K=1

As K is 1, two inputs (i.e. K and Clk) of NAND gate 2 are 1. So output of
this gate will be inversion of its third input which is . Now may be either 0 or
1.
If is 0, output of NAND gate 2 will be1. For NAND gate 4 inputs will be
1 (as output of NAND gate 2), 1 (Cr) and 0 ( ). So output of NAND gate 4 will be
1. i.e. will be 1.
If is 1, output of NAND gate 2 will be 0. For NAND gate 4 inputs will be
0 (as output of NAND gate 2), 1 (Cr) and 1 ( ). So output of NAND gate 4 will be
1. i.e. will be 1.
So, regardless of value of the output of NAND gate 4 i.e. will be 1.
As J is 0, one input of NAND gates 1 is 0. So output of NAND gate 1 is 1.
For NAND gate 3 inputs will be 1 (as output of NAND gate 1), 1 (Pr) and 1 ( ).
So output of NAND gate 3 will be 0. i.e. will be 0.
Thus, remains 0 and remains 1. Both the outputs remain stable as 0
and 1. i.e. flip flop is reset.
When J=1 and K=0

As J is 1, two inputs (i.e. J and Clk) of NAND gate 1 are 1. So output of
this gate will be inversion of its third input which is . Now may be either 0 or
1.
4-11
1 (as output of NAND gate 1), 1 (Pr) and 0 ( ). So output of NAND gate 3 will be
1. i.e. will be 1.
0 (as output of NAND gate 1), 1 (Pr) and 1 ( ). So output of NAND gate 3 will be
1. i.e. will be 1.
So, regardless of value of the output of NAND gate 3 i.e. will be 1.
As K is 0, one input of NAND gates 2 is 0. So output of NAND gate 2 is 1.
For NAND gate 4 inputs will be 1 (as output of NAND gate 1), 1 (Cr) and 1 ( ).
So output of NAND gate 4 will be 0. i.e. will be 0.
Thus, remains 1 and remains 0. Both the outputs remain stable as 1
and 0. i.e. flip flop is set.
When J=1 and K=1

As J is 1 and K is 1, the output of JK flip flop toggles between and .
Truth table of JK flip flop with Preset and Clear inputs is shown below.
Table 4.9: Truth Table for clocked JK Flip Flop with Pr& Cr
Input Output
Pr Cr Clk J K
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 (Toggle)
4.3.2.1 Race around condition in JK flip flop

JK flip flop overcomes the limitation of SR flip flop (which was not
handling the combination of S=1 and R=1). In JK flip flop, when J=1 and K=1,
the output of JK flip flop toggles between and . But in case of a level
triggered JK flip flop like one seen above, it creates a problem.
Let us assume a positive level triggered JK flip flop. This flip flop get
triggered on the positive level. If J=1 and K=1, = . This output is toggled
whenever clock is at HIGH level (i.e. 1). But if width of a clock pulse is greater
than propagation delay (discussed in 1.2.1.1) of the circuit, output state at the
end of HIGH level is not reliable as illustrated in the figures4.16 and 4.17 below.
4-12
Clock
Signal
Output State Here, at the end of

when = 1 and positive level of clock
=1 pulse, = 1
Figure 4.16: Sample (Sample 1) output pulse when J=K=1
Clock
Signal
Output State Here, at the end of

when = 1 and positive level of clock
=1 pulse, = 0
Figure 4.17: Sample (Sample 2) output pulse when J=K=1
This uncertainty in the output state when J=K=1 is called as race-

around condition of JK flip flop. It can be avoided by various ways as
1) Keeping the width of clock pulse smaller than propagation delay of the
circuit (difficult solution).
2) Using edge-triggered JK flip flop instead of level triggered JK flip flop.
3) Using Master-Slave JK flip flop (Discussed in 4.3.2.2).
4.3.2.2Master Slave JK Flip Flop

For avoiding race around condition in JK flip flop, Master Slave JK flip
flop is used. The implementation of Master Slave JK flip flop using two SR flip
flops is shown in following figure.
4-13
Slave SR
Master SR
Flip Flop
Flip Flop
Figure 4.18: Master Slave JK Flip Flop using two SR Flip Flops
Here two SR flip flops are used. First SR flip flop works as master and
second SR flip flop works as slave. Master SR flip flop controls the operation of
slave SR flip flop. A clock is provided to master flip flop and the same clock is
provided to slave flip flop but through a NOT gate. Therefore, when master flip
flop is enabled, slave flip flop is disables and vice-a-versa. So output is not
propagated immediately. Rather it is propagated at the end of a complete clock
pulse. This results in avoidance of race around condition.
Symbol of MS JK flip flop is shown below.
MS JK
Flip Flop
Figure 4.19: Symbol of MS JK Flip Flop
Truth table of MS JK flip flop is shown below.
4-14
Table 4.10: Truth Table for MS JK Flip Flop with Pr& Cr
Input Output
Pr Cr Clk J K
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 (Toggle)
4.3.2.3JK Flip Flop with different triggering methods

Various types of JK flip flops on the basis of triggering methods are
- Positive level triggered JK flip flop
- Negative level triggered JK flip flop
- Positive edge triggered JK flip flop
- Negative edge triggered JK flip flop
JK
Flip Flop
Figure 4.20: Symbol of Positive level triggered JK Flip Flop
Table 4.11: Truth Table for Positive level triggered JK Flip Flop
Input Output
Clk J K
0 X X No change
1 0 0
1 0 1 0
1 1 0 1
1 1 1
4-15
JK
Flip Flop
Figure 4.21: Symbol of Negative level triggered JK Flip Flop
Table 4.12: Truth Table for Negative level triggered JK Flip Flop
Input Output
Clk J K
1 X X No change
0 0 0
0 0 1 0
0 1 0 1
0 1 1
JK
Flip Flop
Figure 4.22: Symbol of Positive edge triggered JK Flip Flop
Table 4.13: Truth Table for Positive edge triggered JK Flip Flop
Input Output
Clk J K
Other X X No change
 0 0
 0 1 0
 1 0 1
 1 1
4-16
JK
Flip Flop
Figure 4.23: Symbol of Negative edge triggered JK Flip Flop
Table 4.14: Truth Table for Negative edge triggered JK Flip Flop
Input Output
Clk J K
Other X X No change
 0 0
 0 1 0
 1 0 1
 1 1
4.3.3T Flip Flop

It is also called as Toggle flip flop. Its output changes its state each time
when it is triggered and T input is 1. We can implement T flip flop using JK flip
flop as shown below.
JK
Flip Flop
Figure 4.24: Implementation of T Flip Flop using JK Flip Flop
Symbol of T flip flop is shown below
4-17
T
Flip Flop
Figure 4.25: Symbol of T Flip Flop
Truth table of T flip flop is given below.
Table 4.15: Truth Table for T Flip Flop

Input Output
T
0 (No change)
1 (Toggle)
4.3.3.1T Flip Flop with different triggering methods

Various types of T flip flops on the basis of triggering methods are
- Positive level triggered T flip flop
- Negative level triggered T flip flop
- Positive edge triggered T flip flop
- Negative edge triggered T flip flop
T
Flip Flop
Figure 4.26: Symbol of positive level triggered T Flip Flop
4-18
Table 4.16: Truth Table for positive level triggered T Flip Flop
Input Output
Clock T
Other X No change
1 0 (No change)
1 1 (Toggle)
T
Flip Flop
Figure 4.27: Symbol of negative level triggered T Flip Flop
Table 4.17: Truth Table for negative level triggered T Flip Flop
Input Output
Clock T
Other X No change
0 0 (No change)
0 1 (Toggle)
T
Flip Flop
Figure 4.28: Symbol of positive edge triggered T Flip Flop
4-19
Table 4.18: Truth Table for positive edge triggered T Flip Flop
Input Output
Clock T
Other X No change
 0 (No change)
 1 (Toggle)
T
Flip Flop
Figure 4.29: Symbol of negative edge triggered T Flip Flop
Table 4.19: Truth Table for negative edge triggered T Flip Flop
Input Output
Clock T
Other X No change
 0 (No change)
 1 (Toggle)
4.3.4D Flip Flop or Delay Flip Flop

It is also called as Delay flip flop. Its output generates the output state
same as its D input each time when it is triggered. i.e. It delays the provided
input. It is used as a memory latch for storing a bit in it. We can implement D
flip flop using SR flip flop as shown below.
4-20
SR
Flip Flop
Figure 4.30: Implementation of D Flip Flop using SR Flip Flop
D flip can also be implemented using JK flip flop. This implementation is

shown below.
JK
Flip Flop
Figure 4.31: Implementation of D Flip Flop using JK Flip Flop
Symbol of D flip flop is shown below
D
Flip Flop
Figure 4.32: Symbol of D Flip Flop

4-21
Truth table of D flip flop is given below.
Table 4.20: Truth Table for D Flip Flop

Input Output
D
0 0
1 1
4.3.4.1D Flip Flop with different triggering methods

Various types of D flip flops on the basis of triggering methods are
- Positive level triggered D flip flop
- Negative level triggered D flip flop
- Positive edge triggered D flip flop
- Negative edge triggered D flip flop
D
Flip Flop
Figure 4.33: Symbol of positive level triggered D Flip Flop
Table 4.21: Truth Table for positive level triggered D Flip Flop
Input Output
Clock D
Other X No change
1 0 0
1 1 1
4-22
D
Flip Flop
Figure 4.34: Symbol of negative level triggered D Flip Flop
Table 4.22: Truth Table for negative level triggered D Flip Flop
Input Output
Clock D
Other X 0
0 0 1
0 1 (Toggle)
D
Flip Flop
Figure 4.35: Symbol of positive edge triggered D Flip Flop
Table 4.23: Truth Table for positive edge triggered D Flip Flop
Input Output
Clock D
Other X No change
 0 0
 1 1
4-23
D
Flip Flop
Figure 4.36: Symbol of negative edge triggered D Flip Flop
Table 4.24: Truth Table for negative edge triggered D Flip Flop
Input Output
Clock D
Other X No change
 0 0
 1 1
Questions:
1. State different applications of flip-flops. [4M]
2. Explain clocked SR flip flop using NAND gate. [4M]
3. Draw clocked SR flip flop. [2M]
4. Draw logic circuit diagram of clocked RS flip flop using NAND gates and
draw the truth table. [4M]
5. Explain function of ‘preset’ and ‘clear’ inputs in Flip-flops. [4M]
6. Draw symbol and truth table of JK flip flop. [2M]
7. Draw logic diagram of JK flip flop and write its truth table. [4M]
8. State function of “Preset” and “Clear” terminals in a JK flip flop. [4M]
9. Give significance of “Preset” and “Clear” terminals in a JK flip flop. [4M]
10. Show logic circuit of JK Flip flop using NAND gates only. Explain its
working with truth table. [4M]
11. Draw neat circuit diagram of clocked JK Flip-flop using NAND gates.
Give its truth table explain race-around condition. [4M]
12. Explain race around condition with respect to JK flip flop. [4M]
13. What is race around condition? How to eliminate it? [4M]
14. What is race around condition? How can it be avoided? [4M]
15. Draw and explain master slave flip flop. [4M]
16. Draw and explain MS-JK flip flop. [4M]
17. List different types of flip flops. Draw diagram of master slave JK flip flop.
18. Convert SR flip flop into D flip flop and explain. [4M]
19. Draw symbol and truth table of negative edge triggered T flip flop and
positive edge triggered D flip flop. [2M]
20. With the help of suitable diagram explain how do you convert JK flip flop
into T flip flop and D flip flop. [4M]
4-24
21. Draw symbol and truth table of T and D flip flop. [4M]
22. Draw logic diagram of D flip flop and write its truth table. [4M]
23. Draw symbol and truth table for following flip-flops.
a. Clocked SR flip flop.
b. JK flip flop.
c. D filp flop.
d. T flip flop.
24. Draw symbol and truth table of T flip flop for negative edge triggered.
[4M]
25. Draw and explain D flip flop using SR flip flop. Also draw truth table.
[4M]
4.4 Applications of Flip flops
Flip flops have large set of applications as they are the basic building
blocks in all the sequential circuits. Major applications of Flip flops are
- Memories (data storage)
- Counters
o Synchronous Counters
o Asynchronous Counters
o Up Counters
o Down Counters
o Mod-N Counters
- Shift Registers
o Serial In Serial Out Shift Registers
o Serial In Parallel Out Shift Registers
o Parallel In Parallel Out Shift Registers
o Parallel In Serial Out Shift Registers
o Ring Counters
o Johnson Counters
- Delay Elements
- Frequency Division
- Data Transfer
4.4.1Counters
Counter is a sequential logic circuit. It is cascaded arrangement of more
than one flip flop with or without some combinational logic devices. It is
basically used for counting applications like.
- Counting objects on conveyors.
- Counting incoming and outgoing vehicles.
- Counting numbers of papers in printing.
- Filling fixed number of tablets in a bottle.
For designing counters either JK flip flops or T flip flops are used. While
using JK flip flops, J and K inputs are to be shortened (i.e. JK flip flop is to be
used as T flip flop).
Counters can be broadly classified in two categories as

- Asynchronous Counters
- Synchronous Counters
4-25
These types are discussed later on.
4.4.1.1Modulus of a counter
Modulus of a counter is number of different states it goes through before
coming back to initial state. i.e. number of states that a counter counts is called
as modulus of counter.
Example 1:
If a counter counts from 0 to 7 (as 0, 1, 2, 3, 4, 5, 6, 7), then this
counter has modulus 8 and it is said to be a mod-8 counter.
Example 2:
If a counter counts from 0 to 5 (as 0, 1, 2, 3, 4, 5), then this counter
has modulus 6 and it is said to be a mod-6 counter.
4.4.1.2Asynchronous counter
Asynchronous counter is also called as ripple counter or serial
counter.In this type of counter, clock pulse is applied to only first flip flop.
Output of first flip flop drives clock input of second flip flop and so on. The
counter is called asynchronous as the clock pulses of all the flip flops are not
same. Due to this all the flip flops do not change their states at the same time.
Second flip flop can change the state only after change in the state of first flip
flop. So these counters have high propagation delay. Hence the operational
frequency is low. Advantage of this type of counter is that it is easy to design.
4.4.1.2.1 Steps for designing asynchronous counter or ripple counter

Fordesigning a n-bit asynchronous counter or ripple counter, following
steps are undertaken.
i. It requires n number of flip flops. The flip flops used may be either
JK flip flop or T flip flop.
ii. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the n flip flops
are connected to logic 1 (or VCC) so that all the flip flops work
properly.
iii. When JK flip flops are used, J and K input of all the n flip flops are
connected to each other and then to logic 1 (or VCC). When T flip
flops are used, T inputs of all the n flip flops are connected to logic
1 (or VCC). Due to this, all the n flip flops always toggle their output
state at each trigger (i.e. output state of each flip flop gives the
negation of previous state on trigger).
iv. External clock pulse is connected to flip flop number 0 (i.e. first flip
flop). Output of first flip flop (i.e. ) is connected to clock input of
flip flop number 1 (i.e. second flip flop). Output of second flip flop
(i.e. ) is connected to clock input of flip flop number 2 (i.e. third
flip flop) and so on.
v. Output of the counter is observed at (LSB), , …, ( )
which are output states of flip flops 0, 1, …, n-1 respectively.
4.4.1.2.2Two bit asynchronous counter or 2-bit ripple counter

For designing 2-bit asynchronous counter (or 2-bit ripple counter or 2-bit
serial counter) 2 JK flip flops or 2 T flip flops are used.Preset and Clear inputs
(i.e. Pr and Cr inputs) of both flip flops are connected to logic 1 (or V CC) so that
4-26
both flip flops work properly. Following two figures show design of 2-bit
asynchronous counter using JK flip flop and using T flip flop respectively. While
implementing this counter using JK flip flop, J and K inputs of both flip flops
are connected to each other and then to logic 1 (or VCC).While implementing this
counter using T flip flop, T input of both flip flops is connected to logic 1 (or V CC).
So, flip flops work in toggle mode. External clock pulse is connected to flip flop
number 0 (i.e. first flip flop). Output of first flip flop (i.e. ) is connected to clock
input of flip flop number 1 (i.e. second flip flop).
Output of this counter is observed at (LSB) and (MSB) which are
output states of flip flop 0 and flip flop 1respectively.
4-27
Following timing diagram illustrates how the flip flops in the above
designs change their state along with the external clock pulse applied to flip flop
0. As the flip flops used are negative edge triggered, output changes on negative
edge of clock pulse.
Timing diagram
Following truth table shows the state transitions in the counter. It shows
how the counter counts from 0 (00) to 3 (11). After state 3 (11), counter again
switches to 0 (00). i.e. it repeatedly counts as 0, 1, 2, 3, 0, 1, and so on.
Truth Table
4.4.1.2.3Three bit asynchronous counter or 3-bit ripple counter

serial counter) 3 JK flip flops or 3 T flip flops are used. Preset and Clear inputs
(i.e. Pr and Cr inputs) of all the three flip flops are connected to logic 1 (or V CC)
so that these flip flops work properly. Following two figures show design of 3-bit
implementing this counter using JK flip flop, J and K inputs of all the three flip
flops are connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of all the three flip flops is
connected to logic 1 (or VCC). So, flip flops work in toggle mode. External clock
pulse is connected to flip flop number 0 (i.e. first flip flop). Output of first flip
flop (i.e. ) is connected to clock input of flip flop number 1 (i.e. second flip flop).
Output of second flip flop (i.e. ) is connected to clock input of flip flop number
2 (i.e. third flip flop).
Output of this counter is observed at (LSB), and (MSB) which are
output states of flip flop 0, flip flop 1 and flip flop 2 respectively.
Design using JK flip flop
4-28
Design using T flip flop
Timing diagram
how the counter counts from 0 (000) to 7 (111). After state 7 (111), counter again
switches to 0 (000). i.e. it repeatedly counts as 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, and so on.
Truth Table
4.4.1.2.4Four bit asynchronous counter or 4-bit ripple counter

serial counter) 4 JK flip flops or 4 T flip flops are used. Preset and Clear inputs
(i.e. Pr and Cr inputs) of all the four flip flops are connected to logic 1 (or V CC) so
that these flip flops work properly. Following two figures show design of 4-bit
implementing this counter using JK flip flop, J and K inputs of all the four flip
flops are connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of all the four flip flops is
connected to logic 1 (or VCC). So, flip flops work in toggle mode. External clock
Output of second flip flop (i.e. ) is connected to clock input of flip flop number
2 (i.e. third flip flop). Output of third flip flop (i.e. ) is connected to clock input
of flip flop number 3 (i.e. fourth flip flop).
Output of this counter is observed at (LSB), , and (MSB) which
are output states of flip flop 0, flip flop 1, flip flop 2 and flip flop 3 respectively.
Timing diagram
how the counter counts from 0 (0000) to 15 (1111). After state 15 (1111), counter
again switches to 0 (0000). i.e. it repeatedly counts as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15, 0, 1, and so on.
4-29
Truth Table
4.4.1.2.5Steps for designing mod-N counter

Mod-N counter can also be called as mod-N asynchronous counter or mod-
N ripple counter or mod-N serial counter. For designing a mod-N counter,
following steps are undertaken.
i. Number of flip flops (i.e. n) required for designing mod-N
counter can be selected as follows. Number of flip flops (i.e. n)
should be the smallest number, for which ≤ .
Example 1: For mod-5 counter
N=5
If n=1, 2n is 2. Here, N is not less than or equal to 2n.
If n=3, 2n is 8. Here, N is less than 2n.
 3 flip flops are required for designing mod-5 counter.

N=10

N=8
If n=3, 2n is 8. Here, N is equal to 2n.
3 flip flops are required for designing mod-8 counter.
ii. Preset inputs (i.e. Pr input) of all the n flip flops are connected to
logic 1 (or VCC).
iii. When JK flip flops are used, J and K input of all the n flip flops are
connected to each other and then to logic 1 (or VCC). When T flip flops
are used, T inputs of all the n flip flops are connected to logic 1 (or
VCC). Due to this, all the n flip flops always toggle their output state at
each trigger (i.e. output state of each flip flop gives the negation of
previous state on trigger).
iv. External clock pulse is connected to flip flop number 0 (i.e. first flip
flop). Output of first flip flop (i.e. ) is connected to clock input of flip
flop number 1 (i.e. second flip flop). Output of second flip flop (i.e. )
is connected to clock input of flip flop number 2 (i.e. third flip flop) and
so on.
v. Calculate binary equivalent of N. Respective output states for
which the bits in the binary equivalent are 1, are connected to
inputs of NAND gate. Output of this NAND gate is connected to
Clear inputs (Cr inputs) of all the flip flops. But if = , no
need of NAND gate as the counter is in its full form.
4-30
N = 6 = 110
1 1 0
Bit # 2 1 0
So outputs and are connected to inputs of NAND gate
and output of NAND gate is connected to Clear inputs (Cr inputs)
of all the 3 flip flops.

N = 11 = 1011
1 0 1 1
Bit # 3 2 1 0
So outputs , and are connected to inputs of NAND
gate and output of NAND gate is connected to Clear inputs (Cr
inputs) of all the 4 flip flops.

As = 2 , no need of NAND gate as the counter is in its full
form.
vi. Output of the counter is observed at (LSB), , …, ( ) which

are output states of flip flops 0, 1, …, n-1 respectively.
Some examples are discussed below. But scope of the topic is not limited
to only these counters. We should be able to design any mod-N counter by using
above steps.
4.4.1.2.6Mod-3 counter
It is also called mod-3 ripple counter, or mod-3 asynchronous counter or
mod 3 serial counter.
Here, N=3
So, 2 JK flip flops or 2 T flip flops are used. Preset input (i.e. Prinput) of
both the flip flops are connected to logic 1 (or VCC). Following two figures show
design of 2-bit asynchronous counter using JK flip flop and using T flip flop
respectively. While implementing this counter using JK flip flop, J and K inputs
of both the flip flops are connected to each other and then to logic 1 (or V CC).
While implementing this counter using T flip flop, T input of both the flip flops
is connected to logic 1 (or VCC). So, flip flops work in toggle mode. External clock
Binary equivalent of N = 3 is 11. So outputs and are connected to
inputs of NAND gate and output of NAND gate is connected to Clear inputs (Cr
inputs) of both flip flops. Due to this modification, 2-bit asynchronous counter is
converted into mod-3 counter.
Output of this counter is observed at (LSB) and (MSB) which are
output states of flip flop 0 and flip flop 1 respectively.
4-31
Timing diagram
how the counter counts from 0 (00) to 2 (01). After state 2 (01), counter is in
state 3 (i.e. 11). But as and are 1, output of NAND gate is 0 which
immediately clears both flip flops. So instead of state 3 (i.e. 11), we get state 0
(i.e. 00). So, counter repeatedly counts as 0, 1, 2, 0, 1, 2, 0and so on.
Truth Table
mod-5 serial counter.
Here, N=5
If n=2, 2n is 4. Here, is not less than or equal to 2n.
So, 3 JK flip flops or 3 T flip flops are used. Preset input (i.e. Pr input) of
all the three flip flops are connected to logic 1 (or VCC). Following two figures
show design of 3-bit asynchronous counter using JK flip flop and using T flip
flop respectively. While implementing this counter using JK flip flop, J and K
inputs of all the three flip flops are connected to each other and then to logic 1
(or VCC). While implementing this counter using T flip flop, T input of all the
three flip flops is connected to logic 1 (or VCC). So, flip flops work in toggle mode.
External clock pulse is connected to flip flop number 0 (i.e. first flip flop). Output
of first flip flop (i.e. ) is connected to clock input of flip flop number 1 (i.e.
second flip flop) and output of second flip flop (i.e. ) is connected to clock input
of flip flop number 2 (i.e. third flip flop).
inputs) of all the three flip flops. Due to this modification, 3-bit asynchronous
counter is converted into mod-5 counter.
Output of this counter is observed at (LSB), and (MSB) which
are output states of flip flop 0, flip flop 1 and flip flop 2 respectively.
4-32
Timing diagram
how the counter counts from 0 (000) to 4 (100). After state 4 (100), counter is in
state 5 (i.e. 101). But as and are 1, output of NAND gate is 0 which
immediately clears all the flip flops. So instead of state 5 (i.e. 101), we get 0 (i.e.
000). So, counter repeatedly counts as 0, 1, 2, 3, 4, 0, 1and so on.
Truth Table
mod-10 serial counter.
Here, N=10
So, 4 JK flip flops or 4 T flip flops are used. Preset input (i.e. Pr input) of
all the four flip flops are connected to logic 1 (or VCC). Following two figures
show design of 4-bit asynchronous counter using JK flip flop and using T flip
flop respectively. While implementing this counter using JK flip flop, J and K
inputs of all the four flip flops are connected to each other and then to logic 1 (or
VCC). While implementing this counter using T flip flop, T input of all the four
flip flops is connected to logic 1 (or VCC). So, flip flops work in toggle mode.
External clock pulse is connected to flip flop number 0 (i.e. first flip flop). Output
of first flip flop (i.e. ) is connected to clock input of flip flop number 1 (i.e.
second flip flop). Output of second flip flop (i.e. ) is connected to clock input of
flip flop number 2 (i.e. third flip flop) andoutput of third flip flop (i.e. ) is
connected to clock input of flip flop number 3 (i.e. fourth flip flop).
inputs) of all the four flip flops. Due to this modification, 4-bit asynchronous
counter is converted into mod-10 counter.
Output of this counter is observed at (LSB), , and (MSB) which
are output states of flip flop 0, flip flop 1, flip flop 2 and flip flop 3 respectively.
4-33
Timing diagram
how the counter counts from 0 (0000) to 9 (1001). After state 9 (1001), counter is
in state 10 (i.e. 1010). But as and are 1, output of NAND gate is 0 which
immediately clears all the flip flops. So instead of state 10 (i.e. 1010), we get 0
(i.e. 0000). So, counter repeatedly counts as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2 and
so on.
Truth Table
4.4.1.3Synchronous counter
Synchronous counter is also called as parallel counter. In this type of
counter, same clock pulse is applied all the flip flops. The counter is called
synchronous as the clock pulses of all the flip flops are same. i.e. all the flip flops
are synchronized. Due to this, all the flip flops change their states at the same
time in synchronization with the clock pulse. So these counters have low
propagation delay. Hence the operational frequency is high. Only drawback of
this type of counter is that it is difficult to design. Extra circuitry is required for
designing these counters.
4.4.1.3.1 Steps for designing synchronous counter

For designing a n-bit asynchronous counter, following steps are
undertaken.
i. It requires n number of flip flops. The flip flops used may be either JK
flip flop or T flip flop.
ii. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the n flip flops are
connected to logic 1 (or VCC) so that all the flip flops work properly.
iii. External clock pulse is connected commonly to all the n flip flops.
iv. When JK flip flops are used, J and K input of first flip flop (flip flop 0)
is connected to logic 1 (or VCC). When T flip flops are used, T input
offirst flip flop (flip flop 0) is connected to logic 1 (or VCC).
v. In case of UP counter, output of flip flop 0 (i.e. ) is connected to J
and K input of flip flop 1. Output of flip flop 1 (i.e. ) is connected to J
and K input of flip flop 2 and so on.
In case of DOWN counter, negated output of flip flop 0 (i.e. ) is
connected to J and K input of flip flop 1. Negated output of flip flop 1
(i.e. ) is connected to J and K input of flip flop 2 and so on.
vi. Output of the counter is observed at (LSB), , …, ( ) which
are output states of flip flops 0, 1, …, n-1 respectively.
5.4.1.3.2 Two bit synchronous counter

For designing 2-bit synchronous counter 2 JK flip flops or 2 T flip flops
are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of both flip flops are
connected to logic 1 (or VCC) so thatboth the flip flops work properly.External
clock pulse is connected commonly to both the flip flops. Following two figures
show design of 2-bit synchronous counter using JK flip flop and using T flip flop
respectively. While implementing this counter using JK flip flop, J and K
inputof first flip flop is connected to each other and then to logic 1 (or VCC).
4-34
While implementing this counter using T flip flop, T input of first flip flops is
connected to logic 1 (or VCC).In case of UP counter, output of flip flop 0 (i.e. ) is
connected to J and K input of flip flop 1 (in case of T flip flop implementation,
is connected to T input of flip flop 1). Output of the counter is observed at
(LSB) and (MSB) which are output states of flip flops 0 and 1respectively.
designs change their state along with the external clock pulse applied to them.
As the flip flops used are negative edge triggered, output changes on negative
Timing diagram
how the counter counts from 0 (00) to 3 (11). So, counter repeatedly counts as 0,
1, 2, 3, 0, 1, 2 and so on.
Truth Table
5.4.1.3.3 Two bit DOWN counter

It is a 2-bit synchronous DOWN counter. For designing 2-bit synchronous
DOWN counter 2 JK flip flops or 2 T flip flops are used. Preset and Clear inputs
(i.e. Pr and Cr inputs) of both flip flops are connected to logic 1 (or V CC) so that
both the flip flops work properly.External clock pulse is connected commonly to
both the flip flops. Following two figures show design of 2-bit synchronous
DOWN counter using JK flip flop and using T flip flop respectively. While
implementing this counter using JK flip flop, J and K input of first flip flop is
connected to each other and then to logic 1 (or VCC). While implementing this
counter using T flip flop, T input of first flip flop is connected to logic 1 (or VCC).
As it is DOWN counter, negated output of flip flop 0 (i.e. ) is connected to J
and K input of flip flop 1 (in case of T flip flop implementation, is connected
to T input of flip flop 1). Output of the counter is observed at (LSB) and
(MSB) which are output states of flip flops 0 and 1respectively.
Timing diagram
4-35
how the counter counts from 3 (11) to 0 (00). So, counter repeatedly counts as 3,
2, 1, 0, 3, 2 and so on.
Truth Table
5.4.1.3.4 Three bit synchronous counter

are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the three flip flops
are connected to logic 1 (or VCC) so that all the flip flops work properly.External
clock pulse is connected commonly to all the flip flops. Following two figures
respectively. While implementing this counter using JK flip flop, J and K input
of first flip flop is connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of first flip flops is
connected to logic 1 (or VCC). In case of UP counter, output of flip flop 0 (i.e. )
is connected to J and K input of flip flop 1 (in case of T flip flop implementation,
is connected to T input of flip flop 1). Output of flip flop 0 (i.e. ) and output
of flip flop 1 (i.e. ) are connected to AND gate whose output is connected to J
and K input of flip flop 2 (in case of T flip flop implementation, output of flip flop
0 (i.e. ) and output of flip flop 1 (i.e. ) are connected to AND gate whose
output is connected to T input of flip flop 2).Output of the counter is observed at
(LSB), and (MSB) which are output states of flip flops 0, 1
and2respectively.
Timing diagram
how the counter counts from 7 (111) to 0 (000). So, counter repeatedly counts as
7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4and so on.
Truth Table
5.4.1.3.5 Three bit DOWN counter

(i.e. Pr and Cr inputs) of all the three flip flops are connected to logic 1 (or V CC)
so that all the flip flops work properly.External clock pulse is connected
commonly to both the flip flops. Following two figures show design of 3-bit
synchronous DOWN counter using JK flip flop and using T flip flop respectively.
While implementing this counter using JK flip flop, J and K input of first flip
4-36
flop is connected to each other and then to logic 1 (or VCC). While implementing
this counter using T flip flop, T input of first flip flop is connected to logic 1 (or
VCC). As it is DOWN counter, negated output of flip flop 0 (i.e. ) is connected to
J and K input of flip flop 1 (in case of T flip flop implementation, is connected
to T input of flip flop 1). Negated output of flip flop 0 (i.e. ) and negated output
and K input of flip flop 2 (in case of T flip flop implementation, negated output of
flip flop 0 (i.e. ) and negated output of flip flop 1 (i.e. ) are connected to AND
gate whose output is connected to T input of flip flop 2).Output of the counter is
observed at (LSB), and (MSB) which are output states of flip flops 0, 1
and2 respectively.
Timing diagram
how the counter counts from 7 (111) to 0 (000). So, counter repeatedly counts as
7, 6, 5, 4, 3, 2, 1, 0, 7, 6 and so on.
Truth Table
5.4.1.3.6 Four bit synchronous counter

are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the four flip flops
are connected to logic 1 (or VCC) so that all the flip flops work properly.External
clock pulse is connected commonly to all the flip flops. Following two figures
respectively. While implementing this counter using JK flip flop, J and K input
of first flip flop is connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of first flip flops is
connected to logic 1 (or VCC). In case of UP counter, output of flip flop 0 (i.e. )
is connected to J and K input of flip flop 1 (in case of T flip flop implementation,
is connected to T input of flip flop 1). Output of flip flop 0 (i.e. ) and output
and K input of flip flop 2 (in case of T flip flop implementation, output of flip flop
0 (i.e. ) and output of flip flop 1 (i.e. ) are connected to AND gate whose
output is connected to T input of flip flop 2).Output of flip flop 0 (i.e. ), output
of flip flop 1 (i.e. ) and output of flip flop 2 (i.e. ) are connected to AND gate
whose output is connected to J and K input of flip flop 3 (in case of T flip flop
implementation, output of flip flop 0 (i.e. ), output of flip flop 1 (i.e. ) and
output of flip flop 2 (i.e. ) are connected to AND gate whose output is
4-37
connected to T input of flip flop 3).Output of the counter is observed at (LSB),
, and (MSB) which are output states of flip flops 0, 1, 2 and3respectively.
Timing diagram
how the counter counts from 15 (1111) to 0 (0000). So, counter repeatedly counts
as 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14and so on.
Truth Table
5.4.1.3.7 Four bit DOWN counter

(i.e. Pr and Cr inputs) of all the four flip flops are connected to logic 1 (or V CC) so
that all the flip flops work properly.External clock pulse is connected commonly
to both the flip flops. Following two figures show design of 4-bit synchronous
DOWN counter using JK flip flop and using T flip flop respectively. While
implementing this counter using JK flip flop, J and K input of first flip flop is
connected to each other and then to logic 1 (or VCC). While implementing this
counter using T flip flop, T input of first flip flopis connected to logic 1 (or V CC).
As it is DOWN counter, negated output of flip flop 0 (i.e. ) is connected to J
and K input of flip flop 1 (in case of T flip flop implementation, is connected
to T input of flip flop 1). Negated output of flip flop 0 (i.e. ) and negated output
and K input of flip flop 2 (in case of T flip flop implementation, negated output of
flip flop 0 (i.e. ) and negated output of flip flop 1 (i.e. ) are connected to AND
gate whose output is connected to T input of flip flop 2). Negated output of flip
flop 0 (i.e. ), negated output of flip flop 1 (i.e. ) and negated output of flip
flop 2 (i.e. ) are connected to AND gate whose output is connected to J and K
input of flip flop 3 (in case of T flip flop implementation, negated output of flip
flop 0 (i.e. ), negated output of flip flop 1 (i.e. ) and negated output of flip
flop 2 (i.e. ) are connected to AND gate whose output is connected to T input of
flip flop 3).Output of the counter is observed at (LSB), , and (MSB)
which are output states of flip flops 0, 1, 2 and3respectively.
4-38
Timing diagram
how the counter counts from 15 (1111) to 0 (0000). So, counter repeatedly counts
as 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14 and so on.
Truth Table
Questions:
1. State two applications of counters. [2M]
2. List any four applications of counters. [2M]
3. Define counter and modulus of counter. [2M]
4. Explain ‘modulus of a counter’ with example. [2M]
5. What is modulus of a counter? [2M]
6. Draw logical circuit diagram of a 3 bit asynchronous counter and explain.
[4M]
7. Explain 4-bit asynchronous counter with circuit diagram and timing
diagram. [4M]
8. Design a 3-bit asynchronous counter. Draw its truth table. [4M]
9. How many flip flops are required to construct the following modulus
counter? Why? [4M]
i) -5 ii) 83 iii) 99 iv) 10
Tip: As counter is used for counting and counting is not done in negative
numbers, counter cannot count up to -5. So instead of -5 consider 5.
10. What is modulus of counter? Design a mod-3 ripple counter using a 2-bit
ripple counter. [4M]
Tip; For mod-3 ripple counter, N=3.  n=2. i.e. 2 flip flops are used. So, it
will be similar to 2-bit asynchronous counter with little modifications
(NAND gate, Clear inputs etc.)
11. Design mod-5 asynchronous counter. [4M]
12. Design a mod-5 ripple counter. [4M]
13. Design mod-6 asynchronous counter. [4M]
14. Design asynchronous mod-6 counter with its truth table. [4M]
15. Design mod-10 asynchronous counter with suitable flip-flop. [4M]
16. Design a mod-11 asynchronous counter giving the steps of design. [4M]
17. Draw mod-11 asynchronous counter using T flip flop. [4M]
18. List steps to design a ‘n’ bit synchronous up counter. [4M]
19. Explain 3-bit synchronous counter. [4M]
20. Explain 3-bit synchronous counter with logical circuit diagram and timing
diagram. [4M]
21. Explain working of 3-bit synchronous counter with circuit diagram. [4M]
22. Explain 3-bit synchronous counter with truth table and timing diagram.
[4M]
23. Design 3-bit synchronous up counter. [4M]
4-39
24. Draw mod 8 synchronous counter with timing diagram of truth table. [4M]
25. Compare between synchronous and asynchronous counter (4 points). [4M]
4.4.2Registers
Register is a sequential logic circuit. It is also cascaded arrangement of
more than one flip flop with or without some combinational logic devices. It is
also called as Shift Register. As seen before, a single flip flop is 1-bit memory
cell. So, a single flip flop is also called as 1-bit register.It is basically used for
storing and/or transferring digital information. Applications of registers or shift
registers are
- Delay Line.
- Serial to Parallel Converter.
- Parallel to Serial Converter.
- Ring Counter.
- Twisted Ring Counter.
- Sequence Generator.
- Sequence Detector.
For designing counters either JK flip flops or D flip flops are used. While
using JK flip flops, J input is connected to K input through a NOT gate. (i.e. JK
flip flop is to be used as D flip flop).
Data can be entered or retrieved in serial or in parallel to or from a shift
register. Depending on the way how data is entered and retrieved, shift
registers can be classified as
- Serial In Serial Out (SISO) Shift Register
- Serial In Parallel Out (SIPO) Shift Register
- Parallel in Parallel Out (PIPO) Shift Register
- Parallel in Serial Out (PISO) Shift Register
Block diagrams of n-bit shift registers of all the above types are shown
below.
Block diagram of SISO
Block diagram of SIPO
Block diagram of PIPO
Block diagram of PISO
4.4.2.1Important design/ implementation issues for registers

While designing or implementing registers or shift registers, following
issues are important.
1. Number of flip flops used
For n-bit register or n-bit shift register, n flip flops are used.
If N is to be stored in a register (or shift register), then n flip flops

are required. Here value of n is selected in such a way that n should be
the smallest number, for which ≤ .
Example 1: For storing 35
4-40
N=35
6 flip flops are required for designing a register which can
store 35.
Example 2: For storing decimal 24

N=24
store decimal 24.
Example 3: For storing hexadecimal C

N=(C)16=(12)10=12
store hexadecimal C.
Example 4: For storing octal 37

N=(37)8=(31)10=31
store octal 37.
Example 5: For storing 32

N=32
If n=5, 2n is 32. Here, N is equal to 2n.
store 32.
2. Sequencing of flip flops

4-41
In the cascaded arrangement of flip flops, the flip flops are
numbered as A, B, C and so on. i.e. first flip is numbered as A, second flip
flop is numbered as B and so on. Serial input is provided at input of flip
flop A. In the truth table the columns of output are numbered as , ,
and so on. Here is considered as MSB and the last output state is
considered as LSB. (This is a major difference from counter
implementation)
3. Types of flip flops used

Either JK flip flops or D flip flops are used for implementing
registers or shift registers. In both the implementations, Preset and Clear
inputs (i.e. Pr and Cr inputs) of all the flip flops are connected to logic 1
(i.e. VCC) so that all the flip flops will work normally.
4. JK flip flop implementation

When JK flip flops are used for implementation, serial input is
provided at J input of flip flop A(i.e. ). J input of flip flop A is connected
to K input of flip flop A (i.e. ) through a NOT gate. (i.e. JK flip flop is to
be used as D flip flop). Then output of flip flop A (i.e. ) is connected to J
input of flip flop B (i.e. ) and negated output of flip flop A (i.e. ) is
connected to K input of flip flop B (i.e. ). This is equivalent to
connecting J to K through a NOT gate. Similar connections are made for
further flip flops.
5. D flip flop implementation

When D flip flops are used for implementation, serial input is
provided at D input of flip flop A (i.e. ). Then output of flip flop A (i.e.
) is connected to D input of flip flop B (i.e. ). Similar connections are
made for further flip flops.
4.4.2.2Four bit Serial In Serial Out (SISO) Shift Register

For designing or implementing 4-bit SISO shift register, either 4 JK flip
flops or 4 D flip flops are used. Both these implementations are shown below.
The flip flops are numbered as A, B, C and D. In both the implementations,
Preset and Clear inputs (i.e. Pr and Cr inputs) of all the four flip flops are
connected to logic 1 (i.e. VCC) so that all the flip flops will work normally. A
common clock pulse is applied to all the flip flops.
In implementation using JK flip flop, Serial Input(Xi) is provided at J
input of flip flop A (i.e. ). J input of flip flop A is connected to K input of flip
flop A (i.e. ) through a NOT gate. (i.e. JK flip flop is to be used as D flip flop).
Then output of flip flop A (i.e. ) is connected to J input of flip flop B (i.e. )
and negated output of flip flop A (i.e. ) is connected to K input of flip flop B
(i.e. ).Output of flip flop B (i.e. ) is connected to J input of flip flop C (i.e. )
and negated output of flip flop B (i.e. ) is connected to K input of flip flop C
(i.e. ). Output of flip flop C (i.e. ) is connected to J input of flip flop D (i.e. )
and negated output of flip flop C (i.e. ) is connected to K input of flip flop D
(i.e. ).
In implementation using D flip flop, Serial Input(Xi) is provided at D
input of flip flop A (i.e. ). Then output of flip flop A (i.e. ) is connected to D
input of flip flop B (i.e. ). Output of flip flop B (i.e. ) is connected to D input
4-42
of flip flop C (i.e. ). Output of flip flop C (i.e. ) is connected to D input of flip
flop D (i.e. ).
Serial Output(Y) is observed at .
Design using D flip flop
Following truth table shows the state transitions in the register for
sample input sequence 10110. It shows how the flip flops change their states on
each clock pulse.
Truth Table
designs change their state along with the external clock pulse applied to them
for the above sample input sequence.
Timing diagram
4.4.2.3Four bit Serial In Parallel Out (SIPO) Shift Register

For designing or implementing 4-bit SIPO shift register, either 4 JK flip
In implementation using JK flip flop, Serial Input (Xi) is provided at J
input of flip flop A (i.e. ). J input of flip flop A is connected to K input of flip
flop A (i.e. ) through a NOT gate. (i.e. JK flip flop is to be used as D flip flop).
Then output of flip flop A (i.e. ) is connected to J input of flip flop B (i.e. )
and negated output of flip flop A (i.e. ) is connected to K input of flip flop B
(i.e. ). Output of flip flop B (i.e. ) is connected to J input of flip flop C (i.e. )
(i.e. ).
In implementation using D flip flop, Serial Input (Xi) is provided at D
input of flip flop A (i.e. ). Then output of flip flop A (i.e. ) is connected to D
input of flip flop B (i.e. ). Output of flip flop B (i.e. ) is connected to D input
of flip flop C (i.e. ). Output of flip flop C (i.e. ) is connected to D input of flip
flop D (i.e. ).
Parallel Output is observed at output states of all the four flip flops i.e.
, , and .
4-43
each clock pulse.
Truth Table
Timing diagram
4.4.2.4Four bit Parallel In Parallel Out (PIPO) Shift Register

For designing or implementing 4-bit PIPO shift register, either 4 JK flip
In implementation using JK flip flop, J input of flip flop A is connected to
K input of flip flop A (i.e. ) through a NOT gate. (i.e. JK flip flop is to be used
as D flip flop). Then output of flip flop A (i.e. ) is connected to J input of flip
flop B (i.e. ) and negated output of flip flop A (i.e. ) is connected to K input of
flip flop B (i.e. ). Output of flip flop B (i.e. ) is connected to J input of flip
flop C (i.e. ) and negated output of flip flop B (i.e. ) is connected to K input of
flip flop C (i.e. ). Output of flip flop C (i.e. ) is connected to J input of flip
flop D (i.e. ) and negated output of flip flop C (i.e. ) is connected to K input of
flip flop D (i.e. ).
In implementation using D flip flop, output of flip flop A (i.e. ) is
connected to D input of flip flop B (i.e. ). Output of flip flop B (i.e. ) is
connected to D input of flip flop C (i.e. ). Output of flip flop C (i.e. ) is
connected to D input of flip flop D (i.e. ).
Parallel Input is provided at all the J inputs (or D inputs) of all the four
flip flops i.e. , , and (or , , and ).
Parallel Output is observed at output states of all the four flip flops i.e.
, , and .
each clock pulse.
Truth Table
4-44
Timing diagram
4.4.2.5Four bit Parallel In Serial Out (PISO) Shift Register

For designing or implementing 4-bit PISO shift register, either 4 JK flip
There is no separate design for Parallel in Serial Out (PISO) shift
register. Rather, this operation can be utilized from the design of universal shift
register. Universal Shift Register is a shift register that can operate in any of
the four typeswhich are SISO, SIPO, PIPO and PISO.
Here, inputs to the flip flops are provided differently. An extra input
SHIFT/LOAD is used. When this input is 1, SHIFT operations takes place. i.e.
Input is given serially. When this input is 0, LOAD operation takes place. i.e.
Input is given in parallel.
In implementation using JK flip flop, J inputs of all the flip flopsare
connected to K inputs of the same flip flops through a NOT gates. (i.e. JK flip
flops are to be used as D flip flops).
J inputs (or D inputs) are driven by output of OR gates. These OR gates
are driven by outputs of two AND gates. For each first AND gate, one input is
taken from SHIFT/LOADinput and the other input is taken from output of
previous flip flop. In case of first flip flop this other input is taken from Serial
Input. For each second AND gate, one input is taken from SHIFT/LOAD input
through NOT gate and the other input is taken fromParallel Inputs , ,
and (or , , and ).
Serial Output may be observed at output of flip flop D. Parallel Output
may be observed at output of flip flops A,B, C and D (i.e.).
Then output of flip flop A (i.e. ) is connected to J input of flip flop B (i.e.
) and negated output of flip flop A (i.e. ) is connected to K input of flip flop B
(i.e. ). Output of flip flop B (i.e. ) is connected to J input of flip flop C (i.e. )
(i.e. ).
In implementation using D flip flop, output of flip flop A (i.e. ) is
connected to D input of flip flop B (i.e. ). Output of flip flop B (i.e. ) is
connected to D input of flip flop C (i.e. ). Output of flip flop C (i.e. ) is
connected to D input of flip flop D (i.e. ).
Parallel Input is provided at all the J inputs (or D inputs) of all the four
flip flops i.e. , , and (or , , and ).
Parallel Output is observed at output states of all the four flip flops
i.e. , , and .

4-45
4.4.2.6Universal Shift Register
As already discussed in 4.4.2.5, Universal Shift Register is a shift
register that can operate universally. It can take serial as well as parallel input.
Alos it can generate serial as well as parallel output. So, it can operate in any of
the four types which are Serial In Serial Out, Serial In Parallel Out, Parallel In
Parallel Out and Parallel In Serial Out.
Design or implementation of universal shift register using JK flip flop as
well as D flip flop is already shown in 4.4.2.5.
IC 7495 can be used as universal shift register.Pin diagram of this 14-pin
IC is shown in following figure. Pin 1 is used for serial input and pin numbers 2,
3, 4 and 5 are used for parallel input. Parallel output can be taken from pin
numbers 13, 12, 11 and 10. Pin 10 (as it is output of last flip flop. i.e. ) is used
for serial output. Pin 6 is used for selecting Mode of operation of the IC. Pin
number 9 (CLK1) is used for providing clock for normal right shift operation and
pin 8 (CLK1) is used for left-shift (or LOAD operation. i.e. parallel input). Pin
number 7 and 14 are used for providing ground and VCC respectively.
4.4.2.7Ring Counter
It is also called as Circulating Register. It is one of the application of
shift register. It shifts a bit within the flip flops continuously.A ring counter is
obtained from a shift register by directly feeding back the output of the last flip-
flop to the J input (or D input) of the first flip-flop.
Ring counter can be implemented using JK flip flops as well as D flip
flops. These implementations are shown in following figuresrespectively.In J-K
flip-flop implementation, outputs of the last flip-flop (i.e. and ) are
respectively fed back to the J and Kinputs of the first flip-flop (i.e. and ).In
D flip-flop implementation, output of the last flip-flop (i.e. ) is fed back to the
D input of the first flip-flop (i.e. ).
Assuming that flip flop A is initially set to 1 and remaining flip flops are
set to 0, initial output of the ring counter will be 1000.With the first clock pulse,
this ‘1’ gets shifted to the second flip-flop output and the counter output becomes
0100. Similarly, with the second and thirdclock pulses, the counter output will
become 0010 and 0001. With the fourth clock pulse, the counteroutput will again
become 1000. The count cycle repeats in the subsequent clock pulses.
Truth table for this sample is shown below.
Truth table
Timing diagram for the same sample is shown below.
Timing Diagram
4.4.2.8Twisted Ring Counter
4-46
It is also called as Johnson Counter. It is one of the application of shift
register. A twisted ring counter is obtained from a shift register by directly
feeding back the negated output of the last flip-flop to the J input (or D input) of
the first flip-flop and output of the last flip flop to K input of the first flip flop.
Twisted ring counter can be implemented using JK flip flops as well as D
flip flops. These implementations are shown in following figures respectively. In
J-K flip-flop implementation, outputs of the last flip-flop (i.e. and ) are
respectively fed back to the K and Jinputs of the first flip-flop (i.e. and ).(i.e.
is fed back to and is fed back to .In D flip-flop implementation,
negated output of the last flip-flop (i.e. ) is fed back to the D input of the first
flip-flop (i.e. ).
Assuming that all the flip flopsare initially reset to 0, initial output of the
ring counter will be 0000. With the first clock pulse, output becomes 1000.
Similarly, with the second, thirdand fourth clock pulses, the counter output will
become 1100, 1110 and 1111. With the fifth clock pulse, the counteroutput will
again become 0111. Then on consecutive clock pulses output will be 0011, 0001,
0000, 1000 and so on.
Truth table for this sample is shown below.
Truth table
Timing diagram for the same sample is shown below.
Timing Diagram
Questions:
1. Compare counters and shift registers. [4M]
2. Give applications of shift register. [4M]
3. List different types of shift registers. [2M]
4. List different types of shift registers and draw 4-bit SISO shift register.
[4M]
5. Draw logical circuit diagram of 4-bit serial in serial out shift register.
Explain with truth table. [4M]
6. Draw and explain SISO with truth table and timing diagram. [4M][
7. Draw block diagram of SISO (Right shift mode) shift register with its
truth table and logic diagram. [4M]
8. Explain the function of 3-bit SISO with waveforms and block diagram.
[4M]
9. Draw and explain working of 4-bit SIPO shift register with truth table.
[4M]
10. Draw diagram of Serial In Parallel Out (SIPO) shift register. Also draw
timing diagram. [4M]
11. Explain 4-bit SIPO shift register with the help of block diagram, truth
table and timing diagrams. [4M]
12. Draw and describe universal shift register. [4M]
4-47
13. Draw pin diagram of universal shift register IC 7495. [2M]
14. Draw pin diagram of universal shift register IC 7495. List any two
applications of shift register. [4M]
15. Study given figure. Initial output condition is QA QB Qc = 010. Write
truth table of output QA QB Qc for 4 clock pulses. [4M]
P P P
D D D
Clk Clk Clk
C C C
Cloc
k
16. With the help of block diagram explain working of ring counter. [4M]
17. How many flip flops are required to build a shift register to store following
number. [4M]
i) Decimal 28 ii) Binary 6 bits iii) Octal 17 iv) Hexadecimal A
4.5 Memories
Semiconductor memories can be classified on the basis of various factors

as.
- Based on principle of operation
- Based on accessing method
- Based on fabrication technology
4.5.1 Classification based on principle of operation

On the basis of principle of operation, semiconductor memories can be
classified as
- Read Only Memory (ROM)
- Random Access Memory (RAM)
4.5.1.1 Read Only Memory (ROM)

In this type of semiconductor memory, data can be only read from the
memory. So, data is written in ROM at the time of manufacturing only. But,
data can be read any number of times from ROM. ROM is non-volatile memory.
i.e. Contents of ROM don’t get vanished even after power given to the computer
is switched off.
Major use of ROM is to store BIOS information and bootstrap program.
ROM can be further classified as

- Programmable Read Only Memory (PROM)
In this type of ROM, data can be written in the memory only once
after manufacturing it. For this PROM Programmer is required.
- Erasable Programmable Read Only Memory (EPROM)
In this type of ROM, data written in it can be erased with the help
4-48
of ultra-violet (UV) rays. As data can be erased at any number of times,
this type of ROM can be programmed (data can be written) at multiple
times.
- Electrically Erasable Programmable Read Only Memory (EEPROM)
As erasing data from EPROM requires UV rays, it becomes
cumbersome task. So, in this type of ROM, data can be erased electrically.
It is also called as E2PROM.
4.5.1.2 Random Access Memory (RAM)

In this type of semiconductor memory, data can be read from the memory
as well as written into the memory. As data can be read or written randomly, it
is called as Random Access Memory. RAM is volatile memory. i.e. Contents of
RAM get vanished when power given to the computer is switched off.
RAM is used as main memory of computer system. It is generally used for
storing data, program instructions and intermediate data during execution of
program. Data can be read or written any number of times.
Depending on type of memory cell used, RAM can be further classified as

- Static Random Access Memory (Static RAM)
- Dynamic Random Access Memory (Dynamic RAM)
4.5.1.2.1 Static RAM

Basic element used in static RAM (also referred as SRAM) is a latch
memory cell. Latch memory cell holds its contents as long as power is provided
to it. So, contents of SRAM don’t get lost until power given to the computer is
not switched off.
Speed of operation of SRAM is more as compared to dynamic RAM. But
Memory capacity of SRAM is less as compared to dynamic RAM.
4.5.1.2.2 Dynamic RAM

Basic element used in dynamic RAM (also referred as DRAM) is a
capacitor and MOSFET. Capacitor stores the contents as charge. But as
capacitor may get discharged contents of DRAM may get lost even if power
given to the computer is not switched off. So, refreshing of memory is required
at regular intervals (after every 5-10 ms) even if power is connected to the
computer. For this, additional refreshing circuit is required which is major
disadvantage of DRAM.
Most important advantage of this memory is its high density. i.e. More
number of bits. So, cost per bit is less. So, memory capacity of DRAM is more as
compared to SRAM whereas cost is less for DRAM as compared to SRAM.
Speed of operation of DRAM is less as compared to SRAM.
4.5.2 Classification based on accessing method

On the basis of accessing method, semiconductor memories can be
classified as
- Sequential Access Memory
In this type of memory, memory is accessed (read/written)
sequentially. e.g. Fifth byte cannot be accessed directly. For accessing
4-49
fifth byte one has to go sequentially as 1st, 2nd, 3rd, 4th and then only 5th
byte can be accessed.
So, in general speed of operation is very less.
- Random Access Memory
In this type of memory, memory can be accessed (read/written)
randomly. i.e. Any byte can be accessed at any time regardless of its
position.
So, in general speed of operation is high.
4.5.3 Classification based on fabrication technology

On the basis of fabrication technology, semiconductor memories can be
classified as
- Bipolar Memory
In this type of memory, memory is fabricated using bipolar
components like transistors.
- Unipolar Memory
In this type of memory, memory is fabricated using unipolar
components like MOSFETs.
Questions:
1. Give classification of different types of semiconductor memories. [2M]
2. Classify memories. Give function of each type. [4M]
3. Describe how memories can be classified. [4M]
4. State how memories can be classified on the basis of principle of operation.
[4M]
5. Give classification of different types of ROM memory. [4M]
6. Give classification of different types of semiconductor memories based on
fabrication technology. [2M]
7. Classify memories and explain ROM. [4M]
8. Compare ROM and RAM (4 points). [2M], [4M]
9. Differentiate between ROM and RAM. [4M]
10. Compare static RAM and dynamic RAM. [4M]
11. Differentiate between static and dynamic RAM. (any four points) [4M]
12. Write advantages and disadvantages of dynamic RAM. [4M]
13. State advantages and disadvantages of static RAM. [4M]
14. Give four features of dynamic RAM. [4M]
15. Explain EPROM. [4M]
16. State advantages and disadvantages of EPROM. [4M]
17. Distinguish between ROM, PROM, EPROM and EEPROM. [4M]
4-50
Chapter 5
A-D and D-A Converters
(No mathematical derivations)
04 Hours
08 Marks
When digital devices are to be interfaced with analog devices (or vice a
versa), Digital to Analog converter and Analog to Digital converter play
important role.
Questions:
Give necessity of data converter. [2M]
5.1 Digital to Analog Converters (D-A Converter/ DAC)
A digital to analog converter (DAC) takes digital data as its input and
converts it into analog voltage or current that is proportional to the weighted
sum of digital inputs. Input to a DAC is N-bit binary signal in parallel form. The
analog output voltage V0 of an N-bit DAC is generally calculated as,
= (2 +2 + ⋯+2 +2 + )
Where, K is a proportionality factor and bn is nth bit of digital input
(whose value can be either 0 or 1).
5.1.1 D to A Converter Specifications

Major performance specifications of digital to analog converters are
specified below.
- Resolution
- Accuracy
- Conversion speed or Setting (or settling) time
- Dynamic range
- Linearity
- Nonlinearity and Differential nonlinearity
- Monotonocity
- Temperature Sensitivity
5.1.1.1 Resolution
Resolution of a digital to analog converter is number of states (2n) into
which the full scale range is divided or resolved. Here ‘n’ is number of bits in the
input digital word. Higher the number of bits, better the resolution.
8-bit DAC has 255 (i.e. 2n – 1) resolvable levels. It has 8-bit resolution.
5.1.1.2 Accuracy
Accuracy of a digital to analog converter is the difference between actual
analog output and expected ideal output when a digital input is given.
Various sources of errors that may affect accuracy are gain errors, offset
errors and nonlinearity errors.
5-1
5.1.1.3 Conversion speed or Setting (or settling) time
Conversion speed of a digital to analog converter is expressed in terms of
its setting time. Setting time is the time period that has elapsed for analog
output to reach its final value after change in digital input has occurred.
General purpose digital to analog converters have setting time in the
range of microseconds whereas some high-speed DACs have setting time in the
range of nanoseconds.
5.1.1.4 Dynamic range

Dynamic range of a digital to analog converter is ratio of the largest
output to the smallest output (excluding zero). It is expressed in dB.
5.1.1.5 Linearity
In DAC, equal increment in digital input should result in equal increment
in the analog output voltage. Linearity of DAC is a measure of the precision
with which linear input output relationship is satisfied.
5.1.1.6 Nonlinearity and Differential nonlinearity

Nonlinearity of a digital to analog converter is maximum deviation of
analog output voltage from a straight line drawn between end-points in terms of
LSBs.
Differential nonlinearity is the worst-case deviation of any adjacent
analog outputs from the ideal one-LSB step size.
5.1.1.7 Monotonocity
In ideal digital to analog converter, analog output should increase by
identical step size for every one LSB increase in digital input. In such case DAC
is said to be having perfect monotonocity.
5.1.1.8 Temperature Sensitivity

Analog output voltage for any fixed digital input varies with temperature.
This is called as temperature sensitivity. This is due to temperature sensitivity
of voltage source, resistors, OP-AMPs and other components.
Questions:
1. State DAC specifications (any four). [4M]
2. State 2 specifications of DAC. [2M]
3. Define specifications of DAC (Any 4). [4M]
4. Define resolution and accuracy with respect to D-A converter. [4M]
5. What are important specifications of DAC (Write any 4). [4M]
6. Define following with respect to DAC. [2M]
i) Resolution ii) Setting time
5.1.2 Types of Digital to Analog Converters

There are various types of digital to analog converts. Two of them are
discussed below. They are,
- Weighted resistor DAC
- R-2R ladder DAC
5-2
5.1.2.1 Weighted resistor DAC
For an N-bit digital input, N resistors are used in a resistor network
which produces current values according to the bit values. Current is produced
for a bit only if its value is 1. For MSB (i.e. N-1th bit) current I is produced. For
N-2th bit, current I/2 is produced. For N-3th bit, current I/22 is produced and so
on. For getting these current values weighted resistors are used. For bit N-1,
resistor value R is used. For bit N-2, resistor value 2R is used. For bit N-3,
resistor value 22R is used and so on.
The sum of all the produced currents is converted to corresponding
voltage by using an OP-AMP.
As shown in the circuit diagram, digital inputs operate the switches
corresponding to bits.
Figure
Advantages:
1. Simple to design
2. Less number of resistors are required as compared to R-2R Ladder
DAC (almost half).
Disadvantages:
1. Wider range of resistors is to be used.
2. Such wide range of resistors are difficult fabricate in monolithic ICs.
Questions:
1. Explain weighted resistor DAC. [4M]
2. Draw circuit diagram of weighted resistor type D-A converter and explain
its working. [4M]
3. Draw circuit diagram of weighted register method of D-A converter and
explain in brief. [4M]
5.1.2.2 R-2R ladder DAC

Instead of using wide range of resistor values, this type of DAC uses only
two resistor values. They are R and 2R. Input is applied to resistor network
through digitally controlled switches.
Figure
Advantages:
1. Only 2 resistor values (i.e. R & 2R) are used.
2. So fabrication becomes easy.
Disadvantages:
1. More number of resistors (almost double) is required as compared to
weighted-resistor DAC.
Questions:
1. List advantages of R-2R ladder type DAC over binary weighted DAC. [4M]
2. With suitable circuit diagram explain the working of R-2R ladder DAC.
Give the output expression. [4M]
5-3
3. Sketch R-2R ladder DAC and describe its working. [4M]
5.1.3 Applications Digital to Analog Converters

There are various applications of digital to analog converters. Some of
them are,
- As a multiplier
- As a divider
- Programmable Integrator
- Low frequency function generator
5.1.4 ICs available as Digital to Analog Converters

- DAC 80 series
5.2 Analog to Digital Converters (A-D Converter/ ADC)
A analog to digital converter (ADC) takes analog voltage as its input and
converts it into N-bit digital output.
In DAC input range is fixed (e.g. for 4-bit DAC only 16 different values of
input are possible). But in ADC, input analog voltage can have any value.
Whereas, for N-bit ADC the digital output can have only 2N discrete values.
Therefore, the whole range of input analog voltage is required to be represented
2N intervals. This process of dividing input voltage range in specific number of
intervals (2N here) is called quantization. For each such interval, unique N-bit
binary code is assigned. This process of assigning unique N-bit binary code to
each interval is called encoding.
5.2.1 A to D Converter Specifications

Major performance specifications of analog to digital converters are
specified below.
- Resolution
- Accuracy
- Gain and offset errors
- Sampling frequency
- Quantization error
- Nonlinearity and Differential nonlinearity
- Conversion time
5.1.1.1 Resolution
Resolution of analog to digital converter is amount of input analog voltage
that needs to be increased for getting increment of digital output to the next
higher binary code.
8-bit ADC can be said to have 8-bit resolution.
5.1.1.2 Accuracy
Accuracy specification of analog to digital converter describes sum of all
errors. Various errors include gain error, offset error and quantization error.
5-4
5.1.1.3 Gain and offset errors
Gain error is difference between actual full-scale transition voltage and
ideal full-scale transition voltage.
Offset error is error at analog zero for A/D converter operating in bipolar
mode.
5.1.1.4 Sampling frequency

As per Shannon-Nyquist sampling theorem rate at which the input
analog signal is sampled should be at least twice of the highest frequency of
input analog signal. This rate is called sampling frequency.
5.1.1.5 Quantization error

Quantization error is natural in digitization process. It can be reduced by
increasing number of bits in the output digital signal. For 8-bit ADC,
quantization error is 0.4%.
5.1.1.6 Nonlinearity and Differential nonlinearity

Nonlinearity of analog to digital converter is its deviation from linear
transfer curve.
Differential nonlinearity is the worst-case difference between actual
analog voltage change and ideal one-LSB voltage change.
5.1.1.7 Conversion time

Conversion time is the time difference between start of conversion to the
completion of conversion of analog input voltage to output digital value.
Questions:
1. Define conversion time with respect to A to D converter. [2M]
2. Define following terms with reference to A/D converters and list any four
applications of A/D converters. [4M]
i) Resolution ii) Quantization error
5.2.2 Types of Analog to Digital Converters

There are various types of analog to digital converts. Three of them are
discussed below. They are,
- Ramp ADC
- Dual-slope ADC
- Successive approximation ADC
Questions:
1. Give classification of ADCs. [2M]
5.2.2.1 Ramp ADC

It is also called as single slope analog to digital converter. Circuit diagram
for ramp ADC is shown below. Analog input voltage (VA) works as positive input
of the comparator. The negative input of comparator is taken form ramp
generator, which is ramp of fixed slope. Counter and ramp generator are
initially reset to zero. Counter starts counting from first clock cycle. Ramp
generator is also synchronized with the same clock pulse. Counter stops when
5-5
ramp input equals to the analog input (VA) voltage. Here count of the counter is
directly proportional to the analog input voltage.
Figure
Advantages:
1. Cost is less.
2. Reasonably good accuracy.
Disadvantages:
1. Accuracy depends on characteristics of ramp generator.
Questions:
1. With suitable diagram explain the working of ramp type ADC. [4M]
5.2.2.2 Dual slope ADC

Dual-slope ADC contains four major blocks as Integrator, Comparator,
Binary counter and Switch driver.
The process begins with switch position S1=0. So integrator gets input
voltage as Va. This results in HIGH value of Vc , which enables AND gate and
clock pulse reaches to clock input of counter. Counter counts from 000... to 111…
Then switch driver changes the switch position to S1=1 giving voltage –VR as
input to integrator. This makes integrator to move in positive direction and thus
resulting LOW value of Vc , which disables AND gate and resulting in stopping
of counting of counter.
Figure
Advantages:
1. Low sensitivity to noise
2. Low cost
Disadvantages:
1. There are limitations on maximum resolution of dual slope ADC.
Questions:
1. Explain dual slope ADC. [4M]
2. Explain dual slope A/D converter. [4M]
3. State advantages and disadvantages of dual slope ADC. [4M]
5.2.2.3 Successive approximation ADC

The concept of successive approximation is similar to weighing an object
of unknown weight with the help of traditional balance scale and predefined
weights of ½Kg, ¼Kg and so on. Different variations are tried on trial and error
basis. i.e. Successive approximation is done for finalizing the actual value.
Circuit diagram of Successive approximation ADC is shown below. The
comparator works as a balance scale. Output of this comparator is used setting
or resetting the bits at the output of programmer. This output is converted into
equivalent analog voltage from which offset voltage is subtracted and then
applied to inverting input terminal of comparator.
5-6
Figure
Advantages:
1. Higher speed of operation.
2. Good ratio of speed to power.
Disadvantages:
1. Cost is high.
Questions:
1. Draw successive approximation ADC. [2M]
2. Draw a block diagram of successive approximation method of A-D
converter. [4M]
3. Draw block diagram of successive approximation method of A-D
conversion and describe it. [4M]
4. Give advantages and disadvantages of successive approximation. [4M]
5. Compare successive approximation and dual slope type ADC (any four
points). [4M]
5.2.3 Applications Analog to Digital Converters

There are various applications of analog to digital converters. Some of
them are,
- Music Recording
- Scientific Instruments
- Rotary Encoder
- Digital Signal Processing
Questions:
1. List any four applications of A to D converter. [4M]
5.2.4 ICs available as Analog to Digital Converters

- ADC 80
Some more Questions:

1. Give any two applications of ADC and DAC. [2M]
2. Give two applications each of DAC and ADC. [4M]
3. Explain the need for DAC and ADC and write one IC number for DAC and
ADC. [4M]
5-7

This Set of Digital Electronic1-Merged-merged-merged

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

This Set of Digital Electronic1-Merged-merged-merged

Uploaded by

Copyright:

Available Formats

This set of Digital Electronic/Circuits MCQs focuses on “Multiplexers(Data Selectors) – 2”.

1. 4 to 1 MUX would have ____________

2. The two input MUX would have ____________

4. 4 to 1 MUX would have ____________

5. Which of the following circuit can be used as parallel to serial converter?

6. A combinational circuit is one in which the output depends on the ____________

a) Input combination at the time

b) Input combination and the previous output

c) Input combination at that time and the previous input combination

d) Present output and the previous output

a) Some but not all Boolean functions of 3 variables

b) All function of 3 variables but none of 4 variables

c) All functions of 3 variables and some but not all of 4 variables

d) All functions of 4 variables

8. A basic multiplexer principle can be demonstrated through the use of a ____________

9. One multiplexer can take the place of ____________

a) Several SSI logic gates

b) Combinational logic circuits

c) Several Ex-NOR gates

d) Several SSI logic gates or combinational logic circuits

10. The inputs/outputs of an analog multiplexer/demultiplexer are ____________

11. If enable input is high then the multiplexer is ______________

12. What is data routing in a multiplexer?

a) It spreads the information to the control unit

b) It can be used to route data from one of several source to destination

d) It can be used to route data and it is an application of multiplexer

Sanfoundry Global Education & Learning Series – Digital Circuits.

Telegram | Youtube | LinkedIn | Instagram | Facebook | Twitter | Pinterest

Youtube | LinkedIn | Instagram | Facebook | Twitter | Pinterest

1. The word demultiplex means ___________

a) One into many

b) Many into one

d) One into many as well as Distributor

2. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs

b) One of the inputs will be selected for the output

c) The output will be distributed to one of the inputs

d) Single input to Single Output

3. Most demultiplexers facilitate which type of conversion?

b) Single input, multiple outputs

d) Odd parity to even parity

4. In 1-to-4 demultiplexer, how many select lines are required?

5. In a multiplexer the output depends on its ___________

6. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be ___________

Explanation: It can be calculated from the figure shown below:

7. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ___________

8. How many select lines are required for a 1-to-8 demultiplexer?

9. How many AND gates are required for a 1-to-8 multiplexer?

10. The output Q4 of this 1-to-8 demultiplexer is ____________

11. Which IC is used for the implementation of 1-to-16 DEMUX?

Sanfoundry Global Education & Learning Series – Digital Circuits.

Telegram | Youtube | LinkedIn | Instagram | Facebook | Twitter | Pinterest

Youtube | LinkedIn | Instagram | Facebook | Twitter | Pinterest

1. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs

b) One of the inputs will be selected for the output

c) The output will be distributed to one of the inputs

d) Single input gives single output

2. Most demultiplexers facilitate which type of conversion?

b) Single input, multiple outputs

d) Odd parity to even parity

3. In 1-to-4 demultiplexer, how many select lines are required?

4. In a multiplexer the output depends on its ____________