Introduction to Verilog and ModelSim

 Earliest digital circuits were designed with

vacuum tubes and transistors.
 ICs were invented.
 SSI Chips had small number of gates.
 MSI had hundreds of gates on a single chip.
 LSI have thousands of gates on a single chip.
 At this point EDA techniques evolved but circuits
were still tested on breadboard.
 With the advent of VLSI technology, a single chip
contains 100,000 transistors.
 Then Computer Aided Techniques were used for
verification and design of VLSI digital circuits.
 In the digital design field Hardware
Description Languages, HDLs are standard for
digital circuits description.
 VHDL and Verilog are the primary industry
tools for programming digital systems.
 Verliog originated in 1983 at Gateway Design
Automation.
 Today Verilog HDL is an IEEE standard.
 By describing designs in HDLs, functional
verification of the design can be done early in
the design cycle.
 Whitespaces: ignored by Verilog.
 Comment: inserted for readability and
documentation.
 one line comment starts with “//”.
 multiple line comment starts with “/*” and
ends with “*/”.
 Operators: three operators;
 unary; proceeds the operand
 binary; appears between two operands
 ternary; has two separate operators that
separates three operands.
 Number Specifications: two types of number
specifications
 Sized numbers; represented as
<size>’<base format> <number>
4’b1111 // this is 4 bit binary number
16’d255 // this is the 16 bit decimal number
 Unsigned numbers;
that are specified without <base format> are
decimal numbers by default.
that are specified without <size> are machine
specific (must be at least 32).
23456 // this is 32 bit decimal number by default
‘o21 // this is 32 bit octal number
 Negative numbers: specified by putting a
minus sign before the size for a constant.
 Underscore characters: allowed anywhere in
number except the first character.
 Strings: sequence of characters that are
enclosed by double quotes.
It cannot be on multiple lines.
 ModelSim is a verification and simulation tool
for VHDL, Verilog, SystemVerilog, and mixed
language designs.
 It is the industry standard simulation tool for
verifying digital designs.