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Introduction to
Microelectronic &
Nanoelectronic
Devices
Prof. Dr. Muhammad EL-SABA

2010/2011
Electronic Devices
Copyright © 2001-2010, by the author. All rights reserved.
1st Edition 2001

2nd Edition 2005
3rd Edition 2011
Reproduction or translation of any part of this work, without permission

of the copyright owner, is unlawful. Requests for permission or further
information should be addressed to the author, at the Dept. of Electronic
Engineering, Faculty of Engineering, 1 Sarayat street, 11517Abbasia,
Cairo, Egypt. E-mail Address mhs@saudia.com
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Electronic Devices
Preface
Electronic devices are widely used, in our daily life in so many
applications. Witness the explosion in the uses of electronics in
computers, information technology, consumer electronics, healthcare,
sensing, automotive applications and communications systems, etc.
This book gives an introduction to electronic devices. The book covers

the curriculum of basic electronic devices and their operation principles.
We chose a midway between just mentioning the final I-V or C-V
characteristics of each device and their full derivation from scratch. The
first approach may be more suitable for technicians rather than engineers.
On the other hand, the experience showed that the full mathematical
derivation of the device characteristics may deviate the attention of the
student to tiny details, away from the main subject of the device
principles and applications. Instead, we show the reader the physical
principles, on which the device characteristics are based and demonstrate
the main procedure, which is usually followed to derive these
characteristics. We then explain the distinct regions on the device I-V
characteristics, and the device modes of operation. We then show the
main functions the device can perform in each mode of operation, such
as amplification or switching. We also show the different circuit
configurations of each device and its small and large signal circuit
models. Finally we demonstrate some of the most important applications
that exploit the device characteristics.
The book is divided into 12 chapters and six appendices. The appendices
contain the acronyms and the SPICE simulator models and parameters of
all the devices contained in this book. In each chapter, I handle one of the
fundamental devices, such as the P-N junction diode, the bipolar junction
transistor (BJT) and the MOSFET. In the beginning I present the device
structure and physical operation, with the least amount of mathematics
for the derivation of its current-voltage (I-V) characterizes. Afterwards, I
present the different possible circuit configurations of the device, its
small signal and large signal AC models and its famous applications. The
deviations from the ideal characteristics are also presented in this stage.
Finally, I present the laboratory testing procedure as well as the device
ratings and its parameters for circuit simulation. The first Chapter of this
book is an introduction and revision of semiconductors and their
important properties. Chapter 2 is dedicated for P-N junction diodes. At
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Electronic Devices
the end of this chapter we introduce almost all the P-N junction related
devices, such as P-I-N diode, Zener diode, tunnel diode, resonant
tunnel diode (RTD), impact ionization and transient transfer (IMPATT)
diode, laser diode, photodiode, and solar cells. Chapter 3 is dedicated for
bipolar junction transistors (BJT’s) and the related devices, such as the
heterojunctions bipolar devices (HBT). Chapter 4 includes the
description of metal-semiconductor (MS) contacts and Schottky diodes.
Chapter 5 is dedicated for basic field effect transistors (FET), such as
Junction FET (JFET), metal-epitaxial semiconductor FET (MESFET)
and high-electron mobility FET (HEMT) as well as modulation-doped
FET (MODFET). Chapter 6 handles the metal-oxide-semiconductor
(MOS) structures and their C-V charactieristics. Chapter 7 is dedicated
for MOS transistors (MOSFET) and their characteristics and variant
structures. Chapter 8 handles the power devices, including silicon-
controlled rectifier (SCR), thyristors, Diac, Triac, gate-turn-off thyristor
(GTO), power BJT and power MOSFETs such as lateral diffused MOS
(LDMOS) as well as insulated-gate BJT (IGBT). In Chapter 9 I present
memory devices, such as static and dynamic RAM cells as well as non-
volatile memory devices. These last three chapters are dedicated for
graduate students to comprehend the physical foundation of nanoscience
and nanotechnology. Chapter 10 is dedicated for low-dimensional
structures and quantum devices. Two-dimensional structures (such as
quantum wells), one-dimensional wires and zero-dimensional quantum
dots are covered. Chapter 11 demonstrates physical basis and the recent
advances in nanotubes and nanodevices. Chapter 12 covers the basic
principles of spintronic devices.
A proper background in undergraduate-level quantum mechanics,

statistical mechanics and solid state physics is required. So far, I have
not found a single textbook that covers all the contents of this book.
After completing this course, the student will be in a position to decide
on the best way to choose the suitable device for a specific application,
define its characteristics, and understand its operation. The book is
typically fundamental, although it is analysis-oriented. This leaves room
for students to do projects based on literature studies or their own
research work. In particular, the course involves hands-on lab assign-
ments and mini-project, to characterize the basic electronic devices.

Cairo in Feb. 2011
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Electronic Devices
CONTENTS
Subject Page
PREFACE ii
CHAPTER 1: Introduction to Electronic Devices 1
1-1. Energy Band Theory in Solids 3

1-1.1. Energy levels and Energy Bands 3
1-1.2. Conductors and Insulators 5
1-2. Intrinsic & Extrinsic Semiconductors 7
1-2.1. n-type and p-type Semiconductors 8
1-2.2. Majority and Minority Carriers 10
1-2.3. Concentration of Electrons and Holes 12
A- Case of n-type Semiconductors 12
B- Case of p-type Semiconductors 12
1-3. Fermi Energy Level 14
1-4. Drift and Diffusion in Semiconductors 15
1-5. Generation-Recombination Mechanisms 19
1-6. Continuity Equation in Semiconductors 21
1-7. Semiconductor Equations 22
1-7.1. Homogeneous Semiconductor Equations 23
1-7.2. Heterogeneous Semiconductor Equations 23
1-8. Quasi-Fermi Levels 25
1-9. Noise in Semiconductor Devices 28
1-9.1. Noise Modeling 28
i. Thermal Noise 28
ii. Shot Noise 29
iii. Flicker (1/f) Noise 30
1-9.2. Equivalent Input Noise 31
1-9.3. Noise Figure and Noise 31
1-9.4. Calculation of Noise Figure from Input Noise 32
1-10. Technology of Semiconductor Devices 33
1-11. Summary 37
1-12. Problems 39
1-13. Bibliography 42
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Electronic Devices
Subject Page
CHAPTER 2: P-N Junctions 43
2-1. Chapter Overview & Learning Objectives 45

2-2. Formation of a P-N Junction 46
2-3. Operation of the P-N Junction 49
2-2.1. Forward Bias 53
2-2.2. Reverse Bias 55
2-4. Terminal (I-V) Characteristics of P-N Junctions 56
2-5. Characteristics of Real P-N Junctions 58
2-5.1. Recombination in the Space Charge Region 58
2-5.2. High Injection Current 59
2-5.3. Avalanche Breakdown 60
2-6. Capacitance of a P-N Junction 64
2-7. AC Circuit Model of a P-N Junction Diode 66
2-8. Transient Behavior of a P-N Junction 67
2-9. Application of a P-N Junction 69
2-9.1. Diode as Rectifier 70
2-9.2. Peak Detector 73
2-9.3. Clipping Circuits 73
2-9.4. Clamping Circuits 74
2-9.5. Voltage Multipliers 75
2-10. P-N Heterojunction Diodes 77
2-11. Other Diode Structures 78
2-11.1. Zener Diode 78
2-11.2. P-I-N Diode 79
2-11.3. Schottky Barrier Diode (SBD) 81
2-11.4. IMPATT Diode 83
2-11.5. Tunnel Diode 86
2-11.6. Resonant Tunnel Diode (RTD) 88
2-11.7. Solar Cell 91
2-11.8. Photodiode 95
2-11.9. Light Emitting Diode (LED) 98
2-11.10. Laser Diode 102
2-12. Laboratory Testing of P-N Junction Diodes 112
2-13. Diode Ratings 113
2-14. Computer Simulation & Modeling Parameters 114
2-15. Summary 117
2-16. Problems 124
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Electronic Devices
Subject Page
2-17. Chapter Assessment 127

2-18. Bibliography 129
CHAPTER 3: Bipolar Junction Transistor 131
3-1. Chapter Overview and Learning Objectives 133

3-2. BJT Structure 134
3-3. Theory of Operation of the BJT 136
3-4. BJT Circuit Configurations 136
3-5. BJT Operating Modes 137
3-6. BJT Currents 138
3-7. BJT Models 148
3-7.1. Ebers-Moll Model 148
3-7.2. Gummel-Poon Model Model 149
3-8. Static I-V Characteristics of a BJT 152
3-9. BJT Circuit Analysis (DC Analysis) 155
3-10. Small Signal Models of a Bipolar Transistor 158
3-10.1. Hybrid- Model 158
3-10.2. Hybrid Parameters Model 159
3-11. BJT as an Amplifier (AC Analysis) 161
3-11.1. Active Mode Biasing Schemes 161
3-11.2. Calculation of the AC Voltage Gain 162
3-11.3. AC Beta Factor 163
3-11.4. Examples 165
3-12. BJT as a Switch 167
3-13. BJT Switching Times 170
3-14. Physical Limitations of the BJT 173
3-14.1. Voltage Limitations (Breakdown Voltage) 173
3-14.2. Early Effect 175
3-14.3. Current Limitations (Maximum Current) 177
3-14.4. Variation of Gain with Collector Current 178
3-14.5. Kirk Effect 179
3-14.6. Maximum Power 179
3-14.7..Safe Operating Area (SOA) of a BJT 180
3-14.8.. Thermal Derating 182
3-15. BJT Fabrication Technology 185
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Electronic Devices
Subject Page
3-16. Other BJT Structures 189

3-16.1. Unijunction Bipolar Transistor (UJT) 189
3-16.2. Hetrojunction Bipolar Transistor (HBT) 191
3-16.3. Resonant tunneling Bipolar Transistor (RTBT) 195
3-17. Laboratory Testing of a BJT 197
3-19. Summary 200
3-20. Problems 204
3-22. References 210
CHAPTER 4: Metal-Semiconductor (M-S) Contacts 211

4-2. Introduction to M-S Junctions 213
4-2.1. Workfunction of a Metal 214
4-2.2. Thermionic Emission Current (Richardson’s) 215
4-2.3. Electron Affinity in a Semiconductor 216
4-3. Metal-n-type Semiconductor Contact 222
4-3.1. Case 1: m > s (Schottky Barrier Contact) 223
4-3.2. Case 2: m < s (Ohmic Contact) 223
4-4. Metal-p-type Semiconductor Contact 224
4-5. Ohmic MS Contact 225
4-6. Tunnel MS Contact 226
4-7. Annealed and Alloyed MS Contacts (Silicides) 228
4-8. Small Signal Model of a Schottky Barrier Diode 231
4-9. Capacitance of MS Structure 231
4-10. Measurement of MS Contact Barrier Height 232
4-11. Switching performance of the SBD 236
4-12. Applications of MS Contacts 237
4-13. Summary 238
4-14. Problems 241
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Electronic Devices
Subject Page
CHAPTER 5: Junction Field Effect Transistor (JFET) 245
5-1. Chapter Overview and Learning Objectives 247

5-2. JFET Structure 248
5-3. JFET Characteristics 248
5-4. JFET Small Signal Model 253
5-5. JFET Amplifiers 253
5-6. Other FET Structures 256
5-6.1. MESFET 256
5-6.2. MODFET (HEMT) 258
5-7. FET Noise Model 261
5-8. JFET Testing 261
5-9. Summary 263
5-10. Problems 265
CHAPTER 6: Metal-Oxide-Semiconductor (MOS) Structure 269
6-1. Chapter Overvieew & Learning Objectives 271

6-2. Energy Band diagram of an MOS 272
6-3. MOS Flatband Voltage 273
6-4. MOS Biasing Regimes 275
6-3.1. Accumulation Mode 276
6-3.2. Depletion Mode 276
6-3.3. Inversion Mode 280
6-5. MOS Capacitance 282
6-5.1. Simple Model 283
6-5.2. Exact Analysis 285
6-5.3. Advanced Analysis & Quantum Effects 286
6-6. Charge-Coupled Devices (CCD) 289
6-6.1. CCD Diffusion Time 289
6-6.2. CCD Camera 292
6-7. Summary 294
6-8. Problems 298
6-9. References 300
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Electronic Devices
Subject Page
CHAPTER 7: MOS Field Effect Transistor (MOSFET) 301

7-2. Types of MOS Transistors (MOSFET’s) 305
7-3. MOSFET Structure 311
7-4. MOSFET I-V Characteristics & Modes of Operation 308
7-4.1. Linear Mode 309
7-4.2. Saturation Mode 310
7-5. MOSFET Sub-threshold Regime 314
7-6. MOSFET Small Signal Circuit Model 315
7-7. MOSFET as an Amplifier 316
7-8. MOSFET as a Switch 318
7-9. MOSFET Scaling 319
7-10. MOSFET Degradation & Hot-Carrier Effects 322
7-10.1. Hot-carrier Injection Currents 323
7-10.2. Gate Tunneling Currents 325
7-11. Advanced MOSFET Structures 329
7-11.1.. CMOS Technology 329
7-11.2. Poly-Silicon Gate Technology 330
7-11.3. Silicon & SiGe on Insulator (SOI & SGOI) 332
7-11.4. Multi-Gate and 3-D MOSFET Structures 334
7-11.5. Thin-Flm Transistors (TFT) 336
7-11.6. Active-Matrix LCD 337
7-12. MOSFET Testing 340
7-14. Summary 342
7-15. Problems 345
7-17. References: 349
CHAPTER 8: Semiconductor Power Devices 351
8-1. Overview and Learning Objectives 353

8-2. Bipolar Power Devices 355
8-2.1. Power PIN 355
i. PIN operation & I-V Characteristics 359
ii. PIN Switching Characteristics 363
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Electronic Devices
Subject Page
8-2.2. Power BJT 366

i. Safe Operating Area (SOA) 366
ii. Emitter Current Crowding 368
iii. Kirk Effect 370
iv. Switching Times & Switching losses 370
A. Turn-ON Characteristics 371
B. Turn-OFF Characteristics 374
C. Switching Losses of a power BJT 376
8-2.3. Power Darlington Transistors 377
8-2.4. Thyristors 378
i- Thyristor Structure & Operation 378
ii- Thyristor I-V Characteristics 381
iii- Thyristor Fabrication Techniques 383
iv- Thyristor Packaging 385
v- Thyristor Testing 386
vi- Thyristor Application Circuits 387
vii- Other Thyristor Devices 389
8-2.5. Diac and Triac 390
8-2.6. GTO 394
i- GTO Basics 394
ii- GTO Structure 395
iii- GTO Operation 396
iv- GTO Switching Circuits 397
82.7. Integrated-Gate Control Thtristor (IGCT) 400
8-3. MOSFET Power Devices 401
8-3.1. DMOS 401
8-3.2. LDMOS 402
8-3.3. VMOS 404
8-3.4. MCT 405
8-3.5. IGBT 406
i. IGBT Structures 408
ii. IGBT Operation 408
A. Forward Blocking Mode 409
B. Reverse Blocking Mode 409
iii. IGBT I-V Characteristics 410
iv. IGBT Circuit Models 412
v. IGBT Switching Characteristics 412
vi. IGBT Ratings 413
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Electronic Devices
Subject Page
8-4. Switching Performance of Power Devices 416
8-5. Protection of Power Devices 421
8-6. Packaging & Thermal Design of Power Devices 423
8-7. Applications of Power Devices 427
8-7.1. Rectification (AC-DC Conversion) 427
8-7.2. Inverters (DC-AC Conversion) 429
8-7.3. Converters (DC-DC Conversion) 429
8-7.4. Cycloconverters (AC-AC Conversion) 430
8-8. Comparison of Power Devices & Vacuum Tubes 432
8-9. Summary 434
8-10. Problems 442
Chapter 9: Memory Devices 447
9-1. Overview and Learning Objectives 449

9-2. History of Memory Technology 451
9-3. MOSFET Memory Devices 454
9-3.1. SRAM Cell 454
9-3.2. DRAM Cell 457
i- DRAM Reading 461
ii- DRAM Writing ‘1’ 462
iii- DRAM Writing ‘0’ 462
iv- DRAM Refreshing 462
v- DRAM Variants 464
vi- DRAM Modules 466
9-4. Bipolar Memory Devices 468
9-4.1. BJT SRAM Cell 468
9-4.2. Thyristor Memory Cell 468
9-4.3. BiCMOS SRAM Cell 470
9-5. Nonvolatile Memory Devices 471
9-5.1. Basic Programming Mechanisms 475
i- Fowler Nordheim (F-N) Tunneling 475
ii- Hot-carrier Injection (HCI) 477
9-5.2. Basic Erasing Mechanisms 478
i- UV Emission 478
ii- Fowler Nordheim (F-N) Tunneling 479
9-5.3. Programming / Erasing Characteristics 479
9-5.4. Nonvolatile Memory Reliability 480
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Electronic Devices
Subject Page
9-5.5. Flash Memory 481
9-6. Emerging Memory Technologies 485
9-6.1. FRAM 485
9-6.2. MRAM 487
9-6.3. PCRAM 489
9-6.4. TMO RAM 492
9-6.5. ReRAM 493
9-7. Memory Errors: Detection & Correction 495
9-8. Simulation of Memory Devices 496
9-8.1. Simulation of a MOS SRAM Cell 496
9-8.2. Simulation of Memory Failure 498
9-9. Summary 500
9-10. Problems 505
Chapter 10: Low-dimensional Structures & Quantum Devices 509
10-1. Introduction & Learning Objectives 511

10-2. Two-dimensional Electron Gas (2DEG) 513
10-2.1. In-Plan and Vertical Transport in 2 DEG 515
i- Schrödinger-Poisson Model 516
ii- In-plane Conductivity of a 2DEG 518
iii- Vertical Transport 519
10-2.2. Resonant Tunneling 519
10-2.3. Resonant Tunneling Diode (RTD) 520
10-3. Quasi-one-dimensional (Q1D) System 522
10-4. Quantum Dots (Q0D) 523
10-4.1. Classical Coulomb Blockade 526
10-4.2. Quantum Coulomb Blockade 529
10-5. Single Electron Transistor (SET) 530
10-5.1. SET Operation 533
10-5.2. Accurate Measure of Charge 536
10-5.3. Room Temperature Operation 537
10-5.4. Future Perspectives 539
10-6. Quantum-Dot Lasers 540
10-7. Summary 542
10-8. Problems 544
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Electronic Devices
Subject Page
Chapter 11 Nanowires, Nanotubes and NanoDevices 547
11-1. Overview & Learning Objectives 549

11-2. Nanotechnology & Nano Effects 549
11-3. Nanowires 552
11-4. Silicon Nanowire Transistor (SiNWT) 555
11-5. Carbon Nanotubes 557
11-5.1 Single-Wall Naotubes (SWNTs) 558
11-5.2 Energy Band Structure of SWNT’s 561
11-5.3 Transport of Charge Carriers in SWNT’s 565
11-5.4. Stuffed Single-Wall Nanotubes (SSWNTs) 568
11-6. Nanotube Devices 570
11-6.1, Nanotube FET (NTFET) 571
11-6.2, Complementary Nanotube FET (CNTFET) 573
10-6.3, Nanotube Solar Cells 576
10-6.4, Nanotube Memory 578
11-7. Other Applications of Nanotechnology 579
10-7.1.Electronics, Communications & Computer 580
10-7.2. Biomedical Applications 584
10-7.3. Water Purification & Environmental 585
10-7.4. Toxicology of Nanotubes 586
11-8. Nano-electromechanical Systems (NEMS) 587
11-8.1. NEMS functions 588
11-8.2. Nano-Machines 588
11-8.3.Nano-Optoelectronic Systems (NOEMS) 589
11-8.4. Challenges of NEMS 590
11-8.5. How to fabricate NEMS 592
11-9. Summary 594
11-10. Problems 596
Chapter 12: Spintrobic Devices 601
12-1. Overview & Learning Objectives 603

12-2. Magnetic Semiconductors 605
12-3. Spin Relaxation Mechanisms 608
12-3.1. D’yakonov-Perel (DP) Mechanism 608
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Electronic Devices
Subject Page
12-3.2. Bir-Aranov-Pikus (BAP) Mechanism 608

12-3.3. Elliot-Yafet (EY) Mechanism 608
12-3.4. Rashba Effect 609
12-3.5. Other Mechanisms 609
12-4. Spin Relaxation Time 610
12-5. Spin Transport Equations 612
12-6. Spintronic Devices 614
12-6.1. Spin Injectors 614
12-6.2. Spin Aligners & Filters 615
12-6.3. Spin Detectors 615
12-6.4. Spin FET 616
12-6.5. Magnetic Bipolar Transistor (MBT) 616
12-6.6. Magnetic Tunnel Transistor (MTT) 619
12-6.7. GMR 620
12-6.8- MRAM 621
12-6.9. MRI 622
12-7. Summary 624
12-8. Problems 626
Appendices 629
Appendix A List of Symbols 631
Appendix B SPICE Model of a P-N Junction 635
Appendix C SPICE Model of a BJT 637
Appendix D SPICE Model of a JFET 639
Appendix E SPICE Model of a MOSFET 643
Appendix F SPICE Model of an IGBT 647
Acronyms 649
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Microelectronic & Nanoelectronic Devices Chapter 1
Introduction to Electronic Devices
Contents:
1-1. Energy Band Theory in Solids

1-1.1. Energy levels and Energy Bands
1-1.2. Conductors and Insulators
1-2. Intrinsic & Extrinsic Semiconductors
1-2.1. n-type and p-type Semiconductors
1-2.2. Majority and Minority Carriers
1-2.3. Concentration of Electrons and Holes
A- Case of n-type Semiconductors
B- Case of p-type Semiconductors
1-3. Fermi Energy Level
1-4. Drift and Diffusion in Semiconductors
1-5. Generation-Recombination Mechanisms in Semiconductors
1-6. Continuity Equation in Semiconductors
1-7. Semiconductor Equations
1-7.1. Semiconductor Equations in Homogeneous Semiconductors
1-7.2. Semiconductor Equations in Heterogeneous Semiconductors
1-8. Quasi-Fermi Levels
1-9. Noise in Semiconductor Devices
1-10. Technology of Semiconductor Devices
1-11. Summary
1-12. Problems
1-13. References
-1-
Prof. Dr. Muhammad El-SABA
-2-
2
Introduction to
Electronic Devices
In this chapter, we summarize some fundamental concepts about
semiconductors, which are used to fabricate electronic devices. We
briefly demonstrate how to exploit these properties to make useful
electronic devices and integrated circuits.
Upon completion of this Chapter, students should:
Understand the fundamentals of solid-state physics, such as the energy

band theory, the electron drift and the concept of holes, which are
necessary for the comprehension of electronic devices.
Review the fundamentals of semiconductors and carrier transport
equations, which are necessary for the analytical description of the
operation of semiconductor devices.
Be acquainted with the appropriate approaches in device modeling.
2-1. Energy Band Theory in Solids

Transistors, diodes, integrated circuits and many solid-state electronic
devices have semiconductor technology in common. Before looking at
how these devices work, it is necessary to have a basic understanding of
conductors, insulators and semiconductors.
1-1.1. Energy Levels and Energy Bands in Solids

In isolated atoms, the electrons are arranged in orbits with strict numbers
of electrons and are orbiting around their nuclei with certain energy
levels. For instance, the Si atom has 14 electrons; the first orbit (1s2) only
contains two electrons, and the second (2s2 and 2p6) has eight the third
(3s2 and 3p2) has four electrons. In this case, the relation between the
electron energy, E, and the electron wave-vector, k, consists of a set of
discrete (quantized) points in the k space. When isolated atoms are
brought together, to form a crystalline solid, various interactions (due to
attraction and repulsion forces) occur between neighboring atoms. At the
position of equilibrium, the forces of attraction and repulsion between
atoms are balanced and the total potential energy of the system becomes
minimal. The adjacent atoms of most intrinsic semiconductors, like Si,
are bonded with covalent bonds.
-3-
As the electron clouds of individual atoms are overlapped, the height of

potential wells of different atoms is lowered and electrons of higher
energies are no longer belonging to a specific atom. As a consequence of
the overlapping process, the electron energy levels are split into dense
groups of levels, known as energy bands. Usually, these energy bands
are separated by successive forbidden regions, that we call energy gaps.
(a) (b)
Fig. 1-1. Schematic representation of the diamond lattice and its atoms (a), and a two-
dimensional representation of the covalent bond (b)
Fig. 1-2. Schematic of energy level splitting and formation of energy bands in a
diamond crystal of N atoms as a function of inter-atomic distance R.
-4-
Figure 1-2 shows the development of the one-electron energy bands in

diamond crystals from the discrete energy levels of an isolated atom. As
shown in figure, when the separation between atoms is decreased, the
energy levels of single atoms (1s, 2s, etc.) are split into bands of a huge
number of adjacent energy levels. Figure 1-3, depicts the energy band
diagram at the state of equilibrium.
The highest filled energy band, in the energy band diagram, is usually
called: the valence band. Also, the energy band just above the valence
band is called the conduction band. The valence band and the conduction
band are separated by a region called the energy gap. The height of
energy gap is given by:
Eg = Ec - Ev (1-1)
where Ec is the lowest (bottom) level in the conduction band and Ev is the
highest (top) level in the valence band. So, in crystalline solids, the E-k
relation, at a certain point in the physical crystal lattice, is characterized
by a sequence of alternating allowed energy bands and energy gaps. The
E-k relation of electrons inside a solid crystal, in the various directions of
the k-space, is usually called the energy band structure of that solid.
E
Energy gap
Conduction Band
Ec
Eg
Ev Band of allowed
Valence Band energy levels
V.B.
Fig. 1-3. Schematic of the energy band diagram (versus crystal spatial position).
1-1.2. Conductors and Insulators

In terms of electricity there are two main classes of material: namely:
conductors and insulators. From their names it can be gathered that
conductors will conduct electricity, whereas non-conductors act as
insulators preventing the flow of an electric current.
-5-
An electric current is made up of the flow of free electrons. This means

that for a current to flow, the electrons must be able to move freely within
the material. At any instance, such free electrons are moving freely but
randomly. By placing a potential difference across a conducting material
the free electrons can be drifted in a certain direction and this constitutes
an electric current.
Metals are all conductors of electricity, and a number of other substances

also conduct it to varying degrees. Other substances do not have free
electrons moving around the lattice. Electrons are firmly held within their
atoms and cannot escape easily. Accordingly when a potential is placed
across the substance very few electrons will move and very little or no
current will flow. These substances are called insulators.
Fig. 1-4. Classification of solids into conductors, semiconductors and insulators.
-6-
1-2, Intrinsic & Extrinsic Semiconductors

As the name suggests a semiconductor is neither a true conductor nor an
insulator, but half way between. A number of materials exhibit this
property, and they include germanium (Ge), silicon (Si), gallium arsenide
(GaAs), and a variety of other substances. To understand how it acts as a
semiconductor it is necessary to first look at their atomic structure. For
instance, let‘s jet a look at the silicon material as an example of
semiconductors.
The electrons in the outer shell of silicon are shared to make up a crystal
lattice, with covalent bond, as shown in Fig.1-5. When this happens there
are no free electrons in the lattice, making silicon a good insulator at zero
absolute temperature.
Si Si Si
Si Si Si
Figure 1-5. Illustration of the covalent bond
A similar picture can be seen for Ge. It has also four electrons in the outer
shell. Thus, at absolute zero temperature, the crystal lattice of such
elements has no free electrons and these elements behave as insulators.
However, at room temperature (about 300K) some of the shared electrons
will have enough energy to break their covalent bonds (and overcome the
energy gap between the valence band and the conduction band) and roam
freely in the crystal.
The density of the quasi-free electrons in a semiconductor is called the

intrinsic carrier concentration of that semiconductor, and termed by ni.
These free (or quasi free) electrons can only convey a very small current
if the semiconductor is subjected to an electric field. Such pure (undoped)
semiconductors are called intrinsic semiconductors.
-7-
1-2.1. N-type and P-type Semiconductors

The conductivity of semiconductors changes very significantly by adding
small amounts of impurities. Doped semiconductors are called extrinsic
semiconductors, and their conductivity depends on the type of added
impurities. If traces of impurities of 5th-valent materials (having five
electrons in the outer shell, like phosphorous) are added they increase the
number of electrons in the crystal lattice of the semiconductor. The extra
electron in the outer shell, becomes almost free to move around the
lattice. This increases the number of free electrons and enables an
appreciable current to flow if a potential is applied across the
semiconductor material. As this type of semiconductor materials has extra
electrons in the lattice it is called N-type semiconductor. Typical
impurities that are used for doping N-type semiconductors are
phosphorous (P) and arsenic (As). Such impurities are called donors.
It is also possible to place elements with only three electrons in their

outer shell into the crystal lattice. When this happens the silicon wants to
share its four electrons with another atom with four atoms. However as
the impurity has only three, there is a space or a hole for another electron.
As this type of material has electrons missing it is known as P-type
material. Typical impurities used for doping P-type material are boron
(B), and aluminum (Al). Such impurities are called acceptors.
Semiconductor
Intrinisic Extrinsic
n= p n p
n-type p-type
n>p p>n
Fig. 1-6. Types of semiconductors.
-8-
Fig. 1-7. Doping elements.
Example 6-2
What is the Arsenic weight to be added to a 100 gm of silicon melt to
produce a 1017 electron/cm3 n-type silicon?
Solution
In a 100 gm of Si there are N atoms such that.
N(Si) = Weight of Si [gm] / Weight of one Si atom [gm]
where the weight of Si atom = Atomic weight of Si / Avogadro‘s number
= 28 [amu/Si atom] / 6 x 1023 [amu / gm] = 4.67x10-23 [gm]
Thus, N(Si) = 100[gm] / 4.67x10-23[gm] = 2.14 x 1024 atom
The density of Si atoms is equal to 5x1022 atom/cm3 and the density of As
atoms needed is 1017 atom/cm3, then the number of As atoms needed is:
1017 [atom / cm3 ]

N ( As)  22 3 x 2.14 x10
24
[atom]  4.28 x 1019 atom
5x10 [atom / cm ]
The required weight of As needed is then given by:
Weight (As) [gm] = N(As) [atom] x Weight of one As atom [gm/atom]
where the weight of As atom = Atomic weight of As / Avogadro‘s
Number = 75 [ amu] / 6x1023 [amu/gm] = 1.25 x 10-22 [gm]
Hence, Weight (As) = 4.28x1019 [atom] x 1.25 x 10-22 = 5.35 x 10-3 [gm]
-9-
1-2.2. Majority and Minority Carriers

It is easy to see how electrons can move around the lattice and carry a
current, under the effect of electric field. However it is not quite obvious
for vacant places or holes. This happens when an electron from a
complete orbit moves to fill a hole, leaving a hole where it came from.
Another electron from another orbit can then move in to fill the new hole
and so forth. The movement of the holes in one direction corresponds to a
movement of electrons in the other, hence an electric current.
Hole
Fifth Electron
Donor Atom Acceptor Atom
Fig. 1-8. Basic bond pictures of N-type and P-type semiconductors
Therefore, both electrons and holes can carry charge and drift, under the
effect of electric field, resulting in an electric current. Consequently, both
electrons and holes are known as charge carriers. Holes are the
majority charge carriers for a P-type semiconductor and electrons are
majority carriers for an N-type semiconductor.
In an N-type semiconductor, the donor impurities create a donor energy
level Ed, in the energy gap, of the semiconductor. The donor ionization
energy Eid is equal to the energy required for transition from Ed to Ec, or
Eid (donor ) = Ec - Ed (1-2)
As for the most of V-group impurities Ed is close to the bottom of

conduction band, and Eid is only few milli electron volts (44 meV for P in
Si). Such impurities are called shallow levels impurities.
Similarly, the acceptor impurities create an acceptor energy level Ea, in

the energy gap, of the semiconductor. The acceptor ionization energy Eia
is equal to the energy required for transition from Ev to Ea , or
Eia (acceptor) = Ea - Ev (1-3)

-10-
For most III-group impurities, Eia is in the order of 10m eV, so that Na- 
Na at room temperature. The following figure depicts the energy band
diagram of P -type and N -type semiconductors, with their acceptor and
donor energy levels. Note that the relative density of ionized donors,
(Nd+/Nd) is a function of temperature. Also, the relative density of ionized
acceptors, (Na-/Na) is a function of temperature, as indicated in the figure
below.
(a) Acceptors (in p-type) (b) Donors (in n-type)
Fig.1-9. Energy levels and partial ionization of acceptor (a) and donor (b) impurities
Fig.1-10. Relative density of ionized donors (P in Si), as a function of temperature.
-11-
1-2,3, Concentration of Electrons and Holes in Semiconductors

According to the neutrality condition in a semiconductor we have:
no  N a  po  N d (1-4)
where no and po are the density of electrons and holes in the

semiconductor at equilibrium. Also Nd+ and Na- are the densities of
ionized donors and acceptors in the semiconductor, respectively. Also,
the mass-action law dictates that
no . po  ni2 (1-5)
where ni is the intrinsic-carrier concentration
34

15 
m *
m *
  Eg 
ni  4.82  10
nd pd
 T 3 2 exp  
(1-6)
 m 2 
 o   2k BT 
where mnd* is called the density-of-states effective-mass in the conduction

band , m*pd is the valence band density-of-states effective-mass, and mo is
the rest mass of electrons in free space (9.1x10-31 kg). In Si, mnd* = 1.08
mo and m*pd = 0.81 mo. The following figure shows the intrinsic carrier
concentration of Si, Ge, and GaAs as a function of temperature.
A- Case of Intrinsic Semiconductors

In intrinsic semiconductors, the number of electrons is equal to the
number of holes (vacant places or broken bonds). Therefore, in thermal
equilibrium we have:
no  po  ni (1-7)
B- Case of Extrinsic Semiconductors

By solving the above algebraic equations, we can calculate no and po
no 
N 
d  
 N a   2n
1  1    i 


2 
 (1-8a)
  
2
  Nd  Na  
-12-
po 
N 
a  
 N d   2n
1  1    i 


2 
 (1-8b)
  
2
  Na  Nd  
where the  sign (inside the square brackets) stands for the type of
majority carries. That is the + sign is taken when we calculate no from (1-
6a) in n-type materials or po from (1-6b) in p-type materials.
Fig 1-11. Intrinsic carrier concentrations of Si, Ge and GaAs versus temperature.
-13-
Similarly, for n-type semiconductor (Na- = 0), we have:
  2ni  
2
N d  ni2 nd2
no  1  1      N d , po   (1-9)
2   N d   no N d

Also, for p-type semiconductor (Nd+=0), we have:
  2ni  
2
N a  ni2 nd2
po  1  1      N a , no   (1-10)
2   N a   po N a

1-3. Fermi Energy Level

The Fermi level (EF) is a reference energy level, which is typically used
in the energy band diagram to illustrate the type of semiconductors and
how they are populated with charge carriers. The difference between the
Fermi energy and the vacuum level of any material is termed the
workfunction (m = Eo - EF). The Fermi energy level in non-degenerate
(not highly-doped) semiconductors is situated inside the energy gap.
In N-type semiconductors, EF is situated near the conduction band edge

(Ec) meaning the number of electrons is greater than the number of holes.
Also, In P-type semiconductors, EF is situated near the valence band edge
(Ev) meaning the number of holes is greater than the number of electrons.
However, in both cases, the Fermi level position is a unction of
temperature.
Intrinsic semiconductor, n-type semiconductor, p-type semiconductor
Fig. 1-12. Variation of the Fermi level position with temperature, in semiconductors
-14-
The density of electrons and holes can be expressed in terms of the

distance between EF and the band edges as follows:
 E  EF   E  Ev 
no  NC exp  C  po  NV exp  F  (1-11)
 k BTL  ,  k BTL 
where NV and NC are the effective density of states in the conduction band
and valence band, respectively. Also, kB is the Boltzmann constant and TL
is the semiconductor crystal lattice temperature.
It should be noted that the Fermi level (or chemical potential) of any two
solids in contact must be equal in thermal equilibrium.
1-4. Drift and Diffusion Currents in Semiconductors

The motion of free charge carriers (electrons and holes) in a solid
semiconductor is different from the motion in free space because of
collisions with the vibrating nuclei of the solid. If an electric field  is
applied to a semiconductor, the free electrons will be affected by a force
F=-e. and they begin to drift against the field, as shown in Fig. 1-13.
Fig. 1-13. Scattering and drift of electrons under the effect of electric field.
If the concentration of free electrons in the conduction band of the

semiconductor is n (electrons/cm3) and their average drift velocity is vn,
then the electron current density Jn (A/cm2) is given by:
Jn = - e n vn = n . (1-12a)
-15-
where n = - e n (vn /  ) is called the electrical conductivity of electrons.

Unlike metals the conductivity of semiconductors depends actually on
many ambient parameters such as temperature, illumination, etc.
Regarding the electrons in the valence band, it is more convenient to

consider the motion of holes instead. This is because the number of holes
is usually much less than the number of valence electrons. If we have a P-
type material with p holes (vacant bonds) per cm3 in the valence band,
then the current produced by the motion of valence electrons to fill in
these holes is equal to the current produced by the motion of holes, along
the field direction. Therefore, the hole current density Jp is given by:
Jp = e p vp = p  (1-12b)
where p = e p (vp /  ) is called the electrical conductivity of holes and

vp is their average velocity.
Fig. 1-14. Drift of electrons and holes under the effect of electric field.
It comes out from the above discussion that the steady-state carrier drift
velocity is proportional to the electric field. The constant of proportion-
ality between the carrier drift velocity vdrift and the electric field  is
called the carrier drift mobility and termed by 
vdrift = ±   with = e  / m* (1-13)
where m* is the effective mass of charge carriers and  is the mean time
between collisions. The mobility of electrons is denoted by n and the
mobility of holes is denoted by p.
-16-
Thus, we can write:
vn (drift) = - n  for electrons (1-14a)
vp (drift) = + p  for holes (1-14b)
The total drift current density is given by the sum of electron and hole
drift current densities:
Jdrift = Jn(drift) + Jp(drift) =   (1-15)
where  = n +p = enn + epp is the total conductivity of electrons and

holes of the semiconductor.
When there exists a spatial variation of carrier concentration (electrons or

holes), carriers will move from the location of higher concentration to the
location of lower concentration. This process is called the charge carrier
diffusion. The current resulting from the diffusion of electrons (or holes)
is proportional to their gradient such that:
Jn, diffusion = e Dn  n (1-16a)
Jp, diffusion = -e Dp  p (1-16b)
where the constants of proportionality Dn and Dp are called the diffusion

coefficients of electrons and holes, respectively. Note that in one-
dimension, the gradient operator is replaced by the differentiation d/dx.
Figure 1-15. Diffusion of electrons in a semiconductor.
-17-
According to Einstein relations, the carrier diffusion coefficient is

proportional to the carrier drift mobility such that:
Dn/n = VT , Dp/p = VT (1-17)
where VT = (kB TL/e) is the thermal voltage
When both carrier-concentration gradient and electric field are present in

a semiconductor, the resultant current is the sum of carrier-drift and
carrier-diffusion currents.
Jn = Jn, drift+ Jn, diffusion = en n + e Dn n (1-18a)
Jp = Jp, drift +Jp, diffusion = e p p  - e Dpp (1-18b)
The above current equations are the basis of the so-called drift-diffusion
model (DDM) of semiconductors.
-18-
1-5. Generation-Recombination Mechanisms in Semiconductors

When the thermal equilibrium state is disturbed in a semiconductor, by
the influence of external force (e.g. via an optical excitation), the charge
carrier densities (n, p) change from equilibrium values (no, po) so that
n = no +  n , p = po +  p (1-19)
where the quantities n and p are called the excess carrier concentr-
ations. Hence at non-equilibrium:
n.p  ni2 (1-20)
Both n and p may be positive (due carrier injection into the

semiconductor) or negative (due to carrier extraction from the
semiconductor). When there is an excess carrier concentration, the
semiconductor will try to restore its equilibrium state by endeavoring
carrier generation or carrier recombination processes.
At the thermal equilibrium state, the thermal generation rate (of electron-
hole pairs), gth, is compensated by a default recombination rate (of
electron-hole pairs), Ro, such that the net recombination rate U = Ro - gth
is null (zero) and there exists no excess carriers.
Figure 1-16. Generation & recombination mechanisms in a semiconductor. C.B

stands for the conduction band and V.B. stands for the valence band of the
semiconductor.
-19-
When n and p are negative, meaning that np < ni2 , then the thermal
generation mechanism gth (which takes place regardless of the presence
of excess carriers) will dominate the default recombination Ro to restore
the equilibrium state.
On the other hand, when n and p are positive, meaning that np > ni2,
then the recombination mechanism will dominate the thermal
generation. Therefore, the net recombination rate of electrons and holes is
given by:
n p
Un  Rn  gth  , U p  R p  g th 
n p (1-21)
where n and p are called the electron and hole lifetimes, respectively.
As shown in figure 1-8, the recombination of charge carriers, may be
direct (radiative) or indirect (non-radiative). In the former case, the
recombination is associated with emission of a photon with equivalent
energy of the energy gap. In the later case, the recombination, releases
smaller energy, which is transmitted to crystal lattice vibrations.
When a semiconductor is doped with impurities that produce profound

energy levels in the energy gap (like gold, Au), these levels will act as
trapping centers for carries. Therefore, carriers will prefer to transit for a
while at these trapping levels during their transitions between conduction
and valence bands. In such a case, the steady-state rate of indirect
recombination in the bulk of a non-degenerate semiconductor is given by
the following Shockley-Read-Hall expression:
np  ni2
U SRH  (1-22)
 po ( p  p1 )   no (n  n1 )
where no and po are the minority carrier lifetimes in heavily-doped semi-
conductors. They can be defined in terms of the density of traps Nt [cm-3]
and the capture rates of electrons and holes Cn, Cp [cm3/s] as follows:
1 1
 no   po  (1-23)
Nt Cno Nt C po
-20-
1-6. Continuity Equations

When the thermal equilibrium state in a semiconductor is disturbed, the
net recombination rate of carriers (U=R-G) is non zero. Therefore, the
density of carriers will change with time. The continuity equations for
electrons and holes in a semiconductor read:
n 1
 (Gn  Rn )  . J n (1-24a)
t e
p 1
 (G p  R p )  . J p (1-24b)
t e
where the electron and current densities, (Jn and Jp), can be expressed by
equations (1-16a) and (1-16b), respectively.
Figure 1-17. Charge continuity in a semiconductor.
-21-
1-7. Semiconductor Equations

By substituting the electron current density expression (1-16) into the
continuity equation (1-24) and assuming the electron mobility is constant,
we obtain the following equation for electrons in the x-direction:
 n   x n  2 npx
x

 t   Gn  Rn  x
 n n 
x
 n x   Dn
x x 2
(1-25a)
Similarly, the continuity equation for holes in the x-direction reads:
 p 

 t   Gp  Rp
x

x
 p p
 x
x
 p x
p
x
 Dp
 2 pnx
x 2
(1-25b)
In order to solve the above 2 equations in (n, p and x ), they must be

complemented by the Poisson equation which relates the carrier densities
n, p with the electric field x or potential  (x = -d/dx).
 2 e
.D   or  ( n  p  N d  N a ) (1-26a)
x 2

where  is the electric charge density, D = is the electric field

displacement vector1, or is the permittivity of the semiconductor and
r being its relative value. In 3-dimensions, the Poisson equation reads:
 2  
e

p  n  N d  N a  (1-27b)
When the density of trapping centers Nt in the semiconductor is

significant, it must be included in the Poisson equation, so that:
2  
e

p  n  N d  N a  N t  (1-27c)
Also the time variation of trap density could be described by an additional

continuity equation that must be added to the previous set of
semiconductor equations.
N t
 U p -U n = (G p  R p ) - (Gn  Rn ) (1-28)
t
1
In case of polar semiconductors, D = (+P), where P is the polarization vector.
. -22-
In addition, if the external bias and hence the electrostatic potential and
electric field are time variant, the total current density should be
appended by the so-called displacement current such that J = Jn+ Jp,+Jd,
where Jd = ∂ /∂t . When the variation of trap density with time is not
important (when no fast states are present in the semiconductor), then one
can set Up=Un in the above set of equations.
1-7.1. Semiconductor Equations in Homogeneous Semiconductors

The continuity equations (1-21a), (1-21b) together with the Poisson
equation (1-27) are called the semiconductor equations. When these
equations are coupled, with the current equations (1-16), they form the
so-called drift-diffusion model (DDM). In this model, we assume a
constant carrier temperature, which is equal to the lattice temperature.
Therefore, it should be noted that the current equations (1-16) are only
valid for homogenous semiconductor structures at low electric fields.
1-7.2. Semiconductor Equations in Heterogeneous Structures

There exist so many semiconductor devices which comprise different
semiconductor materials and heterojunctions. The central feature of
heterojunction devices is that the bandgaps of the participating
semiconductors are usually different. Figure 1-18 depicts the energy band
diagram of a heterojunction of two different semiconductors. The
alignment of energy bands of different semiconductors may be ruled by
the Anderson rule. According to this rule, the energy of the carriers of at
least one of the band edges must change as carriers pass through the
heterojunction. Therefore, in heterojunction devices and heterostructures
the semiconductor properties vary with position.
If a heterojunction is made between two materials for which there exists a

continuum of solid solutions, such as AlxGa1-xAs with 0<x<1, the
chemical transition need not occur abruptly. Instead, the heterojunction
may be graded over a specified distance. Therefore, the composition
parameter x might be some continuous function of the position. Such
structures are called graded bandgap semiconductors and have desirable
properties for many applications. Fig. 1-19 shows the energy band
diagram of a general heterostructure, with graded bandgap.
The Poisson equation in heterostructures, where the dielectric constant

changes with distance, = (x,y,z), should be written as follows:
.(   )     e( n  p  N d  N a ) (1-29)
-23-
Also, the current equations should be written as follows:
J n  e n n(    n )  eDnn (1-30.a)
J p  e p p(   p )  eD pp (1-30.b)
where the band structure parameters n, p are given by:
k BT  N c 
n  ln       r  (1-31.a)
e  cr 
N
k BT  N v  E  Ego
p   ln       r   g (1-31.b)
e  N vr  e
Here T is equal to the lattice temperature and Ego, Nvr, Ncr and Xr are
reference values at the edge of the semiconductor structure.
Fig. 1-18. Energy band diagram of a heterojunction.
-24-
E  e
 eχr Vacuum
Ecr level
 eχ
Ego Ec
Ef
Ev
V.B.
Evr
x
Fig. 1-19. Energy band diagram of a graded bandgap heterostructure.
1-8. Quasi - Fermi Levels

So far we have seen that the so-called Fermi level is related to the carrier
concentration by relations of the kind:
 E c  E fn   E i  E fn 
n  N c Exp    n i Exp   (1-32a)
 kB T   kB T 
and
 E fp  E v   E fp  E i 
p  N v Exp    ni Exp   (1-32b)
 kB T   kB T 
where Ei is the intrinsic Fermi level (almost midway in the energy gap).
At thermal equilibrium, there exist a single Fermi level for both electrons
and holes (Efn= Efp = Ef) such that the np product is equal to ni2.
Therefore,
Efn = Efp (in Thermal Equilibrium) (1-33a)
However, when the thermal equilibrium is disturbed by an external force

(e.g. by an electric field) then pn  ni2. Then we have two distinct Fermi-
energy levels Efn and Efp for electrons and holes (which are not equal):
Efn  Efp (in Non-equilibrium State) (1-33b)
And hence
-25-
 E fp  E fn 
n p ( Non  equilibrium)  ni2 Exp   (1-34)
 kB T 
The electron and hole Fermi levels Efn and Efp are usually called quasi-
Fermi levels. Figure 1-20 illustrates the splitting of the Fermi level into
two quasi Fermi levels in semiconductor regions in non-equilibrium
conditions. According to the above definitions, the carrier current
densities Jn and Jp are related to the Quasi Fermi levels gradient by the
following equations:
Jn = e n n  Efn (1-35a)
Jp = e p p Efp (1-35b)
In thermal equilibrium no current passes through the semiconductor such

that Jn = Jp = 0. Hence, at thermal equilibrium the gradient Efn Efp = 0.
Therefore, at thermal equilibrium both electrons and holes have a
constant Fermi energy level Efn = Efp = Ef, which does not change with
distance throughout the semiconductor sample. For instance, consider the
sample of n-type semiconductor, shown in figure 1-20, where its thermal
equilibrium state is locally disturbed in the middle by means of optical
generation. The single Fermi level Ef (above Ei) appears in the regions at
thermal equilibrium, which are far from the optical excitation.
Light Diffusion Region
n-type
Equilibrium Region
Non-equilibrium Region
C.B
Ec
Efn
Ef
Efp
V.B
Ev
Fig. 1-20. Fermi level splitting and quasi Fermi levels in excited semiconductors
-26-
However, at the region of optical generation, where the semiconductor is

out of thermal equilibrium, Ef is transformed to two distinct quasi-Fermi
levels Efn and Efp for both electrons and holes.
Notice that in n-type semiconductor, where electrons are majority and

holes are minority, Efn is not so far from Ef because the excess electron
concentration n = n - no is assumed much smaller than no (low level
injection). In contrary, we notice that Efp is far from Ef because the excess
holes concentration p = p - po is assumed much greater than po in this
case. It should be also noted that the concept of quasi-Fermi level implies
a displaced Maxwellian distribution function, and hence is only valid near
thermal equilibrium.
-27-
1-9. Noise in Semiconductor Devices (A)

Noise is any electrical signal present in a system or device other than the
desired signal. Thus, all semiconductor devices which allow the flow of
electrical current will exhibit noise. This occurs as some electrons will
have a random motion, causing fluctuating voltage and currents. The
significance of the noise analysis of a circuit is the limitation it places on
the smallest input signal that can be distinguished and treated. This
doesn‘t apply to internal distortion, which is a by-product due to
nonlinearities of electronic components.
As noise is random then it‘s mean value will be zero, hence we use mean
square values, which are measurements of the dissipated noise power.
The effective noise power of a source is measured in root mean square
of rms values.
(1-36)
Noise power spectral density – describes the noise content in a 1Hz

2
bandwidth. Units are V /Hz and denotes as Svn(f).
1-9.1. Modeling of Noise

In electronic circuits, the white thermal noise source may be represented,
using an equivalent input noise voltage vn and source resistance R, as
shown in figure 1-21.
Fig. 1-21. Noise source model
i. Thermal Noise
As shown in figure, the mean square voltage of the thermal (Johnson)
noise, produced by a resistor R, is given by:
-28-
vn2  4 k T .R.B (1-37a)
where k is Boltzmann's constant (1.38 × 10-23 J/K), T is the resistor

temperature in Kelvin, R is its resistance in Ohms and B is the bandwidth
(in Hz) over which the noise voltage is observed. Note that the mean
square noise voltage is sometimes referred to as the noise power PN. For a
given resistor, R, we can maximize this by matching (equalizing) the
noise source resistance and the subsequent system input resistance to get
the maximum available noise power,
vn2
PN   4 k T .B (1-37b)
4R
The Noise Power Spectral Density (NPSD) at any frequency is defined as
the noise power in a 1 Hz bandwidth at that frequency. Putting B =1 into
the above equation, we can see that Johnson (thermal) noise has a
maximum available NPSD of just kBT.
Sv (Thermal Noise) = PN/ B = k T [V2/Hz] (1-37c)
This means that Johnson noise has an NPSD which is white and doesn't
depend upon the fluctuation frequency. However the NPSD does fall at
extremely high frequencies because the total noise power is always finite.
ii. Shot Noise

Shot noise is due to discreteness of the electronic charge arriving at any
anode giving rise to impulses of current. The current noise power
spectrum density is given by:
SI (Shot Noise) = 2 e I [A2/Hz] (1-38)
where I is the average flowing current and e is the electronic charge. This
means the shot noise is white, with constant spectral density, over the
whole bandwidth of the system.
It worth noting that electronic noise levels are often quoted in units of
Volts per root Hertz [V/√Hz] or Amps per root Hertz. [A/√Hz]. In
practice, because noise levels are low, the actual units may be [nV/√Hz].
-29-
iii. Flicker Noise

Unlike Johnson or shot noise, which depend upon simple physical
parameters (the temperature and current level respectively), the flicker
noise (or 1/f noise) is strongly dependent upon the details of the particular
system. In fact the term ‗1/f noise‘ covers a number of noise generating
processes, some of which are poorly understood. For this form of noise
the NPSD, Sn, decreases with frequency approximately as follows:
Sn = 1/ f n (1-39a)
where the value of the index, n, is typically around 1 but varies from case
to case over the range, ½ < n < 2. The mean squared current fluctuation
in a device, due to flicker noise over a frequency range B, is sometimes
modeled as follows:
 I DC
a

i  k I  b
2
n
.B (1-39b)
 f 
where K1 , a and b are constants and IDC is the DC current flowing across
the device
Flicker noise is often characterized by the corner frequency fc between the

regions dominated by each type. MOSFETs have a higher fc than JFETs
or bipolar transistors which is usually below 2kHz for the latter. Flicker
noise is found in carbon resistors, where it is referred to as excess noise,
since it increases the overall noise level above the thermal noise level,
which is present in all resistors. In contrast, wire-wound resistors have the
least amount of flicker noise. Since flicker noise is related to the level of
DC, if the current is kept low, thermal noise will be the predominant
effect in the resistor.
The following figure depicts the power spectral density of the thermal
(Johnson) noise, the shot noise and the flicker noise. Note that the first
two types are white, and have a constant spectral density over the whole
bandwidth of any system.
-30-
Fig. 1-22. Spectral density of thermal, shot (white) and flicker noise.
1-9.2. Equivalent Input Noise

The noise performance of an electronic system (e.g., a semiconductor
device) is usually expressed in terms of an equivalent input noise signal,
which gives the same output noise as the device under consideration. The
following figure illustrates the input and output equivalent noise of a
system. The system is assumed to have two internal noise sources at its
input (vn and in).
Fig. 1-23. Input and output equivalent noise of a system.
1-9-3. Noise Figure and Noise Temperature

In electronic systems, the noisiness of a signal is specified by the signal-
to-noise ratio (S/N). The noise factor (F) of a given system (device or
circuit) is defined as the numerical ratio of signal-to-noise ratios (S/N) in
output and input of this system:
-31-
F = (S/N)in / (S/N)out (1-40)
The noise figure (NF) of a system is defined as follows:
NF = 10 log F = (S/N)in − (S/N)out (1-41)
where (S/N) ratios are in dB here. The noise factor of a system is related
to its noise temperature (Tn) via the following relation:
F = 1 + T n / To (1-42)
where To is the physical temperature of the system. Systems without gain

(e.g., passive attenuators) have a noise figure equal to their attenuation (in
dB) when their physical temperature is equal to T0.
1-9-4. Calculation of Noise Figure from Input Equivalent Noise.

When we know the internal structure of a device (like a transistor or an
amplifier), and its internal noise sources, we can calculate its noise figure
from the input equivalent noise.
veq2 veq2
F  (1-43a)
vs2 4k .T .Rs
For instance, the system shown in figure 1-22, will have a noise figure,
which is given by:
vn2  Rs2 .in2

F 1 (1-43b)
4k .T .Rs
where vn and in are the internal noise sources of the system.
-32-
1-10. Technology of Semiconductor Devices

Since the invention of the point-contact transistor (shown in figure 1-25),
and during about 50 years, so many processing techniques have been
introduced in the course of developing new semiconductor devices and
integrated circuits. We recapitulate here the most famous technologies
that have been developed in the past and those, which we employ today to
fabricate the semiconductor devices and integrated circuits. We start with
the famous methods for the preparation of crystalline silicon wafers.
Then, we illustrate the fabrication technology of electronic devices. We
chose the p-n junction as an example since it is the most important
building block in any semi-conductor device (and the oldest
semiconductor device at the same time).
Fig. 1-24. Schematic of the crystal puller, which is used for the preparation of
crystalline semiconductor wafers.
As shown in figure 1-25 first p-n junctions were made by the so-called
point-contact method. In such a method, a metal wire (a cat whisker wire)
is pressed onto the surface of a semiconductor. Then the junction was
formed by passing a pulse of high current through the wire and the
semiconductor. If the pulse is high enough, the wire is heated and some
of its atoms are diffused into the semiconductor to form a semiconductor
junction.
-33-
Metal wire (Whisker cat) Emitter Collector
p-type
n-type Base n-type Base
a) Point contact junction & point-contact transistor
Al or In Molten Button
n-type n-type n-type

p-type p-type
b) Alloy junction method
B
n n n
p p
n-type p-type
c) Growth junction method
diffusion Beveling
p p
n-type n-type n-type
d) Mesa diffused junction
SiO2 diffusion
n n
n
n+ n+
n+
e) Planar technology
Fig. 1-25. Semiconductor devices fabrication technologies.
Another similar technique, called the alloy junction method, was also
utilized in the past to form semiconductor p-n junctions. In this method, a
pellet containing acceptor-type impurities is placed upon an n-type
semiconductor crystal. The pellet and the crystal are then heated above
the eutectic temperature such that the pellet fuses or alloys into the
semiconductor to form a junction.
-34-
This method has been successfully used till the 1960's in mass production
of germanium diodes and transistors. In the early 1950s, p-n junctions
were also made by the grown junction method. Here, semiconductor
crystals are grown out of semi-conductor melt, which is initially doped by
a certain type of impurities.
Then, at a certain moment of the growth process, the doping material is

changed such that the rest of the pulled crystal becomes of different
impurity type. With the advent of solid-state diffusion (in 1956) and
chemical etching, new methods were then developed. Diffused junctions
are formed by exposing the surface of the semiconductor to a source of
opposite impurity type. Under the effect of high temperature, the
impurities diffuse into the semiconductor and a junction of controlled
depth can be obtained.
In the MESA junction method, the junction is formed by solid-state

diffusion. Then, a part of the surface of the junction is etched out by
chemical agents. This process reduces surface currents and improves the
junction breakdown characteristics.
With the discovery of masking properties of thin SiO2 and Si3N4 films, a
better control over the lateral geometry of the diffused junctions is
achieved. Such masking or insulating layers do not permit the impurities
to diffuse into the underlying semiconductor region over which they are
deposited. In the early 1960`s, the planar technology was introduced in
conjunction with the monolithic integrated circuits. Since then, the planar
technology has been the principal method in the semiconductor industry.
The planar technology involves many processes such as epitaxial growth,

oxide masking, solid-state diffusion and metallization. The integrated
circuits implemented by planar technology are sometimes called
monolithic integrated circuits, because the entire circuit is usually
integrated in the same chip. Figures 1-26 depicts the details of the planar
technology, for P-N junction diodes.
-35-
Fig. 1-26. Planar technology of P-N junction diodes.
-36-
1-11. Summary
Transistors, diodes, integrated circuits and many solid-state electronic

devices have semiconductor technology in common. In this chapter we
reviewed the basics of conductors, insulators and semiconductors physics.
In terms of electricity there are two main classes of material: namely:

conductors and insulators. Metals are all conductors of electricity, and a
number of other substances also conduct it to varying degrees. Other
substances have a large energy gap and do not have free electrons moving
around the lattice. Electrons are firmly held within their atoms and cannot
escape easily. Accordingly when a potential is placed across the
substance very few electrons will move and very little or no current will
flow. These substances are called non-conductors or insulators.
As semiconductor is neither a true conductor nor an insulator, but half

way between. Generally speaking, semiconductors have energy gaps in
the order of 1eV. A number of materials exhibit this property, and they
include germanium (Ge), silicon (Si), gallium arsenide (GaAs), and a
variety of other substances.
The conductivity of semiconductors changes very significantly by adding

small amounts of impurities. Doped semiconductors are called extrinsic
semiconductors, and their conductivity depends on the type of added
impurities. If traces of impurities of 5th-valent materials (having five
electrons in their outer shell) are added they increase the number of
electrons in the crystal lattice of the semiconductor. As this type of
semiconductor materials has extra electrons in the lattice it is called N-
type semiconductor. Typical impurities that are used for doping N-type
semiconductors are phosphorous (P) and arsenic (As). Such impurities are
called donors. It is also possible to dope semiconductors with trivalent
elements. As this type of material has electrons missing it is known as P-
type material. Typical impurities used for doping P-type material are
boron (B), and aluminum (Al). Such impurities are called acceptors.
n-type semiconductor p-type semiconductor

-37-
The Fermi level (EF) is a reference energy level, which is typically used
in the energy band diagram to illustrate the type of semiconductors and
how they are populated with charge carriers. It should be noted that the
Fermi level (or chemical potential) of any two solids in contact must be
equal in thermal equilibrium.
At the end of this chapter we provide a brief outline of the basic

technological processes involved in the fabrication of modern
semiconductor devices and integrated circuits.
-38-
1-12. Problems
1-1) What determines whether a substance is an insulator, semiconductor,
or conductor?
1- The separation between the valence and forbidden bands
2- The separation between the conduction and valence bands
3- The separation between the conduction and forbidden bands
4- The separation between the forbidden band and the energy gap
1-2) When an insulator is compared to a pure semiconductor, (a) which

one requires the least energy to drift an electron and (b) from which band
1. (a) Semiconductor (b) Valence band
2. (a) Insulator (b) Valence band
3. (a) Semiconductor (b) Energy gap
4. (a) Insulator (b) Energy gap
1-3) Electrons are never found in which of the following bands of an

intrinsic semiconductor?
1. Energy band
2. Valence band
3. Energy gap
4. Conduction band
1-4) The semiconductor doping impurities— arsenic, antimony, and

bismuth—are classified as what type of impurities?
1. Active
2. Neutral
3. Trivalent
4. Pentavalent
1-5) Consider the semiconductor slap shown in figure below. The slap is
illuminated from one side such that excess hole concentration at the side
of the semiconductor is a constant and equal pn(0). It is required to
calculate the spatial distribution of excess holes across the semiconductor
slap pn(x), assuming low-level injection. Assume also pn=0 at the other
end of the sample (at x=W). It is required to calculate the hole current
density Jp at x= W.
i) Show that the continuity equation for holes for x > 0 (where there is no
generation) is given by:
-39-
 pn p  pno  2 pn
 - n  Dp
t p x 2
ii) Show that the above equation can be put in the following form in
steady state, where dpn/dt = 0:
 2 pn pn  pno  2 pn pn

 
x 2 Dp p or x 2 L2p
where Lp is the hole diffusion length and given by: Ln  Dn n

iii) Show that the solution of the above differential equation with the
boundary conditions: pn(x=0)=pn(0) and pn(x=W)=0, is as follows:
pn ( x )  pn ( x )  pno  pn ( 0)

sh  
W x
Lp
sh 
W
Lp
1-5) Consider the semiconductor detector shown in figure below. The

semiconductor detector is homogeneously illuminated. It is required to
calculate the concentration of electrons across the semiconductor slap
n(t), assuming low-level injection. Assume also n=0 at the two
contacts of the sample (at x=9, L). It is required to calculate the electron
current density Jn at a given instant t. If the electric field is E, then prove
that the hole current is given by:
-40-
or
Such that the total current is proportional to the power of incident light.
Hint: The recombination rate of electrons is given by:
where  is the electrons lifetime and no is the equilibrium electron

concentration. At steady state R= G such that:
where the number of generated electron-hole pair is: Ptot/ hv
-41-
1-13. References
[1] Jacob Millman, Christos C. Halkis, ―Integrated Electronics, Analog

and Digital circuit and systems‖, Tata McGrow-Hill publishing Company
Limited, New Delhi, 1991.
[2] Michael Shur, Introduction to Electronic Devices, John Wiley &

Sons; January 1996.
[3] Simon M. Sze, Semiconductor Devices. Physics and Technology.

John Wiley Inc. 2002, 2d edition.
[4] A. P. Sutton, Electronic Structure of Materials, Clarendon Press,

Oxford, 2004.
[5] M. H. EL-SABA, Electronic Engineering Materials, Hakim Press,

Cairo, 2010.
-42-
Fundamentals of Electronic Devices Chapter 2
P-N Junctions
Contents:
2-1. Chapter Overview and Learning Objectives

2-2. Formation of a P-N Junction
2-3. Operation of the P-N Junction
2-3.1. Forward Bias
2-3.2. Reverse Bias
2-4. Terminal (I-V) Characteristics of Ideal P-N Junctions
2-5. Characteristics of Real P-N Junctions
2-5.1. Recombination in the Space Charge Region
2-5.2. High Injection Current
2-5.3. Avalanche Breakdown
2-6. Capacitance of a P-N Junction
2-7. Circuit Model of a P-N Junction Diode
2-7.1. Large-signal (DC) Circuit Model of a P-N Junction
2-7.2. Small-signal (AC) Circuit Model of a P-N Junction
2-8. Quiescent Point of a P-N Diode
2-9. Transient Behavior of a P-N Junction
2-10. Applications of the P-N Junction Diode
2-10.1. Rectifier
2-10.2. Peak Detector
2-10.3. Clipping Circuits
2-10.4. Clamping Circuits
2-10.5. Voltage Multipliers
2-10.6. Temperature Sensors
2-11. P-N HeteroJunction Diodes
2-12. Special Diode Structures
2-12.1. Zener Diode
2-12.2. P-I-N Diode
2-12.3. Schottky Barrier Diode (SBD)
71
2-12.4. Step-Recovery Diode

2-12.5. IMPATT Diode
2-12.6. Tunnel Diode
2-12.7. Resonant Tunnel Diode (RTD)
2-12.8. Solar Cells
2-12.9. Photodiode
2-12.10. Light Emitting Diode (LED)
2-12.11. Laser Diode
2-13. Laboratory Testing of P-N Junction Diodes
2-14. Diode Ratings
2-15. Computer Simulation & Modeling Parameters
2-16. Summary
2-17. Problems
2-18. Practical Assessment
2-19. References
72
P-N Junctions

The P-N junction is a basic structure in semiconductor technology. It has
the valuable property that electrons only flow in one direction across it
and as a result it acts as a rectifier. It is also a crucial element in
transistors and other semiconductor devices and this makes it one of the
most important components in semiconductor industry.
Upon completion of this Chapter, the student will be able to answer the
following questions and understand:
What happens at the P-N junction formation when a P-type and an N-

type region are implemented in one single crystal and get in touch?
Why does a space charge layer appear at the P-N junction?
What role plays the so-called built-in potential?
How to control the space charge layer and the space charge
capacitance?
What phenomenon is behind a minority carrier injection current?
Why the current-voltage characteristics of the P-N junction takes the
well known exponential form
Why the P-N junction conducts in one direction (the forward bias)
and blocks current in the other direction (reverse bias) and behaves as
a rectifier in electronic circuits.
How is the appropriate circuit models of a P-N junction can be
applied correctly?
Know the phenomena dominate the switching of a diode,
Draw and explain the turn-on & turn-off characteristics of a diode,
Interpret manufacturer datasheets and ratings of a diode,
Differentiate between different packages of diodes,
Know how to test a diode, using a simple avometer,
How other forms of junction devices, such as heterjunction diodes,
solar cells and laser diodes, can be made and how they operate, under
different bias conditions?
73
2-2. Formation of a P-N Junction

The P-N junction is composed of two attached semiconductor pieces, one
of p-type and another of n-type. Therefore, one end has an excess of
electrons whilst the other has an excess of holes. When the two pieces are
brought in contact, the electrons will fill the holes around the contact
region and there are no free holes or electrons. This means that there are
no mobile charge carries (electrons and holes) in this region. As this area
is depleted of mobile charge carriers it is called as the depletion region.
This region, which extends on both sides of the P-N junction, is also
known as the space-charge region, because of its charge of fixed ions.
Fig. 2.1. Formation of a P-N junction.
Fig. 2.2. The P-N junction symbol and component shape.
74
Note 2-1. History of the P-N Junction

The history of P-N junction diodes started long time ago. Around the
turn of the 20th century semiconductors were quite common as detectors
in crystal radio receivers, in a device called "cat's whisker". A crystal set
or cat's whisker receiver was a very simple radio receiver, popular in the
early days of radio. It needs no battery and runs on the power received
from radio waves by a long wire antenna. It gets its name from its most
important component, a crystal detector, originally made with a piece of
crystalline mineral stone such as galena (lead sulfide). This component is
now called a diode. The galena detectors were troublesome, however,
requiring the operator to move a small tungsten spring (the whisker) on
the surface of a galena stone until it suddenly started working. Then, over
a period of a few hours or days, the cat's whisker would stop working and
the process should have to be repeated. At that time, their operation was
completely mysterious. After the introduction of the more reliable
vacuum tube based radios, the cat's whisker systems quickly disappeared.
The cat's whisker is actually a primitive example of a special type of
diode still popular today, called a Schottky diode.
The next evolution of the "point contact diode" was to enclose the
structure in a glass cylinder, preventing subsequent movement. Galena
crystal was replaced with a crystal of germanium, mounted on a metal
base. A thin tungsten wire was then pressed into the crystal, forming a
reliable point contact diode, suitable for mass production.
75
However, during World War II, radar research quickly pushed radar
receivers to operate at ever higher frequencies and the traditional tube
based radio receivers no longer worked well. The introduction of the
cavity magnetron from Britain to USA in 1940 during the Tizard Mission
resulted in a pressing need for a practical high-frequency amplifier. On a
whim, Russell Ohl of Bell Laboratories decided to try a cat's whisker. At
this time they had not been in use for a number of years, and no one at the
labs had one. After hunting one down at a used radio store in Manhattan,
Ohl found that it worked much better than tube-based systems. Ohl
investigated why the cat's whisker functioned so well. He spent most of
1939 trying to grow more pure crystals. He found that with higher quality
crystals their behavior is lost. One day he found one of his purest crystals
nevertheless worked well, and interestingly, it had a clearly visible crack
near the middle. However as he moved about the room trying to test it,
the detector would mysteriously work, and then stop again.
After some study he found that the behavior was controlled by the light in
the room–more light caused more conductance in the crystal. Ohl invited
several other people to see this crystal, and Walter Brattain immediately
realized there was some sort of junction at the crack. Further research
cleared up the remaining mystery. The crystal had cracked because either
side contained very small amounts of impurities, Ohl could not remove.
One side of the crystal had impurities that added extra electrons and made
it a conductor. The other had no impurities that made it almost insulator.
Because the two parts of the crystal were in contact with each other, the
electrons could be pushed out of the conductive side which had extra
electrons (the emitter) and replaced by new ones provided (by a battery)
where they would flow into the insulating portion and be collected by the
whisker filament (the collector). However, when the voltage was reversed
the electrons being pushed into the collector would quickly fill up the
holes, and conduction would stop almost instantly. This junction of the
two crystals created a solid-state junction diode, and the concept soon
became known as rectification.
76
2-3. Operation of the P-N Junction

After the formation of the depletion region, an internal electric field
(called the built-in field) occurs and prevents any further motion of
electrons or holes to or from each side of the P-N junction. After a while,
the P-N junction reaches to thermal equilibrium and no current flows,
unless an external voltage is applied. We now calculate charge , electric
field ζ, and potential , across the P-N junction.
Fig. 2-3. Illustration of the P-N junction energy bands in thermal equilibrium.
First we find the band offset, E = eo, from the equilibrium conditions:
eO = Eg - [ (EC – EFn) + (EFp – EV) ] (2-1a)

= Eg - kBT ln (NV /Na ) - kBT ln (NC /Nd)
Substituting Eg = kBT ln (NC NV / ni2) yields:
O = VT ln (Na Nd / ni2) (2-1b)
where VT = kBT/e is the thermal voltage. The potential difference O is

sometimes called the built-in voltage (and hence termed Vbi). This is the
difference in the electrostatic potential between the two sides of the
junction at equilibrium. The variation of the potential (x) and the electric
field (x)across the junction can be calculated from the profile of Nd and
Na as shown in figure 2-3. We know that the electric field is equal to the
negative gradient of the electric potential. In one dimension, we have:
 = - d /dx (2-2)
77
If we assume an abrupt junction then the charge distribution (x) will

have the form:
(x) = - e Na - Wp < x < 0

= + e Nd 0 < x < Wn (2-3)
where Wp and Wn are the widths of the depletion region on the p-side and
n-side. The electric field density satisfies Gauss’ law:
.D = .(ζ) =  (2-4a)
where D=ζ and the electrical permittivity =os. In the 1-dimensional

case, we have: .ζ  dζ/dx, such that:
dζ /dx = /os (2-4b)
Substituting the charge density from (2-3) yields:
d ζ /dx = - e Na /os - Wp < x < 0

= + e Nd /os 0 < x < Wn
= 0 elsewhere
(2-5)
The boundary conditions are ζ=0 for x<-Wp and x>Wn since the junction
is in equilibrium. The solution of (2-5) is therefore,
ζ = - e (Na /os).(x + Wp) - Wp < x < 0

= + e (Nd /os).(x – Wp) 0 < x < Wn
(2-6)
Furthermore, ζ must be continuous at x = 0, which gives
Na Wp = Nd Wn (2-7)
The plot of ζ(x) is shown in figure 2-4. As seen from figure, the above
equation is simply the condition of electrical neutrality of the whole
depletion region. Equations (2-2) and (2-6) together give (x)
(x) = e (Na /2os).(x + Wp )

2
- Wp < x < 0
= o – e (Nd /2os).(x – Wn )2 0 < x < Wn
(2-8)
78
Fig 2-4. Distribution of charge carriers, electric field and electrostatic potential
across a P-N junction in equilibrium
79
Since (x) must be continuous at x=0; we get a second relation between

Wp and Wn. Therefore, the built-in voltage, Vbi, is also given by:
Vbi = o = p +n = (e /2os).(Na Wp2 + Nd Wn2) (2-9)
The variation of  with x is shown in figure 2-4(e). Recall that the built-in
field is already known from (2-1). As stated, equations (2-1) and (2-9)
can be solved for the values of Wp and Wn in equilibrium; such that,
1/ 2
 2 o s Na o 
Wn   
(2-10a)
 d a
eN ( N  N d 
)
1/ 2
 2  N  
Wp   o s d o  (2-10b)
 eNa ( Na  Nd ) 
In non-equilibrium, the depletion region width changes with applied bias
Va as follows:
1/ 2
 2  N (V  Va ) 
Wn   o s a bi 
(2-11a)
 eN d ( N a  N d ) 
1/ 2
 2  N (V  Va ) 
Wp   o s d bi 
(2-11b)
 eN a ( N a  N d ) 
Evidently, the space charge region width decreases with forward bias
(when Va is positive) and increases with reverse bias (when Va is
negative).
Example 2-1.
Consider an abrupt silicon P-N diode which consists of a P-type region
containing 1016 cm-3 acceptors and an N-type region containing also 1016
cm-3 acceptors in addition to 1017 cm-3 donors.
i) Calculate the thermal equilibrium density of electrons and holes in the
P-type region as well as both densities in the n-type region.
ii) Calculate the built-in potential of the P-N diode.
iii) Calculate the built-in potential of the P-N diode at 100°C.
iv) Calculate the depletion region width at -2.5V reverse bias.
80
Solution
i) The hole and electron density in the P-type region are:
p = Na = 1016 cm-3, n = ni2/ p = 1020/1016 = 104 cm-3.
The electron density and hole density in the N-type region are:
n =Nd -Na =1017-1016=9x 1016 cm-3, p= ni2/ p=1020/9 x1016=1.11 x103 cm-3
ii) At 300 K, we have Vt = kBT/e = 25.84 mV and ni = 1010 cm-3. The
built-in potential is then given by: Vbi = Vt ln(1016 x 9 x 1017/ni2) = 0.77 V
iii) At 100°C, we have: Vt =kBT/e =32.14 mV and ni =8.55 x 1011 cm-3.
Then the built-in potential is given by: Vbi = Vt ln(1016 x 9 x 1017/ni2) =
0.673 V
iv) The depletion region width is given by W=Wn+Wp. The total depletion
region width is: W = [2 x 11.9 x 8.854 x 10-14 (Vbi - Va)/(1.6 x 10-19)
(1/1016 + 1/(9 x 1016))]1/2 =0.72 m. Wn = W Na/ (Na + Nd) =0.08 m and
Wp = W- Wn = 0.64 m
2-3.1 Forward Bias

If a forward voltage is applied such that the p-type area becomes positive
and the n-type becomes negative, holes are attracted towards the negative
side and diffuse across the depletion layer. Similarly electrons move
towards the positive end and diffuse across the depletion layer. Even
though the holes and electrons are moving in opposite directions, they
carry opposite charges and represent a current flow in the same direction.
In order to calculate the forward current, we solve the minority carrier
diffusion equation in the quasi-neutral regions of the P-N junction
(where the electric field ζ=0) and then determine the currents from the
continuity equations.
In steady state (where ∂pn/dt=0), the continuity equation of excess holes
in the quasi-neutral region of the N-side reads:
 2 pn pn  pno  2 pn pn

  (2-12a)
x 2 Dp p or x 2 L2p
where Dp is the holes diffusion coefficient, p is the holes lifetime and Lp

=√(Dpp) is the holes diffusion length. The solution of the above diffusion
equation (of holes) in the quasi-neutral region of the N-side gives:
 x' 
pn ( x ')  pn (0').exp    (2-12b)
 Lp  for x ≥ 0’
 
81
Fig.2-5. Illustration of a forward-biased P-N junction
According to the Boltzmann relation, at depletion religion boundaries, we

may substitute:
 V   ni2   Vd  
pn (0')  pno exp  d  1  exp   1 (2-12c)
  VT   N d   VT  
So that the distribution of execs hole concentration in the n-side becomes:
ni2   Vd    x' 
pn ( x ')  exp   1 .exp    for X ≥ 0’ (2-12d)
Nd   VT    Lp 
Substituting pn into the continuity equation of holes (Jp = - eDp dpn/dx )
yields:
ni2 Dp   Vd    x' 
Jp  e exp   1 .exp    (2-13a)
Lp Nd   VT    Lp 
Similarly, the solution of the diffusion equation (of electrons) in the
quasi-neutral region of the p-side yields:
ni2 Dn   Vd    x" 
Jn  e exp  
 1 .exp   (2-13b)
Ln Na   VT    Ln 
where Ln = √(Dnn) is the electrons diffusion length. The figure 2-16
82
depicts the distribution of excess electrons (np) and excess holes (pn) in
the quasi-neutral regions of the P-N junction. The current distribution of
electrons (Jn) and holes (Jp) is shown in the subsequent figure 2-7.
Figure 2-6. Schematic representation of the excess carrier concentration in quasi-

neutral regions.
In steady state, the total current density J = Jn+Jp is constant across the P-
N junction (since .J =dJ/dx =0). The total current can be calculated by
summing the electron and hole currents at the edges of the quasi-neutral
regions, i.e. Jn(0”) and Jp(0’). Inside the depletion region, where we
neglect the recombination current, both the electron and hole currents are
considered constants (.Jn=.Jp=0,) and the total current density is then
given by:
 ni2 Dn ni2 Dp    Vd  
J  e   exp   1
(2-14)
 Ln Na Lp Nd
    VT  
Figure 2-7. Schematic representation of the diode current distribution, in forward

bias, with no recombination-generation in the space-charge region
83
2-3.2. Reverse Bias

If a voltage is applied across an ideal P-N junction in the opposite sense,
only a trivial reverse saturation current will flow. The reason for this is
that the holes are attracted towards the negative potential that is applied to
the P-type region. Similarly the electrons are attracted towards the
positive potential which is applied to the N-type region. In other words
the holes and electrons are attracted away from the junction itself and the
depletion region increases in width. Accordingly almost no current flows.
Figure 2-8. Illustration of a reverse-biased P-N junction.
The following figure depicts the carrier concentration in the quasi neutral
regions of the P-N junction in forward and reverse bias.
Figure 2-9. Carrier distribution across P-N junction, in forward and reverse bias.
84
We can make use of equation (2-14) to calculate the reverse saturation

current, which flows in this case, by substituting Vd with a sufficient
negative value, such that exp(-Vd /VT) ≈ 0 and therefore:
 ni2 Dn ni2 Dp 
J  J o  e    (2-15)
 Ln Na Lp Nd
 
2-4. Terminal (I-V) Characteristics of P-N Junctions

The most important property of a P-N junction is its current-voltage
characteristics (Id versus Vd), as shown in figure 2-10. As we have seen in
the last section, the derivation of the I-V characteristics of the P-N
junction requires the solution of diffusion equation of charge carriers. The
result is:
  Vd  
I d  I o exp   1 (2-16a)
  VT  
where the reverse saturation current Io is given by:
Io  e.A.   (2-16b)
 Ln Na Lp Nd
 
Here A is the area of the junction (cross section) and the thermal voltage
VT =kBTL/e is about 26mV at TL =300K. In the forward direction of the
diode I-V characteristics (forward bias), very little current flows until a
certain voltage is reached. This voltage is called the cut-in voltage (V). It
represents the work that is required to enable the charge carriers to cross
the depletion layer. This voltage varies from one type of semiconductor to
another. For Ge diodes it is around 0.3V and for silicon diodes it is about
0.6V. In fact it is possible to measure a voltage of about 0.6V across
small current silicon diodes when they are forward biased. Power rectifier
diodes normally have a larger voltage across them due to the fact that
there is some Ohmic resistance in the silicon. From the diagram it can be
seen that only a small amount of current flows in the reverse direction
(almost constant). In normal circumstances it is very much smaller than
the forward current. Typically it may be in the order of 10-12A (pA).
However the reverse current increases at higher temperatures. This
reverse current results from the diffusion of minority carriers (electrons in
the P-type region or holes in an N-type region).
85
Fig. 2-10(a). Schematic of the I-V characteristics of a P-N Junction diode
Note that the reverse saturation current Io is temperature-dependent. In

fact, Io is proportional to the square of intrinsic carrier concentration of
the semiconductor (ni2), which is temperature dependent. Therefore, Io
increases approximately for 7% in Si for each temperature degree
(doubles each 10 degrees increase).
Fig. 2-10(b). Effect of temperature on the I-V characteristics of a P-N Junction diode
2-5. Characteristics of Real P-N Junctions

The Shockley diode characteristics in equation (2-16) are derived for
ideal P-N junctions. The real P-N junction exhibits some discrepancies
from the ideal case. For instance, we assume low level injection in the
ideal junction characteristics and we neglect the space-charge recombine-
86
ation current. We also assume no electric field inside the neutral regions
of the P-N junction (and hence no Ohmic voltage drop). These effects
lead to modified I-V characteristics of real P-N junctions, as follows:
  V  
I d  I o exp  d   1 (2-16c)
   VT  
where  is called the junction ideality or emission factor (1 <  < 2). On
the other hand, we also neglected the high reverse field effects, which
lead to avalanche breakdown at high reverse bias.
2-5.1. Space-Charge Recombination Current

So far we neglected the recombination current in the space charge region.
This current is dominant at low forward villages. The recombination
current in the space charge region of a P-N junction diode is given by:
Wp Wn   Vd 
J r  12 eni    exp  (2-17a)
  n  p   2VT 
where n and p are the carriers (electrons and holes) mean lifetimes in the
space charge region. Also, Wn and Wp are the widths of space charge
region in the two sides of the P-N junction. This current should be
considered (added to the diffusion currents) in the forward diode current.
In reverse bias, we have the counterpart thermal generation current, in the
space charge region, which may be expressed as follows:
W 
J g  eni . 
(2-17b)
  g 
where W= Wn + Wp is the space charge region width and n is the intrinsic
lifetime (gno +po) in the space charge region. This current should be
considered (added to the diffusion current) in the reverse saturation
current. Note that the space charge region width is proportional to the
square root of the applied voltage, as illustrated by equation (2-11).
Example 2-2:
Calculate the reverse saturation current of a Silicon P-N Junction with
Nd = 3x1016 cm-3, Na = 1017 cm-3, n = p = 1 s, Dn=20cm2/s, Dp =8cm2/s.
87
Solution:
The diffusion lengths are: Lp = √(pDp) = 28 m, Ln =√(nDn) = 43m
For the reverse bias of 1V, the depletion width W= 0.26µm
The diffusion current density is about 10-12 A/cm2
The generation current density is about 10-9 A/cm2
Note that the generation current is several orders of magnitude larger than
the diffusion current, under reverse bias. Indeed, this is true in Si P-N
junctions. For Ge P-N junctions, the two currents are comparable.
2-5.2. High Injection Current

At high currents of the P-N junction, the density of injected carriers, from
one side to another, may be comparable or even higher than the
background doping concentration. In p+-n junction, the diode current may
be expressed as follows at sufficient high injection level:
J = 2e (Dp / Lp) ni exp (Vj /2VT) (2-18)
where Vi is the part of applied bias, across the space-charge region of the
P-N junction. In fact, the total applied bias across the P-N junction diode
(between the cathode and anode contacts) Va is equal to Vj in addition to
the Ohmic drops across the quasi-neutral regions and contacts. The figure
2-10 depicts the forward characteristics of a real silicon P-N junction.
Fig. 2-10(a). Forward characteristics of a real P-N Junction diode
88
Fig. 2-10(b). Forward characteristics of Si, Ge and GaAs P-N Junction diodes
Note that  ≈2 at high injection level, where Va > 0.5V. When the applied
bias is greater than 0.8V, the Ohmic drops across the quasi-neutral
regions should be considered and added like a series resistance. Note that
the onset of the high injection regime depends on the semiconductor
material, which is utilized to fabricate the P-N junction
2-5.3. Avalanche Breakdown

At sufficient high reverse bias (near a certain threshold, called the
breakdown voltage VB) the reverse current increases abruptly. This
abrupt increase in reverse current is due to the multiplication of high
energy charge carriers, by impact ionization, in the depletion region.
Impact ionization is characterized by a parameter called the impact
ionization coefficient (n and p for electrons and holes, respectively). It
is logic to expect that the ionization coefficients would be a function of
carrier energy and the electric field. For instance, one may simply
consider n = p = 1.8 x 10-26 ζ 7 in silicon. When increasing the reverse
bias voltage, the reverse current gets multiplied by the avalanche
multiplication process. The reverse current multiplication factor (M),
across the space charge region is related to the ionization coefficients ()
by the following relation (for electrons).
89
(2-19a)
Similarly, the multiplication factor for holes is given by:
(2-19b)
Here xn and xp are the space charge widths in the N- and P-sides
(equivalent to Wn and Wp). When the avalanche multiplication becomes
large (M∞), a very large reverse current begins to flow. Consequently,
the device may breakdown, unless a series resistance is connected to limit
current. The expression for multiplication factor shown above suggests
that multiplication can be empirically modeled as follows:
M = [1 – (V/VB)n ]-1 (2-19c)
The exponent n depends on the P-N junction structure (n≈4 for abrupt
silicon P+-N junction).
Fig. 2-11. Multiplication factor in silicon diode (APD) as a function of voltage,
The breakdown criteria (VVB and M∞) may be simply written as

follows, when n = p = eff :
∫ aeff .dx = 1 (2-19d)

90
where the integration is taken along the space-charge region (-xn > x > xp).
According to Fulop, the effective impact ionization coefficient is given by
aeff .= ao ζ7 (2-19e)
For silicon we have, ao is about 1.8x10-38 cm6/V. This law is useful to

derive a closed-form of the breakdown voltage of P-N junctions.
Fig. 2-12. Illustration of the impact ionization process and breakdown in P-N junctions
Fig. 2-13. Impact ionization coefficient in silicon as a function of electric field,
For Si, the maximum electric field at breakdown is then given by:
7/8
ζc = 4010 x NI (2-20a)
91
Also, the space charge region width at breakdown is given by:
WB = 2.67 x 1010 NI -7/8 (2-20b)
The breakdown voltage of an abrupt P-N junction may be then expressed

as follows:
VB = 60 (Eg /1.1)3/2 (NI /1016)-3/4 (2-21)
Here NI is the doping concentration of the low-doped side of the P-N

junction, where the depletion region has a wider extension. The following
figure depicts the breakdown voltage of abrupt P-N junctions of different
semiconductors, as a function of doping. Note that the above relation is
only valid for long abrupt P-N junctions, where the low-doped side is not
entirely depleted. As the depletion region width increases with applied
reverse voltage, it is desirable to increase the diode base length in order to
have a high breakdown voltage. However, increasing the base width will
increase the Ohmic drop across the P-N junction in forward bias.
Fig. 2-14. Breakdown voltage of abrupt P-N junction, as a function of doping.
In order to cope with this problem, the low-doped base region of the
diode is usually followed by a highly doped layer, before the contact
region. If the diode base layer is completely depleted the space charge
region becomes trapezoidal, as shown in figure 2-15. In this case, the
92
diode is called a punch-through diode. Therefore, the diode can support

more applied reverse bias, without need to increase the base width.
The breakdown of a punch-through diode is related to the breakdown
voltage of a long (abrupt junction) diode, VB, by the following relation:
VBPT = 2VB (Wb/W).[ 1 - ½(Wb/W ) ] (2-22)
where W is the depletion region width, as given by equation (2-11), and

Wb is the base length of the punched-through diode.
Fig. 2-15. Long diode & punch-through diode and their field distribution at high
reverse bias
The above discussion is valid for one-dimensional diodes. Such one
dimensional junction diodes can be obtained by crystal growth or by
beveling the diffusion junction sides. The beveled P-N junction structure
is sometimes called the MESA diode.
In planar technology, the diffused junctions will have either a cylindrical

or spherical sides. As the potential lines become closer near the junction
corners, the electric field is higher at the junction sides and the
breakdown takes place there, at voltage well below the values calculated
for one-dimensional diodes. The relative breakdown voltage (VBC/VB) of
cylindrical and spherical junctions, as a function of the curvature (rj/W) is
shown in figure 2-16.
93
Fig. 2-16. Planar P-N junction and doping profile
For instance, the relative breakdown cylindrical junction voltage

(with respect to plane abrupt junction) may be expressed as follows:
(2-23)
Fig. 2-17. Relative breakdown voltage of cylindrical and spherical Silicon junctions
(with respect to plane abrupt junction).
2-6. Capacitance of a P-N Junction

We have seen so far that there is a charge separation in the transition
region of a P-N junction. This transition region behaves like a capacitor,
and the capacitance is given by:
1/ 2
 e o  s  N a .N d
 o A 
CT   A.    (2-24a)
W 2
 biV  V 
a  Na  Nd 

where A is the cross section area of the P-N junction and the transition
region width W = Wn+Wp. Therefore, the capacitance can be varied by
changing the applied voltage (Va). In practice, reverse bias is
94
needed so that the current flow is small. The P-N junction device, which
is used as a voltage-variable capacitor, is known as a varactor diode. The
capacitance of a reverse-biased P-N junction is sometimes called the
transition capacitance. The transition capacitance of an abrupt P-N
junction may be put in the following form:
CT 
CTo  o s A
with CTo  (2-24b)
V  2 o s  Na  Nd 
1   a    Vbi
 Vbi  e  N a .N d 
For instance, if we have a Si diode with cross section A=10-3 cm2, Na =

1018 cm-3; Nd = 1015 cm-3, s= 11.7, Vbi= 850 mV, then CTo 10pF.
In forward bias, one can also observe another capacitance called diffusion
capacitance, due to excess stored charges, Qs, across the two sides of the
P-N junction. The diffusion capacitance of a forward-biased P-N
junction, Cd, is given by:
dQs dQs dI d  a
Cd   .  (2-24c)
dVd dId dVd rd
where rd = dVd/dId is the forward dynamic resistance of the P-N junction
and a = Qs/Id is the average lifetime of minority carriers, in the two sides
of the junction. The following figure depicts the variation of the junction
capacitance (Cj=CT+Cd) as a function of the applied voltage. As shown in
the following figure this variation depends on the diode doping profile.
95
Fig. 2-18. Transition and diffusion capacitances of a P-N junction
Practically, the P-N junction capacitance varies with bias as follows:
C jo
Cj  m
  Va  (2-24d)
1   
  Vbi 
where the index m depends on the doping profile. For Si we have m= ½

for abrupt doping profile and m =1/3 for linear (graded) doping profiles.
96
Fig. 2-19. The junction capacitances of a P-N junction
Example 2-3.
Consider an abrupt p-n diode with Na = 1018 cm-3 and Nd = 1016 cm-3.
Calculate the built-in voltage, the depletion region width and the junction
capacitance at zero bias. The diode area equals 10-4 cm2. Take s=1pF/m
Repeat for a one-sided diode and calculate the relative error.
Solution
The built in potential of the diode equals
Vbi =VT ln(NaNd/ni2) = 0.83V

The depletion layer width at zero bias is given by:
2 o s  Na .  Nd  2 o s
W  .Vbi  Va   Vbi  0  0.33m
e  Na Nd  eN d
The junction capacitance at zero bias equals

 o s A
C jo   3.17 pF
W Va 0
Repeating the analysis while treating the diode as a one-sided diode, one
only has to consider the region with the lower doping density so that
97
2 o s
W  Wn  Vbi  Va   0.31m
eNd
And the junction capacitance at zero bias equals
 o s A
C jo   3.18 pF
W Va 0
The error is 0.5%, which justifies the use of the one-sided approximation
2-7. Circuit Models of a P-N Junction Diode

The diode allows current to flow in only one direction. The perfect diode
would be a conductor in one direction (forward bias) and an insulator in
the other direction (reverse bias). If a large signal is applied, the diode
may switch between forward and reverse bias regions, according to the
applied signal amplitude. In many situations, using an ideal diode
approximation, as a switch, is acceptable.
Fig. 2-21. Ideal diode (switch) model.
2-7.1. Large-signal (DC) Circuit Model of a P-N Junction

The diode modeling involves the formulation of either small-signal
linearized model, which is valid about an operating point or a piecewise-
linear equation model. The linearized equation model describes the circuit
in terms of its equivalent passive elements and controlled voltage/current
sources. The following figure depicts a practical model of the P-N
junction diode, which includes a barrier voltage and series resistance in
the forward direction. This model is suitable for DC and large signal
circuits. The linear forward resistance (RF) can be calculated from the
slope of the linear portion of the I-V characteristics. However, this is
usually not necessary since the forward resistance value is almost
constant. For low-power Ge and Si diodes the RF value is about 2 to
5, while higher power diodes have RF closer to 1. In forward bias, the
drop Vd is about 0.3V for Ge diodes and 0.7V for Si diodes.
98
Fig. 2-22. Large signal diode model, with barrier voltage and forward resistance
Example 2-4.
Assume a low-power diode with a forward resistance value of 5. The
barrier voltage V is 0.3V. Determine the diode current Id if the diode is
connected to a series resistance Rs=50 and an applied voltage Va = 5V.
Solution
We write the KVL equation for the circuit:
VA = Id RS - V – Id RF
ID = (Va – V)/(RS + RF ) = (5 – 0.3)/( 50 + 5) = 85.5 mA
Diode Circuit Equivalent Circuit
Fig. 2-23. Diode model and équivalent circuit
2-7.2. Quiescent Point of a Junction Diode

The quiescent point (Q-point) of a diode is the operating point, which
indicates its DC current (Id) and DC voltage drop (Vd). The Q-point can
be obtained graphically from the diode I-V characteristics. The example,
below, shows how the Q-point is determined using the I-V curve of the
diode and the load line. The load line plots the possible combinations of
diode current and voltage for a given circuit. The maximum Id equals
Va/Rs, and the maximum Vd equals Va. The Q-point is located where the
load line and the characteristic curve intersect.
99
Figure 2-25. Illustration of the Q-point and the graphical solution of a diode. circuit
2-7.3. Small-signal (AC) Circuit Model of a P-N Junction

The small circuit model is constructed by linearizing the diode I-V
characteristics around a certain Q-point. Figure 2-17(c) depicts the small-
signal model of a forward biased P-N junction at low frequencies. The
dynamic resistance rd depends on the forward diode current Id (at the Q-
point) and is typically in the order of Ohms. Mathematically speaking, the
diode dynamic resistance is given by:
dVd .VT
rd   (2-25)
dI d Id
where  is the non-ideality factor of the P-N junction. At high frequency,

we have to consider the P-N junction capacitance. The diode capacitance
includes the diffusion capacitance Cd =a/rd in parallel with the transition
capacitance CT in forward bias and only the transition capacitance CT in
reverse bias. Therefore, the transition capacitance CT, which is present in
both reverse and forward biased diodes, is due to space-charge layer
around the diode junction. On the other hand, the diffusion capacitance Cd
is present only in forward bias because it is due to stored minority carriers
under forward biased conditions. In both cases, the diode capacitance
(Cj=CT+Cd) is a function of the applied bias, as given by equation (2-
24d). The figure 2-24 depicts the small-signal AC model of a P-N
junction. A more general diode model, which is suitable for computer
simulation, is given in Appendix B of this book.
Figure 2-24. Small-signal (AC) model of a P-N junction diode.

100
2-8. Transient Behavior of a P-N Junction Diode

We know that an ideal diode conducts current in one direction (forward)
and blocks current in the other direction (reverse). A common use of the
P-N junction is to switch between the on-state and the off state. However,
when a real P-N junction is subjected to fast switching or step voltage it
doesn’t change from forward to reverse state instantaneously, but needs a
certain time to recover from a strong forward conduction state to cut-off.
The phenomenon of charge storage during forward conduction is present
in all semiconductor junction diodes and is due to finite lifetime of
minority carriers in semiconductors. The following figure depicts the
collapse of the stored charge in one side of a P-N junction diode (holes in
the n-side), when the diode is switched off.
When diode is forward biased, a charge Qs is stored in the device. This
stored charge depends on:
1. Intensity of the forward anode current IF in steady state.
2. Minority carrier lifetime τ, i.e. the mean time a free charge carrier
moves inside a semiconductor region before recombining.
Figure 2-26 depicts the switching-off waveforms of a P-N junction. As
shown in figure, the total reverse recovery time (trr) is composed of two
components, namely: the storage time (ts) and the fall time (tf). The
storage time (ts) is given by:
erfc[(ts/)½] = IF / (IR + IF) (2-26a)
where erfc() is the error function. When both forward and reverse
currents flow for long time, compared to the lifetime , then one can use
the following approximate relation for ts:
ts   ln [1+(IF / IR)] (2-26b)
101
Fig. 2-26. Switching characteristics of a P-N junction diode.
Fig. 2-27. Collapse of the stored charge (here holes in the n-side) in a P-N junction
diode, when it is turned off.
102
The fall time (tf) is the time required for the reverse current, IR, to fall
from 90% to 10% of its maximum value (IR =E2/R). It is given by the
following equation:
erfc[(tf /)½] +[(tf /)] -½.exp[-(tf /) ]= 1+0.1(IR / IF) (2-26c)
The delay time (td) is the time required for the forward current, IF, to rise
from 0% to 10% of its maximum value (IF =E1/R). The rise time (tr) is the
time required for the forward current, IF, to rise from 10% to 90% of its
maximum value (IF =E1/R).
Note 2-2. Charge Control Model of a P-N Junction
Consider the N-side quasi-neutral region of a forward-biased P-N junction:
pn  2pn pn
The minority carrier diffusion equation  DP  can be put in the
t x2 p
(epn ) J epn
following form in N-side quasi neutral region  P 
t x p
Integrating over the N-side quasi-neutral region results:
dQp Q
 I P ( xn )  p
dt p
where Qp is the, excess minority carriers stored in the N-side quasi-neutral regions:


n2

Qp  eA pn ( x)dx  eApn ( xn ) Lp =  eA i e qVA / kT  1 L p
xn Nd
Where we substituted the excess hole pn expression in a normal long diode. In a
short diode, the same expression holds, with replacing the diffusion length with half
the P-side neutral width Ln  ½ Wp’.Similarly, we can write the following equation
for excess charge in the P-side neutral region
dQn Q
 I n ( x; )  n with
dt n


n2
Qn  eA n p ( x)dx  eAn p ( x p ) Ln =  eA i eqVA / kT 1 Ln
xp Na

The steady-state diode current (I =In +Ip) can be viewed as the charge supply required
to compensate for charge loss by recombination (for long base) or collection at the
contacts (for narrow base).
 Qn Qp
I 
τn τp
Note that for a short diode, the minority carrier life time n, p should be replaced with
½Wn2/Dp and ½Wp2/Dn, respectively.
2-9. Applications of the P-N Junction

In this section we depict some important applications of the P-N junction
diode in electronic engineering systems. Here, we briefly describe the
diode applications in the following circuits:
103
1- Rectification and DC power supplies,

2- Peak detectors,
3- Clipping circuits,
4- Clamping circuits, and
5- Voltage multipliers
2-9.1. Diode as a Rectifier (Rectification)

Generally speaking, rectification is the conversion of alternating current
(AC) to direct current (DC). This usually involves a device that only
allows one-way flow of electrons. We have seen that the P-N junction
can be operated as a rectifier element, because of its high resistance in the
reverse direction and its very low resistance in the forward direction.
Figure 2-27 depicts the rectifier action on AC input voltage, in different
circuit configurations. If we need to rectify AC power to obtain the full
use of both half-cycles of the sine wave, a certain circuit must be used.
This circuit is called a full-wave rectifier. One kind of full-wave rectifier,
called the center-tap rectifier, uses a transformer with a center-tapped
secondary winding and two diodes, as shown in figure 2-27(b). One
disadvantage of this full-wave rectifier design is the need of a center-
tapped transformer. The center-tapped rectifier is only useful for small-
power DC power supplies. Figure 2-27(c) depicts another popular full-
wave rectifier circuit, called the bridge rectifier.
Note that regardless of the polarity of the input, the current flows in the
same direction through the load. That is, the negative half-cycle of source
is a positive half-cycle at the load. The current flow is through two diodes
in series for both polarities. Thus, two diode drops of the source voltage
are lost (0.7x2=1.4V for Si) in the diodes. This is a disadvantage
compared with a full-wave center-tap design. This disadvantage is only a
problem in very low voltage power supplies.
Finally, diode can be also employed to rectify polyphase AC sources.

Figure 2-21(d) depicts 3-phase diode rectifier. In this configuration, each
line of the three-phases is connected between a pair of diodes: one to
route power to the positive (+) side of the load, and the other to route
power to the negative (-) side of the load.
104
(a) Half-wave rectifier
(b) Full-wave rectifier
(c) Bridge (full-wave) rectifier
Operation of the bridge rectifier

Figure 2-27. Application of the P-N junction diode as a rectifier. (a) Half-wave
rectifier. (b) Full-wave rectifier using a center-tapped transformer, (c) Full-wave
rectifier, using a bridge rectifier.
The figure 2-28 depicts how the P-N junction diode can be employed in a
simple DC power supply, which consists of a simple rectifier and an R-C
filter, to obtain an average DC output across a load resistor. The average
DC voltage output of such a simple DC power supply is given by the
following relation:
105
VDC = Vp - ½ V ≈ Vp ( 1 – 1/RLC) (2-27)
where Vp is the peak value of the input AC voltage, is its frequency.
Also, C is the smoothing capacitor, RL is the load resistance and V ≈

2Vp/RLC is called the output ripple voltage. The ratio of RMS value of
AC component to the DC component in the output (Iac/Idc) is known as
the ripple factor
Figure 2-28. Application of the P-N junction diode in a simple power supply
Example 2-5.
Consider the 2-diode circuit shown below. Calculate each diode current
and voltage drops.
Solution:
Make a guess as to one of the possible states of the circuit. If a diode is
assumed on, verify the current calculated flows in the correct direction
consistent with the diode being on. If a diode is assumed off, verify the
voltage across the diode calculated has a polarity consistent with the
diode being off. The possible states of the two diodes are as follows:
106
We select the ideal diode model.
* Assume first both diodes are on, then:
But IA = ID1+ID2 such that ID1 = -0.5 m. This contradicts the assumption
that D1 is on. Now, let’s assume diode 1 is on, diode 2 is off:
ID2 = 0 mA , vb = -10V, and hence Vd1 = va –vb = 0 –(-10)V = 10V.

This contradicts the assumption that D2 is off.
Finally, let’s assume D1 is off and D2 is on

IA = ID2. Also we have: 15V-10000 IA- (-10V) = 0, so that IA= 1.7mA.
Also, va -0 = Vd1 = 15-10000IA = -1.7V
Thus, Assumptions: D1 off and D2 on verified! Check yourself that the

fourth combination (both diodes are off) cannot be verified.
2-10.2. Peak Detector

As shown in the following figure, the peak detector is a series connection
of a diode and a capacitor which produces a DC voltage equal to the peak
value of the input AC signal. When the AC input voltage is applied to the
peak detector, it charges the capacitor to the peak of the input waveform.
The diode conducts during the positive half cycles, and charges the
capacitor to the waveform peak
107
Figure 2-29. Application of the junction diode in a peak detector circuit.
When the input waveform falls below the attained DC peak, which is
stored on the capacitor, the diode is reverse biased, and blocks the current
flow from the capacitor back to the input source. Thus, the capacitor
retains the peak value even as the waveform drops to zero. This circuit is
usually employed in AM radios, in the demodulation stage.
Figure 2-30. Application of the junction diode in a peak detector circuit.
2-10.3- Clipping Circuits

The clipping circuit clips the peak of an input waveform to certain
amplitude. The following figure shows a bipolar clipping circuit, with
two back-to-back diodes. This circuit clips the positive and negative
peaks of an AC input to the forward diode drop (≈ 0.7V for Si diodes).
Such clipping circuits are usually employed in voltage limiters, in a wide
range of applications, like wireless transmitters, as shown in figure 2-32
108
Figure 2-31. Simple clipping circuits,
Figure 2-32. Application of the diode clipping circuits in a wireless transmitter.
2-10.4- Clamping Circuits

A clamping circuit is used to place either the positive or negative peak of
a signal at a desired level. As shown in the following figure, the clipping
circuit clamps (or lifts) the peak of a waveform to a specific DC level. As
shown in figure 2-33(a), the clamp voltage is 0V, if we ignored diode
drop (0.7V in Si diodes). Ignoring the diode forward drop, the positive
peak of Va is clamped to the 0V (really 0.7V). On the first positive half
cycle, the diode conducts charging the capacitor left end to +5V (4.3V).
This is -5V (-4.3V) on the right end at Va. The right end of the capacitor
is -5V (-4.3V) with respect to ground. It also has 5V peak coupled across
it from source Vs. The sum of the two is a 5V peak riding on a -5V DC (-
4.3V) level. The diode only conducts on successive positive excursions
of source Vc if the peak Vc exceeds the charge on the capacitor.
109
The charge on the capacitor is equal to the positive peak of Vc (less 0.7V).
The AC riding on the negative end, right end, is shifted down. The
positive peak of the waveform is clamped to 0V (0.7V) because the diode
conducts on the positive peak.
Figure 2-33. Application of the junction diode in clamping circuits. Three

configurations are shown (a) Positive peak clamped to 0 V. (b) Negative peak
clamped to 0 V. (c) Negative peak clamped to 5 V
2-10.5- Voltage Multipliers

The voltage multiplier can produce an output which is theoretically
multiple of the input waveform peak. Thus, it is possible to get 220VDC
from a 110VAC source by a voltage doubler. However, in practical
circuits the load will lower this value. As shown in figure 2-34()a), the
voltage doubler consists of two diodes and two capacitors, connected as
clamping circuit and a peak detector. The operation is as follows. The
following figure depicts the output waveform of a voltage doubler.
During the negative half-cycle of input voltage, diode D1 is forward
biased and diode D2 is reverse biased. Therefore, diode D1 is represented
by a short and diode D2 as an open. The equivalent circuit then becomes
as shown in the following figure. C1 will charge until voltage across it
becomes equal to peak value of source voltage VSpk. At the same time, C2
will be in the process of discharging through the load RL.
110
Figure 2-34(a) Application of the junction diode in a voltage doubler circuit.
When the polarity of the input voltage reverses (during positive half-
cycle), D1 is reverse biased and D2 is forward biased as shown in figure
below. In this case, C1 (charged to VSpk) and the source voltage VS now act
as two voltage sources in series. Thus C2 will be charged to the sum of the
sum of their series peak voltages (2VSpk). As C2 barely discharges between
input cycles, the output waveform of the voltage doubler resembles that
of a filtered half-wave rectifier. The most common type of voltage
multipliers is the half-wave series multiplier, also called the Villard
cascade. Such a circuit is shown in figure 2-35.
Figure 2-34(b). Output waveform of the voltage doubler circuit.
Figure 2-34(c). Output waveform of the voltage doubler circuit.
111
The voltage multipliers may be employed in high voltage DC power

supplies. Voltage multipliers are also extensively used in TV sets, to
produce extra high tension (EHT) voltage, which is necessary for the
operation of a TV cathode ray tube (CRT).
Figure 2-35. Application of the junction diode in a voltage multiplier circuit.
2-10.6. Temperature Sensor

We can make use of a P-N junction as a measuring instrument to determine
the ambient temperature. The ordinary semiconductor diode may be used
as a temperature sensor. When a constant current (I) passes across a
forward biased P-N junction, the forward voltage (Vd) is given by:
Vd = ( kB T / e ) . ln [ 1 + ( Id / Is ) ] (2-28a)
Figure 2-36(a) depicts the current-voltage characteristics of P-N junction

and how it is affected by temperature variations. As shown in figure, the
forward voltage drop increases by almost a constant rate (dVd/dT) as
temperature increases:
(dVd / dT) = ( kB / e ) . ln [ 1 + ( Id / Is ) ] (2-28b)
The diode is the lowest cost temperature sensor and can produce more
than satisfactory results if you are prepared to undertake a two point
calibration and provide a stable excitation current. Almost any silicon
diode is ok. The forward biased voltage across a diode has a temperature
coefficient of about 2.3mV/°C and is reasonably linear. The measuring
circuit is simple as shown in figure 2-36(b). The bias current should be
held as constant as possible - using constant current source or a resistor
from a stable voltage source. To improve the performance of the diode as
a temperature sensor, two diode voltages (V1 and V2) can be measured at
different forward currents (I1 and I2), typically selected to be about 1:10
ratio. The absolute temperature can be calculated from the equation:
T = (V1 - V2) / (8.7248x10-5 ln( I1 / I2)) (2-28c)

112
The result is in Kelvins (K). This is the method employed by most

integrated circuit temperatures sensors and explains why some output a
signal proportional to absolute temperature.
I T1
T2
T3
Reverse Saturation T3 > T2 > T1

current
Is
Vd
Forward Voltage
proportional to the
Temperature
Figure 2-36(b). Variation of I-V characteristics of a junction diode with temperature
Figure 2-36(a). Application of the junction diode as a temperature sensor.
2-11. P-N Heterojunction Diodes

Thus far, we described the behavior of homogeneous P-N junctions,
which are fabricated from a single semiconductor material, such as Si.
However, it is sometimes desirable to make P-N junctions with P-side
from a specific semiconductor material and N-side from another one. This
structure is called heterojunction. The following figure depicts the
energy band diagram of such a heterojunction diode. Note that there
exists a discontinuity in conduction and valence bands of the junction.
Their magnitudes may be expressed as follows:
EC = 1 - 2 (2-29a)
EV = Eg - EC  (2-29b)
113
Fig 2-37. Band structure of a heterojunction (N-Al0.3Ga0.7As /P-GaAs) in equilibrium.
The barrier height (heterojunction built-in voltage) is given by:
eVbi = Eg (GaAs) – e (p +n ) + (GaAs) - (AlGaAs) (2-29c)
For the case GaAs /AlGaAs heterojunction, EC = (GaAs) - (AlGaAs)

= 0.244 eV and EV = Eg - EC = 0.136 eV.
One of the intersting P-N heterojunctions is the N-GaN / P-SiC structure.

This structure is obtained by deposition of GaN on SiC. Usually GaN is
deposited on (0001) face of a SiC substrate. Both Si and Mg can be used
as donor and acceptor impurities, respectively. Ni, Ti or Pd metals are
employed to form Ohmic contact for the top-GaN. The turn-on voltage
of such diodes is about 2V, which corresponds to the built-in potential of
the heterojunction.
2-12. Special Diode Structures

There exist a variety of semiconductor diodes that are typically used in
electrical and electronic circuit applications. These diodes include Zener
diode, P-I-N diode, varactor diode (varicap), Schottky barrier diode
(SBD), resonant tunneling diode (RTD) and tunnel diode.
114
Fig 2-37. Band structure of a heterojunction (N-Al0.3Ga0.7As /P-GaAs) in equilibrium.
2-12.1. Zener Diode

The Zener diode is a special P-N junction diode with highly doped sides.
The highly doped regions of the P-N junction results in a high electric
field across a very thin depletion region, as shown in figure 2-38. This
results in tunneling current leading to a non-destructive breakdown (when
connected with a limiting resistor). For tunneling, there should be a
sufficient field greater than a certain critical value ζcr in the order of
2x107 V/cm. In this condition, the Zener breakdown voltage is given by:
 o s . cr2  Na  Nd 
VZ    (2-30)
2e  a d 
N N
Fig. 2-38. Band structure of a Zener diode.
Zener diodes can be formed to breakdown at voltages from about 4 volts

to several hundred volts. The I-V characteristics of the Zener diode are
shown in figure 2-39. The constant reverse voltage VZ of the Zener diode
makes it a valuable component for the regulation of the output voltage
115
against both variations in the input voltage from an unregulated power

supply or variations in the load resistance.
Fig. 2-39. The I-V characteristics of a Zener diode
Fig. 2-40. Application of a Zener diode in voltage regulation.
The analysis of Zener diode circuits is very similar to the analysis of P-N
diodes. The first step is to determine the state of Zener diode, whether it
is OFF or ON. Next, the Zener is replaced by its appropriate model.
When the Zener is operating in the breakdown region, it is represented by
a voltage source (VZ) and a small series resistance (rZ). Finally, the
unknown quantities are determined from the equivalent circuit.
Example 2-6
Show how to design a 5V stabilized power supply from a 12V DC power
supply, given that the maximum power rating PZ of the Zener is 2W.
Solution
116
a) The maximum current flowing through the Zener is given by.

Maximum Zener current (Iz) = Pz/Vz = 2W/5V= 400 mA
b) The minimum value of the series resistor, RS is given by:
Rs = (Vs –Vz )/Iz = (12-5) / 400mA = 17.5 k
c) The load current IL if a 1kΩ load resistor is connected across the Zener.
IL = Vs /RL = 5V / 1k =5 mA
d) The total supply current IS is then:
Is = IL + Iz = 5mA+400mA = 405 mA
Example 2-7
For the circuit shown below, find (i) the output voltage (ii) the voltage
drop across series resistance and (iii) the current through zener diode
Solution.
If we removed the Zener diode, the voltage across the open-circuit would
be:
V = RL.Ei /(R+RL) = 10x120/(5+10) = 80V.
Since voltage across Zener diode is greater than VZ (= 50V), the Zener is
in the ―Zener ON‖ mode. It can, therefore, be represented by a battery of
50V (assuming internal resistance rz= 0 ), as shown in the above figure.
(i) Output voltage = VZ = 50V
(ii) Voltage drop across Rs = Input voltage − VZ = 120 − 50 = 70 V
(iii) Load current, IL = VZ/RL = 50 V/10 kΩ = 5 mA
Current through Rs, I = 70 V / 5 kΩ = 14 mA. As, I = IL + IZ . Therefore,
The Zener current, IZ = I − IL = 14 − 5 = 9 mA
Zener diodes can be also used in voltage clipping and squaring circuits, as
shown in the figure 2-41.
117
Fig. 2-41. Application of a Zener diode in voltage regulation.
2-12.2. P-I-N Diode1

The PIN diode is some sort of P-N junction diodes, with a wide, intrinsic
semiconductor region between the P-type and N-type semiconductor
regions. As a result of its special structure, the P-I-N diode is used in a
variety of applications. The properties introduced by the intrinsic layer
make it suitable for some applications where ordinary P-N junction
diodes are less suitable. There are three main applications for P-I-N
diodes, although they can also be used in other areas as well:
High voltage rectifier: The P-I-N diode can be used as a high voltage
rectifier. The intrinsic region provides a greater separation between the
P and N regions, allowing higher reverse voltages to be tolerated.
RF (Microwave) switch: The P-I-N diode is an ideal RF switch. The
intrinsic layer between the P and N regions, decreases its capacitance,
thereby increasing the isolation level, in reverse bias.
Photodetector: The intrinsic layer improves the efficiency of the P-I-N
photodiode by increasing the volume in which light conversion occurs.
Fig. 2-42. Structure of a typical P-I-N diode.
However, the P-I-N diode has a poor reverse recovery time. At higher
frequencies, the device cannot response as quickly because there is no
enough time to remove the excess charge. Therefore, the P-I-N diode
1
P-I-N diodes are also presented in Chapter 8 (Power Devices) and Chapter 10 (Microwave devices)
118
never turns OFF at high frequencies. Although the P-I-N diode has many
applications in high voltage, it is usually employed in RF applications
where it is best known. The fact that when it is forward biased, the diode
is linear, behaving like a resistor, can be put to good use in a variety of
applications. For instance, it can be used as a variable resistor in a
variable attenuator, a function that few other components can achieve as
effectively. Actually, the P-I-N diode obeys the diode equation only for
very slow signals. At high frequency, the diode looks like a perfect
resistor. The high-frequency resistance is inversely proportional to the
DC current through the diode. The P-I-N series resistance is given by:
(2-31)
where IF is the forward current and  is the average carrier lifetime in the
base region, By changing the bias current through a PIN diode, it is
possible to quickly change the RF resistance. This high-frequency
resistance may vary over a wide range (from 0.1 Ω to 10 kΩ). Thus the
PIN diode is usually employed as a variable RF attenuator. Under reverse
bias, a PIN diode has low capacitance. The low capacitance will not pass
much of RF signal. Under a forward bias of 1mA, a typical P-I-N diode
will have an RF resistance of about 1, making it a good RF switch.
Fig. 2-43. Application of the P-I-N diode, as an attenuator in RF circuits.
Microwave P-I-N diodes are manufactured using an epitaxial process.

The i-layer is nominally a 100 -cm layer, grown on a heavily doped P+
or N+ substrate. Such diodes provide adequate switching performance
above 2GHz. The depletion region of a P-I-N is larger than in a P-N
diode, and almost independent of the applied reverse bias. This increases
the area where electron-hole pairs can be generated. For these reasons
many photo-detectors include P-I-N diodes.
119
Applications of P-I-N diodes also include: IR-remote control, video tape

recorders, dimmers, remote control as well as light reflecting switches.
More details about P-I-N diodes and their applications in power and
microwave applications will come in Chapters 8 and 10 of this book.
Fig. 2-44. Application of the P-I-N diode, as variable attenuator in automatic gain
control (AGC) of radio signals.
2-12.3. Schottky Barrie Diodes (SBD)2

Schottky barrier diode (SBD) is a semiconductor diodes based on a
metal-semiconductor interface. The earliest study on metal semiconductor
system was done by Karl Ferdinand Braun in 1874. The Schottky diode
(named after the German physicist Walter Schottky, 1886-1976) is made
by joining a suitable piece of metal with a semiconductor. In 1937
Schottky showed that a potential barrier arises in such a structure and that
it has rectifying characteristics. SBD’s have very fast switching time and
low forward voltage drop.
Fig. 2-45. Schottky barrier diode structure and symbol
Typical applications of SBD’s include RF detection and discharge-

protection for solar cells systems and in power supplies. In such
2
SBD’s are also presented in Chapter 10 (Microwave devices) and Chapter 11 (Photonic Devices).
120
applications, the low forward voltage of the BSD leads to increased

efficiency. While silicon diodes have a forward voltage drop of about
0.7V and germanium diodes 0.3V, Schottky diodes voltage drop at
forward biases is in the range 0.15V to 0.46V at 1mA, which makes them
useful in prevention of transistor saturation. Schottky diodes are also used
as high sensitivity microwave detectors.
Most important difference between P-N junction and Schottky diodes is
reverse recovery time, when the diode switches from OFF to ON state
and vice versa. Schottky diodes do not have a storage time, and hence the
recovery time is trivial. The switching time is ~100ps for the small signal
diodes, up to tens of nanoseconds for special high-capacity power diodes.
It is often said that the Schottky diode is a majority carrier semiconductor
device. This means that if the semiconductor body is doped N-type, only
the N-type carriers (mobile electrons) play a significant role in normal
operation of the device. The majority carriers are quickly injected into the
conduction band of the metal contact on the other side of the diode to
become free moving electrons. Therefore no slow, random recombination
of N- and P- type carriers is involved, so that this diode can cease
conduction faster than an ordinary P-N rectifier diode. This property in
turn allows a smaller device area, which also makes for a faster transition.
This is another reason why Schottky diodes are useful in switch-mode
power converters.
The high speed of SBD's permits them to operate at frequencies in the
range 200 kHz to 2 MHz, allowing the use of small inductors and
capacitors with greater efficiency than other diode types. Schottky diodes
can be also used in power supply to isolate the internal battery from
mains adaptor input. Small-area Schottky diodes are the heart of RF
detectors and mixers, which often operate up to 5GHz. Schottky junctions
are also used in the logic gates, as clamps in parallel with the collector-
base junctions of the bipolar transistors to prevent their saturation.
Thereby, Schottky diodes can greatly reduce the turn-off delays of the
clamped transistors. The most evident limitations of Schottky diodes are
the low reverse voltage rating and the high reverse leakage current (for
silicon-SBD).The voltage ratings are now up at 200V. More details, about
the SBD will come in Chapter 4, when we talk about metal-
semiconductor (M-S) contacts.
2-12.4. Step-Recovery Diode (SRD)3
The step-recovery diode (SRD) is sometimes called & fast-recovery
diode, snap-off diode, or snap-back diode. The response of a standard P-
3
SRD’s are also presented in Chapter 10 (Microwave devices)
121
N junction is limited by the minority-carrier storage, with the reverse

recovery. A step-recovery diode has a special doping profile such that the
field confines the injected carriers much closer to the vicinity of the
junction. This results in a much shorter transition time ttr. The sharp
turnoff of current approaches a square waveform which contains rich
harmonics and is often used in applications of harmonic generation and
pulse shaping.
2-12.5. IMPATT Diode4
The IMPact ionization Avalanche Transit-Time (IMPATT) diode is a
high power P-N junction structure used in high-frequency and microwave
applications (up to 100GHz). At constant reverse bias, the IMPATT diode
current will oscillate if the applied voltage is just above breakdown of its
P+-N junction. IMPATT diode is typically made with silicon carbide
(SiC) because of its high breakdown field. These diodes are used in a
variety of applications from low power radars to alarms.
A. IMPATT Diode Structure
The IMPATT diode family includes many different junctions and metal
semiconductor devices. Figure 2-46 depicts one of these structures. The
first IMPATT oscillation was obtained from a simple silicon P-N junction
diode biased into a reverse avalanche breakdown and mounted in a
microwave cavity. Because of the strong dependence of the ionization
coefficient on the electric field, most of the electron–hole pairs are
generated in the P+-N high field region. The generated electrons drifts
into the depletion region, while the generated holes moves through the
P+-region to the anode contact (A). The time required for electrons to
reach the cathode contact (K) represents the transit time of the diode.
Fig. 2-46. Basic structure of IMPATT diode.
The original proposal for a microwave device of the IMPATT type was
made by Read. The Read diode consists of two regions as illustrated in
figure 2-46, namely the avalanche region and the drift region. The
Avalanche region (P+–N region with relatively high doping and high
field), in which avalanche multiplication occurs and the drift region (N -–
4
IMPATT’s are also presented in Chapter 10 (Microwave devices), with more details
122
region with essentially intrinsic doping and constant field), in which the
generated electrons drift towards the cathode contact. A major drawback
of IMPATT diodes is their high phase noise. This results from the
statistical nature of the avalanche process. Nevertheless these diodes
make excellent microwave generators for many applications.
2-12.6. Tunnel Diode5

The tunnel diode (or Esaki diode) is a type of semiconductor diodes,
which is capable of very fast operation, well into the microwave region,
utilizing quantum mechanical effects. It was named after Leo Esaki, who
received the Nobel Prize in Physics in 1973 for discovering the electron
tunneling effect used in such diodes. These diodes have a heavily doped
P-N junction over only some 10nm width. The high doping results in a
narrow energy barrier, where conduction band states on the N-side are
more or less aligned with valence band states on the P-side, permitting
electrons to tunnel through the barrier. The figure 2-49 depicts the I-V
characteristics of the tunnel diode, its circuit symbol and energy band
diagram. Under normal forward bias operation, as voltage begins to
increase, electrons at first tunnel through the narrow P-N junction barrier
because filled electron states in the conduction band on the N-side
become aligned with empty valence band hole states on the P-side. As
voltage increases further these states become more misaligned and the
current drops — this is called negative resistance, because current
decreases with increasing voltage.
Fig. 2-49. Tunnel diode I-V characteristics and energy band diagram.
5
Tunnel diode is also presented in Chapter 10 (Microwave devices) and Chapter 12 (Quantum devices)
123
As voltage increases yet further, the diode begins to operate as a normal

diode, where electrons travel by diffusion across the P-N junction.
The tunnel diode showed great promise as a high-frequency oscillator
since it operates at frequencies well into the microwave bands. However,
since its discovery, other semiconductor devices have surpassed its
performance using conventional oscillator techniques. Tunnel diodes are
also relatively resistant to nuclear radiation, as compared to other diodes.
This makes them well suited to higher radiation environments, in space
applications. Figure 2-50 shows an application of the tunnel diode, as an
oscillator.
Fig. 2-50. Tunnel diode oscillator circuit.
2.12.7. Resonant Tunnel Diode (RTD)6

A resonant tunnel diode (RTD) is a device which uses quantum effects
and negative differential resistance (NDR). RTD’s are formed as a single
quantum well structure surrounded by very thin layer barriers. As an RTD
is capable of generating a terahertz wave at room temperature, it can be
used in ultra high-speed circuits. The figure 2-51 depicts the structure of
an AlGaAs/InP RTD. This device is called a double-barrier structure.
When a voltage is placed across an RTD, a terahertz wave is emitted
which is why the energy value inside the quantum well is equal to that of
the emitter side. As voltage increased, the terahertz stops because the
energy value in the quantum well is outside the emitter side energy.
Tunneling through a double barrier was first discussed by David Bohm in
1951, who pointed out that resonances in the transmission coefficient
occur at certain incident electron energies. It turns out that, for certain
energies, the transmission coefficient is equal to one, i.e., the double
barrier is totally transparent for particle transmission. This phenomenon is
called resonant tunneling. The GaAs and AlAs in particular are used to
form resonant tunneling structure. This structure can be fabricated by
molecular beam epitaxy (MBE).
6
RTD’s are also presented in details in Chapter 8 (Microwave Devices) of this book.
124
Also, Si/SiGe heterojunctions can be used to fabricate RTD’s. The typical

I-V characteristics of a GaAs/Al0.3GaAs0.7 RTD at low bias regimes are
illustrated in figure 2-53. The corresponding energy band diagram and
state wavefunctions, are illustrated in figure 2-54. Figure 2-46 shows an
application of the RTD, as an oscillator. Because of the negative
differential resistance exhibited by RTD’s, and since tunneling is an
inherently fast transport mechanism, these devices have been proposed
for use in extremely high frequency oscillators.
Fig. 2-51. Structure of AlGaAs/InP double-barrier RTD and its circuit symbol.
Fig. 2-53. Typical I-V characteristics of a GaAs/Al0.3GaAs0.7 RTD.
125
Fig. 2-56. Application of an RTD as a negative resistance oscillator.
2-12.8. Solar Cells7

A solar cell or photovoltaic (PV) cell is a semiconductor device that
converts light energy into electrical energy by the photovoltaic effect. The
solar cell structure is shown in figures 2-57. The equivalent circuit and I-
V characteristics are also shown in figure 2-58. Groups of PV cells are
usually configured into modules, which can be used to charge batteries,
operate motors, and to power electrical loads.
Fig. 2-57. Structure of a conventional solar cell
7
Solar Cells are presented in details in Chapter 8 (Photovoltaic Devices) of this Book.
126
Fig. 2-58 Solar cell operation, and circuit symbol
The operating current of a solar cell is given by:
  Vd  
I  I ph  I d  I ph  Io exp   1 (2-33)

  T .V
where Iph is the photocurrent, and Id is the diode current. The solar cell I-
V characteristics depend on the ambient temperature and the
semiconductor material, which is used in its fabrication. In fact, the open
circuit voltage of the solar cell is proportional to the energy gap of the
semiconductor material. Also, the short-circuit current of the solar cell is
smaller for higher open-circuit voltage.
Fig. 2-59 Solar cell equivalent circuit and I-V characteristics.
127
2-12.9. Photodiode8
The photodiode is a biased version of the solar cell. It works in reverse
bias, as shown in figure 2-66. The I-V characteristic of the photodiode is
similar to that of the conventional P-N junction, with addition of a
photocurrent component due to electron-hole generation n the space
charge region.
  Vd  
I =Id + Iph = o 
I exp    1  eA.(Wn  W  Wp ).GL (2-34)
   VT  
where the dark current, Id, has the same expression of the conventional
diode current, and the photocurrent, Iph, is related to the total space –
charge region width (the intrinsic region W plus the depleted regions on
both sides Wn+Wp) as well as the light generation rate GL. For short
diodes, without intrinsic region, the total depletion width (W+Wn+Wp)
should be replaced with the sum of carrier diffusion lengths (Ln+Lp).
Fig. 2-66. Operation of a photodiode, without and with light illumination.
8
Photodiodes are presented in details in Chapter 11 (Photonic Devices).
128
Fig. 2-67. The I-V characteristics of a Photodiode, at different illumination powers.
2-12.10. Light-Emitting Diode (LED)9

Light-emitting diode (LED) is a special P-N junction device, which emits
visible light when forward biased. Light is emitted when electrons and
holes recombine in the space charge region of the P-N junction. The
following figure illustrates the operation of the photodiode. LEDs are
available in a wide range of shapes, colors and various sizes with
different light output intensities.
Fig. 2-70. Structure and radiation pattern of a light-emitting diode (LED).
9
LED’s are presented in details in Chapter 11 (Photonic Devices).
129
The first commercially available LEDs started to appear in the late 1960s.
The early LEDs used a semiconductor made of gallium, arsenic and
phosphorus - GaAsP. This produced a red light, and although the
efficiency of the devices was low (typically around 1 - 10 mCd at 20mA)
they started to be widely used as indicators on equipment. Later, in 1993
HP started to use GaP (gallium phosphide) to provide high output green
LEDs. Also further developments of this technology allowed the
production of high output orange lamps. After a decade of intense
research, a bright blue LED was successfully produced in 1994, using
gallium nitride GaN. Other ways of producing blue light from solid state
sources involve doubling the frequency of red or infrared Laser diodes.
The subsequent figure shows the I-V characteristics of LEDs of different
semiconductor materials (and different colors).
Fig. 2-71. Band structure and operation of a light-emitting diode (LED).
130
Fig. 2-72. Forward I-V characteristics of LEDs of different materials.
The nominal forward voltage drop of the LED determines the suitable
value of the series resistor to be connected with it, as shown in the
following circuit:
Fig. 2-76. Circuit connection of a light-emitting diodes.
131
Example 2-11,
An amber LED with a forward drop of 2V is to be connected to a 5V DC
power supply. Using the circuit above calculate the value of the series
resistor required to limit the forward current to less than 10mA.
Solution
The series resistance is given by:
Rs = (Vs - VF)/IF = (5-2)V / 10mA = 300
Most light emitting diodes produce just a single output of colored light.
However, multi-colored LEDs that can also produce two or three different
colors from within a single device are also available.
2-12.11. Laser Diode10

Laser is the acronym of Light Amplification of Stimulated Emission of
Radiation. Like LED’s, Laser diodes are luminescent devices, which emit
light in response to electronic excitation. However, the emission involved
in LED’s is said to be spontaneous emission, while emission involved in
Lasers is said to be stimulated emission.
Fig. 2-81. Laser diode structure and real component.
Laser diodes consist of a P-N diode with an active region where electrons
and holes recombine resulting in light emission. In addition, a laser diode
contains an optical cavity where stimulated emission takes place. The
laser cavity consists of a waveguide terminated on each end by a mirror.
The charge accumulation is realized by means of multiple reflection
between two reflecting mirrors (or a cavity) whose length is deliberately
chosen to match the required radiation wavelength.
10
Laser diodes are presented in details in Chapter 11 (Photonic devices).
132
Fig. 2-83. Illustration of the stimulated emission in a Laser diode.
The current for which the gain satisfies the lasing condition is the
threshold current of the laser, Ith. Below the threshold current a little light
is emitted by the laser device. When the applied current is larger than the
threshold value, the output power, Pout, increases linearly with current, as
illustrated in figure 2-89, below. The output power therefore equals:
e Pout =  h (I - Ith) (2-39)
where h is the energy per photon. The factor, , indicates that only a
fraction of the generated photons contribute to the output power of the
laser as photons are partially lost through the mirror and the waveguide.
Fig. 2-82. Spontaneous and stimulated (Laser) emission from a LED and a Laser
diode, versus current.
2-13. Laboratory Testing of P-N Junction Diodes

The figure 2-83 depicts an experiment to plot the I-V characteristics of a
P-N junction diode. Being able to characterize and test the diode is a very
important skill. Since we know that a diode is a one-way valve for
electrical current (rectifier), we should verify its one-way nature using a
DC battery-powered ohmmeter as shown in figure 2-94. The meter
133
should show a very low resistance in forward direction and the other way
it should show a very high resistance at (b).
Fig. 2-93. Plotting the diode I-V characteristics, using an ammeter and a voltmeter.
Fig. 2-94. Diode testing using an ohmmeter (a) Low resistance indicates forward
bias, (b) Reversing leads shows high resistance indicating reverse bias.
2-14. Diode Ratings

A typical diode datasheet will contain figures for the following
parameters:
Maximum forward voltage (VF), is specified at the diode's rated forward
current. Ideally, this figure would be zero. In reality, the forward voltage
is described by the diode equation.
134
Maximum DC reverse voltage (VR), is the maximum amount of voltage

the diode can withstand in reverse-bias mode on a continual basis.
Ideally, this figure would be infinite.
Maximum repetitive reverse voltage (VRRM), the maximum amount of
voltage the diode can withstand in reverse-bias mode, in repeated pulses.
Ideally, this figure would be infinite.
Maximum (average) forward current (IF), is the maximum average of
current the diode is able to conduct in forward bias. This is fundamentally
a thermal limitation. Ideally, this figure would be infinite.
Maximum (peak or surge) forward current (IFSM), is the maximum peak
amount of current the diode is able to conduct in forward bias mode.
Again, this rating is limited by the diode junction's thermal capacity, and
is usually much higher than the average current rating due to thermal
inertia (the fact that it takes some time for the diode to reach maximum
temperature for a given current). Ideally, this would be infinite.
Maximum total dissipation (PD), the amount of power (in watts)
allowable for the diode to dissipate, given the dissipation (P=I 2R) of
diode current squared multiplied by bulk resistance.
Operating junction temperature (TJ), the maximum allowable
temperature for the diode's PN junction, given in degrees Celsius (oC).
Storage temperature range (TSTG), the range of allowable temperatures
for storing a diode (unpowered). Sometimes given in conjunction with
operating junction temperature (TJ).
Thermal resistance (Θ), is the temperature difference between junction
and outside air (Θ.A) or between junction and leads (ΘL) for a given
power dissipation. Expressed in units of degrees Celsius per watt (oC/W).
Maximum reverse current (IR), the amount of current through the diode
in reverse-bias operation, with the maximum rated inverse voltage
applied (VR). Sometimes referred to as leakage current. Ideally, this
would be zero, as a perfect diode blocks current when reverse-biased.
Typical junction capacitance (CJ), the typical amount of capacitance
intrinsic to the junction, due to the depletion region acting as a dielectric
separating the anode and cathode connections. This is usually a very
small figure, measured in the range of pico Farads (pF).
Reverse recovery time (trr), is the amount of time it takes for a diode to
―turn off‖ when the voltage across it switches from forward to reverse
polarity. Ideally, this figure would be zero. For typical
135
diodes, trr is in the range of tens of micro secends; for a fast switching
diode, it may only be a few nanoseconds.
Most of the above indicated parameters vary with temperature and other
operating conditions, and there is no figure to fully describe a given
rating. Therefore, the device manufacturers provide graphs of ratings
plotted against several parameters (such as temperature), so that the
circuit designer can choose the suitable device for a specific application.

Electronic devices are usually described by their nonlinear terminal
voltage-current (I-V) characteristics. Circuits containing electronic
devices are analyzed and designed either graphically, using measured
characteristics or by linearizing their voltage-current characteristics, with
suitable circuit models.
There exist so many simulation programs that can be used to simulate the
behavior of electronic devices and circuits. The circuit simulators replace
the active device with its circuit model and perform nodal analysis of the
resultant circuit. Among these simulators, the most famous is SPICE.
SPICE is the acronym of ―Simulation Program with Integrated Circuit
Emphasis‖. PSPICE is a PC version of SPICE, from MicroSim
Corporation which was recently acquired by Cadence Corporation. A
demo version of the program is available in a limited use from the
following link: http://www.orcad.com/Product/Simulation/PSpice/eval.asp
The circuit simulator PSPICE supports the following types of Analysis:

Quiescent operating point determination (.OP)
DC sweeps of current/ voltage sources (.DC)
Time-domain (transient) response (.TRAN)
Small-signal frequency response (.AC)
Fourier analysis (.FOUR)
Noise analysis (.NOISE)
Sensitivity analysis (.SENS)
Thevenin equivalents (.TF)
The PSPICE model of P-N junction diodes is depicted in details, together

with its parameters, in Appendix B at the end of this Book.
136
Fig. 2-95. SPICE model of a P-N junction, in forward bias.
The diode statement begins with a diode element name which must
begin with ―D‖ plus optional characters, such as are: D1, d2, Da. Two
node numbers specify the connection of the anode and cathode,
respectively, to other components. The node numbers are followed by a
model name, referring to a subsequent ―.MODEL‖ statement.
The model statement line begins with ―.MODEL,‖ followed by the

model name matching one or more diode statements. Next, a ―D‖
indicates a diode is being modeled. The remainder of the model statement
is a list of optional diode parameters of the form ParameterName =
ParameterValue. None are used in Example below. The following
Examples have some parameters defined. The list of diode parameters is
shown below.
General form:
D<name> <anode node> <cathode node> <modelname>
.MODEL <modelname> D ([parmtr1=x] [parmtr2=y] . . .)
Example 2-12:
D1 1 2 mod1
.MODEL mod1 D
Example 2-13:
D2 1 2 Da1N4004
.MODEL Qa1N4004 D (IS=18.8n RS=0 BV=400 IBV=5.00u CJO=30
M=0.333 N=2)
A simple strategy is to build a SPICE model from those parameters listed

on the data sheet. Another strategy is to take measurements of an actual
device. Then, calculate, and adjust the SPICE parameters.
137
Table 2-3: Diode SPICE Parameters
Symbol Name Parameter Units Default

IS IS Saturation current (diode equation) A 1E-14
RS RS Parsitic resistance (series resistance) Ω 0
n N Emission coefficient, 1 to 2 - 1
τD TT Transit time s 0
CD(0) CJO Zero-bias junction capacitance F 0
υ0 VJ Junction potential V 1
m M Junction grading coefficient - 0.5
- - 0.33 for linearly graded junction - -
- - 0.5 for abrupt junction - -
Eg EG Activation energy: eV 1.11
- - Si: 1.11 , Ge: 0.67, Schottky: 0.69 - -
xi XTI IS temperature exponent - 3.0
- - P-N junction: 3.0, Schottky: 2.0 - -
kf KF Flicker noise coefficient - 0
af AF Flicker noise exponent - 1
FC FC Forward bias capacitance coefficient - 0.5
BV BV Reverse breakdown voltage V ∞
IBV IBV Reverse breakdown current A 1E-3
138
2-16. Summary

P-N junction is one of the fundamental structures within semiconductor

device technology. It has the valuable property that electrons only flow in
one direction across it and as a result it acts as a rectifier. After joining p-
type and n-type semiconductors, electrons near the p–n interface tend to
diffuse into the p region. As electrons diffuse, they leave positively
charged ions (donors) in the n region. Likewise, holes near the p–n
interface begin to diffuse into the n-type region, leaving fixed ions
(acceptors) with negative charge. The regions nearby the p–n interfaces
lose their neutrality and become charged, forming the space charge region
or depletion layer. When no external energy is applied, an equilibrium
condition is reached in which a potential difference is formed across the
junction. This potential difference is called built-in potential
Vbi = VT ln(NaNd/ni2).
When a diode is short circuited, a potential barrier equal to the built-in

voltage is developed across the depletion layer, which is approximately
0.7V for Si diodes and 0.3V for Ge diodes. However, even when the P-N
junction is short circuited (zero bias), no current pass across the diode.
The I-V characteristics of the P-N junction can be deduced from the
concentration of excess carriers, which can be obtained by solving the
diffusion equation in the quasi neutral regions, on both sides of the
depletion region.
The diffusion currents on the two sides give a total of
Unlike a resistor, a diode does not behave linearly with respect to the
applied voltage and therefore we cannot describe its operation by Ohm's
law. Most textbooks tell us that the I-V characteristics of a P-N junction
have an exponential form, typically as follows:
139
  V  
I d  Io exp  d  1
  .VT  
where the thermal voltage VT =kBTL/e is about 26mV at TL =300K, kB is
Boltsmann's constant, Io is the reverse saturation current and  is the
ideality factor.
The reverse saturation current Io is given by:
Io  e.A.  
 Ln Na Lp Nd
 
Both Io and depend upon the diode structure and ambient temperature.
The forward voltage drop, at which the P-N junction diode starts to
conduct appreciable current is in the order of 0.7V (for Si diodes), as
shown in the following figure. In addition to the diffusion current, one
should consider the space-charge recombination current (in forward bias):
Wp Wn   Vd 
J r  12 eni    exp 
  n  p   2VT 
At high current densities, the diode current is influenced by high-level
injection phenomena and is given by:
J = 2e (Dp / Lp) ni exp (Vj /2VT)
where Vi is the part of applied bias, across the space-charge region of the
P-N junction. The rest of applied bias is dissipated as Ohmic drops on
the quasi-neutral regions on both sides of the P-N junction. In reverse
140
bias, the space-charge generation current should be also considered
W 
J g  eni . 
  g 
The ideal diode will behave like a short circuit (closed switch) when it is
forward biased. Also the ideal diode will behave like an open circuit
(open switch) when it is reverse biased. Practically, the diode will have a
small forward resistance (rd =VT/I) and a very high reverse resistance.
The following table shows the various equivalent circuit models of diode
There exist two processes which give rise to breakdown of P-N junctions:
(1) Avalanche multiplication by impact ionization, in low-doped junctions
(2) Zener breakdown by quantum tunneling, in highly-doped junctions
The breakdown voltage of an abrupt P-N junction may be then expressed

as:
VB = 60 (Eg /1.1)3/2 (NI /1016)-3/4
where NI is the doping concentration of the low-doped side of the
junction. The breakdown of a punch-through (short) diode is related to
the breakdown voltage of a long diode, VB, by the following relation:
VBPT = VB (Wb/W).[ 2 - (Wb/W ) ]
where Wb is base width and W is the depletion region width (W=Wn+Wp).
1/ 2 1/ 2
 2  N (V  Va )   2  N (V  Va ) 
Wn   o s a bi  Wp   o s d bi 
 eNd ( N a  N d )  ,  eNa ( N a  N d ) 
141
There exist so many variant diode structures, which have more or less
important applications as P-N junctions. The different diode types of
types of diodes include those for small signal applications, diodes for
light emission (LEDs) and detection, variable capacitance diodes
(varicaps) and Zener diodes.
Semiconductor diodes have taken a long rout of temporal evolution to

reach to their current technology. The following table shows the
milestones in the history of semiconductor diodes
Diode Family Time Frame Construction Application

Galena, Si, with tungsten
Cat's Whisker 1906 AM radio reception
wire on "sweet spot"
Subsequent Ge with tungsten wire, AM reception, microwave
Point Contact
improvement usually housed in glass. detection
Stacked Copper oxide
Copper Oxide 1927 High current battery charger
and Iron disks on a bolt
Stacked Selenium and High Voltage rectifier,
Selenium 1933
metal deposits. battery charger
Ge or Si, Chemical General purpose, computer
Junction Diode 1940
deposition of impurities diode
Schottky Barrier Metal deposition on n- RF detection, high speed
1938
Diode (SBD) type Silicon high power rectification
Junction diode, doping
Varicap Diode Voltage controlled tuning
profile
Junction diode with Current controlled
PIN Diode
intrinsic layer attenuation
Junction diode, doping Voltage regulation,
Zener Diode
profile clamping
Light Emitting Junction Diode, exposed Indicator lamp, house
Diode (LED) junction lighting
Junction Diode, exposed Light detection, Optical
Photodiode
junction isolation, Optocouplers
Junction Diode, Wide Solar electrical power
Solar Cell
Area generation
Tunnel diode Highly doped junction Microwave oscillators
Employs impact
Impatt diodes Microwave oscillators
ionization phenomenon
Step Recovery Junction Diode, with Harmonic generation at
Diode low storage time microwaves
142
2-17. Problems
2-1) What quantities determine the widths of the space charge layer near
the stochiometric (metallurgic) P-N-junction?
2-2) When the P-N junction diode is reversed biased, what happens to the
majority carriers?
1. They combine with minority carriers at the junction
2. They move toward the junction
3. Both 1 and 2 above
4. They move away from the junction
2-3) What causes small leakage current in a reverse-biased P-N
junction?
1. Holes 2. Electrons
3. Minority carriers 4. Majority carriers
2-4) The depletion region in a P-N junction diode contains
(a) only charge carriers (of minority type and majority type)
(b) no charge at all
(c) vacuum, and no atoms at all
(d) only ions i.e., immobile charges
2-5) Consider a semiconductor P-N junction shown in figure. If carriers
are injected from one side such that excess hole concentration at the side
of the semiconductor is a constant and equal pn(0). It is required to
calculate the spatial distribution of excess holes pn(x), across the N side,
assuming low-level injection. Assume pn=0 at the end of the diode
(x=W). Calculate the hole current density Jp at x= W.
Hint: Solve the continuity equation for holes for x > 0 (where there is no
generation):
 pn pn  pno  2 pn
 -  Dp
t p x 2
2-6) What capacitance dominates the dynamics of the forward and
reversed biased diode, respectively?
2-7) Prove that the formula of the P-N junction transition capacitance at
reverse bias may be put in the conventional form:
CT = A/W,
where W is the depletion region width and A is the diode area
143
2-8) The diode in the following circuit has a cut-in voltage of V= 0.6V
and a forward resistance rd = 150. If the diode can dissipate a
maximum power of 200mW, calculate the maximum battery voltage (VB).
Hint: Replace the diode with its equivalent circuit and the circuit to the
left of a-b by its Thevenin equivalent circuit.
2-9) Verify the listed expressions for the DC output current and voltage,
ripple factor and efficiency of the shown half-wave rectifier circuit.
2-10) Calculate the average DC voltage at the load of the following

center-tap full wave rectifier (verify that VDC ≈ 0.65 Vm ≈ 0.9 Vrms)
2-11) Find an expression for the ripple voltage (V) and average DC
output voltage (VDC = Vp - ½ V) of the following full-wave rectifier.
What will be the average DC value of the output voltage when a capacitor
is connected across the output load?
144
2-12) Why the Zener diode is considered as a good voltage regulator?

1. It compensates for low supply voltage
2. It uses an unlimited number of carriers
3. Operating in the breakdown region does not harm it
4. The voltage across the diode remains almost constant after breakdown
2-13) Which breakdown theory explains the action that takes place in a
heavily doped P-N junction with a reverse bias above 5V?
2-21) Find the built-in potential (Vbi) for a P-N junction Si diode at room
temperature if the bulk resistivity of Si is 1cm. The electron mobility in
Si is 1400 cm2/V.s , μn/μp = 3.1, ni = 1.5 × 1010 cm−3 at room temperature.
2-22) For the Si P-N junction from the previous problem calculate the
width of the space-charge region for the applied voltages −10V and 0.3V.
Take s = 11.9
2-23) For the parameters given in the previous problem find the
maximum electric field within the space charge region. Compare these
values with the electric field within a shallow donor: Eid ≈ e/(saB2),
where aB is the Bohr radius of a shallow donor, aB = (s 2/e2mn*) and
mn*/mp* = 0.33.
2-24) Calculate the transition capacitance of the P-N junction from the
problem 2-22 if the area of the junction is 0.1 cm2.
2-26) At room temperature under the forward bias of 0.15V the current
through a P-N junction is 1.66mA. What will be the current through the
junction under reverse bias?
145
2-27) For a P+N Si junction the reverse current at room temperature is

0.9 nA/cm2. Calculate the minority-carrier lifetime if Nd = 1015 cm−3, ni =
1.5 × 1010 cm−3 and μp = 450 cm2 /V.s.
2-28) How does the reverse current of a Si p-n junction change if the
temperature raises from 20 to 50 ◦C? The same for a Ge P-N junction.
Band gaps of Si and Ge are 1.12 and 0.66 eV, respectively.
2-30) A Si P+N junction (ni = 1.5×1010 cm−3, s = 11.9) is formed in an n-
type substrate with Nd = 1015 cm−3. If the junction contains 1015 cm−3
recombination centers located at the intrinsic Fermi level and the capture
cross section σn = σp = 10−15 cm2 (vth = 107 cm/s), calculate generation
current density at a reverse bias of 10 V.
2-31) For a Si P-N junction with the p-side doped to 1017 cm−3, the n-side
doped to 1019 cm−3 (N+P junction), and a reverse bias of −2V, calculate
the generation current density at room temperature, assuming that the
effective lifetime is 10−5 s.
2-32) Find the donor/acceptor concentrations for a GaAs P-N junction at
which de Broglie wavelength (λ=h/√2m*E) of electrons/holes is equal to
the width of the space charge region at 300K. Assume <E> = 3kBT/2,
mn*/mo=0.063, mp*/mo= 0.53, s =12.9, ni = 2.1×106 cm−3 and Na = Nd.
2-33) When a Si P+N junction is reverse-biased to 30V, the depletion-
layer capacitance is 1.75 nF/cm2. If the maximum field at breakdown is
3×105 V/cm, find the breakdown voltage. Take s= 11.9.
2-34) For a P+N Si junction with Nd = 1016 cm−3, the breakdown voltage
is 32V. Calculate the maximum electric field at the breakdown.
2-35) Repeat the solution to Example 2-7, with considering the internal
zener diode resistance in breakdown, as rz = 2.
2-36) Consider a Si P-N junction solar cell of area 2cm2.
If the doping of the solar cell is Na=1.7×1016 cm−3 and Nd = 5×1019 cm−3,
Also, n =10 μs, τp =0.5μs, Dn =9.3 cm2/s, Dp =2.5 cm2/s, and IL = 95 mA,
(i) calculate the open-circuit voltage, and (ii) determine the maximum
output power of the solar cell at room temperature.
2-37) At room temperature, an ideal solar cell has a short-circuit current
Isc= 3A and an open-circuit voltage Voc= 0.6 V. Calculate and sketch its
power output as a function of operation voltage and find its fill factor.
146
2-19. References
[1] N.F. Mott, The Theory of Crystal Rectifiers, Proc. Roy. Soc.
London, vol. A 171, pp.27-38, 1939.
[2] R. S. Ohl, "Light-sensitive electric device," U.S. Patent 2,402,662.
Filed May 27, 1941, Granted June 25, 1946.
[3] W. Shockley, "The theory o£ P-N junctions in semiconductors and
P-N junction transistors," Bell Syst. Tech. Journal., vol. 28, p.435, 1949.
[4] W. Shockley, Electrons and Holes, Van Nostrand, N.J., 1950.
[5] C. T. Sah, R. N. Noyce and W. Shockley, ―Carrier Generation and
Recombination in P-N Junction and P-N Junction Characteristics,‖ Proc.
IRE, Vol. 45, No. 9, p. 1228, 1957.
[7] J. L. Moll, "The evolution of the theory for the voltage-current
characteristic of P-N junctions," Proc. IRE, vol. 46, p.1076, 1958.
[8] John L. Moll, "Variable capacitance with large capacity change," IRE
Wescon Convention Record, Part 3, pp.32-36, 1959.
[9] S. M. Sze and G. Gibbons, ―Avalanche breakdown voltages of abrupt
and linearly graded P-N junctions in Ge, Si, GaAs, and GaP,‖ Applied
Physics Letters, vol.8, p.111, 1966.
[10] Chih-Tang Sah (University of Illinois) ―The spatial variation of the
quasi-Fermi potentials in p-n junctions,‖ IEEE Transaction on Electron
Devices, ED-13, 839-846, December 1966.
[12] H.A. Watson, ―Microwave Semiconductor Devices and their Circuit
Applications,‖ McGraw-Hill, 1969.
[14] B. G. Streetman, Solid State Electronic Devices, Prentice Hall,
Englewood Cliffs, 1972.
[15] S.K. Ghandhi, Semiconductor Power Devices, John-Wiley Sons,
New York, 1977.
[17] E. S. Yang, Microelectronic devices, McGraw-Hill, NY, 1988.
[19] Mike. J. Cooke, Semiconductor Devices, Prentice Hall
International, UK, 1990.
[22] K. Ismail "Electron resonant tunneling in Si/SiGe double barrier
diodes". Applied Physics Letters, Vol. 59, p. 973, 1991.
[29] S. M. Sze, Semiconductor Devices, Physics and Technology, John-
Wiley Inc., 2d eEdition, 2002.
[30] Antonio Luque, Hegedus, (Editors). Handbook of Photovoltaic
Science and Engineering. John Wiley and Sons, 2003.
[31] W. Koechner, Solid-State Laser Engineering, 6th Edition., Springer,
Berlin , 2006.
[32] Raymond T. Tung, The physics and chemistry of the Schottky
barrier height, Appl. Phys. Rev., Volume 1, Issue 1, p.011304, 2014.
147
Bipolar Junction Transistors (BJT’s)
Contents:

3-2. BJT Structure
3-3. Theory of Operation
3-4. Circuit Configurations
3-5. BJT Operating Modes
3-6. BJT Currents
3-7. Static I-V Characteristics of a BJT
3-8. BJT Models
3-9. BJT Circuit Analysis (DC Analysis)
3-10. Small Signal Model of a Bipolar Transistor
3-10.1. Hybrid- Model
3-10.1. Hybrid Parameters Model
3-11. BJT as an Amplifier (AC Analysis)
3-11.1. Active Mode Biasing Schemes
3-11.2. Calculation of the AC Voltage Gain
3-11.3. AC Beta Factor
3-11.4. Examples
3-12. BJT as a Switch
3-13. BJT Switching Times
3-14. Physical Limitations of the BJT
3-14.1. Breakdown Voltage
3-14.2. Maximum Current
3-14.3. Maximum Power
3-14.4. Safe Operating Area (SOA)
3-14.5. Thermal Derating
3-14.6. Variation of Current Gain with Collector Current
3-14.7. High Voltage Effects (Early Effect)
3-14.8. Kirk Effect
131

3-15. BJT Fabrication Technology

3-16. Other BJT Structures
3-16.1. Unijunction Bipolar Transistor (UJT)
3-16.2. Hetrojunction Bipolar Transistor (HBT)
3-16.3. Resonant tunneling Bipolar Transistor (RTBT)
3-17. Laboratory Testing of a BJT
3-19. Summary
3-20. Problems
3-21. Chapter Assessment
3-22. References
132

Bipolar Junction
Transistors (BJT)
A bipolar junction transistor (BJT) is a semiconductor element made up
of two P-N junctions. In this chapter, we present the fundamental
concepts about BJTs and their basic circuits. We briefly demonstrate how
to use such electronic devices to amplify and switch signals in different
configurations.
Upon Completion of this Chapter, the student should:
Understand the principle function of bipolar transistors.

Be acquainted with the circuit configurations and biasing methods of
the BJT,
Identify the different current components and the current amplification
factor of the BJT
Draw and explain the input and output I-V characteristics of the BJT,
Distinguish between, cut off, active, and saturation region operation of
a BJT,
Be acquainted with the BJT circuit models (Ebers-Moll, and Gummel-
Poon models),
Be acquainted with the small signal equivalent circuit (hybrid-pi and
h-parameter models) of the BJT,
Apply the appropriate circuit models correctly,
Know the phenomena dominate the switching of a BJT,
Draw and explain the turn-on & turn-off characteristics of a BJT,
Identify the BJT quirks and physical limitations,
Interpret manufacturer datasheets and ratings of BJTs,
Differentiate between different packages of a BJT,
Know how to test a BJT, using a simple avometer,
Know other forms of bipolar transistor, such as heterjunction bipolar,r
transistor (HBT), and how they operate.
133

3-2. BJT Structure

There exist two types of bipolar junction transistors according to whether
the central area is of type N or P. The two types of transistors are
represented on figure 3-1(a). As shown in figure, the tow types are NPN
and PNP BJT’s. Their study is led strictly in the same way and the
properties of the one apply to the other.
Figure 3-1. P-N-P and N-P-N bipolar transistors and their circuit symbols.
Note 3-1. History of the Bipolar Transistor
The history of bipolar transistor started about fifty years ago, after the
World War II, when William Shockley decided to build a triode-like
semiconductor device, to replace vacuum tube triodes with solid-state
devices. He secured funding and lab space, and went to work on the
problem with Brattain and John Bardeen. The key to the development of
the transistor was the further understanding of the process of the electron
mobility in a semiconductor. It was realized that if there was some way to
control the flow of electrons from the emitter to the collector of the newly
discovered diode, one could build an amplifier. The Bell team made many
attempts to build such a system with various tools, but generally failed.
Setups where the contacts were close enough were invariably as fragile as
the original cat's whisker detectors had been. Their work led them first to
the point-contact transistor. The following figure shows the schematic of
the first point-contact transistor. They made it from strips of gold foil on a
plastic triangle, pushed down into contact with slab of germanium. In
1948, Bells Lab unveiled the transistor.
134

They decided to name it transistor instead of Point-contact solid state

amplifier. John Pierce invented the name, combining trans-resistance with
the ending common to devices.
Later, Shockley made the bipolar Junction transistor (sandwich). This

transistor was more practical and easier to fabricate. The bipolar junction
transistor was the first solid-state amplifier element and started the solid-
state electronics revolution.
135

3-3. Theory of Operation of the BJT

Figure 3-2 shows a schematic structure of a P-N-P bipolar junction
transistor. As shown, the BJT consists of two back-to-back P-N junctions,
who share a thin common base (termed B). Contacts are made to all three
regions, including the emitter (termed E) and collector (termed C). The
device is called bipolar since its operation involves both types of charge
carriers; electrons and holes. Note that the emitter current, IE, is equal to
the sum of the collector current, IC, and the base current, IB, that’s (IE = IC
+ IB). Actually, a small part of the emitter current recombines in the base
region so that IC = F IE +Is, where F is called the forward current gain
(typically 0.99) and Is is the reverse saturation current of the collector
junction.
Fig. 3-2. Schematic structure of a P-N-P bipolar junction transistor.
3-4. BJT Circuit Configurations

The current-voltage (I-V) characteristics of the bipolar transistors consist
of the relations between the currents and input voltages of the transistor.
According to the adopted circuit configuration, the I-V characteristics
will be different. There exist three configurations for the bipolar
transistors, namely:
1- Common-base (C-B) configuration,
2- Common-emitter (C-E) configuration, and
3- Common collector (C-C or emitter follower) configuration.
The following figure depicts the first two configurations.
136

Fig. 3-3. Principal circuit configurations of a bipolar junction transistor
3-5. BJT Operating Modes

The BJT has 4 possible operation modes, as shown in figure 3-4 and the
following table. While the forward-active mode of operation is the most
useful bias mode when using a bipolar junction transistor as an amplifier,
the other bias modes are useful when using the device as a switch. In the
reverse-active mode, we reverse the function of the emitter and the
collector. We reverse bias the base-emitter junction and forward bias the
base-collector junction, or VBE < 0 and VBC > 0. In this mode we replace
the emitter parameters by the collector parameters.
Fig. 3-4. Different operation modes of a BJT.
Table 3-1. BJT operation modes.
B-C Junction
B-E Junction
Forward Reverse
Forward Saturation (ON) Forward-Active
(Amplifier)
Reverse Reverse-Active Cut-off
(Bad Amplifier)
137

3-6. BJT Currents

Figure 3-5 depicts the current components of a P-N-P transistor. As
shown in figure, the emitter base junction is forward biased by VEB and
the collector-base junction is reverse biased by VCB. The majority carriers
in the emitter (holes) are injected by the aid of the forward bias into the
base region, Then, the injected holes are diffused inside the N-base and
part of them reaches the collector boundary where they are extracted
(collected) by the aid of the base-collector reverse bias.
The total emitter current is the sum of the hole diffusion current, IE,n, the
electron diffusion current, IE,p and the base-emitter depletion layer
recombination current, Ir,d.
(3-1)
Fig. 3-5. Current components of a P-N-P bipolar junction transistor.
The total collector current is the electron diffusion current, IE,n, minus the
base recombination current, Ir,B.
(3-2)
The base current is the sum of the hole diffusion current, IE,p, the base
recombination current, Ir,B and the base-emitter depletion layer
recombination current, Ir,d.
(3-3)
138

The transport factor, , is defined as the ratio of the collector and emitter
current:
(3-4)
Using Kirchoff's Current Law (KCL), we find that the base current equals
the difference between the emitter and collector current. The common
emitter current gain, , is defined as the ratio of the collector and base
current as follows:
(3-5)
This explains how a bipolar junction transistor can provide current

amplification. If the collector current is almost equal to the emitter
current, the transport factor, , approaches one. The current gain, , can
therefore become much larger than one. To facilitate further analysis, we
now rewrite the transport factor, , as the product of the emitter
efficiency, E, the base transport factor, T, and the depletion layer
recombination factor, r.
= E Tr. (3-6)
The emitter efficiency, E, is defined as the ratio of the electron current in
the emitter, IE,n, to the sum of the electron and hole current diffusing
across the base-emitter junction, IE,n + IE,p.
(3-7a)

Assuming constant doping concentrations in emitter and base (NE, NB)
and constants diffusion coefficients of minority carriers (Dp,E , Dn,B), the
above relation may be related to the BJT physical parameters as follows:
E = 1/[1+(IE,p /IE,n) ] ≈ 1/[1+ (NBWB Dn,E)( NEWE Dp,B)] (3-7b)
139

The base transport factor, T, equals the ratio of the current due to
electrons injected in the collector, to the current due to electrons injected
in the base.
(3-8a)
Again, assuming constant doping concentrations and diffusion

coefficients, the base transport factor may be given by:
T = IC,n /IE,n = sech(WB /Lp,B ) ≈ 1- ½ (WB / Lp,B )2 (3-8b)
where Ln,B = √(Dp,B p) is the mean free length of minority carriers
(electrons) in the P-base of an NPN BJT, Dp,B is their diffusion coefficient
and p is their lifetime.
Recombination in the depletion-region of the base-emitter junction

further reduces the current gain, as it increases the emitter current without
increasing the collector current. The depletion layer recombination factor,
r, equals the ratio of the current due to electron and hole diffusion across
the base-emitter junction to the total emitter current:
r = (IE - I r,d) / IE = 1 – ( Ir,d / IE) (3-9)
This parameter is voltage-dependent, because the recombination current

in the emitter-base depletion region depends on the junction voltage
(VEB). However, for simplicity, we may neglect recombination in the E-B
depletion region and consider r ≈1.
Example 3-1
Consider a PNP BJT with emitter doping of 1018 cm-3 and base doping of
1017 cm-3. The quasi-neutral region width in the emitter is 1 m and 0.2
m in the base. Take n = 1000 cm2/V.s and p = 300 cm2/V.s. The
minority carrier lifetime in the base is 10ns. The BJT when it is biased in
the forward active mode. Calculate the following parameters of the BJT:
(i) the emitter efficiency,

(ii) the base transport factor, and
(iii) the current gain
Assume there is no recombination in the depletion region.
140

Solution
The emitter efficiency of a PNP BJT is given by E = IE,p / (IE,p + IE,n),
and may be approximated as follows:
Substituting the emitter and base doping concentrations (NE, NB) and
widths (wE, wB) as well as their diffusion constants (Dn,B, Dp,E), results
inE =0.995.
Similarly, the base transport factor T ≈ 1- ½ (WB / Lp,B)2, which may be

approximated as:
If we neglect the recombination in the E-B depletion region (r =1), then
the common-base current gain = E T = 0.993 and the common emitter
current gain  is given by:
The above current components can be calculated and related to the BJT
physical parameters, by substituting the minority carrier distributions and
the electrical potential into the semiconductor current equations, in the
different regions of the transistor, at different bias conditions. The
minority carrier distributions, themselves, can be obtained by solving the
semiconductor continuity equations, using the appropriate boundary
conditions. Usually, we make use of the regional approach, that’s to
divide the BJT into quasi-neutral regions and space charge regions
(around metallurgical junctions).
Thus, the electrical potential () can be obtained by solving the Poisson
equation inside the space charge regions (SCR). The energy band diagram
across an NPN BJT in the forward mode is shown in figure 3-6(a). This
distribution, can be obtained from the electrical potential (E = -e),
which can be obtained by solving the Poisson equation, in space-charge
regions.
141

Fig. 3-6(a). Energy band diagram across an NPN BJT in the forward active mode.
Note that the electrical potential and hence the energy bands are flat in
quasi-neutral regions (QNR), as shown in figure 3-6(b).
142

Fig. 3-6(b). Energy band diagram across an NPN BJT in the forward active mode.
After solving Poisson's equation in the space-charge regions, we solve the

semiconductor continuity equations in the quasi-neutral regions of the
emitter, the base and the collector to get the minority carrier distributions
(n,p). The distributions of minority carriers, together with the electrostatic
potential, can be then utilized to determine the BJT current as functions of
the applied bias voltages and other transistor physical parameters.
An approximate solution of the continuity equations in one-dimension

can be obtained by assuming the following conditions:
Low level injection (injected carriers in the base: nB = nB-nBo <<NB)
Uniform doping in each region with abrupt junctions
Negligible bandgap narrowing in the emitter ( Eg<< Eg)
Negligible recombination-generation in space charge regions
Negligible electric fields outside of space charge regions.
The following figure shows the minority carrier distributions in an NPN

BJT in the forward active mode.
143

Fig. 3-6(c). Minority-carrier distribution in quasi-neutral regions of an NPN BJT
After rather long mathematical procedures, we can calculate the transistor

current components. The I-V characteristics of an N-P-N BJT, in the
forward active mode, may be then described by the following equations:
 v  
I C  I S exp  BE   1 (3-10a)
  VT  
I S   vBE  
IB  exp    1 (3-10b)
 F   VT  
I S   vBE  
I E  IC  I B  exp    1 (3-10c)
 F   VT  
where Vt = kBT/e is the thermal voltage (about 26 mV at 300K), F is the

forward current amplification factor and F = F /(1-F) is the forward
144

current gain (in the order of 100). Also, IS is the collector reverse
saturation current (about 1 pA) and given by:
 DnB   DnB ni2 

I S  eAE  pBo   eAE   (3-10d)
 WB   WB N B 
The general I-V characteristics of an NPN BJT, at any bias condition are
given by the following equations:
 v  v  I S   vBC  
I C  I S exp  BE   exp  BC   exp    1 (3-11a)
  VT   VT   R   VT  
I S   vBE   I S   vBC  
IB  exp    1  exp    1 (3-11b)
 F   VT    R 
  VT  
 v  v  I S   v BE  
I R  I S exp  BE   exp  BC   exp    1 (3-11c)
  VT   VT   F   VT  
Here, F and R are the forward and reverse current gain of the BJT.
The so-called Gummel plot depicts the above currents of the BJT (IE , IC
and IB versus VBE) on one plot. The following figure shows the Gummel
plots for a BJT in the forward active mode.
Fig. 3-7. Gummel plots of a BJT in the forward active mode

145

From the above equations, one can derive many useful expressions for the
BJT at specific bias values. For instance, the saturation voltage VCEsat, is
given by the following relation.
 I  
 1  (1   R ). C  
  IB   (3-11d)
VCEsat  VT ln 

 R .1   I C . 1   F   
 I   .
   B  F

  
Example 3-2.
Calculate the saturation voltage of a BJT (in saturation mode) with a base
current IB = 1mA and a collector current IC =10 mA. Take aR =0.993, aF =
0.2 and substitute VT = 26mV.
Solution
The saturation voltage of the BJT is given by:
 I  
 1  (1   R ). C  
  IB  
VCEsat  VT ln 
  
= 0.1 V

 R .1   I C . 1   F .
   I   
 B  F   
Note 3-1. Derivation of the Current Equations
Referring to figure 3-6(c) and starting from the continuity equation of

minority carriers (electrons in NPN transistor) in the base region:
 n   x n  2 npx
x

 t   Gn  Rn x
 n n 
x
 n x   Dn
x x 2
Using the above mentioned assumptions, the continuity equation can be
transformed into the following diffusion equation in steady state:
 2 n  2 n n n
  
x 2 x 2 Dn n L2n
where we dropped the time derivative (∂n/∂t=0) in steady-state, neglected

the electric field (=0) in the base-neutral region and substituted the net
recombination rate (R-G)=n/n.
146

We also substituted Ln  Dn n where Ln is the electron diffusion length

in the base region (assumed constant). The solution of this diffusion
equation with current boundary conditions at the base edges is hence
given by:
 x   x 
n( x)  C1. exp     C2 . exp  
 Ln   Ln 
For simplicity, we consider a uniformly doped base. The expression for

collector current that has been used in the past discussion was based on
low level injection approximation. This approximation allowed the
collector current to be expressed as a purely electron diffusion current:
 dn 
I C  eA.Dn  .
 dx 
Neglect of recombination results in linear variation of electron density
across the base so that
 n(0) 
I C  eA.Dn  .
 B 
W
Where n(0)= n(0) - nBo with nBO =ni2/NB. The second simplification that
low level injection resulted in was that the expression:
n(0). p(0)  n(0).n(0)  N B   n(0).N B
Also, we have from Boltzmann relations:
V 
n(0). p(0)  ni2 . exp  BE .
 Vt 
As p(0) = NB, therefore, we can write:
ni2   VBE  
n(0)  n(0)  nBo  .exp    1.
N B   Vt  
And hence:
 Dn ni2    VBE    V  
I C  eA. ..exp    1  I S exp  BE   1
 WB N B    Vt     Vt  
147

3-7. BJT Models

The components of the currents that we derived in the preceding sections
are those resulting from normal operation of the transistor in the forward
active direction. If the effect of VBC bias is taken into account, one can
rewrite the transistor currents in a more general way, as indicated by
equations (3-11). In addition, one can translate these equations into a
transistor model, which can be utilized in the circuit analysis. Such
models, which are based on the stationary current-voltage relations, are
sometimes called the large signal models.
Actually there exist tenths of BJT large signal models, which have been
introduced since the invention of the BJT, through the academic research
and by the electronic industry (e.g., by HP and Phillips). In the following
sections, we introduce the most salient models (namely: the Ebers-Moll
model and Gummel-Poon model), upon which most of other models are
based.
3-7,1, Ebers –Moll Model

The BJT current equations (3-11) can be translated into the so-called
Ebers-Moll model, as shown in figure 3-8(a). A more elaborate model,
which takes the effect of parasitic capacitances, between the transistor
electrodes, is shown in the following figure.
Fig. 3-8(a). Simplified model of Ebers-Moll.
148

Fig. 3-8(b). Ebers-Moll model, with parasitic capacitances & resistances
Note that the emitter and collector currents in the Ebers-Moll model are
given by:
IE = -IF +aRIR=-IES [exp(VBE/Vt)-1]+ aRICS [exp(VBC/Vt)-1] (3-12)
IC = -IR +aFIF=-ICS [exp(VBC/Vt)-1] – aFIES [exp(VBE/Vt)-1] (3-12)
3-7.2. Gummel–Poon Charge-control Model

The Gummel–Poon (GP) model is a detailed charge-controlled model of
BJT dynamics, which has been adopted and elaborated by others to
explain transistor dynamics in greater detail than the terminal-based
models typically do. For instance, this model includes the dependence of
transistor β-values upon the direct current levels in the transistor, which
are assumed current-independent in the Ebers–Moll model.
As shown in the following figure, the GP model is a three-terminal model

(emitter, base, and collector) and consists of three current sources, If, Ir
and IT, two capacitances associated with the charges and stored between
the base and collector terminals and between the base and emitter
terminals, respectively, and four series resistances, two associated with
the base region and one each associated with the base and collector
regions.
149

Fig. 3-8(c). Gummel-Poon model, including parasitic capacitances & resistances
The basic of all variants of the GP model is the integral charge control
model for the DC current passing through the emitter and collector
terminals. In this model, the collector current is split-up into two currents
IC = If - Ir. The currents of the Gummel-Poon model be expressed in
terms of the base charges, as follows:
Ic = (Qbo /Qb ).Is[exp(VBE/Vt) - exp(VBC/Vt) ], (3-13a)

If = (Qbf /Qb ).Is[exp(VBE/Vt) - 1 ], (3-13b)
Ir = (Qbr /Qb ).Is[exp(VBC/Vt) - 1 ] (3-13c)
where:
Qbo is the zero-bias base charge,
QTe and QTc are the depletion charges of the emitter an collector
junctions, respectively, Qbr = QTe+ QTc,
Qbe and Qbc are the stored charges of the minority carriers, injected
respectively from the emitter and collector, Qbf = Qbe+ Qbc,
150

The total base charge consists of the following charges:
Qb = Qbo + Qbf + Qbr = Qbo + Qbe + Qbc + QTe + QTc (3-14)
The stored charges and Qbc can be related to the forward and reverse
currents If and Ir by the charge-control principle
Qbe =f If (3-15a)

Qbc =r Ir (3-15b)
where the constants f and r are the forward and reverse base transit
times. Also, the depletion charges of the emitter and collector junctions
can be related to the respective transition capacitances (CTe, CTc).
QTe =  CTe dv (from 0 to VBE) (3-15a)

QTc =  CTc dv (from 0 to VBC) (3-15b)
After calculating and summing all the components of Qb, it may be

expressed as follows:
Qbo =(1+VBC/VAF+VBE/VAR).{ ½+ √[ ¼+ If/IKF+ Ir/IKR]} (3-17)
The total current can be hence expressed as follows:
IT = (Qbo /Qb ).(If - Ir). (3-18)
Hence, the collector current in the forward-active mode is given by:
V  1  (VCE  VBE ) / VAF

I C  2 I S . exp  BE . (3-19a)
 Vt  1  1  (4 I S / I KF ). exp(VBE / Vt )
where IKF is the corner value of the collector current for beta factor (F)
roll-off. A similar expression for the emitter current in the reverse active
mode is given by:
V  1  (VBE  VCE ) / VAR

I E  2 I S . exp  BC . (3-19b)
 Vt  1  1  (4 I S / I KR ). exp(VBC / Vt )
where IKR is the corner value of the emitter current for the inverse beta
factor (R) roll-off.
151

3-8. Static I-V Characteristics of a BJT

There exist two basic sets of plots of the current-voltage characteristics of
a BJT, as described by equations (3-11). These plots express the BJT
input and output currents variations versus input and output voltages, and
they hence depend on the bias configuration. In the common-emitter (C-
E) configuration of a BJT, these plots are:
The BJT input characteristics (IB versus VBE, at different values of VCE)
The BJT output characteristics (IC versus VCE, at different values of IB).
In the common-base (C-B) configuration of a BJT, the plots are:

The BJT input characteristics (IE versus VBE, at different values of VCB)
The BJT output characteristics (IC versus VCB, at different values of IB).
As the C-E is the most famous configuration, the BJT output (IC vs VCE)
and input (IE vs VBE) characteristics are the best known and usually given
in data sheets. As shown in figure 3-9, the output characteristics (IC versus
VCE) are actually a family of curves at different values of the base current
(IB). We consider here a BJT in the common-emitter configuration circuit.
We apply a forward bias to the emitter junction and a reverse bias to the
collector junction. Then, we have a family of curves for each value of
base current in the output characteristics.
Fig. 3-9(a). Input characteristics (IE -VBE at different values of VCB) of an NPN BJT.
152

Fig. 3-9(b). Output characteristics (IC –VCE at different values of IB) of an NPN BJT.
Fig. 3-10. Schematic of the output characteristics of an NPN BJT in the CE and CB
configurations
153

The operating point (Q) of the BJT is determined by the intersection of

the load line of the collector resistance (RC) with one of this family of
curves.
The operating point base current is determined by the base resistance (RB)
and base bias voltage (Vbb). Note the limits of saturation region (VBE >
VBEsat, IB = IBsat) and cutoff region (VBE < V, IB = 0).
Fig. 3-11. BJT output characteristics (IC versus VCE for different values of IB) in the
forward active region.
154

3-9. BJT Circuit Analysis (DC Analysis)

Using the superposition principle, the transistor circuit analysis may be
divided into DC analysis and AC analysis. However, when we analyze a
BJT circuit, we don’t know- a priori – the operation mode of the BJT, so
we do not know in which state: Cut-off, Active-linear, or Saturation it is.
Therefore, in order to analyze a BJT circuit, we need to assume that BJT
is in a particular state, and proceed with the BJT DC analysis to check the
validity of our assumption.
The formal DC analysis procedure of a BJT is as follows:
1) Write down a KVL including the BE junction (BE-KVL).
2) Write down a KVL including CE terminals (CE-KVL).
3) Assume BJT is in cut-OFF (simplest case). Set IB = 0. Calculate VBE
from BE-KVL.
3a) If VBE < Vγ , then BJT is in cut-OFF, IB = 0 and BE is what you
just calculated. Set IC = IE = 0, and calculate VC E from CE-KVL. You
are done.
3b) If VBE > Vγ, then BJT is not in cut-OFF. Set VBE = Vγ . Solve above
KVL to find IB. You should get IB > 0.
4) Assume that BJT is in active linear region. Let IE ≈ IC = β.I B . Calculate
VC E from CE-KVL.
4a) If VC E > Vγ, then BJT is in active-linear region. You are done.
4b) If VC E < Vγ, then BJT is not in active-linear region. It is in
saturation. Let VC E = Vsat and compute IC from CE-KVL. You should find
that I C < β I B. You are done.
Example 3-3:
Calculate the quiescent point of the following BJT circuit. Take β = 100.
155

Solution
BE-KVL: 4 = 40× 103IB +VBE
CE-KVL: 12 = 103 IC +VC E ,
Assume BJT is in cut-OFF. Set IB = 0 in BE-KVL:
BE-KVL: 4 = 40× 103IB + VBE  VBE= 4 > Vγ ( 0 .7 V ) , So BJT
is not in cut OFF and BJT is ON.
Set VBE = 0.7V and use BE-KVL to find IB.
BE-KVL: 4= 40× 103IB +VBE  IB = 4−0.7Then 40,000 IB = 82.5µA
Assume BJT in active linear mode, Find IC = β I B and use CE-KVL to
find VC E : IC= β IB= 100 IB= 8 .25 mA
CE-KVL: 12 = 1, 000 IC + VC E  VC E = 12 − 8.25 = 3.75 V
As VC E = 3.75 > Vγ, the BJT is indeed in active-linear and we have: VBE
= 0.7 V, IB = 82.5µA, IE ≈ IC = 8.25 mA, and VC E = 3.75 V.
Example 3-4:
Calculate the quiescent point parameters of the following BJT circuit.
Take β = 100.
Solution
BE-KVL: 4 = 40× 103 IB + VBE + 103 IE
CE-KVL: 12 = 1, 000 IC + VC E + 1, 000 IE
Assume BJT is in cut-OFF. Set IB = 0 and IE = IC = 0 in BE-KVL:
BE-KVL: 4 = 40× 103 IB +VBE + 103 IE  VBE = 4 > 0.7 V
So BJT is not in cut OFF and VBE = 0.7 V and iB > 0. Here, we cannot
find iB right away from BE-KVL as it also contains IE.
Assume BJT is in active linear, IE ≈ IC = β I B:
BE-KVL: 4 = 40× 103IB + VBE + 103βI B
156

4− 0.7 = (40×103 + 103×100) IB. Then IB=24µ IE ≈ iC = β IB = 2 .4 mA

CE-KVL: 12 = 1000 IC + VC E + 1000 IE. VCE = 12− 4.8 = 7.2 V
As VC E = 7.2> V γ , the BJT is indeed in active-linear and we have: VBE
= 0.7 V, IB = 24µA, IE ≈ IC= 2 .4 mA, and VC E = 7 .2 V.
Example 3-5
For the example above, find the load like equation and the Q-point of the
BJT graphically:
Solution
The operating point of a BJT can be found graphically using the concept
of a load line. For BJTs, the load line is the relationship between IC and
VC E that is imposed on BJT by the external circuit. The intersection of the
load line with the BJT characteristics represent a pair of IC and VC E
values which satisfy both conditions and, therefore, is the operating point
of the BJT (often called the Q point for Quiescent point). The equation of
a load line for a BJT should include only IC and VC E (no other unknowns).
This equation is usually found by writing a KVL around a loop with VC E .
KVL: 12 = 1000 IC + VC E +1000 IE But IE = IC_+ IB = 1.01 IC Then the
load line equation is
2010 IC + VC E = 12
The load line, the IC-VC E characteristics of a BJT, and the Q-point are all
shown below.
157

3-10. Small Signal Models of a BJT

At small signals the transistor characteristics can be considered linear
around a specific quiescent point (Q-point). Therefore, the transistor can
be replaced by an equivalent network (usually 2-port network), whose
parameters are related to the BJT physical characteristics, such as the
input resistance and beta factor (current gain).
3-10.1. Hybrid- Model

Figure 3-12 depicts a small signal equivalent circuit for a bipolar junction
transistor. This model is called the hybrid- model of a BJT. It consists
of input impedance (rbé), an output impedance (rce) and a voltage
controlled current source described by the transconductance (gm).
Fig. 3-12. BJT equivalent circuit at low frequency.
The above model is only valid at low frequencies, because it does not
take the BJT inter-electrodes capacitances. Figure 3-13 shows a high-
frequency version of the hybrid- model. This model is sometimes called
the Giacoletto model. Note the existence of the BJT parasitic capacitors,
Cb’c and Cb’e.
The so called cutoff frequency, of the BJT, is given by:
fT = F / [2 rb’s (Cb’e + Cb’c)] (3-20)
For the 2N2222A transistor with Q-point (IC =10mA, VCE =10V), we
have: F =225, gm = 0.385S, rb’e = F /gm = 585, rbb’= 19, Cb’c = 8pF,
Cb’e = 196pF, rb’c =1.5M, rce = 22.5 k, fT =300 MHz.
158

Fig. 3-13. BJT equivalent circuit at high frequency (Giacoletto model)
3-10-2. Hybrid-Parameters Model

Any linear two-port network can be described by the so-called hybrid-
parameter model. It consists of input impedance (h11) an output
conductance (h22) and a current controlled current source described by the
current amplification factor (h21) and voltage controlled voltage source
described by (h12), as shown in the following figure. By the aid of the
hybrid parameters model we can describe the input voltages (v1) and
output current (i2) of the network in terms of the input current (i1) and
output voltage (v2), as follows:
v1 = h11 i1 + h12 v2 (3-21)
i2 = h21 i1 + h22 v2 (3-21)
Fig. 3-14. Hybrid parameter model of a linear two-port network.
159

We can make use of such hybrid parameter model to describe the BJT
behavior for small signals, where the transistor characteristics can be
considered linear around a certain quiescent point (DC bias). For
instance, figure 3-15 depicts the hybrid circuit model of BJT in its
common emitter (C-E) configuration.
It consists of input impedance (hie), an output conductance (hoe) and a

current controlled current source described by the current amplification
factor (hfe) and voltage controlled voltage source described by (hre).
vbe = hie ib + hre vce (3-22a)
ic = hfe ib + h1 vce (3-22a)
Fig. 3-15. Hybrid parameter model of a common emitter BJT .
The hybrid parameters may be related to the Giacoletto (hybrid-) model

parameters, as follows:
hfe = rbé gm (3-23a)
hre = rbé / (rbé + rbc)  rbé / rbc (3-23a)
hoe = 1/ rce + 1 / (rb’c + rbé) + hre rbé  1/ rce (3-23a)
These parameters can be also related to the other conventional 2-port

network parameters, such as the impedance z-parameters and the
admittance y-parameters.
160

3-11. BJT as an Amplifier (AC Analysis)

When the BJT is operating in the active region, (i.e., when the base-
emitter junction is forward biased with VBE > V) while the base collector
junction is reverse biased), then IB > 0 and IC = F IB and it can amplify
small input signals.
3-11.1. Active Mode Biasing Schemes

The following figures show the basic biasing schemes of a BJT in the
forward active mode (as an amplifier), in its three possible configurations.
The corresponding real circuits are also shown besides.
C-B Basic Bias circuit C-B Practical Amplifier Circuit
Fig. 3-16.Application of the BJT as an amplifier, in common-base (C-B)

configuration
C-E Basic Bias circuit C-E Practical Amplifier Circuit

Fig. 3-17. Application of the BJT as an amplifier, in common-base (C-E)
configuration
161

C-C (Emitter follower) Basic Bias circuit C-C Practical Amplifier Circuit
Fig. 3-18. Application of the BJT as an amplifier, in common-collector (C-C) or

emitter follower configuration
3-11.2. Calculation of the AC Voltage Gain

Consider the common-emitter circuit in figure 3-20, where the base bias
Vbb is supplemented with a small signal alternating source vb(t). In this
case the total base current is composed of a quiescent value (say IB2) and
a superimposed alternating value ib(t). We denote the total base current as
the sum iB(t) =IB+ ib(t). Also, the total collector current is iC(t) =IC+ic(t).
Similarly, the total collector voltage is vCE(t)=VCE+ vce(t). Figure 3-20
depicts the variation of the output voltage vo(t) = vCE(t) as a result of the
variation of iB(t) from IB2 up to IB3 and down to IB1. As shown, the output
voltage swing is much greater than the input voltage swing, and the AC
voltage gain is given by:
Av = vo / vb= VCE/(VBE +RBIB)

= RcIC/[(rbe+RB)IB] ≈ - FRc/(rbe+RB)]
(3-24)
Here we neglect the output resistance of the transistor (rce), which may be
much greater than the load resistance RC. We may also consider RB much
greater than the BJT input resistance, rbe, which is typically about 10
We can use one of the simple AC models of the BJT, such as the h-
parameters model shown in figure 3-15 , to derive the AC voltage gain in
a much easier way. Note that the trans-conductance of the BJT (gm) is
162

related to the forward beta factor such that F = gmrb’e. Note also that gm
can be obtained from the DC analysis (gm=VT/IC ≈1/40IC at 300K).
Fig. 3-20. BJT operation as an amplifier.
Also, the current source (gm vb’e) is equal to F ib, which describes the
amplification factor of the BJT. The input resistance in the C-E
configuration is given by rbe = rb’e + rbb’. The base spreading resistance
rbb’ is sometimes neglected so that vb’e ≈ vbe. Note also that all DC sources
(VBB and VCC) are grounded in the AC equivalent circuit of the amplifier.
3-11.3. AC Beta Factor

It should be also noted that the beta factor (F) mentioned so far is only
constant (F = gm rb’e) at low frequencies (up to several MHz). For this
reason it is sometimes called the DC beta factor. Actually, the beta factor
is frequency dependent, as shown in figure 3-21.
The frequency dependence of the forward beta factor (F), may be

described by the following equation:
F = Fo / [1+ j2 rb’e Cb’e] (3-23)
While the unity gain frequency, fT, is an important figure of merit of a

bipolar transistor, another even more important figure of merit is the
163

maximum oscillation frequency, fMAX. This figure of merit predicts the

unity power gain frequency and as a result indicates the maximum
frequency at which useful power gain can be expected from a device.
Fig. 3-21. Current amplification factor versus frequency.
The maximum oscillation frequency, fMAX, is linked to the transit

frequency, fT, and is obtained from:
fMAX = [ fT / (2 rbe Cb’c )] 1/2 (3-24)
where rbe = rb’e + rbb’ is the total base resistance and Cb’ç is the base-
collector capscitsnce.
3-11.4. Examples
The following examples demonstrate the complete analysis of BJT
circuits and the calculation of its voltage gain. For simplicity, we denote
the forward beta factor as β, and consider it as constant.
Example 3-6.
Consider the following BJT circuit. Calculate the quiescent point and the
voltage gain Av = (vo/vin). Take β = 100.
164

Solution
Using the superposition principle, the analysis may be divided into DC
analysis and AC analysis, as shown in the following figure.
DC Analysis
We start with the DC analysis to check if the BJT is in active mode or not
BE-KVL: 4 = 40× 103 IB + VBE + 103 IE
CE-KVL: 12 = 1, 000 IC + VC E + 1, 000 IE
Assume BJT is in cut-OFF. Set IB = 0 and IE = IC = 0 in BE-KVL:
BE-KVL: 4 = 40× 103 IB +VBE + 103 IE  VBE = 4 > 0.7 V
So BJT is not in cut OFF and VBE = 0.7 V and iB > 0. Here, we cannot
find iB right away from BE-KVL as it also contains IE.
Assume BJT is in active linear, IE ≈ IC = β I B:
BE-KVL: 4 = 40× 103IB + VBE + 103βI B
4− 0.7 = (40×103 + 103×100) IB. Then IB=24µ IE ≈ iC = β IB = 2 .4 mA
CE-KVL: 12 = 1000 IC + VC E + 1000 IE. VCE = 12− 4.8 = 7.2 V
165

As VC E = 7.2> V γ , the BJT is indeed in active-linear and we have: VBE

= 0.7 V, IB = 24µA, IE ≈ IC= 2 .4 mA, and VC E = 7 .2 V.
AC Analysis
After confirming that the BJT is in active mode, we proceed with the AC
Analysis. Here we short all the DC battery sources and replace the BJT
with a suitable small signal model (e.g., the h-parameter model).
For simplicity, we may consider hfe =  and neglect hre and hoe and (unless
they are given) and then redraw the equivalent circuit as follows
Now we calculate the voltage gain:

Av = (vo/vin) = -ic Rc = - ib Rc.
The base current can be calculated from the E-B KVL
ib = vin /[RB+hie+(+1)RB].
Substituting ib in the above equation results in
Av = - Rc/[RB+hie+(+1)RB]
Note that can be calculated from the DC analysis hie ≈ Vt/IE =1k
If (+1)RB>>RB+hie, then the AC voltage gain may be approximated as:
Av = - Rc/[(+1)RB] ≈ - Rc/ RB
which is a well know formula for the common-emitter amplifier.
3-12. BJT as a Switch
166

When the BJT leaves the active region, it enters one of two extreme cases
(cutoff or saturation), as shown in Fig. 3-22. When the input voltage is
reduced to zero Volt (actually, anything under the cut-in voltage; VBE ≈
0.6V in Si BJTs), there will be no forward bias to the emitter-base
junction, and the transistor does not conduct. Therefore enters cutoff and
no current flows through the collector resistor (IC ≈ 0) and hence the
collector output voltage is VCC. Alternatively, when the applied base
voltage is sufficiently high, the collector-emitter voltage reaches its
minimum value (VCEsat) and the collector current reaches its maximum
value ICsat = (VCC -VCEsat)/RC.
Fig. 3-22. BJT equivalent circuit in cutoff and saturation states.
Note that, if the base current is further increased (from the base drive
circuit), the collector current cannot exceed this maximum collector
current (ICmax). In fact, the BJT, in saturation is no longer an amplifier and
the condition of saturation is sometimes written in the following form:
IB ≥ ICmax / or  IB ≥ (VCC – VCESAT) / RC (3-25)
Consider the BJT switching circuit in figure 3-23. We will only be

applying one of two voltages to the input 0 V (logic 0) or VCC (logic 1).
We will assume an ordinary N-P-N transistor, with a reasonable current
gain, an emitter-base forward voltage of 0.8V, and a collector-emitter
saturation voltage of about 0.1V. The base resistor is assumed 470 and
the collector resistor is 640. The BJT operates as follows.
167

Fig. 3-23. BJT switching circuit and characteristics in the saturation and cutoff
Fig. 3-24. BJT simple switching circuit
When the input voltage is zero volt (actually, anything under 0.6V), there
will be no forward bias to the emitter-base junction, and the transistor
does not conduct. Therefore no current flows through the collector
resistor, and the output voltage is VCC. Hence, logic 0 input results in
logic 1 output. The amount of forward drop that switches a silicon NPN
BJT is almost 0.8V, and referred to as VBESAT. So, when Vi ≥ VBEsat = 0.8V
then the base current becomes:
IB = IBsat = (Vi – VBESAT) / RB (3-26)
For those who like the mathematics, we assume a similar output circuit
connected to this input, as shown in figure 3-20. Thus, we have a voltage
of 5 - 0.8 = 4.2V applied across a series combination of a 640 output
168

resistor and a 470 input resistor. This gives us a base forward current
of:
IB2 = IBsat= (5-0.8)/ (RB + RC) =4.2V/1110 = 3.78 mA (3-27)
Then IC2 will continue to increase until it reaches its saturation value:
IC2 = ICsat = (Vcc – VCEsat ) / Rc (3-28)
Also, Vo drops to the saturation value VCEsat=0.1V. The time it takes for
the collector current Ic to increase from 0 to 0.1 Icsat is called the delay
time (td).
Fig. 3-25. BJT switching ON circuit, via another switching OFF BJT.
169

3-13. BJT Switching Times

The time it takes for IC to increase from 0.1 Icsat to 0.9 Icsat is called the
rise time (tr). The turn-ON time (tON) is the sum of both the delay time td
and the rise time tr, and given by:
 
 1 
t ON  t d  t r   B .ln   (3-29)
 IC 
 1  
  F .I B 
where B is the base minority carriers lifetime. When the BJT is deeply
driven into saturation then IB continues to increase while IC is saturated at
ICsat, such that:
ICsat / (F IB) ≤ 1 (3-30)
Alternatively, when the transistor is switched OFF and Vi < VBE(about

0.6V for Si BJT’s) then the transistor will still conduct in the reverse
direction for a while, until the storage charge in the base disappears.
IB = (Vi - VBE) / RB. (3-31)
The time it takes for IC to decrease from ICsat to 0.9 ICsat is called the
storage time (ts).
 I Csat 
I 
 B2  
ts   s  F
 (3-32)
 I  I Csat 
 B1  
 F 
where s is the storage lifetime. After the storage charge vanishes, then
the base current goes to zero and the transistor is open.
IB = 0 , IC = 0 , Vo = VCE ≈ VCC. (3-33)
170

The time it takes for Ic to decrease from 0.9 Icsat to 0.1 Icsat is called the
fall time (tf). The switching time (time it takes for Ic to decrease from Icsat
to 0) is called the turn-OFF time (tOFF) and is given by:
tOFF = ts + tf (3-34)
The propagation delay of the BJT inverter is the sum of (tON + tOFF).
Figure 3-21 depicts the BJT switching waveforms and switching times.
One can distinguish the following switching times:
1- td delay time: it is the time necessary to charge the line capacity of the
Emitter junction bases so that the first electrons injected into the base
typically reach the collector. For transistor 2N2219, td = 10ns.
2- tr rise time: it is the time which puts the collector current to pass from
0.1 ICsat to 0.9 ICsat. For 2N2219 at IC =150mA; IB = 15mA, tr=25ns.
3- ts storage time: It is time necessary to evacuate the load stored in the

base. For 2N 2219 with IC =150 mA; IB = 15mA, we have ts = 200ns.
4- tf fall time: The time it takes for Ic to decrease from 0.9 Icsat to 0.1 Icsat
Actually the storage time may be divided into 2 times: ts1 (where IB =
constant and IC = constant) is the time which the transistor spends to pass
from the mode of super-saturation to the active mode. ts2 (where IC
deceases wherease IB = constant) is time necessary to evacuate the stored
load charge in extreme cases of saturation.
In order to decrease the time of storage time ts it is necessary to avoid

supersaturating the transistor. For that, one can place a diode between
collector and bases in the way indicated by figure.3-18. This diode is
called anti-saturation diode. It is generally a Schottky barrier diode
(SBD) and the transistor thus made up is called Schottky transistor.
With such diodes the collector-emitter voltage will be always reverse

biased by at least, the following difference:
VCE = VBE – VSD = 0.7 – 0.45 = 0.25V. (3-35)
where VSD is the nominal forward drop of a Schottky diodes at 300K.

More details about Schottky diodes will be presented in Chapter 4.
171

Fig. 3-26. BJT Switching times and waveforms
Fig. 3-27. Schottky transistor structure and circuit symbol
172

3-14. Physical Limitations of the BJT

Like all electronic devices, the bipolar transistor can function only within
well defined limits of voltage and currents. Data sheets usually have a full
set of charts, showing the various device parameters and limitations as a
function of voltage, current and frequency. Without a thorough
knowledge of the device limits, the device may cease to work and may
even breakdown. In this section we discuss the physical limitations that
should be taken into account, in order to ensure a reliable operation of the
transistor. The basic limitations are grouped in the following categories:
Voltage limitations (Breakdown voltages, and Early effect),
Current limitations (Fall of beta factor current gain and Kirk effect),
Power limitations (safe operating area and thermal derating).
3.14.1. Voltage Limitations (Breakdown Voltage)

The avalanche breakdown of the transistor junctions is an important
effect, which arises at high voltages. Particularly, the reverse bias of the
collector junction, may lead to a high electric field, which leads to an
avalanche multiplication, by impact ionization. Figure 3-28 shows the
avalanche breakdown on the BJT output characteristics (Ic-Vce), at high
collector voltages. In common emitter configuration, when one increases
the base-emitter voltage VBE, the field around the E-B junction increases
and an avalanche multiplication mechanism occurs. Data sheets of
transistors define a certain value of VCE (termed VCEBO and sometimes as
BVCEO), above which the transistor breaks down, when the base terminal
is open. This voltage is represented on the figure 3-28.
Fig. 3-28. Effect of high voltage on the BJT output (Ic-Vce) characteristics
173

Example 3-7.
Determine the open-emitter breakdown voltage (BVCB0) for a power
bipolar NPN transistor with the following parameters. The N+ emitter has
a doping concentration NE=2x1019 cm-3 and thickness WE= 10um. The P-
base has a doping concentration NB=2x1017 cm-3 and thickness WB
=10um. The N-collector drift region has a doping ND=2x1014 cm-3 and
thickness WD=40um. Confirm that the left depletion region has not
penetrated the entire base region.
Solution:
Considering base doping to be much higher than the collector doping, the
electric field profile (x) in the collector can be sketched as follows:
The value of the critical electric field for breakdown in Si is given by:
C (Si) = 4010 ND1.8
The critical electric field for breakdown of the N-drift region doping
concentration of 2x1014 cm-3 is then 2.46 x105 V/cm. The punch-through
breakdown voltage for the P-base/N-drift region junction is:
BVCBO= C WD- ½ eNDWD2/s
Using the values of depletion region width WD and uniform doping ND =
2x1014 cm-3 yield an open-emitter breakdown voltage (BVCB0) of 737V.
Example 3-8.
A BJT has a common emitter current gain of 50 and open-emitter break-
down voltage of 1000V. Determine its open-base breakdown voltage.
Solution
The open-base breakdown voltage (BVCBO) is related to the open-emitter
breakdown voltage (BVCEO) and the common emitter current gain by:
BVCEO = BVCBO /(1+Fo)1/n
where n 6 for Si. Substituting yields BVCBO of 519V.
174

3-14.2. Early Effect

When the voltages applied to the base-emitter and base-collector
junctions are changed, the depletion layer widths and the quasi-neutral
regions vary as well. This causes the collector current to vary with the
collector-emitter voltage as illustrated in Fig. 3-29. A variation of the
base-collector voltage results in a variation of the quasi-neutral width in
the base. The gradient of the minority-carrier density in the base therefore
changes, yielding an increased collector current as the collector-base
current is increased. This effect is referred to as the Early effect.
Fig. 3-29. Effect of high voltage on minority carrier distribution in the base.
The Early effect is observed as an increase in the collector current with

increasing collector-emitter voltage as illustrated in figure 3-24. The
Early voltage, VA, is obtained by drawing a line tangential to the transistor
I-V characteristic at the point of interest. The Early voltage equals the
horizontal distance between the point chosen on the I-V characteristics
and the intersection between the tangential line and the horizontal axis. It
is indicated on the figure by the horizontal arrow. The change of the
collector current when changing the collector-emitter voltage is primarily
due to the variation of the base-collector voltage, since the base-emitter
junction is forward biased. The collector current depends on the base-
collector voltage since the base-collector depletion layer width varies,
which also causes the quasi-neutral width, in the base to vary. This
variation can be calculated from the transistor characteristics, as follows:
175

dI C dI I dWB
 C  C . (3-36a)
dVCE dVCB WB dVCE
This variation can be expressed by the Early voltage, VA, which calculates
the voltage variation that would result in zero collector current.
IC
VA  (3-36b)
dI C / dVCE
We can also prove that the Early voltage VA is equal to the base charge,
QB, divided by the base-collector junction capacitance CBC = s/(xp + xn),
where xp and xn are the extensions of Base-Collector depletion region
width, on both sides of the base-collector junction.
QB eN BWB
VA   (3-37a)
C BC  s /( x p  xn )
Which can be put in the following form:
(3-37b)
with KE = 8 for Si devices. The Early voltage can also be related to the
BJT output resistance, rc, as follows:
dVCE V A
rc   (3-38)
dI C IC
In addition to the Early effect, there is a less pronounced effect due to the
variation of the base-emitter voltage, which changes the ideality factor of
the collector current. However, the effect at the base-emitter junction is
much smaller since the base-emitter junction capacitance is larger and the
base-emitter voltage variation is very limited since the junction is forward
biased. This effect leads to a variation in the ideality factor of the B-E
junction, which is given by:
1 dVBE V C
 .  1  t . BE (3-39a)
Vt d (ln I C ) V A C BC
176

The collector current is therefore given by:
IC = ICs [ exp (VBE /Vt ) -1] (3-39b)
where the ICs is the collector reverse saturation current.
Fig. 3-30. Effect of high voltage on minority carrier distribution in the base.
Example 3-9
What is the Early voltage for the bipolar transistor described in the above
examples?
Solution:
The Early voltage is given by:
where KE is a constant and ND is the collector (drift region) doping

concentration, NAB is the base doping, WB is the base width. Using the
parameters with KE = 8 yields an Early voltage of 3.1 x10 7 V.
3.14.3. Current Limitations (Maximum Current)

The emitter area determines the maximum current capability of the
device. The emitter current ratings depend on the emitter area and
bonding wire size. Therefore, excessive collector currents may damage
the transistor. So, when designing a specific BJT, we should take care if
the load such that the maximum current allowed is not exceeded.
177

3.14.4. Variation of the Current Gain with Collector Current

In all the precedent discussion, we considered the DC current gain of
common emitter transistor (F) as constant. Actually, this value decreases
at very high collector currents, because of the high injection level (base
conductivity modulation). Also, the beta factor at small currents is not
constant because of the base recombination current, which limits the
current gain at small emitter (collector) currents.
Fig. 3-31. Variation of the DC current amplification factor (F) with collector current
The forward current gain (F) at high current levels can be expressed as:
 Fo
F (JC ) 
1  ( J C / JW ) (3-40a)
where BFO is the low injection level current gain (sometimes termed BLL)
and JW is called the Webster current density1, which is given by:
JW = e DnB NB/WB (3-41b)
Here, DnB is the diffusion constant of minority carriers in the base, NAB is
the doping concentration (assumed constant) and WB is the base width.
The high-level injection (HLI) means the increase of the level of injected
minority carriers in the base (electrons in NPN transistor) above the base
concentration. That's when nB = nB - nBo > NB., as shown in the
following figure. The HLI affects the characteristics of BJT and cause
the fall-off of the beta factor at high collector currents.
1
The Webster current is sometimes referred to as the corner current and termed as IKF in BJT models.
178

Fig. 3-32. Carrier distributions in the base of an NPN BJT at low-level injection (LLI)
and high-level injection (HLI).
3-14.5. Kirk Effect

The Kirk effect is the apparent base-width increase in a BJT at high
collector current densities. The base widening into the collector drift
region of a BJT is well known to be the cause of the falloff of the current
gain and cutoff frequency at high collector current densities.
For an NPN silicon bipolar transistor with a uniformly doped drift region,
the Kirk effect was found to begin when the collector current density
reaches a critical value, called the Kirk current density. The Kirk current
density can be expressed in terms of the device physical parameters and
the applied collector bias voltage:
(3-42)
where ND is the doping concentration in the collector drift region, vsat is

the carrier saturation velocity, VC is the applied voltage and WN is the
collector drift length.
3.14.6. Maximum Power

In order to avoid a too significant heating with the collector, the power
dissipated with the collector must remain lower than a maximum value
(Pmax) such that:
179

(3-43)
The power limiting area is thus a hyperbole in the plan (Ic, Vce). In
particular the operating point Q of the transistor must be inside the zone
of reliable operation, as shown in Fig. 3-33.
Fig. 3-33. Physical limitations and safe operating area of a BJT
3.14.7. Safe Operating Area (SOA) of a BJT

In the design phase, all are physical limitations are important, but the
most important of all are the thermal derating and safe operating area
(SOA). There is a great deal you need to know to be able to make proper
use of the charts of these parameters. Fig. 3-28 shows the practical SOA
curve for a switching transistor (MJL4381A). In such a case, it is not only
important to determine the maximum rating values of current and
voltages, but also the switching periods, along which these values can be
applied. As shown in figure, repetitive peak currents of up to 30A are
only permissible for less than 10ms, with collector voltages up to 30V,
when the junction temperature is 25°. This represents a peak power of
300W (the device rating is 230W). Therefore, the transistor will be
stressed and these conditions must not be allowed to continue beyond the
time specified (10ms).
180

For longer stress periods (e.g., for 1 sec), the SOA shrinks and the device
limitations should be reduced. For instance, for 1 second, the maximum
rated current of 15A may only be drawn at collector-emitter voltages
below 15V. This region is limited by the maximum rated current of the
transistor, and will never allow continuous operation at maximum power
because of the thermal derating. Remember that all peak currents and
power dissipations in the above chart are for a junction temperature of
25°. Actually, no transistor can maintain high temperature for long time
in real life. Therefore there is a thermal resistance between the die and
case, and further thermal resistance between case and heatsink.
Fig. 3-34. SOA of a bipolar transistor, for different stress times, at 25C.
Thus, the devices must be derated by 1.84° C/W above 25°, as shown in
figure 3-35. The thermal resistance from junction to ambient air (via the
case, and heatsink) can be expected to be around 1.5-2° C/W (for a big
heatsink), so all dissipation limits quoted can be expected to be as little as
1/2 of those shown in the specifications.
3.14.8. Thermal Derating

Under ideal conditions, a transistor's power dissipation rating refers to the
maximum average power that the device can handle, with the junction
temperature at 25° C.
181

At any temperature above 25°, the power is derated (reduced) linearly,

until it reaches zero at around 150° C. Actually, the maximum power
dissipation PD that a semiconductor device circuit can tolerate at a given
ambient temperature TA is given by:
TJ  TA TJ  TA
PD   (3-44)
 JA  JC  CA
where Tj is the maximum allowed junction temperature (about 125 °C for

Si and more for large gap semiconductors), JA is the thermal resistance
between junction and ambient, JC is the thermal resistance between
junction and case and CA is the thermal resistance between case and
ambient. The thermal resistance is measured in °C/Watt. The following
figure depicts the power dissipation derating of a semiconductor device
versus case temperature (Tc).
Fig. 3-35. Power dissipation derating of a bipolar transistor versus temperature.
182

Fig. 3-36. Mounting of a heat sink on a power BJT
Example 3-9.
Design an NPN transistor that has a current gain  = 500 at VCB = 0.
Assume NDE =1022cm-3 and WE = 0.1um for the emitter and take Dp = 2
cm2/s and Dn = 17cm2/s. The corresponding bandgap narrowing (BGN) in
the emitter side is Eg = 89.3meV. Therefore, the effective intrinsic
concentration in the emitter side is nie = 5.57 ni.
Solution:
The transistor design is an iteration process. We start here with a first
order approximation. The assumptions that are made will have to be
refined in the next iteration.
We will take small doping in the base so as to obtain this high value of
gain. As a result BGN in base can be neglected. This gives
NAWB=5.5x1011. We have several choices here for base doping and the
resulting base thickness. Let us take NA=5.5x1016 and WB= 0.11um
This is the effective base width. Let us calculate the metallurgical base
width. For this we will have to calculate the depletion regions within the
base due to emitter-base and collector-base junctions. For the emitter base
junction we assume a forward bias of 0.7 volts and built-in voltage of
0.95 Volts. Most of the depletion region will lie in the base so that
183

Similarly, the depletion width due to collector junction can be calculated:
The metallurgical base width will be
The punchthrough voltage for such a lightly doped and narrow-base can
be calculated using the expression
This is a very small voltage meaning that transistor can only be operated
close to zero collector-base voltage. The early voltage is also very small.
Thus a large current gain is obtained only at the expense of very small
punch-through and Early voltages.
184

3-15. BJT Fabrication Technology

The first bipolar junction transistors were fabricated from a bar of
germanium with two closely spaced alloyed contacts. This approach was
soon abandoned and replaced by a double diffusion process, where the
base and emitter region are formed by diffusion of impurities. A low-
doped collector region is epitaxially grown on the buried collector contact
layer and isolation is done with a diffusion of opposite type. Figures 3-30
and 31 show a cross section of a diffused epitaxial bipolar transistor and
its fabrication steps.
Fig. 3-37. Profile of a diffused epitaxial BJT.
Fig. 3-38. Fabrication steps of a diffused epitaxial BJT.
185

The following figure 3-39 shows the main processes involved in

integrated bipolar technology. Note the presence of buried epitaxial n+
region to reduce the collector resistance.
(i) Buried layer (v) Emitter diffusion & Collector contact
(ii) Epitaxial layer (vi) Contacts
(iii) Insulation regions (vii) Metallization
(iv) Base diffusion 3-dimensional view of a npn transistor
Fig. 3-39. Sequence of major processes involved in monolithic bipolar technology.
186

The BJT's described above were non-self-aligned structures, typical of

transistors used in 1970's. Since then, so many improvements have been
introduced in the BJT technology. For instance, the so-called poly-emitter
and the self-aligned BJT technologies have resulted in faster BJT's, for
high-speed digital and RF circuits.
Through use of self-aligned techniques, both the extrinsic base resistance,

as well as extrinsic base capacitance can be sharply reduced resulting in
overall improvement in delay. The self-aligned structures are described
below, as shown in figure 3-40.
Self-aligned BJT Double-poly self-aligned BJT
Fig. 3-39. Structure of modern modern bipolar transistors.
The oxide spacer layer shown in the self-aligned structure is very narrow
so that the base contact is very close to the intrinsic base region as
compared to the non-self-aligned structure shown in the first Figure. The
use of poly silicon facilitates formation of the spacer to isolate emitter
and base contacts and also improves the current gain. Note that the base
contact is formed on the P+Poly which makes the contact with the
extrinsic base region.The following figure depicts the cross section of a
modern RF-bipolar transistor.
187

Fig. 3-40. Profile of an RF BJT.
188

3-16. Other BJT Structures

There exist several variant structures of the BJT, which provide additional
degrees of freedom, and allow higher operation frequency and faster
switching speeds. For instance, the heterojunction bipolar transistor
(HBT) is an improvement of the BJT that can handle signals of very high
frequencies up to hundreds GHz.
3-16.1. Unijunction Transistor (UJT)

The basic structure of a uni-junction transistor (UJT) and its equivalent
circuit are shown in figure 3-40. It is essentially a bar of N-type
semiconductor material into which P-type material has been diffused
somewhere along its length.
Fig. 3-40. Structure and equivalent circuit of a unijunction transistor (UJT).

A simple bias circuit is also shown at the right-hand side.
Fig. 3-41. I-V characteristics of a UJT.
189

As shown in figure 3-41, the UJT emitter current versus voltage

characteristic have a peak of emitter voltage at a certain emitter current IP.
Beyond the peak point, current increases as voltage decreases within a
negative resistance region. The voltage reaches a minimum at the valley
point and the saturation resistance RB1 is low at this valley point. For
instance, IP and IV, for a 2n2647, are 2µA and 4mA, respectively. Also,
VP is the voltage drop across RB1 plus a 0.7V diode forward drop. The
valley voltage VV is about 10% of the bias VBB.
The UJT was especially designed to trigger thyristors and this is where its
main application lies. The following figures depict the application of a
UJT as an R-C oscillator or as a trigger circuit for a thyristor. As we’ll see
in a following Chapter, the thyristor is a power switching device, which
can be controlled through its gate by timely-controlled pulses. It should
be noted that the so-called Programmable UJT (PUT) is a four-layer
structure, which belongs to the thyristor family, but its I-V characteristics
are similar to those of the UJT.
Fig. 3-42. Application of a UJT as an oscillator.
Fig. 3-43. Application of a UJT to provide time delay for a thyristor

190

Fig. 3-44. Comparison between the structure and symbols of the UJT and the PUT
3-16.2. Hetrojunction Bipolar Transistor (HBT)

Heterojunction bipolar transistors (HBT) is an improvement of the
bipolar junction transistor (BJT) that can handle signals of very high
frequencies up to several hundred GHz. HBT’s are common in modern
ultrafast and RF systems. HBT’s are composed of at least two different
semiconductors. As a result, the energy bandgap as well as all other
material properties can be different in the emitter, base and collector. This
allows high doping to be used in the base, creating higher electron
mobility while maintaining high gain.
The analysis of the device starts with the calculation of the DC current
gain. To this end we recall the equations for the electron and hole current
in the base-emitter junction, namely:
(3-45a)
(3-45b)
191

where the intrinsic carrier density in the emitter, ni,E, and base, ni,B, are
different (because of the different materials), is indicated explicitly by the
additional subscripts.
Fig. 3-45. Cross Section of GaAs/GaInP HBT
The emitter efficiency of the transistor is still calculated from the electron
current relative to total emitter current and equals:
(3-46)
If we now assume that the effective density of states for electrons and
holes are the same in the emitter and base, we find that the maximum
current gain from the definition:
 (3-47a)
such that the DC current gain  of an HBT is approximately given by

or
(3-47b)
where Eg is the difference between the bandgap energy in the emitter
and the bandgap energy in the base. The current gain depends
exponentially on this difference in bandgap energy.
192

As a result one can obtain a very large current gain in a heterojunction

bipolar transistor, even if the base doping density, NB, is larger that the
emitter doping, NE. Therefore, the emitter of a heterojunction bipolar
transistor has a wider bandgap than its base. This difference should be
around 0.2V - 0.4V for optimum performance. A smaller value gives a
small improvement. A larger difference causes the gain to be strongly
temperature dependent, and creates a distinct spike in the energy diagram,
which in turn limits the current.
The advantages of HBTs are not restricted to its DC performance. The

HBT devices can also be improved dramatically by using an appropriate
heterojunction material system. In order to illustrate this point we now
recall the equations for the transit frequency, fT, and the maximum
oscillation frequency, fMAX
fT = 1/ (2 ) (3-48)
where the total transit time is given by the sum of emitter, base and
collector transit times:
VT WB2 x
   E   B   C  Cbe   d , BC (3-49)
IE 2 DnB 2vsat
Fig. 3-46. I-V characteristics of an HBT

193

Also, the maximum operating frequency of the device is given by:
fT
f Max  (3-50)
2 .rbb ' .Cbc
Here rbb’ is the base spreading resistance and Cbc is parasitic transition
capacitance at the B-C junction.
Since a heterojunction transistor can have large current gain, even if the
base doping density is higher than the emitter doping density, the base
can be much thinner even for the same punch-through voltage. As a result
one can reduce the base transit time without increasing the emitter
charging time, while maintaining the same emitter current density. The
transit frequency can be further improved by using materials with a
higher mobility for the base layer and higher saturation velocity for the
collector layer.
An HBT can be further improved by grading the composition of the base

layer such that the energy of the material is gradually reduced throughout
the base. The grading causes an electric field, which in turn reduces the
base transit time:
(3-51a)
with
(3-51b)
where Eg,MAX and Eg,MIN are the maximum and minimum energy bandgap
at the edges of the base region (at x’ = 0, x’ = xB). A linear variation may
be assumed in between. δ
The improved transit time immediately increases fT. The higher base
doping also provides a lower base resistance and a further improvement
of fMAX. As in the case of a BJT, the collector doping can be adjusted to
trade off a lower collector transit time for a lower base-collector
capacitance. The fundamental restriction of heterojunction structures is
the mismatch of lattice constants of different materials.
194

Fig. 3-47. The AC model of an HBT. Note the intrinsic model is shaded and the
external packaging and stray parasitics are also indicated in the outside.
3-16.3. Resonant Tunneling Bipolar Transistor (RTBT)

The resonant tunneling bipolar transistors (RTBT) have many advantages
such as their high current handling capability and high current gain. The
following figure depicts the structure of an InGaP/GaAs RTBT, with
super lattice emitter. This device is usually grown by low-pressure metal
organic chemical vapor deposition (LP-MOCVD) system on an N+-GaAs
substrate.
The vertical integration of RTBT and three terminal transistor structures

reduces the signal delay and power dissipation. As compared to the
AlGaAs/GaAs material system, the InGaP/GaAs system is more suitable
for super-lattice applications since the normal InGaP/GaAs and inverted
GaAs/InGaP interfaces are both smooth on the atomic scale.
The following figure illustrates the typical I-V characteristics of the

RTBT. Experimentally, the studied device exhibits excellent transistor
characteristics including the high current gain, high breakdown voltage,
low saturation voltage, and low offset voltage.
195

Fig. 3-48. RTBT structure and circuit symbol.
Fig. 3-49. RTBT I-V characteristics.
196

3-17. Laboratory Testing of a BJT

As BJT’s are composed of two P-N junctions, their laboratory test
involve the checking of both the base-emitter (BE) and collector-base
(CB) junctions, in both sides, as shown in the following figure. We may
use here the ohmmeter check, which should show a low resistance in the
forward direction of each junction and a high resistance in the reverse
direction. Meter readings should be opposite, of course, for an N-P-N
transistor, with both P-N junctions connected the other way. You may
distinguish the emitter, the base and the collector terminals, using
conventional packaging arrangment, shown below in figure 3-50.
Fig. 3-50. Testing of a BJT, using a simple millimeter (Ohmmeter). The pin-
assignment of some famous BJT packages are shown below.
However, some multimeters are equipped with diode check, which can be
used to check the forward drop of each diode. Better than this, some
multimeters, have an “hfe” check, for testing bipolar transistors and
197

giving the current amplification factor (). If your meter has a designated
diode check function, use that rather than the resistance range, and the
meter will display the actual forward voltage of the P-N junction and not
just whether or not it conducts current.
You may also check the voltage gain of a simple BJT amplifier, using a
multimeter, as shown in the following figure. Fortunately, some digital
multimeters are equipped with oscilloscope screens, and can plot the
voltage waveforms. You may check that the AC voltage gain of the
shown amplifier is given by: Av = vout/vinput = - Rout/Rin, where Rout is the
resistor in series with the collector (the speaker resistance, 8 ) and Rin is
the resistor connected in series with the base (1k). Note that AC output
voltage, vout, is equal to the AC collector-emitter voltage, vce.
Fig. 3-51. Testing of a BJT amplifier, using a millimeter, with oscilloscope.
198


The PSPICE model of a BJT is depicted, together with its parameters, in
Appendix B at the end of this Book.
The BJT statement begins with a diode element name which must begin
with “Q” plus optional characters. Example diode element names include:
d1, d2, da, db. Two node numbers specify the connection of the anode
and cathode, respectively, to other components. The node numbers are
followed by a model name, referring to a subsequent “.model” statement.
The model statement line begins with “.model,” followed by the model
name matching one or more diode statements. Next, a “d” indicates a
diode is being modeled. The remainder of the model statement is a list of
optional diode parameters of the form ParameterName=ParameterValue.
None are used in Example below. Example2 has some parameters
defined. The detailed list of BJT parameters is shown in Appendix D.
General form:
Q<name> < collector node> <base node> <emitter node>
[substrate node] <model name> [area value]
.MODEL <model name> NPN [model parameters]

.MODEL <model name> PNP [model parameters]
Example 3-7:
Q1 1 2 3 mod1
.MODEL mod1 NPN
Example 3-6:
Q2 1 2 3 Qa2N222
.MODEL Qa2N222 PNP (BF=100 VJE=0.7V IS=1nA CJE=1pF)
199

3-19. Summary
In 1947 Bardeen and Brattain built the point contact transistor. They
made it from strips of gold foil on a plastic triangle, pushed down into
contact with slab of germanium. In 1948, Bells Lab unveiled the
transistor. They decided to name it transistor instead of Point-contact
solid state amplifier. John Pierce invented the name, combining trans-
resistance. Later, Shockley made the Junction transistor (sandwich). This
transistor was more practical and easier to fabricate. The bipolar junction
transistor was the first solid-state amplifier element and started the solid-
state electronics revolution. During the 1950’s, Sony received a license
from Bell Labs to build transistors. They used these transistors to build
battery-powered radio receivers. In United States they initially used the
transistors primarily for computers and military uses. The following
figures show the photographs of some early transistors
The following figures show one of the biasing schemes of the bipolar
junction transistor (BJT) and how it can be used as an amplifier.
200

The following figure depicts the internal current components of a BJT.
The following equations depict the BJT currents in all modes of

operation:
 v  v  I S   vBC  
I C  I S exp  BE   exp  BC   exp    1
  VT   VT   R   VT  
I S   vBE   I S   vBC  
IB  exp    1  exp    1
 F   VT    R 
  VT  
 v  v  I S   v BE  
I R  I S exp  BE   exp  BC   exp    1
  VT   VT   F   VT  
where F and R are the forward and reverse mode current gains. The
above relations are based on the following assumptions when deriving
ideal current-voltage characteristics of a BJT
 Low level injection
 Uniform doping in each region with abrupt junctions
 One-dimensional current flow
 Negligible bandgap narrowing in the emitter
 Negligible recombination-generation in space charge regions
 Negligible electric fields outside of space charge regions.
201

For a given value of IB, the output characteristics curve of a BJT is the
relationship between IC and VC E that is set by BJT internals. Figure3-8
depicts the output characteristics (IC versus VCE) at different values of the
base current (IB).
The operating point (Q) is determined by the intersection of the load line
with one of this family of curves. The limits of the saturation region are
VBE > VBEsat, and IB = IBsat . Also, the cutoff region is limited by VBE < V
and IB = 0.
202

Like all electronic devices, the bipolar transistor can function only within
well-defined limits of voltage and currents. Data sheets usually have a
full set of charts, showing the various device parameters and limitations
as a function of voltage, current and frequency. Without a thorough
knowledge of the device limits, the device may cease to work and may
even breakdown. In this section we discuss the physical limitations that
should be taken into account, in order to ensure a reliable operation of the
transistor. The basic limitations are grouped in the following categories:
Current limitations (Fall of beta factor current gain and Kirk effect),
Voltage limitations (Breakdown voltages, and Early effect),
Power limitations (safe operating area and thermal derating).
At high collector currents, the level of injected minority carriers in the

base (electrons in NPN transistor) increases above the base concentration
and cause the fall-off of the beta factor. The high injection levels also
affects the I-V characteristics of the BJT as shown in the following figure.
203

3-20. Problems
3-1) What are the majority current carriers in (a) the P-N-P transistor and
(b) the N-P-N transistor?
1. (a) Holes (b) holes
2. (a) Holes (b) electrons
3. (a) Elements (b) holes
4. (a) Electrons (b) electrons
3-2) In a BJT, what percent of the total current flows through the emitter
lead?
1. 100%
2. 98%
3. 60%
4. 5%
3-3) What term is used to indicate current gain in a common-emitter

configuration, of a bipolar transistor?
1. Alpha
2. Beta
3. Gamma
4. X-ray
3-4) For normal operation of a bipolar transistor, what is the bias of the
(a) emitter-base junction and (b) base-collector junction?
1. (a) Forward (b) reverse
2. (a) Forward (b) forward
3. (a) Reverse (b) forward
4. (a) Reverse (b) reverse
3-5) Consider an NPN transistor. The N-type emitter has a concentration

NE and width WE, the base is P-type with concentration NB and width WB,
and the collector with concentration NC and width WC.
i) Express the density of holes in the emitter at equilibrium (pEo) and the
density of electrons in the base at equilibrium (nBo) as functions of NE and
NB
ii) Using Boltzmann relation, show that potential barrier at the emitter
base (E-B) junction is given by:
VEB = VE – VB = (kBT/e) ln (NE.NB/ni2)
iii) Calculate VEB if NE = 5.1019 cm-3, NB = 1018 cm-3, ni = 1.45.1010 cm-3

204

iv) If we applied a forward bias VBE > 0, the carrier concentration will
change in base and emitter. Show that the carrier concentrations at the
edges of emitter and base will become:
pE(0) = pEo exp(eVBE/kBT), and nB(0) = nBo exp(eVBE/kBT)
v) Apply the definition of diffusion current and hence derive an

expression for the current of electrons in base (JnB) and the current of
holes in emitter (JpE).
vi) As a first order approximation, assume the definition of the current
gain = (JnB / JpE), and hence prove that:  = (NE WE/NB WB).(DnB/DpE)
vii) Calculate  if: WE = 0.8m, DpE =1.3 cm2/s, WB =0.8 m, DnB =15
cm2/s
viii) Using the above BJT structure, show that in forward active mode we
have:
IC = IS exp (eVBE/kBT) with IS = e AE (DnB ni2 / NB WB )
ix) Calculate IS if NB = 1018 cm-3, ni = 1.45 1010 cm-3, DnB = 15 cm2/s, AE
= 100m2.
3-6) Consider the current mirror circuit shown in figure below (right),
which has two identical BJT’s.
i) Prove that IC2 is given by: IC =  I / (+2)
ii) If  is given by the value you obtained in problem 3-5, calculate R
such that I = 1 mA.
205

3-7) In integrated circuits, it is not desirable to have large resistors,

because they occupy a large area on the chip. In order to reduce the value
of the resistance R, in the above current mirror circuit of problem 3-6, the
circuit is slightly modified as shown above (right). This circuit is called
the Widlar current mirror.
i) Neglecting IB1 and IB2, express VBE1 and VBE2 in terms of I and IC2
ii) Prove that RE is given by : RE = (kBT/eIC2) ln (I/IC2)
iii) Calculte RE such that I = 1 mA and IC2= 1A.
3-8) What method for checking transistors is cumbersome when more

than one transistor is bad in a circuit?
1. Ohmmeter
2. Transistor checker
3. Voltage check
4. Substitution
3-9) Calculae the DC quiescent point (IB, IC and VCE) of the following
common collector (Emitter follower) amplifier. Consider  = 100. Derive
an expression for the AC voltage gain Av = Vout/Vin, when C1 and C2 are
very large (short circuit).
206

3-10) Write down a SPICE program to simulate the following common

collector amplifier (Emitter follower) and check the input/output wave-
forms at the indicated points. Check that the voltage gain is almost unity.
3-11) Laboratory Assignment

In this practical assignment, you will characterize the current-voltage
characteristics of an npn BJT. To do this, you can use the MIT
Microelectronics WebLab at http://ilab.mit.edu/. The BJT is labeled npn
BJT (2N3904). This exercise involves three phases: (i) characterization of
the devices, large and small signal parameter extraction, (ii) using the
measurements to choose bias voltages for a common collector amplifier
to meet amplifier specifications, and (iii) using the measurements to
determine small signal parameters (h-parameters or pi-parameters) at the
bias point.
207

Photocopy the following two pages, read the assessments carefully and
answer on the page. Carry out the required measurements, and comment
if there exist a discrepancy between the measured and calculated values.
Don't forget to write your name and ID.
Assessment #3-1.
208

Assessment #3-2.
209

3-22. References
[1] William. Shockley, Electrons and Holes, Van Nostrand, Princeton,

N.J, 1950.
[2] J. J. Ebers and J. L. Moll. “Large Signal Behavior of Junction
Transistors,” Proceedings I.R.E. vol. 42, p. 1761, 1954.
[3] Walter H. Brattain, "Genesis of the Transistor." The Physics
Teacher, pp. 109-114, March, 1968.
[4] H. K. Gummel and H. C. Poon. “An Integral Charge-Control
Relation for Bipolar Transistors,” Bell Syst. Technical Journal. vol. 49,
p. 115, 1970.
[5] William Shockley, “How we Built the Transistor", New Scientist,
December 1972.
[6] S. Millman, Editor, The Early History of the Transistor. "A History
of Engineering and Science in the Bell System", Physical Sciences,1925-
1980.
[7] S. M. Sze, Semiconductor Devices: Physics and Technology, John
Wiley Inc., 1st Edition, 1985.
[8] P. Antognetti, and G. Massobrio Semiconductor Device Modeling
with SPICE, 2nd ed., McGraw Hill, NY, 3rd ED, 1993.
[9] C. McAndrew, AT&T/Motorola; J. Seitchik, Texas Instruments; D.
Bowers, Analog Devices; M. Dunn, Hewlett Packard; M. Foisy,
Motorola; I. Getreu, Analogy; M. McSwain, MetaSoftware; S. Moinian,
AT&T Bell Laboratories; J. Parker, National Semiconductor; P. van
Wijnen, Intel/Philips; L. Wagner, IBM, VBIC95: An Improved Vertical,
IC Bipolar Transistor Model.
[10] D. Neamen, A. Irvin, Semiconductor Physics & Devices, Chicago,
1997
[11] S. M. Sze, Semiconductor Devices. Physics and Technology. John
Wiley Inc., 2d edition, 2002.
[11] Jongchan Kang, Youngoo Yang, Sungwoo Kim, and Bumman Kim,
“A Heterojunction Bipolar Transistor Large-signal Model Focused on the
Saturation Region,” 32nd European Microwave Conference Digest, vol.
3, pp. 147-150, Sep., 2002.
Oxford, 2004.
210

Metal-Semiconductor
(M-S) Contacts
Contents

4-2. Introduction to M-S Junction
4-2.1. Workfunction of a Metal
4-2.2. Thermo-ionic Emission Current of a Metal (Richardson’s Law)
4-2.3. Electron Affinity in a Semiconductor
4-3. Metal-n-type Semiconductor Contact
4-3.1. Case 1: m > s (Schottky Barrier contact)
4-3.2. Case 2: m < s (Ohmic Barrier)
4-4. Metal-p-type Semiconductor Contact
4-5. Ohmic MS Contact
4-6. Tunnel MS Contact
4-7. Annealed & Alloyed (Silicide) Contacts
4-8. Small Signal Model of the Schottky Barrier Diode
4-9. Capacitance of MS Structure
4-10. Measurement of MS Contact Barrier Height
4-11. Switching Performance of the SBD
4-12. MS Contact Applications
4-13. Summary
4-14. Problems
4-15. References
211

212

Metal-Semiconductor
(M-S) Contacts

Metal-semiconductor contacts are obvious components of any semi-
conductor device or integrated circuit. In this chapter, we summarize the
fundamental concepts about Metal-Semiconductor (M-S) contacts and
their basic characteristics. We show how to employ such junctions to
implement Shottkey barrier diodes (SBD) and Ohmic contacts, in
electronic devices and integrated circuits.
1. Be acquainted with the principle types of M-S contacts.

2. Understaand the physical operation of SBD’s
3. Identify the I-V characteristics of the Schottky barrier diodes and
their advantages in power and RF applications
4. Be aware of the switching performance of SBD’s
5. Understand the conditions necessary for making Ohmic contacts.
4-2. Introduction to M-S Junctions

The M-S contacts cannot be assumed to have as low resistance as that of
two connected metals. In fact, a large mismatch between the Fermi
energy of the metal and semiconductor may result in a high-resistance or
rectifying contact. A proper choice of materials can provide a low
resistance Ohmic contact. However for a lot of semiconductors there is no
appropriate metal available. Instead, one can create a tunnel contact. Such
contact consists of a thin barrier – obtained by heavily-doping the
semiconductor – through which carriers can readily tunnel. Contact
formation is also affected by thin interfacial layers and is typically
finished off with a final anneal or alloy formation after the initial
deposition of the metal. In the following section we review some
important definitions concerning metals and semi-conductors. We then
describe the different types of M-S contacts.
213

4-2.1. Workfunction of a Metal

The workfunction of a metal is defined as the work exerted to liberate an
electron from that metal. The following figure illustrates the definition of
the metal workfunction (em), as the energy difference between Fermi
energy level of electrons (EFm) inside the semiconductor and the vacuum
(free electron) energy level (Eo).
em = Eo - EFm (4-1)
Fig. 4-1. Illustration of the metal workfunction definition.
The following table shows the workfunctions of some metals of interest.

Table. 4-1. Workfunctions of some metals of interest
Low workfunction Metals High workfunction Metals

Metal
Na K Fe Al Au Cu
Workfunction (eV) 2.3 2.2 1.8 4.3 4.8 4.4
4-2.2. Thermionic Emission Current of a Metal (Richardson Law)

If a sufficient voltage is applied across a metal filament, then electrons
are heated up and can emit from the surface of metal. Eventually, these
electrons may be attracted and collected by a positive anode. The
intensity of such thermo-ionic current may be calculated as follows.
Assuming the electrons obey the quasi-free electron model inside a metal,
then the thermo-ionic current in a given direction (say the x-direction) is
given by:
Jnx = -e  vgx(knx) f(knx) g(knx) dknx (4-2a)
The total 3-dimensional current is therefore
214

Jn = -e    vg(kn) f(kn) g(kn) dkn dkn dkn (4-2b)
where vg(kn) is the group velocity of electrons and g(kn) is the density of
electron states in the k-space
g(kn) = 2/(2)3 , as g(knx) = g(kny) = g(knz) = 2/(2) (4-2c)
Also, f(kn) is the electron distribution function in the k-space (assumed as

Fermi-Dirac distribution)
f(kn) = (2mn kBT/ħ2) .exp [- ( E - EF )/kBT] (4-2d)
where En is the electron energy, which is eventually related to the wave

vector kn by the parabolic relation:
En = (ħkn)2 / 2mn = (ħ2 /2mn).( knx2+ kny2 + knz2) (4-3a)
The group velocity is related to the wave vector by the relation:
vgn(kn) = ∂En / ∂kn = ħ2kn /mn (4-3b)
Also, we have following condition, for electron emission
En = ħ2kn2 /2mn = ½ mn vgn2 > EFm + em (4-3c)
Such that the electrons are emitted with a minimum velocity, which is
given by:
vgn (min) = √ 2 (EFm + em)/mn (4-4)
Substituting all the above relations and integrating, yields:
Jn = - R T2 exp [- (em/ kBT)] (4-5a)
where the constant R is called the Richardson constant
R = 4  (e mo kB2/h3) = 1.6 106 [A / cm2 K2] (4-5b)
215

4-2.3. Electron Affinity of a Semiconductor

It is well known that non-degenerate semiconductors and isolators have
no free electrons (under the Fermi level), like metals. The work exerted
to liberate an electron in the bottom of conduction band of a semi-
conductor is called the electron affinity (es):
es = EO - EC (4-6a)
Fig. 4-2. Illustration of the electron affinity definition.
A workfunction of a semiconductor can be also defined as follows:
e s = Eo - EF (4-6b)
Table. 4-2. Electron affinity of some semiconductors of interest
Semiconductor Si Gi GaAs InP

Affinity (eV) 4.01 4.13 4.07 4.38
4-3. Metal-n-type Semiconductor Contact

We have pointed out so far that the Fermi level of any two solids in
contact must be equal in thermal equilibrium. As a result, whenever a
metal and a semiconductor are in contact, there exists a potential barrier
between the two materials that prevents most charge carriers (electrons or
holes) from passing from one material to another. Only a small number of
carriers will have enough energy to get over the barrier and cross to the
other material. When a bias is applied across the MS junction, it may
have one of two cases: it may make the barrier appear lower from the
semiconductor side, or it may make it appear higher. In order illustrate
the different cases of an MS contact, assume a metal of workfunction m
is brought into contact with an n-type semiconductor with electron
affinity s and workfunction s.
216

4-3.1. Case1: n-type Semiconductor with m> s (Schottky barrier diode)

In the first case we assume that m > s. The following figure depicts
energy band diagram of the two materials before and after contact. In this
case, the MS junction forms a positive barrier (ms = m - s > 0), called
Schottky (or Mott) barrier. The barrier height across the metal-
semiconductor junction at thermal equilibrium is
eBo= em - es= e(m -s ) + (Ec–EF) = eVbi +(Ec–EF) (4-7a)
where Vbi=m-s=ms is called metal-semiconductor built-in voltage.

Also the emref (EC-EF) is related to the doping concentration as follows:
(EC –EF) = kBT ln(NC /Nd ) (4-7b)
When a bias Va is applied across the MS contact, this barrier is lowered

or raised, according to the polarity of the bias. Actually, the barrier height
is further modified because of the eventual flow of electrons and image
forces, as shown in figure 4-3. Therefore, the effective barrier height is:
B = Bo - B , (4-7c)
Note 4-1. Barrier Lowering, and Image Forces

The MS barrier is reduced under applied bias due to the image force of the carrier, as
illustrated in figure 4-3. The image force results from the electrostatic attraction of the
carrier at a distance x from the electrode–semiconductor interface leading to a charge
build-up at the electrode interface that gives the same potential as an equal and
opposite charge a distance −x from the electrode, the image charge. The attractive
image force is then given by the following expression:
The resulting potential energy is
The the Schottky barrier lowering, e φB is given by the condition dU/dx = 0, such
that:
The value of ε is12ε0 in Si and 13ε0 in GaAs, increasing the importance of the
barrier-lowering term. This contribution must be included for any device model to be
successful
217

Fig. 4-3. Energy band diagram for the interface between a metal and semiconductor.
The effective barrier is lowered when an electric field is applied to the surface. The
lowering is due to the combined effects of the field and image force.
The barrier lowering B, in the case of a metal-semiconductor (n-type)

contact, is given by:
B = [ (e3Nd/83).(Vbi - Va )] 1/4 (4-7d)
The above relation may be obtained by integrating the Poisson equation,

around the MS contact, taking into account the electrostatic image force
of electrons.
Figure 4-4 depicts the energy band diagram of a metal-semiconductor

contact at thermal equilibrium and with applied forward bias. Usually, the
Schottky barrier is a large barrier height (ms = m - s >> 0) and low
doping concentration. When a forward bias is applied across this barrier,
such that the metal is positive and the semiconductor is negative, the
energy barrier is lowered by the amount of applied bias and current
passes, as shown in Fig. 4-4(c). There exist 4 possible conduction
mechanisms across such a barrier:
1- Thermoionic emission (TE), over the barrier

2- Tunneling through the barrier either by field emission (FE) or by
thermoionic field emission (TFE)
3- Minority carrier injection in the quasi neutral region
4- Recombination in the depletion region.
218

Fig. 4-4(a). Energy band diagram of a metal-semiconductor (n-type) contact,

with m > s. at thermal equilibrium
Fig. 4-4(b). Energy band diagram of a metal-semiconductor (n-type) contact,

with m > s. with applied bias (Va).
219

Fig. 4-4(c). Illustration of the barrier height lowering effect
However, the current transport across ordinary (thick) Schottky barriers,

is mainly due to majority carriers, by thermo-ionic emission. The number
of emitted majority carriers (electrons in n-type semiconductors) over the
barrier (Vbi-Va) may be given by the Maxwellian distribution:
nth = no exp [-e(Vbi - Va) / kBT), (4-8a)
where the no is the number of majority carriers (electrons) near thermal

equilibrium.
no = NC exp [-e(C – EF) / kBT] (4-8b)
Here NC is the effective density of states in the conduction band of the n-

type semiconductor. The thermo-ionic emission current may be then
expressed using the kinetic theory of gases :
| JmS | = e vn nth = ¼ e <vth> nth = C1 nth (4-8c)
where vn = ¼ <vth> is the average velocity of emitted electrons, vth is the

thermal velocity of electrons and C1 = ¼ e<vth>. Therefore, we can write:
| JmS | = | JmS |V=0 = C1 nth = C1 NC exp (-e B / kBT) (4-9a)

and
|JSm | = C1 NC exp [- e (B – Va) / kBT ] (4-9b)
220

The total thermoionic current across a Schottky barrier junction is then

given by the sum:
J = JSm - JmS = Js [ exp (- e Va / kBT) -1 ] (4-9c)
Here, Js = C1 NC exp (-e B / kBT), is the reverse saturation current, which

may be put in the following form
Js = R* T2 exp (- eB / kBT) (4-9d)
where R* = R (mn*/mo) is the effective Richardson constant. For n-type

Si, we have R*= 250 [A/cm2K2] and for n-type GaAs we have R*= 8.1
[A/cm2K2]. In contrary, when a reverse bias is applied across such a
contact, the energy barrier height increases, and a small leakage current
due to emission of metal electrons (Js) passes in the reverse direction. As
Js is very small compared to J, this type of MS contact is a rectifying
contact, and called Schottky Barrier Diode (SBD).
The diffusion of minority carriers and recombination current across the

SBD, can be derived on the basis of semiconductor current equations.
Alternatively, the I-V characteristics of the SBD can be derived starting

from the so-called “diffusion theory”. According to the diffusion theory,
the current across an n-type Schottky diode is given by:
J = Js’ [ exp (- e Va / kBT) -1 ] (4-10a)
with
Js‘= (e2DnNC/Vt).[2e(Vbi – Va).Nd /s]½ .exp (-eB / kBT) (4-10b)
Generally speaking, the practical I-V characteristics of the SBD (shown

in figure 4-4) can be expressed as follows:
J = Js [ exp ( - Va /  Vt) - 1 ] (4-11)
Where  is called the ideality factor. For, Al-Si (n-type) Schottky barrier
diodes, we have  = 1.066. The practical structure of Si and GaAs SBD’s
are shown in Fig. 4-5.
221

Fig. 4-5 I-V characteristics of Al-Si Schottky-barrier diode (SBD).
Fig. 4-6 Structure of Si , GaAs and SiC Shottkey barrier diodes (SBD).
222

4-3.2. Case 2: n-type Semiconductor with m < s.

When a metal and an n-type semiconductor are joined and Φm < ΦS,
electrons will flow from the Fermi energy level in the metal into the
semiconductor conduction band to lower their energy. This will cause the
chemical potential of the semiconductor to move up into equilibrium with
that of the metal. It will also deform the semiconductor bands, so that
they curve upwards away from the metal. This situation is depicted in the
animation below. Use the tabs to navigate through the animation.
This type of contact yields a linear relationship between the voltage

applied and the current that flows across the junction. It is therefore called
an Ohmic contact, because it obeys Ohm's law. This type of contact is
also described as metallization, and is used to supply electric current into
semiconductor devices.
Fig. 4-7. Energy band diagram of a metal-semiconductor (n-type) contact,

with m < s.
223

4-4. Metal-p-type Semiconductor Contact

When a metal and an p-type semiconductor are joined and m < s,
electrons will flow from the conduction band of the semiconductor into
the metal conduction band to lower their energy. This will cause the
chemical potential of the semiconductor to move down with that of the
metal. It will also deform the semiconductor bands, so that they curve
downwards to the metal. This situation is depicted in the Fig. 4-8. Table
4-3, summarizes all the types of MS contacts.
Fig. 4-8. Energy band diagram of a metal-semiconductor (p-type) contact,

with m < s.
224

Table 4-3. Types of a metal-semiconductor contacts.
4-5. Ohmic Contacts

A metal-semiconductor junction results in an Ohmic contact if the energy
barrier at the junction has zero or negative height (ms ≤ 0). In such case,
the carriers are free to flow in or out of the semiconductor so that there is
a minimal resistance across the contact. For an n-type semiconductor, this
means that the workfunction of the metal must be close to or smaller than
the electron affinity of the semiconductor.
For a p-type semiconductor, it requires that the workfunction of the metal

must be close to or larger than the sum of the electron affinity and the
bandgap energy. Since the workfunction of most metals is less than 5V
and a typical electron affinity is about 4V, it can be problematic to find a
metal that provides an Ohmic contact to wide bandgap semiconductors
such as GaN or SiC.
Fig. 4-9. Current-voltage characteristics of MS contacts.

225

4-6. Tunnel MS Contacts

An alternate and more practical contact is a tunnel contact. Such contacts
do have a positive barrier (ms > 0) at the metal-semiconductor interface,
but also have a high enough doping in the semiconductor that there is
only a thin potential barrier separating the metal from the semiconductor.
If the width of the depletion region at the metal-semiconductor interface
is very thin, on the order of 3nm or less, carriers can readily tunnel across
such thin barrier. The required doping density for such contact greater
than 1019 cm-3.
Fig. 4-10. Tunneling across a thin Schottky barrier of MS contact.
When tunneling is dominant, the MS contact is almost Ohmic. The

tunneling currents can be calculated using the WKB approximation or the
Fowler–Nordheim formula. In the latter case, the electron tunneling
current density is given by:
(4-12)
226

with a similar expression for the hole tunneling current density Jptun. In
this case, the following relation gives the contact resistance:
 V   2 m*  s 
Rc     exp  B
 (4-12)
 J V 0  
 ND 

where B is the M-S barrier height, Nd is the semiconductor doping

concentration and other symbols have their usual meaning. Figure 4-11
depicts the contact specific resistance Rc of various metals on n-type and
p-type silicon as a function of the doping concentration.
Fig. 4-11. Contact specific resistance of some metals on n-type and p-type Si versus
doping concentration. Solid lines are calculated from the model of Swirhun.
227

For Al-Si contact we have eB =0.7eV for n-type Si and eB =0.6 eV for
p-type Si. Therefore, aluminum can also make Ohmic contact with
heavily doped n-type Si. In this case the MS current is dominated by the
tunneling current component and the Ohmic resistance Rc becomes so
small as given by:
 4.4 x10 10B 

Rc  10 -5 exp    cm 2 (4-13)
 ND 
Table 4-4. Some Silicides and the barrier height of their silicon contact
Silicide PtSi PdSi Ni Si TiSi2 TaSi2

eB (eV) 0.89 0.74 0.66 0.6 0.59
4-7. Annealed and Alloyed Contacts (Silicides)

The fabrication of Ohmic contacts frequently includes a high temperature
step so that the deposited metals can either alloy with the semiconductor
or the high-temperature anneal reduces the unintentional barrier at the
interface. In the case of silicon, one can simply deposit a metal such as
aluminum or any other metal and obtain a reasonable Ohmic contact.
However a subsequent anneal of Si/Al at 475°C in a reducing ambient
such as (20:1 N2/H2) will further improve the contact resistivity. The
temperature is chosen below the eutectic temperature of the Si/metal
eutectic composition. Such silicon-metal alloys are called Silicides, and
their contact with silicon have a small barrier height (B), as shown in the
following table. Annealing at higher temperature causes the formation of
Si/Al alloys, which may cause pits in the silicon. This effect is referred to
as spiking and when penetrating through an underlying P-N junction
would dramatically affect the quality of the junction as can be observed in
the high leakage current or reduced breakdown voltage.
Contacts to compound semiconductors require some more attention.

Selecting a material with the right workfunction might still not result in
the expected Ohmic contact. This is due to pinning (bending) of the
Fermi energy at the interface due to surface states. In order to further
improve MS tunnel contacts one adds dopants such as Ge in the case of
an n-type contact and Sn in the case of a p-type contact to the metal. An
anneal around 400°C for about tens minutes causes the dopants to alloy
with the semiconductor, thereby forming a thin high-doped region as
desired for a tunnel contact.
228

Recently, the copper have been used in semiconductor technology to

form interconnects between devices, as shown in figure 4-12. Copper
offers higher performance than aluminum because of its lower resistivity
(1.67 Cm). Copper layers can also be made thinner and hence reduce
interconnects delay. Copper contacts can be applied by electroplating or
via the so-called Damascene process, as shown in Fig. 4-13.
Fig. 4-12. Damascene process main steps
229

Fig. 4-13. Photograph of copper contacts.
230

4-8. Small Signal Model of the Schottky Barrier Diode

The Schottky barrier diode (SBD) is a majority carrier device. Unlike a p-
n diode, in forward bias no minority carrier injection occurs. Thus there is
no diffusion capacitance and the device response can be very fast. The
following figure depicts the small signal equivalent model of the SBD, in
series with a resistor and inductor.
The depletion capacitance (Cd) of the SBD is given by:
(4-14a)
And the diode resistance Rd is given by:
(4-14b)
Fig. 4-12. Equivalent circuit of a Schottky barrier diode, including series resistor and
inductor as well as parallel packaging capacitance.
4-9. Capacitance of MS Contacts

The Schottky barrier diode capacitance can be calculated, at a certain
applied bias as follows. We start by solving the Poisson equation, to
determine the potential and field distribution, at a certain applied bias
voltage. Then, from the definition of capacitance (C = dQ/dV) we can
calculate the MS contact capacitance.
The charge density in the semiconductor side (s) is assumed

homogenous, and extended over a limited depletion region width of W,
such that s = e.Nd W. By integrating the Poisson equation:
2 V = - ζ = s / (4-13a)
we get the electric potential:

231

V(x) =(Va–Vbi)+ (eNd/).(W-x)=(Va–Vbi)- xζm(eNd/2)x2 (4-13b)
and electric field
ζ(x) = (eNd/). (W - x) = ζm - (eNd/).x (4-13c)
where the constants of integration V(0) = Va – Vbi and the maximum

electric field ζ(0) = ζm = (eNd/).W.
Fig. 4-13. Charge density, electric field and potential across a Schottky barrier contact.
232

The applied bias (Va) is related to the depletion region width by the
following relation:
Vbi – Va = ½ ζm W = ½ (eNd/).W2 (4-14)
The total charge inside the depletion region, is then given by:
Qs = eNdW = eNd [2 (Vbi –Va)/ eNd]½ = [2eNd(Vbi – Va)]½ (4-15)
If we take the mobile charges (n) into account, the above relation
becomes:
Qs = [2eNd(Vbi – Vt - Va)]½ (4-15)
where Vt = kBT/e is the thermal voltage. Therefore,
C = | ∂Qs / ∂Va | = [ eNd(Vbi – Vt – Va)] = ( /W)

½ (4-16)
Or in a more convenient form:
1/C2 = (Vbi – Vt – Va ) / e Nd (4-17)
4-10. Measurement of the Barrier Height of MS Contacts

The barrier height (B) and background doping concentration (Nd), of a
metal-semiconductor contact can be determined from the C(V)
characteristics, as shown in Fig. 4-14. For instance, referring to the this
figure, we have:
slope = d(1/C2) dVa = - 2 / e Nd (4-18a)
Intercept = (Vbi – Vt ) / e Nd (4-18b)
IF the slope = - 4.4 x 1015 (cm2/F)2/V], then the doping concentration is

given by:
Nd = - 2 / e [ d(1/C2) dVa] = - 2 / (e slope) = 2.7 x1015 cm-3

From the intercept, we have Vbi = 0.24 V. Therefore, one can determine
barrier height as follows.
233

The barrier height lowering can be first calculated from equation (4-7d).
However, this equation should be also modified, if we take the density
mobile carriers (n) in the MS depletion region, into account:
B = [ (e3Nd/8o3).(Vbi - Vt - Va )]1/4 (4-19)
Thus, at Va = 0, the barrier height lowering is given by:
B = [( e2 Nd / 82 3)(Vbi - Vt )]¼ = 0.017 V

Also, the emref of the Fermi level (EC - EF)/e = Vt ln (Nd/NC) = 0.24 V.
Then the total barrier height is given by:
B = Bo - B =ms + Vt ln (Nd/NC) - B = 0.42+0.24-0.0173= 0.66V.
Fig. 4-14. Capacitance of a Schottky barrier contact versus applied bias.
234

The following figure shows the measured barrier height of some metals
with n-type Si and GaAs contacts.
Fig. 4-15. Measured barrier height of a metal Si and metal GaAs (n-type) contacts.
235

4-11. Switching Performance of the SBD

The transient response of the SBD is better than that of the usual P-N
junction diodes. This is because the SBD is a majority carrier device,
which has no minority carrier storage. Therefore, the carrier storage time
(ts) of the SBD is zero, as shown in figure 4-16.
Fig. 4-16. Switching characteristics of a Schottky barrier diode.
236

4-12. Applications of MS Contacts

In conclusion, of all the above discussion, it is interesting to summarize,
what MS contacts are good for? The important applications of MS
contacts include, but not restricted to:
Ohmic contacts, which are essential components of any electronic
device to carry current into and out of the semiconductor device.
Determining of doping profiles, through the measurement of the MS

contact capacitance versus applied bias C(V).
Shunt diodes, to reduce switching transients in bipolar transistor logic
Microwave diodes, which is taking advantage of the negligible

minority carrier injection. Switching speed is much higher than N-N
junctions
The gate of MESFETs, which are a sort field effect devices.
Ultraviolet detectors.
237

4 –13. Summary
We have pointed out so far that the Fermi level of any two solids in
contact must be equal in thermal equilibrium. As a result, wwhenever a
metal and a semiconductor are in contact, there exists a potential barrier
between the two materials that prevents most charge carriers (electrons or
holes) from passing from one material to another. Only a small number of
carriers will have enough energy to get over the barrier and cross to the
other material.
When a bias is applied across the MS junction, it may have one of two
cases: it may make the barrier appear lower from the semiconductor side,
or it may make it appear higher. The result of this is a Schottky
(rectifying) Barrier contact, where the junction conducts in one direction,
but not the other. Almost all metal-semiconductor junctions will exhibit
some of this rectifying behavior. The following figure depicts the energy
band diagram of metal-semiconductors at equilibrium.
Schottky Contacts make good diodes, and can even be used to make a
kind of transistor, but for getting signals into and out of a semiconductor
device, we generally want a contact that is Ohmic. Ohmic contacts
conduct the same for both polarities. The following figure shows a
photograph of some of the early metal-semiconductor (CuO) rectifiers,
which are usually called Schottky barrier diodes (SBD)
238

There are two ways to make a metal-semiconductor contact look ohmic

enough to get signals into and out of a semiconductor (or doing the
opposite makes a good Schottky contact).
 Lower the barrier height: The barrier height is a property of the

materials we use. We try to use materials whose barrier height is
small. Annealing can create an alloy between the semiconductor and
the metal at the junction, which can also lower the barrier height.
 Make the barrier very narrow: The probability of tunneling
becomes high for extremely thin barriers (in the tens of nanometers).
We make the barrier very narrow by doping it very heavily (> 1019
atoms/cm3).
239

Comparison between Schottky barrier diode and conventional P-

N junction diodes:
240

4–14. Problems
4-1) Using the work functions listed in the summary, predict which
metal-semiconductor junctions are expected to be Ohmic contacts.
Use the ideal interface model.
4-2) Find the barrier height, built-in voltage, maximum field, and the
depletion layer width at equilibrium for W-Si (n-type) contact.
Given: m = 4.55eV for W; (Si) = 4.01eV; Si doping = 1016 cm3.
Draw the band diagram at equilibrium.
4-3) What is the basic structure of a Schottky diode? What are its most
important parasitics?
4-4) How do Schottky diodes switch? What sets their time response?
4-5) What does one have to do for a metal-semiconductor junction to

become an ohmic contact?
4-6) Draw the energy band diagram and determine the contact potential
for the following metal/semiconductor systems using the ideal
Schottky diode theory.
Of these which will have rectifying and which will have ohmic
characteristics.
4-7) Determine the work-function of a metal, which when deposited on

an N-type semiconductor with
would form a contact with zero contact potential.
4-8) Draw the qualitative energy band diagram of the Schottky barrier for
the following system:
241

4-9) Determine the magnitude of doping required such that the voltage
drop in the lightly doped N-region is 0.6 Volts. Assume that Schottky
barrier height is 0.7 Volts
4-10) Determine the Schottky barrier height required so that the turn-on
voltage of the diode is 0.45 Volts for a forward current of 1 A. Assume
that the Richardson’s constant is and the area of the diode is
4-11) Schottky barrier diodes are commonly used as gates in field effect
transistors (FETs). The gate leakage current under reverse bias conditions
is an important consideration in these FETs. For a gate dimension of
, determine the minimum barrier height required to obtain a
leakage current < 10pA. Assume that Richardson’s constant is .
4-12) Calculate the reverse leakage current of a Schottky diode for

reverse voltages of –1, -5, -25, -50Volts with and without taking Schottky
barrier lowering into account. Assume that the Richardson’s constant is
and the area of the diode is
4-13) Schottky barrier diodes are frequently used as a Photodetector.

Suppose an electron-hole pair is generated within the depletion region of
the diode as a result of absorption of a photon.
242

(a) Indicate the direction of flow of the photo-generated carriers.

(b) What will be the direction of current flow?
(c) In which mode, forward bias or reverse bias should the diode be
operated to obtain maximum sensitivity.
4-14) Explain what will happen if the photon is absorbed outside the
depletion region. Hint: Consider diffusion and recombination of photo-
generated minority carriers.
4-15) The depletion capacitance measured for a Schottky barrier diode

with area = at different reverse bias voltages is given below:
Bias (V) Capacitance (F/cm2)

0 3.43
-1 2.2
-2 2.65
(a) Determine the doping of N region

(b) Determine the barrier height
(c) Determine the depletion width at zero bias
4-16) Obtain the small signal model for a Schottky diode on Silicon
biased at a current of 1mA. Assume that the Richardson’s constant is:
243

4-15. References:
[1] S. M. Sze, Semiconductor Devices. Physics and Technology. J.

Wiley Inc. 2002, 2d edition.
[2] S. M. Sze, Semiconductor Devices. Physics and Technology. J. Wiley

Inc. 1985, 1st edition.
[3] A. P. Strutton, Electronic Structure of Materials, Clarendon Press,

Oxford, 2004.
244

Junction Field Effect Transistor

(JFET)
Contents:

5-2. JFET Structure
5-3. JFET Operation & I-V Characteristics
5-4. JFET Small Signal Model
5-5. JFET Amplifiers
5-6. Other FET Structures
5-6.1. MESFET
5-6.2. MODFET (HEMT)
5-7. FET Noise Model
5-8. FET Testing
5-9. Summary
5-10. Problems
5-11. Assessment
5-12. References
245
246
Junction Field Effect

Transistor (JFET)

The field effect transistor (FET) is a three terminal device which is
capable of both amplification and switching. Field effect transistors
include the Junction FET (JFET), Metal-Semiconductor FET
(MESFET) and Metal-Oxide-Semiconductor FET (MOSFET).
All field effect transistors are majority carrier devices. This means that
current is conducted by the majority carriers of these devices. The JFET
and MESFET are depletion mode devices whereas the MOSFET can
operate in depletion mode or in enhancement mode. Depletion mode
devices are controlled by depleting the charge carriers in their conduction
channels.
In this chapter, we present the fundamental concepts about JFETs and

their basic circuits. We briefly demonstrate how to use such electronic
devices to amplify and switch signals in different configurations.
Understand the principle function of Field effect transistors.

Be acquitted with the circuit configurations and biasing methods of
the JFET,
Identify the different current components and the current amplification
factor of the JFET
Identify the input and output I-V characteristics of the JFET
Be acquainted with the JFET circuit models
Apply the appropriate circuit models correctly.
Identify the JFET quirks and physical limitations
Know other forms of field effect transistor, such as high electron
mobility transistor (HEMT), and how they operate.
247
5-2. JFET Structure

Like all field-effect devices, the JFET has two basic types, namely: n-
channel and p-channel JFET. For an n-channel FET, the device is
constructed from a bar of n-type semiconductor, doped with areas of a p-
type material as shown in figure 5-1. Between the source and the drain,
the n-type material acts as a resistor. The current flow (from drain to
source) consists of majority carriers (electrons for n-type material).
Fig. 5-1. JFET structure (symmetric)
5-3. JFET Characteristics

The junction field effect transistor (JFET) is different from the common
bipolar junction transistor (BJT) in many aspects. Unlike BJT’s, the input
diode junction of a JFET is reverse biased, and hence it has a very high
input impedance. Having high input impedance minimizes the device
loading effect on the signal source.
The control element of the JFET comes from depletion of charge carriers
in the n-channel. When the gate is made more negative, it depletes more
majority carriers. This reduces the drain current (ID) for a given value of
source-to-drain voltage (VDS). However, for a given value of gate voltage
(VGS), the JFET current is very nearly constant (saturated) over a wide
range of source-to-drain voltages.
248
Fig. 5-2. JFET principle of operation.
The typical current-voltage characteristics of n-channel JFET are shown

in Figure 5-3. The three primary regions shown on the graph are the
linear region, the saturated region, and the breakdown region. The linear
region is that region where the drain to source voltage is less than the
drain saturation voltage. It can be seen that the voltage current
relationship is a linear function. At the point where the drain to source
voltage reaches the drain saturation voltage, the saturated region begins.
The curves illustrate that increasing the gate reverse voltage reduces the
drain current as well as the drain saturation voltage.
This shows the manner in which the drain current is modulated when
modulating the gate voltage. The general relation describing the channel
current of a JFET is as follows:
ID = b [VDS.Vp½ – 2/3 (VDS+Vbi – VGS)3/2 + 2/3(Vbi – VGS)3/2] (5-1a)
where b = 2 n (W/L).(2e Nd )½ and Vbi is the junction built-in voltage
Vbi = Vt ln (Nd.Na / ni2) (5-1b)
Here W is the channel width, L is the channel length , μn is the electron

mobility, Nd is the channel doping concentration and VP is the pinch-off
voltage.
249
The pinch-off voltage (VP) is the gate voltage at which the drain current
reaches zero, as shown in Fig. 5-3.
Vp= (eNd / 2 ) a2 (5-1c)
Fig. 5-3. JFET modes of operation.
The above I-V characteristics may be simplified in two distinct regions as

shown in Fig. 5-4.
1- In the saturation region (where | VDS - VGS | > VP )
ID = IDSS [1+ (VGS /Vp ) ] 2 (5-2a)
where
IDSS = (2a) (W/L).(e Nd n).VdS (5-2b)
2- In the linear region (where | VdS - VgS | < Vp )
ID = (2a) (W/L).(e Nd n). [1-√ (VGS /Vp) ] VDS (5-3a)

or
ID = 2 (IDSS /Vp2).[VGS - Vp – ½ VDS ] VDS (5-3b)
250
Fig. 5-4. JFET output characteristics.
The following figure the transfer characteristics (ID versus VGS) of the n-
channel JFET. The transfer characteristic for the JTET is useful for
visualizing the gain of the device and identifying the linear region. The
gain is proportional to the slope of the transfer curve. The current value
IDSS represents the value when the gate is shorted to ground, the maximum
current for the device. This value is a part of the data sheet supplied by
the manufacturer of any JFET.
It worth notice that the tangent line representing the gain in the linear
region intersects with the zero current line at about half the pinch voltage
(VP/2). Note that the trans-conductance of the JFET (gm) in the saturation
region is given by:
gm = ∂Id / ∂Vgs = 2( Ip /Vp ) (5-4)
where we put Vgs = Vbi in saturation and hence
Ip = IDSS / [1- Vbi/Vp ]= 2e2 W n Nd2 a3 /3 L (5-5)
251
Fig. 5-5. JFET output and transfer characteristics.
252
5-4. JFET Small Signal Model

One can use one of the simple AC models of the JFET, such as the one
shown in figure 5-6(a) or the equivalent h-parameters model, to derive the
AC voltage gain in an easy way. Figure 5-6(b) depicts the JFET AC
model at high frequencies. Note the existence of the JFET parasitic
capacitors, Cgs and Cgd.
Fig. 5-6(a). JFET equivalent circuit at low frequency.
Fig. 5-6(b). JFET equivalent circuit at high frequency.
The so called transition frequency, of the FET, is given by:
fT = gm / [2 (Cgs+Cgd)] (5-6)
Cgs = Cgo/(1 – VGS/Vbi)½ (5-7a)
Cgd = Cgo/(1 – VGD/Vbi)½ (5-7b)
with
Cgo = ½ W.L (e  Nd /2 Vbi)½ (5-7c)
253
Example 5-1:
Consider a Si n-channel JFET, with Nd =3x1016 cm-3, Na = 1019 cm-3, a =
0.5m, L = 5m, W = 100m and n = 1350 cm2/Vs. Calculate fT.
Vp = e Nd a2 /2  = 5.65 V
Ip = 2e2 W n Nd2 a3 /3 L = 73.2 mA
Vbi = (kBT/e) ln (Na.Nd/ni2) = 0.87V
IDS = Ip (1-Vbi/Vp) = 62 mA
gm = 2 Ip / Vp = 25.9 mS
Cgo = ½ W.L (e  Nd /2 Vbi)½ = 140 pF
fT = gm / [2 (Cgs+Cgd)] = gm / [2 Cgo] = 16.8 GHz.
5.5. JFET Amplifiers

In much the same way as BJT’s, JFET’s can be mounted in three
configurations, namely:
1- Common gate (C-G) configuration,

2- Common source (C-S) configuration, and
3- Common drain (C-D or source follower ) configuration.
Fig. 5-5. JFET circuit configurations.
Figure 5-5 depicts the circuit configurations, for a n-channel JFET’s.

Also, Fig. 5-6 depicts the JFET small signal equivalent circuit, in
common source configuration.
The AC voltage gain of such a circuit is given by:
Av = Vo / V= - gm ( RL // rd ) (5-8)
254
where gm is the JFET transconductance (gm=DS/VGS) and rd is the

output resistance of the JFET (rd =VDS/IDS). For an n-channel JFET
in the linear mode rd is defined as follows:
rd = VDS / ID = Ron / [1- √(Vbi-VGS)/Vp ] (5-9)
where Ron = Vp /3Ip is called the ON resistance of the JFET.
The most frequently encountered configuration for a JFET amplifier is

the common source circuit. The source is common to the input and output
as shown in the diagram.
Fig. 5-6. JFET in common-source configuration
255
5-6. Other FET Structures

There exist several variations of field effect transistors. However, all
field-effect transistors are distinguished by the method of insulation
between channel and gate. Field effect transistors include, but not
restricted to:
 JFET (Junction Field-Effect Transistor) uses a reverse biased p-n

junction to separate the gate from the body.
 MESFET (Metal–Semiconductor Field-Effect Transistor)

substitutes the p-n junction of the JFET with a Schottky barrier; used in
GaAs and other III-V semiconductor materials.
 HEMT (High Electron Mobility Transistor), which makes use of

bandgap engineering in a ternary semiconductor like AlGaAs. HEMT is
also called an HFET (heterostructure FET). The fully depleted wide-
band-gap material forms the isolation between gate and body.
 MODFET (Modulation-Doped Field Effect Transistor) uses a

quantum well structure formed by graded doping of the active region.
 MOSFET (Metal–Oxide–Semiconductor Field-Effect Transistor)

utilizes an insulator (typically SiO2) between the gate and the body.
5-6.1. MESFET
Metal Epitaxial Semiconductor Field Effect Transistor (MESFET) is
quite similar to a JFET in construction and terminology. MESFET
consists of a conducting channel positioned between a source and drain
contact region, as shown in the figure 5-7. The difference is that instead
of using a P-N junction for a gate, a Schottky (metal-semiconductor)
junction is used.
The MESFET differs from the insulated gate FET (IGFET or MOSFET)
in that there is no insulator under the gate over the active region. This
implies that the MESFET gate should, be reverse biased such that one
does not have a forward conducting metal semiconductor (Schottky)
diode. While this restriction inhibits certain circuit possibilities, MESFET
devices work reasonably if kept within the design limits. Generally the
narrower the gate-modulated channel the better the frequency handling
capabilities. MESFETs are usually constructed in compound semi-
conductor technologies such as GaAs, InP, or SiC, rather than silicon.
256
The use of GaAs rather than silicon MESFETs provides two significant
advantages: first of all the electron mobility is more than 5 times larger,
while the saturation velocity is about twice that of Si. Second it is
possible to fabricate semi-insulating (non-doped) GaAs substrates, which
eliminates the problem of absorbing microwave power in the substrate.
MESFETs can be operated up to approximately 30 GHz, and are
commonly used for microwave frequency communications and radar.
Fig. 5-7(a). Idealized structure of a GaAs MESFET
The equivalent circuit of a MESFET is quite similar to that of the FET.

The following figure depicts the equivalent circuit model of a MESFET
at microwave frequencies.
Fig. 5-7(b). equivalent circuit model of a MESFET

257
5-6.2. MODFET & HEMT

The modulation-doped field effect transistor (MODFET) is a type of
heterojunction field-effect transistor, also known as the High Electron
Mobility Transistor (HEMT). Like other FETs, MODFETs are used in
integrated circuits as digital switches. MODFETs can also be used as
amplifiers for large amounts of current.
Figure 5-8 depicts an AlGaAs MODFET and its carrier and field
distribution. The high carrier mobility and switching speed of MODFETs
come from the following. The wide bandgap element is doped with donor
atoms; thus it has excess electrons in its conduction band. These electrons
diffuse to the adjacent narrow bandgap material. The motion of electrons
cause a change in potential and electric field between materials. The
electric field will push electrons back to the conduction band of the wide
bandgap element. The diffusion process continues until electron diffusion
and drift balance each other, creating a junction. The fact that the charge
carriers are majority carriers yields high switching speeds, and the fact
that the low bandgap semiconductor is undoped means high mobility.
Fig.5-8(a). Idealized structure of an AlGaAs modulation doped FET (MODFET)
258
Fig.5-8(b). Electric charge density and electric field across an AlGaAs MODFET
An important aspect of a HEMT is that the band discontinuities across the

conduction and valence bands can be modified separately. This allows the
type of carriers in and out of the device to be controlled. Figure 5-9
shows the structure of a SiGe HEMT.
As HEMTs require electrons to be the main carriers, a graded doping can

be applied in one of the materials making the conduction band
discontinuity smaller, and keeping the valence band discontinuity the
same.
This diffusion of carriers leads to the accumulation of electrons along the

boundary of the two regions inside the narrow band gap material. The
accumulation of electrons leads to a very high current in these devices.
The accumulated electrons are also known as two dimension electron gas
(2 DEG). Note that most of MESFETs (and other FET structures) use a
top layer of low resistance metal on the gate, so that the FET profile looks
like a mushroom in cross section
259
Fig. 5-9. Detailed structure of a SiGe HEMT
5-7. FET Noise

A prime application of MESFETs has been in low-noise amplification.
Therefore is important to derive a simple analytic expression for
calculating the minimum noise figure of a FET. Since the noise figure of
a FET is affected by both bias point and generator impedance, the
minimum noise figure, NFmin, defined here is an absolute minimum
noise figure obtained by adjusting both bias and generator impedance.
According to Fukui, the minimum noise figure of a FET (NFmin) is
empirically given by:
(5-10)
where the factor KF 2.5 to 3.0 for FETs and KF 1.5 to 2.0 for
HEMTs. The factor KF is a gross simplification of the drain-current noise
contribution to the overall noise. However, using the relationship of the
equivalent circuit elements, the expression can be further simplified:
260
(5-11)
5-8. JFET Testing

Testing a JFET with a multimeter might seem an easy task, because it has
only one PN junction to test: either measured between gate and source, or
between gate and drain. When a JFET is checked as a diode (gate-to-
channel junction) multi-meter should indicate low resistance between
gate and source with one polarity and very high resistance between gate
and source with meter polarity reversed. If the meter indicates high
resistance with both the polarities, it means that the gate junction is open.
On the other hand, if meter indicates low resistance with both polarities, it
means that the gate junction is shorted.
Fig. 5-10(a). Testing a JFET with a multimeter
Testing continuity through the drain-source channel is another matter,

though. Remember from the last section how a stored charge across the
capacitance of the gate-channel PN junction could hold the JFET in a
pinched-off state without any external voltage being applied across it?
This can occur even when you're holding the JFET in your hand to test it!
Consequently, any meter reading of continuity through that channel will
be unpredictable, since you don't necessarily know if a charge is being
stored by the gate-channel junction.
261
Of course, if you know beforehand which terminals on the device are the
gate, source, and drain, you may connect a jumper wire between gate and
source to eliminate any stored charge and then proceed to test source-
drain continuity with no problem.
Fig. 5-10(a). Testing a JFET with a multimeter
However, if you don't know which terminals are which, the

unpredictability of the source-drain connection may confuse your
determination of terminal identity. A good strategy to follow when testing
a JFET is to insert the pins of the transistor into anti-static foam (material
used to ship and store electronic components) just prior to testing. The
conductivity of the foam will make a resistive connection between all
terminals of the transistor when it is inserted. This connection will ensure
that all residual voltage built up across the gate-channel PN junction will
be neutralized. Since the JFET channel is a single, uninterrupted piece of
semiconductor material, there is usually no difference between the source
and drain terminals. A resistance check from source to drain should yield
the same value as a check from drain to source. This resistance should be
low (a few hundred ohms) when the gate-source PN junction voltage is
zero. By applying a reverse-bias voltage between gate and source, pinch-
off of the channel should appear by an increased resistance reading on the
meter.
262
5-9. Summary
All field-effect transistors are unipolar rather than bipolar devices. That
is, the main current through them is comprised either of electrons through
an N-type semiconductor or holes through a P-type semiconductor. The
previous discussion of the JFET illustrates that:
1- The junction field effect transistor in its simplest form is essentially a

voltage controlled resistor. The resistive element is usually a bar of
silicon. For an N-channel JFET this bar is an N-type material sandwiched
between two layers of P-type material.
2- The JFET operates as a depletion mode device, and,
3. The JFET performs as a voltage controlled current amplifier.
The JFET is preferred in many circuit applications due to its high input
impedance because it is a reverse biased PN junction. Its operation is that
of the flow of majority carriers only and therefore acts as a resistive
switch. It also is inherently less noisy than bipolar devices and can be
used in low signal level applications.
The junction field effect transistor (JFET) is different from the common
bipolar junction transistor (BJT) in many aspects. Unlike BJT’s, the input
diode junction of a JFET is reverse biased, and hence it has a very high
input impedance. In this chapter, we summarize some fundamental
concepts about junction field effect transistors (JFET). Having high input
impedance minimizes the device loading effect on the signal source.
263
The following figure depicts the operation of the JFET at different bias
conditions.
To calculate drain current (ID) for any given gate-source voltage (VGS),
there is a simple equation that may be used. It reflects the nonlinear
behavior of the dynamic (ID-VGS) characteristics of a JFET:
There exist several variations of field effect transistors. However, all

field-effect transistors are distinguished by the method of insulation
between channel and gate. Field effect transistors include, but not
restricted to:
 JFET (Junction Field-Effect Transistor) uses a reverse biased p-n
junction to separate the gate from the body.
 MESFET (Metal–Semiconductor Field-Effect Transistor) substitutes the
p-n junction of the JFET with a Schottky barrier; used in GaAs and other
III-V semiconductor materials.
 HEMT (High Electron Mobility Transistor), which makes use of
bandgap engineering in a ternary semiconductor like AlGaAs. HEMT is
also called an HFET (heterostructure FET). The fully depleted wide-
band-gap material forms the isolation between gate and body.
 MODFET (Modulation-Doped Field Effect Transistor) uses a quantum
well structure formed by graded doping of the active region.
 MOSFET (Metal–Oxide–Semiconductor Field-Effect Transistor) utilizes
an insulator (typically SiO2) between the gate and the body.
264
5-10. Problems
5-1) What is the basic structure of a JFET? What are its most important
parasitics?
5-2) What are key technological constraints in the design and fabrication
of JFET?
5-3) Consider the JFET circuit in left-hand side of the figure below. The
FET has VP = −3 V, IDSS = 9 mA. Find the values of all resistors so that
Vgs = 5 V, Id = 4 mA, and Vds = 11 V. Assume a 0.05 mA current in the
voltage divider.
If an AC source, vin, is connected to the gate, and the amplified output,

vout, is taken from the drain, prove that the AC voltage gain is given by:
Av = vo/vin = - gm RD / (1 + gmRS)
5-4) Repeat the above problem for the differential amplifier in the right
side figure.
5-5) How do JFET switch? What sets their time response?
5-6) Calculate the ON resistance and the transition frequency of an n-

channel Si JFET, given that Nd =3x1016 cm-3, Na = 1019 cm-3, a = 0.5m, L
= 5m, W = 100m and n = 1350 cm2/Vs.
265
5-7) The field-effect transistor (FET) combines what desired character-

istic of the vacuum tube with the other advantages of a BJT?
1. Low output impedance
2. High output impedance
3. Low input impedance
4. High input impedance
5-8) What does the FET use to control the electrostatic field within the
BJT?
1. Current
2. Voltage
3. Low input impedance
4. High input impedance
5-9) The JFET gate element corresponds very closely in operation with
(a) what part of a BJT and (b) what part of a vacuum tube?
1. (a) Emitter (b) cathode
2. (a) Base (b) grid
3. (a) Base (b) cathode
4. (a) Collector (b) plate
5-10) If a P-type material is used to construct the gate of a JFET, what

material should be used to construct the remaining part of the JFET?
1. N-type
2. P-type
3. Mica type
4. Junction type
5-11) When reverse bias is applied to the gate of a JFET, what happens to
(a) source-to-drain resistance of the device and (b) current flow?
1. (a) Decreases (b) decreases
2. (a) Decreases (b) increases
3. (a) Increases (b) decreases
4. (a) Increases (b) increases
5-12) What is the "pinch off" voltage of an FET?

1. The voltage required for the FET to conduct
2. The voltage required to overcome the FET reverse bias
3. The voltage required to reduce drain current to zero
4. The voltage required to reduce gate voltage to zero
266
Photocopy the following page, read the assessment carefully and answer
on the page. Carry out the required measurement, and comment if there
exist a discrepancy between the measured and calculated values. Don't
forget to write your name and ID.
267
5-12. References:
[1] P. H. Ladbrooke, MMIC Design: GaAs FETs and HEMTs, Artech

House, MA, 1989.
[2] J. Millman, and C. Halkias, Integrated Electronics Analog and

Digital Circuits and Systems, McGraw-Hill Book Company, New York,
1972
[3] A. S. Grove, Physics and Technology of Semiconductor Devices, John

Wiley And Son, New York, 1967.
[4] H. Fukui, “Design of Microwave GaAs MESFETs for Broad-Band

Low-Noise Amplifiers,” IEEE Trans. Microwave Theory and Tech., Vol.
MTT-29, No. 10, pp. 176–183, 1979.

Inc., 2d edition, 2002.

Inc., 1st edition, 1985.
[7] R. Goyal, Editor, Monolithic Microwave Integrated Circuits:

Technology and Design, , Artech House, MA, 1989.
268
Metal-Oxide-Semiconductor (MOS)
Structure & Charge-Coupled Devices
Contents:

6-2. MOS Energy Band diagram
6-3. MOS Flatband Voltage
6-4. MOS Biasing Regimes
6-4.1. Accumulation Mode
6-4.2. Depletion Mode
6-4.3. Inversion Mode
6-5. MOS Capacitance
6-5.1. Simple Model
6-5.2. Exact Analysis
6-5.3. Advanced Analysis & Quantum Effects
6-6. Charge-Coupled Devices (CCD)
6-6.1. CCD Diffusion Time
6-6.2. CCD Camera
6-7. Summary
6-8. Problems
6-9. References
269
270
Metal-Oxide-Semiconductor
(MOS) Structure & Charge-
Coupled Devices

MOS refers to Metal- Oxide- Semiconductor. The semiconductor is
usually silicon. Other material systems have similar structures formed by
Metal Insulator–Semiconductor (MIS). The MOS capacitor forms the
basis of DRAM storage capacitors and may be simply a capacitance in an
analog integrated circuit, like voltage-controlled oscillators (VCO). The
MOS structure is also the main building block for the MOS field effect
transistor (MOSFET). The substrate is normally grounded and the Gate
electrode is usually biased with a voltage, VG, as shown in figure 6-1.
Fig. 6-1. MOS structure
Understand the function of the MOS structure.

Be acquitted with the biasing methods of the MOS capacitor,
Identify the depletion, and inversion modes of the JFET
Identify the C-V characteristics of the MOS structure
271
6-2. Energy Band diagram of an MOS

The following figure depicts the energy band diagram of an ideal MOS
structure. Here EO is the vacuum energy level (of free electrons). The
minimum energy an electron must have to free itself from the material is
called work function. The workfunction of a metal is termed ΦM. This is
the energy difference from the Fermi energy (average energy) of an
electron in the metal to the vacuum energy level. The work function of
the semiconductor is termed ΦS. This is the energy difference from the
Fermi energy of an electron in the semiconductor to the vacuum energy
level. Note that this energy depends on doping since EF depends on
doping.  is the electron affinity of the semiconductor. This is the energy
difference from the conduction band minimum in the semiconductor to
the vacuum energy level. Note that this energy does not depend on
doping. Note also that (EC - EF)FB = ΦS –  in the quasi-neutral region
where the bands are not bent (in flat band condition).
Fig. 6-2. Ideal (flatband) MOS energy band structure (n-type semiconductor)
272
The insulator is a very wide bandgap material, characterized by an

electron affinity, i. In certain situations, of non ideal structures, there
may exist some charges near the insulator-semiconductor interface. In
such a case, the semiconductor can have an electric field near the
insulator that forces the energy bands to bend near the insulator-
semiconductor interface, as shown in Fig. 6-3.
Fig. 6-3. Energy band diagram of a Non-ideal MOS, with band bending.
6-3. MOS Flatband Voltage

The flatband energy diagram means that the energy band diagram of the
semiconductor has no band bending, which implies that no charge exists
in the semiconductor, as shown in figure 6-4.
The flatband voltage is obtained when the applied gate voltage equals the
workfunction difference between the gate metal and the semiconductor
(VFB = MS = M - S). When there is a fixed charge in the oxide or at the
oxide-silicon interface, the above expression for the flatband voltage
should take them into account. Note that the workfunction of a
semiconductor, S, requires some more thought since the Fermi energy
varies with the doping type as well as with the doping concentration. This
workfunction equals the sum of the electron affinity in the
semiconductor, , the difference between the conduction band energy and
the intrinsic energy divided by the electronic charge in addition to the
bulk potential. This is expressed by the following equation:
MS = M M – – ½ Eg /e – Vt ln (Na / ni) (6-1)
273
Fig. 6-4. Energy band diagram of a flatband MOS structure (Here Al-SiO2-Si).
For a MOS capacitor, which has an n-type substrate with doping density
Nd, the workfunction difference equals:
MS =M -s = M – – ½ Eg /e + Vt ln (Nd / ni) (6-2)
The flatband voltage of real MOS structures is further affected by the

presence of charge in the oxide (ox) or at the oxide-semiconductor
interface (Qi). In this case, the flatband voltage still corresponds to the
voltage, which, when applied to the gate electrode, yields a flat energy
band in the semiconductor:
(6-3)
The second term in the above equation is the voltage across the oxide due
to the charge at the oxide-semiconductor interface (Qi) and the third term
is due to the charge density (ox) inside the oxide (insulator) layer.
274
6-4. MOS Biasing Regimes

To understand the effect of different bias modes on the operation of the
MOS capacitor we consider three distinct bias conditions. We assume
here n-type semiconductor. In the first case, which is called the
accumulation mode, the gate voltage is positive and below the flatband
voltage (VFB > VG > 0). In the second case, which is called the depletion
mode, the applied gate voltage is negative and between the flatband
voltage and the threshold voltage (VT < VG <VFB). As we will see, the
threshold voltage is the applied gate voltage, which is necessary to induce
an inverted layer at the top of semiconductor. For n-type MOS the
threshold voltage is negative. The third case, which is called the
inversion mode, the gate voltage is more negative and lower than the
threshold voltage (VG < VT). The charge distributions associated with
these bias regimes are shown in the following figure.
Fig. 6-4(a). Different bias conditions of the MOS structure, with n-type substrate
Fig. 6-4(b). Different bias conditions of the MOS structure, with p-type substrate
275
6-4.1. Accumulation Regime

It should be noted that for all VG values the Fermi level (EF) along the
MOS structure remains flat due to zero current through the structure. The
applied bias separates the Fermi levels at the metal and semiconductor
ends by eVG, such that:
EF (semiconductor) - EF (metal) = e VG (6-4)
If the semiconductor is grounded, then metal Fermi level at the metal side
moves downward if VG > 0. However, when VG < 0 the Fermi level of the
metal side moves upward. In either of the two cases the energy band
structure bends (down or up) at the semiconductor-oxide interface.
Fig. 6-5. Ideal MOS in accumulation node (n-type semiconductor with VG> 0).
Applying Poisson’s equation to the oxide, assuming there are no charges

in the oxide, yields
d ζox /dx =  = 0  ζox = constant

V =  ζox dx  V(x) is Linear with x (6-5)
6-4.2. Depletion Regime

When VG > 0 the metal Fermi-energy is lowered (E= -eV), the insulator
has an electric field across it that terminates almost immediately in the
near perfectly conducting metal, but terminates over a finite distance in
the semiconductor of finite resistivity. The charge model indicates that
negative charge must be created in the semiconductor near the interface.
This charge is in the form of electrons.
Since n = ni exp[(EF - Ei / kBT], the electron concentration in the

semiconductor near interface increases. This is called accumulation.
276
We now derive the MOS parameters at threshold with the aid of figure
6-7. To simplify the analysis we make the following assumptions:
1) Assume that we can use the full depletion approximation,

2) Assume that the inversion layer charge is zero below the threshold
voltage.
Beyond the threshold voltage we assume that the inversion layer charge
changes linearly with the applied gate voltage. The derivation starts by
examining the charge per unit area in the depletion layer, Qd. As can be
seen in Figure 6-7(a), this charge is given by:
Qd = - e Na xd (6-6)
Where xd is the depletion layer width and Na is the acceptor density in the
substrate. Integration of the charge density then yields the electric field
distribution shown in figure 6-7(b). The electric field in the
semiconductor at the interface, ζs, and the field in the oxide equal, ζox:
ζs = - e Na xd /s and ζox = - e Na xd /ox (6-7)
The electric field changes abruptly at the oxide-semiconductor interface

due to the difference in the dielectric constant. At Si/SiO2 interface the
field in the oxide is about three times larger since the dielectric constant
of the oxide (ox = 3.9 0) is about one third that of silicon (s = 11.9 0).
The electric field in the semiconductor changes linearly due to the
constant doping density and is zero at the edge of the depletion region,
based on the full depletion approximation. The potential shown in Figure
6.3 (c) is obtained by integrating the electric field. The potential at the
surface, s, equals:
s = e Na xd2 / 2s (6-8)
The calculated field and potential is only valid in depletion.
In accumulation, there is no depletion region and the full depletion

approximation does not apply.
In inversion, there is an additional charge in the inversion layer, Qinv. This

charge increases as the gate voltage is increased. However, this charge is
only significant once the electron density at the surface exceeds the hole
density in the substrate, Na.
277
Fig. 6-6. nMOS in depletion regime and onset of inversion (VG =VT).
Fig. 6-7. pMOS in depletion regime.

(a) Charge density, (b) electric field, (c) potential and (d) energy band diagram
We therefore define the threshold voltage as the gate voltage for which
the electron density at the surface equals Na. This corresponds to the
situation where the total potential across the surface is twice the bulk
potential, F.
278
F = Vt ln (Na /ni) (6-9)
The depletion layer in depletion is therefore restricted to this potential

range:
xd = (2ss/eNa), for 0 ≤ s ≤ 2F (6-10)
For a surface potential larger than twice the bulk potential, the inversion
layer charge increases exponentially with the surface potential.
Consequently, an increased gate voltage yields an increased voltage
across the oxide while the surface potential remains almost constant. We
will therefore assume that the surface potential and the depletion layer
width at threshold equal those in inversion. The corresponding
expressions for the depletion layer charge at threshold, Qd,T, and the
depletion layer width at threshold, xd,T, are:
QdT = - e Na xdT (6-11a)
xdT = √[2s(2F)/eNa] (6-11b)
Beyond threshold, the total charge in the semiconductor has to balance

the charge on the gate electrode, QM, or:
QM = - (Qd + Qinv) (6-12)
where we define the charge in the inversion layer as a quantity, which

needs to determined but should be consistent with our basic assumption.
This leads to the following expression for the gate voltage, VG:
VG = VFB + F + QM /Cox = VFB + F + (QM + Qinv) /Cox (6-13)
In depletion, the inversion layer charge is zero so that the gate voltage
becomes:
VG = VFB + F +√(2esNas) /Cox for 0 ≤s ≤ 2 F (6-14)
while in inversion this expression becomes:
VG = VFB + 2F +√(4esNaF) /Cox - Qinv/ Cox (6-15)
The third term in (6-15) states our basic assumption, namely that any
change in gate voltage beyond the threshold requires a change of the
279
inversion layer charge. From equation (6-15), we can write the threshold
voltage as follows:
VT = VFB + 2F +√(4esNaF) /Cox (6-16)
The threshold voltage dependence on the doping density is illustrated

with figure 6-8 for both n-type and p-type MOS structures with an
aluminum gate.
Fig. 6-8. Threshold voltage of nMOS (with n-type semiconductor) and pMOS (with
p-type semiconductor) structures.
6-4.3. Inversion Regime

The following figure depicts the Charge distribution and energy bands of
MOS structure in inversion mode for n-type semiconductor (VG < VT) and
p-type semiconductor (VG > VT). The basis assumption of the MOS model
is that the inversion layer charge is proportional to the applied voltage. In
addition, the inversion layer charge is zero at and below the threshold
voltage. Thus, for a p-type substrate, we have:
Qinv = Cox (VG -VT) for VG > VT

(6-17)
Qinv = 0 for VG < VT
The linear proportionality can be explained by the fact that a gate voltage
variation causes a charge variation in the inversion layer. The
proportionality constant between the charge and the applied voltage is
therefore expected to be the gate oxide capacitance.
280
Fig. 6-9. Charge distribution and energy bands of MOS structure in inversion mode
for n-type semiconductor (VG < VT ) and p-type semiconductor (VG > VT)
The above assumption implies that the inversion layer charge is located
exactly at the oxide-semiconductor interface. Because of the energy band
gap of the semiconductor separating the electrons from the holes, the
electrons can only exist if the p-type semiconductor is first depleted. The
threshold voltage (VT) is the gate voltage at which the electron inversion-
layer starts at the surface of the semiconductor.
Example 6-2:
Calculate the P-base doping concentration (assuming it is uniformly
doped) of an n-channel silicon MOSFET structure to obtain a threshold
voltage of 2V. The gate oxide thickness is 500A. The fixed charge in the
gate oxide is 2 x 1011 cm-2. Assume N+ polysilicon with a doping
concentration of 1020 cm-3 is used as the gate electrode.
281
Solution:
The threshold voltage is given by:
VT = VFB + 2F - Qox /Cox = VFB + 2Vt ln (Nd/ni) +√(4esNaF) /Cox

where we neglected the is the total effective charge in the oxide QOX. In
addition, the work-function difference between heavily doped N+
polysilicon and P-silicon must be taken into account. A threshold voltage
of 2V is achieved at a doping concentration of 1.16 x 10 17 cm-3. The
contribution from the fixed oxide charge is -0.469V. The shift due to the
N+ polysilicon gate electrode is -0.968.
6-5. MOS Capacitance

The capacitance-voltage (C-V) measurements of MOS capacitors provide
a wealth of information about the structure, which is of direct interest
when one evaluates a certain MOS process. Since the MOS structure is
simple to fabricate, the technique is widely used. To understand
capacitance-voltage measurements one must first be familiar with the
frequency dependence of the measurement. This frequency dependence
occurs primarily in inversion since a certain time is needed to generate
the minority carriers in the inversion layer. Thermal equilibrium is
therefore not immediately obtained.
The low frequency or quasi-static measurement maintains thermal

equilibrium at all times. This capacitance is the ratio of the change in
charge to the change in gate voltage, measured while the capacitor is in
equilibrium. A typical measurement is performed with an electrometer,
which measures the charge added per unit time as one slowly varies the
applied gate voltage. The high frequency capacitance is obtained from a
small-signal capacitance measurement at high frequency. The bias
voltage on the gate is varied slowly to obtain the capacitance versus
voltage. Under such conditions, one finds that the charge in the inversion
layer does not change from the equilibrium value at the applied dc
voltage. The high frequency capacitance therefore reflects only the charge
variation in the depletion layer and the (small) movement of the inversion
layer charge.
In this section, we first derive the simple capacitance model, which is
based on the full depletion approximation and our basic assumption. The
comparison with the exact low frequency capacitance will reveal that the
largest error occurs at the flatband voltage. We therefore derive the exact
flatband capacitance using the linearized Poisson's equation. Then we
discuss the non-ideal effects in MOS capacitors.
282
6-5.1. Simple Model

The capacitance of an MOS capacitor is obtained using the same
assumptions, we supposed so far. The MOS structure is treated as a series
connection of two capacitors: the capacitance of the oxide Cox and the
capacitance of the semiconductor Cs, which may be in depletion or
accumulation or inversion, according to the value of VG.
C(VG) = [1/Cox + 1/ Cs ] -1 (6-18)
Fig. 6-10(a). Schematic model of the equivalent capacitance of a MOS capacitor.
In accumulation, there is no depletion layer. The remaining capacitor is

the oxide capacitance, so that the capacitance equals:
CLF = CHF = Cox, for VG ≤ VFB (6-19)
In depletion, the MOS capacitance is obtained from the series connection

of the oxide capacitance and the capacitance of the depletion layer, or:
CLF = CHF = (1/Cox + xd /s )-1 for VFB ≤ VG ≤ VT (6-20a)
where xd is the variable depletion layer width which is calculated from:
xd = [ 2s s /e Nd]½ (6-20b)
In order to find the capacitance corresponding to a specific value of the

gate voltage, we also need to use the relation between the potential across
the depletion region and the gate voltage, which is given by:
VG = VFB + s +√(2esNas) /Cox for 0 <s <2F (6-21)
In inversion, the capacitance becomes independent of the gate voltage.

The low frequency capacitance equals the oxide capacitance since charge
is added to and removed from the inversion layer. The high frequency
capacitance is obtained from the series connection of the oxide
283
capacitance and the capacitance of the depletion layer having its

maximum width, xd,T. The capacitances are given by:
CLF = Cox and CHF = (1/Cox + xdT /s )-1 for VG≥VT (6-22)
The flatband capacitance of the MOS structure is obtained by calculating

the series connection of the oxide capacitance (Cox) and the capacitance of
the semiconductor (Cs) at flatband condition, yielding:
CFB = (1/Cox + LD /s )-1 (6-23)
where s is the potential at the surface of the semiconductor and LD is the

Debye length such that
 = s exp(- x / LD) with LD = (sVt /eNa)½ (6-24)
Non-ideal effects in MOS capacitors include fixed charge, mobile charge

and charge in surface states. Performing a capacitance-voltage
measurement can identify all the three types of charge.
The capacitance of an MOS capacitor as calculated using the simple

model is shown in figure 6-10(b). The dotted lines represent the simple
model while the solid line corresponds to the low frequency capacitance
as obtained from the exact analysis.
Fig. 6-10(b). Low frequency capacitance of an n-MOS capacitor. The exact solution
for the low frequency capacitance (solid line) and the low and high frequency
capacitance obtained with the simple model (dotted lines). Na=1017cm-3 and tox=20nm
284
Example 6-2.
Calculate the oxide capacitance (Cox), the flatband capacitance (CFB) and
the high frequency capacitance in inversion of a Si n-MOS capacitor.
Consider the substrate doping Na = 1017 cm-3, the oxide thickness is 20nm
(ox = 3.9 e0) and an aluminum gate (M = 4.1V).
Solution (Using the above simple models)

The oxide capacitance is given by:
The flatband capacitance is given by:
The high-frequency capacitance is given by:
The depletion region width at threshold is given by:
where F = Vt ln (Na / ni) = 0.419V.
6-5.2. Exact Analysis

In the exact analysis of the MOS structure, we solve the Poisson equation
with making use of the Fermi-Dirac statistics:
d2/dx2 = - d /dx = -/s = (e/s) [n – p - Na- + Nd+ ] (6-25)
At thermal equilibrium, the hole and electron densities can be expressed

as functions of the potential,and a reference (Fermi) potential, F.
285
n = ni exp[ -F)/Vt ]
p = ni exp[F -)/Vt ] (6-26)
Also, the net doping concentration may be expressed as follows:
Nd+ - Na- = -2ni sinh (F / Vt ) (6-27)
So that the Poisson equation may be written as follows in equilibrium:
d2/dx2 = (2e ni /s) [sinh [ (F) /Vt ] - sinh (F /Vt )] (6-28)
Integrating this equation gives the distributions of electric field (x) and
the potentialV, in equilibrium. For instance, the electric field at the
surface of the semiconductor s is given by the following expression:
(6-29)
After solving the Poisson equation we can get the low-frequency

capacitance of the MOS structure, as follows:
CLF = |dQs /dVG |= dss]/d[s+toxs(s/ox)]=(1/ Cs,LF + 1/Cox)-1 (6-30a)
where we substituted the semiconductor charge Qs = ss (from Gauss

law), the infinitesimal change dVG = d[s+toxs(s/ox)], Cox = ox/tox) and
Cs,LF =|dQs /ds|= |s(ds/ds) |. After substituting s from (6-29) we get:
(6-30b)
The corresponding gate voltage is:
VG = VFB + s + Vox (6-30c)
and Vox = tox(s/ox), with s and s are the semiconductor surface

potential and electric field values. Also, the high frequency value of the
MOS capacitance is given by:
286
CHF = (1/Cs,HF +1/Cox)-1 (6-31a)
where
(6-31b)
and s,dd is the electric field value at the semiconductor surface in deep
depletion mode. It should be noted that the above expression is actually
an approximate solution. In this approximate solution, the redistribution
of the inversion layer charge with applied gate voltage is ignored though
it does affect the depletion layer width and capacitance. This solution
therefore introduces an error of about 6% at the onset of strong inversion
and the error increases almost linearly with increasing surface potential.
6-5.3. Advanced Analysis & Quantum Effects (A)

In the above classical analysis of the MOS structure, we solved the
Poisson equation and considered the Fermi-Dirac (or Boltzmann)
statistics in thermal equilibrium. In this analysis, we neglected the
confinement of charge carriers in the inversion layer beneath the SiO2/Si
interface, which creates subbands of energy levels. This led to an
approximate solution of the C-V characteristics.
A more accurate analysis can be carried out by solving the Schrödinger

equation, self consistently, with Poisson's equation at this region to get
the charge carrier concentration and subsequently, the accurate C-V
characteristics, as shown in figure 6-11.The solution of the Schrödinger
equation at the SiO2/Si interface results in the following eignevalues
(energy levels) of subbands:
(6-32a)
where j = 0, 1, 2,… is the subbabnd number and the effective mass mx =

0.9mo for (100) Si. If we consider only the ground state E0 is populated by
electrons, then the thickness of the inversion layer is given by:
(6-32b)
287
More details about the quantization of energy levels in the inversion layer
of the MOS structures and their effect on their C-V characteristics can be
found in Chapter 10 (section 10-2.1).
Fig. 6-11. Real C-V characteristics of a an MOS structure. The measured and
classical analysis characteristics are also shown for the matter of comparison.
Fig. 6-12. Energy levels (subbands) at the SiO2/Si interface of a an MOS structure.
288
6-6. Charge-Coupled Devices (CCD’s)

Charge-coupled devices (CCD’s) are analog shift registers, enabling
electric charges to be transported through successive stages (capacitors),
using a clock signal. Technically speaking, CCDs consist of a series of
closely spaced MOS capacitors, separated by channel stops (implanted
potential barriers) as shown in Fig 6-11.
Fig. 6-11. CCD structure and potential distribution, at different bias conditions
These MOS capacitors usually operate in deep depletion with 1 bit per 3
capacitors (by the aid of a 3-phase clock) as shown in Fig. 6-12. Charge
moves with diffusion time given by:
(6-33)
For instance, consider a silicon CCD array with 5m wide electrodes.
Calculate the electron diffusion time. Use an electron mobility of 400
cm2/V.s. The diffusion time in this case is given by:
6-6.1. CCD Diffusion Time

Derivation of the electron diffusion time starts from the time dependent
continuity equation
(6-34)
289
Simplify by eliminating any generation or recombination and considering

diffusion only, results in the time dependent diffusion equation:
(6-35)
A general solution to this partial differential equation can be obtained by

assuming that the carrier density can be written as the product of a
function T, which only depends on time and a function X, which only
depends on position. Substitution into the diffusion equation and re-
arrangement results in two parts, one a function of t only and one a
function of x only. Since both have to equal each other they must equal a
constant. The unit of the constant is s-1 and one would expect the desired
solution to decrease with time so that the equation can be rewritten as:
(6-36)
The general solution is therefore
(6-37)
where the constants A and B must be determined. At x = 0, there is no

current since the potential barrier caused by the lower voltage applied to
the electrode to the left block any carrier flow. Since the diffusion current
depends on the gradient of the current, the derivative of the carrier density
must be zero, which eliminates the sine function as a possible solution.
The solution therefore reduces to:
(6-38)
Where n(0,0) is the initial carrier density at x = t = 0. The boundary

condition at x = L is obtained by assuming that the electric field between
two adjacent capacitors will immediately remove any carriers that arrive
so that the carrier density is zero at any time, t, so that n(L,t) = 0. The
argument of the cosine function should therefore equal p/2. From this one
then finds the diffusion time constant, td.
290
(6-39)
Fig. 6-12. Operation of a 3-phase CCD.
291
6.6.2. CCD Cameras

A CCD is a highly sensitive photon detector. The CCD camera is divided
up into a large number of light-sensitive small areas (known as pixels)
which can be used to build up an image. CCD camera must perform 4
tasks to generate an image:
o Generate Charge: by photoelectric Effect

o Collect Charge pixels: by an array of electrodes called gates
o Transfer Charge: Apply a voltage across gates. Electrons move
down vertical registers to horizontal register. Each line is serially
read out by an on-chip amplifier.
o Detect Charge: individual charge packets are converted to a digital
output and then digitally encoded.
Figure 6-13 shows the block diagram of a CCD camera. The following
figure shows a photograph of a CCD camera on a single chip and its
internal structure.
Fig. 6-13. Block diagram of a CCD camera.
292
Fig. 6-14. Photograph of a CCD camera chip and its internal structure
293
6-7. Summary
MOS refers to Metal- Oxide- Semiconductor. The following figure

depicts the general structure of an MOS structure, which acts as voltage
controlled capacitor.
The n-MOS capacitor has an n-type substrate, a positive charge in the

depletion layer and a positive charge in the inversion layer.Since the
Fermi energy is at eF above the intrinsic energy level (midgap), the work
function difference is given by:
MS = M M – – ½ Eg /e + F

where
F = Vt ln (Nd / ni) for n-type substrate
Alternatively, the p-MOS structure has
MS = M M – – ½ Eg /e – Vt ln (Na / ni)

The depletion layer width at the onset of inversion (when VG=2F) is
given by the following relation (for n-MOS):
xdT = √(2s(2F/eNd)
The threshold voltage of n-MOS is typically negative due to the positive

charge in the depletion layer width
VT =VFB - 2F - √[2s(2F)eNd] / Cox
Whereas the flatband voltage is given by:
294
When the MOS structure is acted upon by a gate voltage, VG, it may be in
any of the following 3 modes, according to the value and polarity of
applied bias (VG):
Accumulation mode,
Depletion mode, and
Inversion mode.
The following figure depicts these modes for n-MOS structure:
And the following figure depicts these modes for p-MOS structure:
295
The MOS structure is treated as a series connection of two capacitors: the

capacitance of the oxide Cox and the capacitance of the semiconductor Cs,
which may be in depletion or accumulation or inversion, according to the
value of VG.
C(VG) = [1/Cox + 1/ Cs ] -1
According to simple models, the low-frequency C-V characteristics of a

MOS capacitor is given by the following relations:
In accumulation, there is no depletion layer. The remaining capacitor is

the oxide capacitance, so that the capacitance equals:
CLF = CHF = Cox, for VG ≤ VFB
In depletion, the MOS capacitance is obtained from the series connection

of the oxide capacitance and the capacitance of the depletion layer, or:
CLF = CHF = (1/Cox + xd /s )-1 for VFB ≤ VG ≤ VT
where xd is the variable depletion layer width which is calculated from:
xd = [ 2s s /e Nd]½
In inversion, the capacitance becomes independent of the gate voltage.
The low frequency capacitance equals the oxide capacitance since charge
is added to and removed from the inversion layer. The high frequency
capacitance is obtained from the series connection of the oxide
capacitance and the capacitance of the depletion layer having its
maximum width, xd,T. The capacitances are given by:
CLF = Cox and CHF = (1/Cox + xdT /s )-1 for VG≥VT
The flatband capacitance of the MOS structure is obtained by calculating

the series connection of the oxide capacitance (Cox) and the capacitance of
the semiconductor (Cs) at flatband condition, yielding:
296
CFB = (1/Cox + LD /s )-1

where s is the potential at the surface of the semiconductor and LD is the
Debye length such that
 = s exp(- x / LD) with LD = (sVt /eNa)½

Non-ideal effects in MOS capacitors include fixed charge, mobile charge
and charge in surface states. Performing a capacitance-voltage
measurement can identify all the three types of charge.
The capacitance of an MOS capacitor as calculated using this simple

model is shown below. The dotted lines represent the simple model while
the solid line corresponds to the low frequency capacitance as obtained
from the exact analysis.
297
6-8. Problems
6-1) Calculate the depletion region width in a silicon n-MOS capacitor,

with aluminum gate,
(i) If the applied bias is equal to half the threshold voltage. Take the
substrate doping concentration as 1016 cm-3 and the oxide (insulator)
thickness is 30 nm.
ii) Calculate the surface potential (s) of this n-MOS capacitor.
6-2) Show how to use the low and high frequency C-V measurements of
an n-MOS structure to determine the surface states density at the oxide-
semiconductor interface.
6-3) The measurement of the capacitance-voltage characteristics of a

silicon n-MOS was fitted by the following expression. The capacitor area
is 100m x100m and its relative permittivity is 3.9.
C(VG) = 5 pF + 15 pF/[1 + exp(VG / 40Vt)]
i) Calculate the oxide capacitance (Cox) per unit area and the oxide
thickness. From the minimum capacitance, calculate the maximum
depletion layer width and the substrate doping density.
ii) Calculate the bulk potential.
iii) Calculate the flatband capacitance and the flatband voltage.
iv) Calculate the threshold voltage of the MOS structure.
6-4) An MOS capacitor with an oxide thickness of 20 nm has an oxide

capacitance, which is three times larger than the minimum high-
frequency capacitance in inversion. Find the substrate doping density.
6-5) A CMOS gate requires both n-type and p-type MOS capacitors with
a threshold voltage of 2V and -2V, respectively.
i) If the gate oxide is 50 nm what are the required substrate doping
densities? Assume the gate electrode is aluminum.
ii) Repeat for a p+ poly-silicon gate CMOS.

298
The structure and schematic circuit of the CMOS are shown below, for
the matter of illustration.
299
6-9. References:
[1] S. M. Sze, Semiconductor Devices. Physics and Technology. John-

Wiley Inc., 1st edition, 1985.
[2] S. M. Sze, Semiconductor Devices. Physics and Technology. John-

[3] E. R. Fossum, “CMOS image sensors: Electronic camera-on-a-chip,”

in IEEE IEDM Tech. Dig., pp. 17–25, 1995.
[4] A. P. Strutton, Electronic Structure of Materials, Clarendon Press,

Oxford, 2004.
300
MOS Field Effect Transistor

(MOSFET)
Contents:

7-2. Types of MOS Transistors (MOSFET‟s)
7-3. MOSFET Structure
7-4. MOSFET I-V Characteristics and Modes of Operation
7-4.1. Linear Mode
7-4.2. Saturation Mode
7-5. MOSFET Sub-threshold Regime
7-6. MOSFET Small Signal Circuit Model
7-7. MOSFET as an Amplifier
7-8. MOSFET as a Switch
7-9. MOSFET Scaling
7-10. MOSFET Degradation & Hot-Carrier Effects
7-10.1. Hot-carrier Injection Currents
7-10.2. Gate Tunneling Currents
7-11. Advanced MOSFET Structures
7-11.1. PolySilicon Gate Technology.
7-11.2. CMOS Technology
7-11.3. Silicon on Insulator & SiGe on Insulator (SOI & SGOI)
7-11.4. Multi-Gate and 3-D MOSFET Structures
7-11.5. Thin-Flm Transistors (TFT)
7-11.6. Active-Matrix LCD
7-12. MOSFET Testing
7-14. Summary
7-15. Problems
7-17. References:
301
302
MOS Field Effect Transistor

(MOSFET)

MOS field-effect transistors (MOSFET‟s) are very important electronic
devices, which have founded a dedicated circuitry. For instance, field-
effect transistors with an insulated gate electrode are widely used in very
large scale integrated (VLSI) circuits, in particular, for applications in the
digital circuits, memories and microprocessors.
History of MOSFET's
In 1959, Ahmed Atalla et al. have implemented a passivation of the

silicon surface when an oxide-layer (SiO2) was grown on silicon. The
way to implement a Field-Effect Transistor (FET) was proposed. In 1960
Kahng and Atalla have discussed a silicon Metal-Oxide-Semiconductor
(MOS) transistor. Also, Hofstein and Heiman have proposed a Metal-
Oxide-Semiconductor Field-Effect Transistor (MOSFET) in 1963. An
extensive theory of MOSFET operation has been developed in next few
years by Ihantola et al., Sah, Reddi and Pao, Hofstein and Warfield and
several other researchers. Since then, a tremendous research in the MOS
technology, devices and circuits has been resulting in a dramatical
reduction in size and improvement of the MOSFET performance. As an
interesting fact, the basic MOSFET structure and the principle of the
operation, however, did not change. Most of the research effort has been
put into solving the problems which have arised as a consequence of size
reduction or because of the application of new technologies. Today, MOS
devices are common in industrial production, with gate length of
L<100nm and gate-oxide thickness of tox <10 nm.
In this chapter, we present the basic concepts of MOSFET devices and

their operation. Basically, this Chapter is intended to help the students to
understand the physical meaning of the device equations and its model
parameters. We briefly demonstrate how to use MOSFET devices to
amplify and switch signals in electronic circuits and engineering systems.
In particular, this Chapter is considered to understand and find a clear
answer for the following questions:
303
1. What„s the meaning of field-effect devices?

2. What makes the difference between an N-channel and a P-channel
transistor?
3. What are the main types of MOSFETs, with respect to their channel
structure (depletion and enhancement mode)?
4. What‟s meant by the weak and strong inversion of the MOSFET
channel
5. What is the threshold voltage, and what‟s its relation to the physical
parameters of the MOSFET device?
6. What do the linear and saturation modes mean?
In addition, upon completion of this Chapter, the student should:
7. Draw and explain the output I-V characteristics of a MOSFET

8. Be acquainted with the MOSFET circuit models.
9. Apply the appropriate circuit models correctly.
10.Be acquainted with the MOSFET scaling rules and their effects
11.Identify the MOSFET physical limitations
12.Know the phenomena dominate the switching of a MOSFET,
13.Draw and explain the turn-on & turn-off characteristics of a MOS,
14.Interpret manufacturer datasheets and ratings of a MOSFET,
15.Differentiate between different packages of MOSFETs,
16.Know other forms of MOS transistor, such as thin-film transistors
(TFT) and how they operate?
304
7-2. Types of MOSFET’s

In electronic circuits, the metal-oxide-semiconductor (MOS) field effect
transistors (MOSFET‟s) may come in four different types. They may be
enhancement or depletion mode and they may be also classified as N-
channel (NMOS) or P-channel (PMOS), as shown in Fig. 7-1.
MOSFET
Enhancement Depletion
Mode Mode
n-Channel n-Channel
p-Channel p-Channel
Fig. 7-1. Basic types of MOSFET’s
As shown in the above figure, the MOSFET devices are three terminal
devices, with isolated gate (G) and a drain (D) and a source (S), which are
separated with a channel region. The depletion mode MOSFETs have a
deposited or implanted channel of the same type of the drain and source,
while the enhancement MOSFETs have not. In the later case, the channel,
between the source and drain, is created by the action of electric field,
through a gate bias. In all cases, the conductance of the created or
deposited channel is controlled by field effect due the gate bias.
305
7-3. MOSFET Structure

Figure 7-2 depicts the two-dimensional geometry of an-n-channel
MOSFET. Also, figure 7-3 depicts the structure of N-channel and P-
channel enhancement mode MOSFET‟s, their dynamic characteristics
(drain-source current IDS versus gate –source voltage VGS) and their circuit
symbols. Enhancement mode MOSFET doesn‟t conduct current unless a
sufficient gate bias is applied, to form the channel.
Fig. 7-2. Illustration of the geometry of an n-channel MOSFET’s
Fig. 7-3. Enhancement MOSFET structure, symbol and dynamic characteristics
306
You may note in the enhancement MOSFET, a fourth node, called the
substrate (or body) node. This node is normally connected to the lowest
voltage potential of the circuit (usually the source).
Figure 7-4 depicts the structure of N-channel and P-channel depletion

mode MOSFET‟s, their dynamic characteristics (drain-source current IDS
versus gate –source voltage VGS) and their circuit symbols. As shown, the
depletion mode MOSFETs have diffused channels, so that they conduct
even at VGS = 0.
Fig. 7-4. Depletion mode MOSFET structure, symbol and dynamic characteristics
307
7-4. MOSFET I-V Characteristics and Modes of Operation

Fig. 7-5 depicts the static I-V characteristics (IDS versus VDS at various
values of VGS) of an N-channel MOSFET. As shown in figure, MOS
transistors have three modes of operation:
1- Linear (or triode),

2- Saturation (or active) and
3- Cut-off modes.
Note that enhancement mode MOSFET‟s, are normally cut-off. In order

to turn-ON the enhancement MOSFET, the gate-to-source voltage (VGS)
should exceed a threshold voltage, VTN (for the NMOS) or VTP (for the
PMOS).
VTN  VTNO    2 F  VBS  2F  (7-1a)
VTTP  VTPO    2 F  VBS  2F  (7-1b)
Here VTNO and VTNO are the threshold voltage of the N-channel and P-
channel MOSFETs at zero substrate bias (when VBS = 0), respectively.
4.e s N a F
VTNO  VFB  2 F  (7-2a)
Cox
4.e s N d F
VTPO  VFB  2 F  (7-2a)
Cox
Here, and VFB is the flatband voltage, Na and Nd are the substrate doping
concentrations of N-channel and P-channel MOSFETs, respectively.
Also, 2F is the channel surface potential at inversion onset. Note that the
threshold voltage (VTN,P) is the sum of three components; namely:
1- The flatband potential (VFB), which is necessary to overcome the

energy band bending, due to the semiconductor surface states and oxide
charges.
2- The semiconductor surface potential, (s), which is equal to double the
Fermi level potential (s,= 2 F), at the onset of strong inversion, and
3- The underlying depletion region potential, Qd/Cox = √(4esNF)/Cox,
308
Note also that, in the presence of substrate bias (VBS), the gate to source
voltage becomes:
VGS = VGB + VBS (7-3)
Therefore, the threshold voltage is shifted from VTNO to VTN (or VTPO to
VTP ), as indicated from equation (7-1), to take the substrate bias effect.
The parameter, , is called the body effect parameter and given by:
 = (2eNAs)1/2 /Cox (7-4)
Fig. 7-5. Static I-V characteristics of an N-channel MOSFET
7-4.1. Linear (Triode) Mode

In the linear region, of an enhancement n-channel MOS transistor, the
current voltage characteristics are given by:
I DS  K n/ (
W
L
 
). (VGS  VTN ).VDS  12 VDS
2
, VGS -VTN ≥ VDS > 0 (7-5)
where Kn’ = n Cox for n-channel MOSFET and W and L are the gate
width and effective length. Also, n is the channel effective mobility and
Cox is the gate oxide capacitance.
309
Fig. 7-6. Charge distribution of an N-channel MOSFET, in the linear mode
7-4.2. Saturation Mode

In the saturation (active) region, of an enhancement n-channel
MOSFET, the current voltage characteristics are given by:
I DS  12 K n .VGS  VTN  (1  .VDS ) ,

2
VDS ≥VGS -VTN > 0 (7-6)
where Kn = Kn’(W/L) and  is the channel modulation parameter (with

zero default value). Note that for enhancement mode MOSFET‟s VTN is
positive and VTP is negative.
Fig. 7-7. Charge distribution of an N-channel MOSFET, in the saturation mode
310
In contrary, the depletion mode MOSFET‟s are normally ON and their

threshold voltages are reversed in sign with respect to the corresponding
enhancement MOSFET‟s, as shown in Fig. 7-6. Therefore, depletion-
mode MOSFET‟s are often used as active loads (active resistors) in both
analog and digital circuits.
Example 7-1.
Calculate the drain current of a silicon NMOS with VT = 1V, W = 10 m,
L = 1 m and tox = 20 nm. The device is biased with VGS = 3 V and VDS =
5 V. take the surface mobility as 300 cm2/V-s and set VBS = 0 V. Also
calculate the transconductance at VGS = 3 V and VDS = 5 V and compare it
to the output conductance at VGS = 3 V and VDS = 0 V.
Solution
The MOSFET is biased in saturation since VDS > VGS - VT.
Therefore the drain current equals:
The trans-conductance is given by:
The output conductance is given by:
311
Note 7-2. Derivation of the MOSFET I-V Characteristics
1-In the linear region where VGS >VT and 0< VDS < Vdsat
Neglecting the diffusion current, and admitting the current in the y-

direction only, we have the channel current density is given by:
where  is the lateral potential. The drain current is given by:
Integrating along the channel in the y-direction yields:
Now we need a relation between the inversion layer charge and the lateral
potential . Neglect all but the mobile inversion charge. The charge in the
semiconductor is a linear function of position y, such that.
312
2-In the saturation region (for VDS > VDsat) we have
In this case the charge is zero (refer to figure 7-7) such that

Substituting this in the expression of ID yields:
313
7-5. MOSFET Subthreshold Regime

As the power supply voltage VDD is continuously reduced to minimize
energy per operation, MOSFET‟s make the transition from super-
threshold (super-VTH) operation in strong inversion with large gate
overdrives, to near-VTH operation in weak inversion with very small
overdrives, and finally into sub-threshold (sub-VTH) operation.
The sub-threshold operation of a MOSFET differs from the normal super-

threshold operation. In fact, the existence of the inversion layer above
threshold is a basic assumption of the MOSFET analysis. Accordingly,
when no inversion layer exists, no current will flow below threshold.
However, the actual sub-threshold current is not actually zero but reduces
exponentially below the threshold voltage as follows (for NMOS):
W   V  VTN  V 
I on _ SUB  K n/  .(n  1).VT2 . exp  GS .1  exp  DS  (7-7a)
L  n.VT   VT 
where n is the sub-threshold ideality factor :

.
1  eN a 
n 1   (7-7b)
2C ox   F 
The on-current of a MOSFET is defined as IDS, when VGS = VDS = VDD. It

is important to highlight the implicit VTN dependence on L because Ion-sub
becomes very sensitive to L due to the VTN term. VTN is also dependent on
VDS via drain-induced barrier lowering (DIBL).
314
7-6. MOSFET Small Signal Equivalent Circuit Model

The small signal model shown below can be useful for extrapolating and
interpolating the S-parameters as well as for use in circuit simulators that
cannot handle S-parameters directly. The element values are derived by
fitting the calculated S-parameters of the model to measured data. The
bias points and bonding configuration are as described in the individual
device data sheets. The MOSFET parasitic capacitances are bias
dependent, as shown in the following figure.
Fig. 7-8. AC model of a MOSFET at high frequency. The intrinsic MOS model is
shaded, and the external packaging and stray parasitics are indicated in the outside.
Fig. 7-9. Bias dependence of the MOSFET parasitic capacitances.
315
7-7. -MOSFET as an Amplifier

In much the same way as BJT‟s, MOSFET‟s can be mounted in three
configurations, namely:
1- Common gate (C-G) configuration,

2- Common source (C-S) configuration, and
3- Common drain (C-D or source follower ) configuration.
Figure 7-10 depicts the circuit configurations, for an N-channel

MOSFET‟s. Also, figure 7-11 depicts the NMOS small signal equivalent
circuit, in common source configuration.
The AC voltage gain of such a circuit is given by:
Av = Vo / vg= - gm (RL//rd) (7-8)
where gm is the MOSFET transconductance (gm=ds/Vgs) and rd is the

output resistance of the MOSFET (rd =Vds/Ids). For an n-channel
MOSFET in the linear mode rd is defined as follows:
rd = vds / ids = K’(W/L).(VGS - VTN) (7-9)
Fig. 7-10. MOSFET circuit configurations.
Fig. 7-13(a). MOSFET small signal equivalent circuit at low frequency

316
At high frequencies, the parasitic inter-electrode capacitances, between

MOSFET layers, become significant and should be considered in the
small-signal equivalent circuit. The following figure depicts the small
signal model of a MOSFET, at high frequencies. Aside from the low-
frequency lumped elements, we can find gate-drain capacitance Cgd, gate-
source capacitance Cgs. The extra elements include the gate resistance RG
and drain resistance RD and the substrate resistance as well as the
corresponding lead inductances RS. RD and RSUB.
Fig. 7-11(b). AC model of a MOSFET at high frequency. The intrinsic MOS model is
shaded, and the external packaging and stray parasitics are indicated in the outside.
The MOSFET cutoff frequency or the unity current gain frequency (ft) is
defined when the transistor current gain equals one. This frequency is
given by:
ft ≈ gm /2Cg (7-10)
where Cg = Cgs + Cgd.
317
7-8. -MOSFET as a Switch

Figure 7-12 depicts the switching circuit for a p-channel MOSFET as
well as its switching waveforms and times. The maximum switching
frequency fsw is determined by the total of delay and rise time td(ON) + tr for
the turn-ON, and delay and fall time td(OFF) + tf for turn-OFF.
Fig. 7-12. MOSFET switching circuit and waveforms
318
7-9. MOSFET Scaling

The reduction of the MOSFET dimensions has been dramatic during the
last three decades. Starting at a feature length of 10m in 1970‟s and
reached below 0.1m in 2005. Proper scaling of MOSFET however
requires not only a size reduction of the gate length L and width W. It also
requires a reduction of all other dimensions including the oxide thickness.
This also implies scaling of the substrate doping density.
There are two common types for scaling: constant field scaling and
constant voltage scaling. Constant field scaling yields the largest
reduction in the power-delay product of a single transistor. However, it
requires a reduction in the power supply voltage. Constant voltage scaling
provides voltage compatibility with older circuit technologies. The
disadvantage of constant voltage scaling is that the electric field
increases as the minimum feature length is reduced. This leads to
mobility degradation and increased leakage currents.
The following figure depicts the ideal and real scaling parameters of a
MOSFET. The scaling parameters of MOSFET devices are also listed in
Table 7-2. It should be noted that the drain induced barrier lowering
(DIBL) refers to the effect of the drain voltage on the output conductance
and threshold voltage. This effect occurs in MOSFET devices when only
the gate length is reduced without properly scaling the other dimensions.
Fig. 7-13. Illustration of the MOSFET Scaling parameters.
319
Figure 7-14 depicts the effect of scaling down the channel length on the
static I-V characteristics of an N-channel MOSFET. This effect is called
the channel modulation effect and is modeled by adding the channel
modulation parameter ()to the I-V characteristics in the saturation
region, as indicated by equation (7-3).
Fig. 7-14. Effect of channel length modulation on the static I-V characteristics of an
n-channel MOSFET
Table 7-2. MOSFET scaling factors
320
The reduction in device size causes several problems in MOS transistor

design. They may be roughly divided into several groups:
Problems due to an increased electric field strength:

The oxide reliability; Time-dependent dielectric breakdown (TDDB)
is strongly dependent on the oxide thickness, supply voltage and the
technology process (the density distribution and the size of defects).
The reliability problems caused by the hot-carrier effects in silicon:
the avalanche multiplication, the avalanche breakdown and the hot-
carrier injection into the oxide.
The mobility reduction due to the high field at the interface; the
transit time increases and the drain current decreases, causing a
degradation of the driving capabilities of the devices and its speed.
The reliability problems and the leakage current caused by the
tunneling through the gate oxide
Problems due to increased power dissipation.

Increasing resistances of the contacts and the interconnection lines.
The electro-migration in the contacts and the interconnection lines.
The contacts and interconnectors must be low resistance and high
reliable.
The problems related to the distributions of potential and charge:
The drain-induced-barrier-lowering (DIBL) effect; the turn-off
characteristics degrade.
The punch-through effect
The parasitic bipolar-transistor action (between source, bulk and
drain); the breakdown voltage (BVCEO) decreases because the
diffusion length of minority carriers does not scale down
Threshold voltage variations; sensitivity to the process parameters and
the fluctuations in the dopant distribution
Series resistances; There is a strong demand for the low-resistance
shallow junctions.
The polysilicon-gate depletion effect
Statistical variations increase with reduction of dimensions.

Moreover, with lowering supply voltages and reducing threshold
voltages the leakage currents become increasingly important. In
addition, the problems of isolation between adjacent devices and
between the devices and the substrate, as well as the latchup
phenomena in CMOS circuits.
321
7-10. MOSFET Degradation & Hot Carrier Effects

As MOSFET dimensions shrink to submicron and below, the limits of
conventional MOS structures are becoming more pronounced due to
strong short-channel and hot carrier effects, causing a significant
degradation of device performance. The following table depicts the main
mechanisms of hot carrier in MOSFET devices.
Table 7.3. Mechanisms of degradation due to high electric field in MOSFETs.
Mechanism Carrier Energy Effects

(E, eV)
Light Emission E > Eg =1.12eV Leakage current
Impact Ionization 1.3 < E <1.8 eV Latch-up, Snap-back,
Leakage
Hot Electron Injection E >3.2eV Threshold shift due
trapping and trap
Hot-Hole Injection E > 4.8 eV generation
7-10.1. Hot-carrier Injection Currents

Among the various known mechanisms one can cite 4 carrier injection
(over the barrier) mechanisms, which are commonly encountered in
MOSFET devices.
drain avalanche hot carrier injection (DAHCI),

channel hot electron injection (CHEI),
substrate hot electron injection (SHI) and
secondary generated hot electron injection (SGHEI)
The channel hot electron injection (CHEI) occurs when the gate voltage
is high enough and VG ≈VD. Channel carriers which are accelerated by
lateral fields and transported from the source to the drain may be driven
towards the gate oxide before they reach the drain.
The drain avalanche hot carrier injection (DAHCI) occurs when a high
drain voltage is applied in non-saturatation mode (VD>VG) which results
in a high electric field near the drain, and hence accelerating channel
carriers into the drain depletion region. The accelerated channel carriers
collide with Si atoms valence electrons, creating electron-hole pairs by
impact ionization. Some of the generated electron-hole pairs are again
accelerated and may acquire sufficient energy to surmount the Si/SiO2
barrier. The hot carriers that surmount the gate oxide barrier can inject
into the gate oxide where they may be trapped and cause a shift in the
MOSFET threshold voltage.
322
The substrate hot electron injection (SHEI) occurs at high substrate bias,
|VB| >> 0 and strong inversion, usually with both drain and source
grounded. Under this condition, carriers of one type in the substrate are
driven by the substrate field toward the Si-SiO2 interface. Carriers can be
generated by external optical or thermal excitation. As carriers move
toward the substrate-oxide interface, they gain further kinetic energy from
the high field in surface depletion region. They eventually overcome the
surface energy barrier and get injected into the gate oxide, where some of
them are trapped. The secondary generated hot electron injection
(SGHEI) occurs under conditions similar to DAHCI, when VD>VG,
which lead to impact ionization of hot carriers. However, SGHEI
involves secondary carriers that are created by an earlier incident of
impact ionization and driven under the influence of the substrate bias.
This bias produces a field that drives hot carriers toward the surface
region, where they gain more energy to overcome the gate oxide barrier.
The so-called “channel-initiated secondary electron (CHISEL) is a
variant of the SGHEI, which relies on ionization feedback and is
activated by a negative substrate bias VB<0. CHISEL is used as a reliable
programming technology in low-voltage Flash EEPROM devices, with
floating gate lengthes down to 0.2 m. The following figures illustrate the
different tunneling and hot injection mechanisms in MOSFET devices.
DCHEI (VG ≈ ½ VD) CHI (VG ≈ VD)
SHEI (VB >> 0) SGHEI (VB > 0)
Fig. 7-15. Illustration of different hot carrier injection mechanisms in MOSFET Devices.
323
The injection of hot-electrons into the gate-oxide has been usually

modeled by the lucky-electron model, which was initially proposed by
Shockley to model the impact ionization phenomenon. In fact,
measurements of hot carrier emission probability by Ning et al. and
Garrigues and Hillouin showed an exponential behavior, like the lucky
electron model. According to the lucky electron model, the electron
emission probability Pn is equal to the probability that an electron drifts,
under the effect of electric field ζ, a distance greater than d without
collision.
Pn(ζ) = Pno exp [ - d / n ] (7-11)
where d = (B/eζ) is the minimum path an electron should travel to gain

an energy equal to the barrier height and n is the mean value of the
electron free path between collisions. According to Ning‟s measurement,
Pno =2.9 and n=91Å at room temperature.
According to Hu, the probability of emission of a channel electron

through gate is a combination of the probabilities of the following events:
the electron gains sufficient energy from the lateral field to overcome
the interface barrier,
the electron reaches the interface without suffering any collision, and
the electron is not scattered back into the semiconductor in the image-
force potential well.
On the basis of the lucky-electron model, it can be shown that the fraction
of the channel carriers which are injected into the gate oxide is given by:
 B 
I inj  I sub exp    (7-12a)
 en // 
Here ζ// is the effective lateral electric field and B is the effective
potential barrier of the Si/SiO2 interface, which is given by:
 B   Bo  a  ox  b ox2 / 3 (2-12b)
where Bo, a and b are constants, expressing the main barrier height and
lowering effects due to image force and quantum tunneling. The last
lowering term was added by Ning to account for the tunnel injection
current when band bending is lower than the potential barrier.
324
For Si/SiO2 interface, we have: Bo =3.2eV, a=2.59x10-4 e(Vcm)½ and

b=10-5 e(Vcm2)1/3 at 300K. Also, for ζox= 106V/cm, B =3.1eV.
As the substrate current is generated due to impact ionization in the

lateral electric field close to the drain, it is expected to be linearly
proportional to the drain current. Therefore, it can be shown that the
substrate current is given by:
Ld
I sub  I ds   n dy (7-13)
0
where Ids is the drain current, Ld is the length of the pinch-off region and
n is the electron impact ionization coefficient in the velocity-saturated
part of channel.
Fig. 7-16. Hot carrier injection and gate currents.
7-10.2. Gate Tunneling Currents

In addition to the above indicated hot-carrier effects, one can add the
gate-tunneling leakage current, as one of the degradation effects in small
MOSFET devices. There exist a variety of tunneling processes that can be
identified in semiconductor-insulator structures in general and MOS
devices in particular. When we consider the shape of the energy barrier of
such structures, we can distinguish the Fowler-Nordheim (FN) tunneling
and the direct tunneling.
325
Fig. 7-17. Schematic of the tunneling current in a MOSFET device
The direct tunneling can take place at low gate voltages via thin oxides
layers (less than 50Å) and has a weak dependence on the gate field. The
FN tunneling is a field-assisted mechanism which is strongly dependent
on the gate field and dominates in modern MOS structures. The gate
tunneling current density may be given by the following formula:

(7-14)
J G   g c ( E n ).u n f n ( E n ).T ( E n ).dE n
0
where T(En) is the tunneling probability, gc(En) is the density of states in

the conduction band, un┴ is the electron group velocity perpendicular to
the semiconductor surface (un┴ ≈ ¼ un). The integration in the above
equation starts from the semiconductor conduction band edge, as a
reference.
For trapezoidal barrier of upper height B and lower hight (o B - eVox),
where Vox is the potential voltage across the insulator gate, the tunneling
probability is usually expressed using the WKB approximation as
follows:
 4 2mox 
T ( En )  exp  B  En 3 / 2  (7-15a)
 3e ox 
326
In the upper triangular part of the barrier, where B > En > o and
 4 2mox
T ( En )  exp  
.  B  En    B  En  eVox 
3/ 2 3/ 2
 (7-15b)
 3e ox 
in the lower rectangular part of the barrier where En < o. Here ζox and mox
are the electric field and effective mass of electrons at the insulator (for
SiO2, mox =0.42m0).
Fig. 7-18. Tunneling coefficient across gate dielectric barrier (of thickness tox) in a
MOS structure as a function of electron energy
In the case of the field-assisted Fowler-Nordheim mechanism, we

consider the triangular part of the barrier. Assuming the energy
distribution function as Maxwellian and the energy bands as parabolic,
we get the following field-dependent gate current density:
JG = J0 .ζox2 exp [ζ0 / ζox] (7-16a)
327
where the Jo and ζ0 are constants, related to the energy barrier height B
between the insulator and the injecting conductor as follows:
4 2mox
o  . B 
3/ 2
(7-16b)
3e
e2
Jo  . (7-16c)
16 2 ( mox / mo )..B
328
7-11. Advanced MOSFET Structures

The explosion of digital technologies has pushed the advancement of
MOSFET technologies faster than any other Si transistor. This has
happened due to the MOSFET being the prime building block of CMOS
digital logic circuits.
The MOSFET has become increasingly smaller in the last two decades,
today's MOSFETS used in ICs have a channel length of less than 100nm.
MOSFETs which are smaller have two main advantages. The first is that
smaller MOSFETs allow more current to pass since conceptually a
MOSFET acts a variable resistor in the on state and a shorter resistor
corresponds to less resistance and energy dissipated. Secondly, the gates
are smaller which means the capacitance is lower, decreasing the amount
of time in which it takes the capacitor to charge, thus increasing switching
time and increasing processing power. Lastly, smaller MOSFETs result
in more transistors per chip, thus either increasing the processing power
per chip or reducing the cost per chip. Recently, the small size of
MOSFETs has created operational problems as producing such tiny
transistors is an enormous challenge, often limited by advances in
semiconductor device fabrication. Also due the small size, the amount of
voltage that can be applied has to be reduced to keep the device stable.
Due to these reduced threshold voltages, when the transistor is turned off
it will still conduct a small amount of current. This is due to a weak
inversion layer which consumes power when the transistor is off, called
the sub threshold leakage. Previously this was a non-issue with larger
transistors, however in the smaller devices of today, the sub threshold
leakage can result in 50% of the total power consumption of the
transistor. Therefore, the extrapolation of the current designs for high
frequency MOSFETs is necessary to process information at higher
speeds. An alternative approach has been to attempt to find new devices.
In fact, an extensive research has been devoted for the fabrication of new
classes of MOSFET devices, which are capable of scrapping new
horizons of applications. In the following subsections, we present the
main developments, which have been carried out to improve the
performance of MOSFET devices or to introduce new MOS devices, with
new concepts.
7-11.1. CMOS Technology

Complementary Metal-Oxide-Silicon (CMOS) circuits make use of both
nMOS and pMOS transistors on the same substrate. Therefore, an n-type
well is provided in the p-type substrate. This structure dissipates minimal
power, only during switching times.
329
The gate oxide, poly-silicon gate and source-drain contact metal are
typically shared between the pMOS and nMOS technology, while the
source-drain implants must be done separately. The following figure
depicts a CMOS inverter and its layout diagram.
Fig. 7-19. Schematic of a CMOS inverter
CMOS circuits are advantageous because they allow virtually no current

to input through and thus consume very little power. This is done by
wiring every PMOSFET with a NMOSFET in a way such that whenever
one is conducting, the other is not. This not only conserves energy but
also helps to reduce heat dissipation which otherwise would cause the
circuit to fail.
7-11.2. Poly-Silicon Gate Technology

An early improvement of the MOS technology was obtained by using a
poly-silicon gate (instead of metal gate), yielding a self-aligned structure
which is both compact and better performance. In fact the Si/SiO2
interface has fewer defects and lower workfunction than M-S contact. In
addition, the poly-silicon gate is used as a mask during the implantation
so that the source and drain regions are self-aligned with respect to the
gate. This self-alignment structure reduces the device size. It also
eliminates the large overlap capacitance between gate and drain, while
maintaining a continuous inversion layer between source and drain. A
further improvement of this technique is the use of a low-doped drain
(LDD) structure, as shown in the following figure. Here a first shallow
implant is used to contact the inversion layer underneath the gate. The
shallow implant causes only a small overlap between the gate and
source/drain regions. After adding a sidewall to the gate a second deep
implant is added to the first one. This deep implant has a low sheet
resistance and adds a minimal series resistance.
330
Fig. 7-20. Schematic of self-aligned poly-silicon gate transistor with local oxidation
isolation (LOCOS) isolation
The combination of the two implants therefore yields a minimal overlap

capacitance and low access resistance. The use of a poly-Si gate has the
disadvantage of increasing the sheet resistance of the gate. This leads to
high delay time of long poly-Si lines. This delay can be reduced by using
silicides (like WSi, TaSi) on top of poly-Si.
Fig. 7-21. Schematic illustration of a recent 90nm MOSFET structure, showing the
n+ source/drain extensions (SDE) and p+ pockets (or halo extensions).
331
The so-called deep-submicron MOS (DSM) devices have channel lengths

smaller than 0.1 m. Such MOSFET‟s can operate at low voltage with
high performance, in terms of gain and maximum frequency. Figure 7-21
depicts a 0.09m N-channel MOSFET (L=90 nm) in bulk silicon with
super steep retrograde (SSR) channel doping, source/drain extension
(SDE) and highly-controlled pockets or halo extension. The later
additions help to suppress the short channel effects. The thin salicide
(self-aligned silicide) layers such as TiSi or CoSi2, are usually deposited
beneath the thin oxide, to prevent spiking into shallow junctions during
metallization of contacts.
7-11.3. Silicon on Insulator (SOI) and SiGe on Insulator (SiGeOI)

The conventional MOSFET structures, such as bulk MOS transistors, are
approaching fundamental physical limits. Further increase in speed of
integrated circuits is obtained by introducing the so-called silicon-on-
insulator (SOI) technology. In SOI technology, all processes are worked
on 1m thick mono-crystalline silicon layer, which is deposited on
insulated substrate. Alternatively, the silicon-on-oxide (SOX) technology
consists in implementing CMOS processes on buried oxide, as shown in
figure 7-20. A buried oxide layer is formed in a bulk Si substrate by high-
dose oxygen implantation and high-temperature annealing.
Fig. 7-22. Schematic of SOI and SiGe on insulator MOSFET’s
Actually, SOI MOSFETs are some sort of quantum devices, because

electrons are quantized into 2-dimensional electron gas (2DEG) by the
gate electric field applied perpendicular to the Si/SiO2 interface. Figure
7-21 depicts the I-V characteristics of an SOI-NMOS at VGS =1V.
332
As shown in figure 7-23, the so-called floating body effect lead to a

pronounced kink in the I-V characteristics, as follows. At the onset of
impact ionization, electron-hole pairs are created. The holes accumulate
in the body and raise the effective body potential and the drain current
increases.
Fig. 7-23. The I-V characteristics of an SOI MOSFET (at VGS=1V), showing, the kink
effect. Note that this effect is tightly related to the impact ionization mechanism.
The following figure shows the cross section of single and dual-gate SOI
transistors, where tof , tsi, and tob represent front-gate oxide, silicon film,
and back-gate oxide thickness, respectively. tof is usually taken as the
minimum oxide thickness for high performance. tob is usually larger than
tof . When the silicon film is thicker than the maximum gate depletion
width, SOI exhibits a floating body effect and is regarded as a partially-
depleted SOI MOSFET. If the silicon film is thin enough such that the
entire film is depleted before the threshold condition is reached, the SOI
device is referred as a fully-depleted SOI MOSFET.
Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next

generation VLSI circuits. The following Table shows the roadmap of
DG-SOI MOS and its parameters
333
Fig. 7-24. Single-gate and double-gate SOI MOSFETs
Table 7-4. Roadmap of MOSFET transistors
Year 2005 2008 2011 2014

(Technology Node) (100nm) (70nm) (50nm) (35nm)
Gate Length (L), 65nm 45nm 32nm 22nm

Gate-oxide thickness (tox), 1.5nm 1.2nm 0.8nm 0.6nm
Channel Doping (Na), cm-3 6x1018 9x1018 1.5x1019 2.5x1019
Supply Voltage (VDD), 1.2V 0.9V 0.6V 0.6V
Performance (fT), 2 GHz 2.5GHz 3GHz 3.6GHz
The strained Si and SiGe technologies have been used recently in CMOS
fabrication to substantially improve performance. In fact, the strained Si
technology has gained an industrial interest due to its better transport
properties and compatibility with CMOS processes.
7-11.4. Multi-Gate and 3-D MOSFET Structures

With the availability of DSM devices, the miniaturization of silicon
further progresses into the nanometer range. Considerable interest has
focused on MOSFET device structures in which current channels are
fabricated on a 3D substrate, as shown below in figure 7-25.
The multi-gate MOS reduce spread of Vd, gives lower threshold voltage,
enables lower channel doping and lower effective field (and hence better
channel mobility), which all give higher speed The following figure
shows the electrostatic potential contours in a dual gate MOSFET.
334
Fig. 7-25. Multi-gate MOSFET’s. (a) planar dual-gate MOS, (b) vertical transverse
channel MOS and (c) vertical longitudinal channel MOS (fin-type MOSFET)
Fig. 7-26. electrostatic potential contours in a dual gate MOSFET

335
In addition to multi-gate planar FET, the future trends in MOSFET

technology include the following points:
 Advanced Channel Materials (such as Ge, SiGe and III-V materials),

 Tunnel Transistors
As shown in the following figure, the FinFET is actually a double gate

device, one of a number of geometries being introduced to mitigate the
effects of short channels and reduce drain-induced barrier lowering.
Fig. 7-27. Schematic of a FinFET (double-gate MOSFET).
7-11.5. Thin-Flm Transistors (TFT)

The thin film transistor (TFT), is a MOSFET device that is used as a
switch for each pixel in the active matrix LCDs technology. The TFTs are
fabricated in a thin film of amorphous or polycrystalline Si material that
is deposited on a glass substrate. The figure 7-30 depicts the
technological steps for fabrication TFT‟s.
Fig. 7-28(a). Schematic simple gate, dual-gate N-channel TFT
336
Fig. 7-28(b). Schematic of a CMOS TFT
7-11.6. Active-Matrix LCD

The active matrix LCD‟s is one of the most interesting types of flat panel
displays, nowadays. A TFT liquid crystal display is a device controlled
by electric signals. The liquid crystal sits between two transparent layers
of conductive Indium-tin-oxide (ITO) electrodes. Liquid crystal
molecules are aligned in different directions by varying the voltage
applied to the ITO electrodes. The direction of the LCD molecules
directly affects the penetration level of the light source, which in turn
creates the desired light and darkness in the image. Color is produced by
the color filter substrate.
Fig. 7-29. TFT array and display structure
As we have pointed out earlier, the TFTs are fabricated in a thin film of
amorphous or polycrystalline semiconductor material that is deposited on
a glass substrate. The first thin film semiconductor material that was
investigated for AM-LCD‟s was polycrystalline CdSe.
337
Amorphous silicon was proposed in the late seventies and proved to

combine the advantages of both polycrystalline CdSe and amorphous
silicon films.
Fig. 7-30. Thin film transistor technology.
338
Fig. 7-31. LCD with TFT
339
7-12. MOSFET Testing

While checking MOSFET, the resistance measured between gate and
drain should be infinitely high in either polarity. Low resistance means
faulty device. A rather simple MOSFET tester is shown in figure 7-32(b),
below. As shown in figure, the if the N-MOS under test is good, then the
orange Led should glow.
Fig. 7-32(a). Simple MOSFET testing circuits
Fig. 7-32(b). MOSFET tester circuit

340

To examine the parameters of MOSFETs, it is useful to have a sample
datasheet in hand. The SPICE model of a MOSFET includes a variety of
parasitic circuit elements and some process related parameters in addition
to the elements previously discussed in this chapter. The syntax of a
MOSFET incorporates the parameters a circuit designer can control:
MOSFET syntax
M <name> <drain node> <gate node> <source node> <substrate node>
+ [L=][W=][AD=][AS=]
+ [PD=][PS=][NRD=][NRS=]
+ [NRG=][NRB=]
where L is the gate length, W the gate width, AD the drain area, AS the
source area. PD is the drain perimeter, PS is the source perimeter
Example:
M1 3 2 1 0 NMOS L=1u W=6u
.MODEL NFET NMOS (LEVEL=2 L=1u W=1u VTO=-1.44 KP=8.64E-
6 NSUB=1E17 TOX=20n)
where M1 is one specific transistor in the circuit, while the transistor

model "NFET" uses the built-in model NFET to specify the process and
technology related parameters of the MOSFET. A list of selected SPICE
parameters is provided in the table below.
Table 7.3: SPICE parameters and corresponding equations
341
7-14. Summary
The Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) may

be divided into two major types.
1- Enhancement Mode MOSFET. It is called enhancement because

conduction occurs only after the channel conductance is improved” or
enhanced.
2- Depletion Mode MOSFET. The channel is pre-fabricated, during the
device fabrication.
Both enhancement mode and depletion mode MOSFETs may be n-

channel or p-channel. The following figure depicts the circuit symbols of
all MOSFET types.
Structure of an N-channel enhancement MOSFET
342
The MOSFET I-V characteristics have 3 distinct regions of operation,

namely:
1- Cutoff mode,
2- Linear region and
3- Saturation region.
The trans-conductance (gm) of an enhancement MOSFET in the linear

region is given by:
The output conductance (gd) of an enhancement MOSFET in the linear

region is given by:
343
The following table summarizes the main parameters and modes of

operation of the enhancement MOSFETs.
The small signal model of the MOSFET is as simple as follows:
344
7-15. Problems
7-1) The MOSFET has which of the following advantages over the
JFET?
1. Less bias
2. Higher input impedance
3. Higher output impedance
4. All of the above
7-2) The MOSFET is normally constructed so that it operates in either the

depletion mode or the enhancement mode. The depletion mode MOSFET
(a) uses what type of bias and (b) has what type of doped channel to cause
a depletion of current carriers in the channel?
1. (a) Reverse (b) lightly-doped
2. (a) Forward (b) lightly-doped
3. (a) Reverse (b) heavily-doped
4. (a) Forward (b) heavily-doped
7-3) The enhancement mode MOSFET (a) uses what type of bias and (b)
has what type of doped channel to enhance the current carriers in the
channel?
1. (a) Reverse (b) lightly-doped
2. (a) Forward (b) lightly-doped
3. (a) Reverse (b) heavily-doped
4. (a) Forward (b) heavily-doped
7-4) Consider the following I-V characteristic for an N-channel MOSFET

with W = L = 100μm , measured at VGS = 2V and VDS = VGS :
345
The following figure shows MOS capacitors fabricated on the same

substrate as the N-MOSFETs, with the same N+ polysilicon gate material,
gate oxide thickness, and substrate doping, and an area A= 2100 μm ×
100 μm, with the following C-V characteristic:
(a) Find the oxide capacitance per unit area, Cox , and the threshold
voltage, VTN , for the N-MOSFET
(b) Derive an expression for the electron mobility, μn , in the MOSFET
channel, in terms of the slope, gd , and the other parameters given above.
(c) Sketch ID versus VDS, for VGS = 2V, VBS = 0V, for the N-MOSFET.
Label the values of the saturation voltage, VDsat, and current, IDsat. Indicate
the regimes of operation.
(d) Calculate the electron velocity at the source end of channel, vy (y = 0)
and at the drain end of the channel, vy (y = L), for VGS = 2V, VDS = 0.5V,
and VBS = 0V .
(e) The value of VBS is now changed to −3V. Calculate the new values for
VDS sat and IDsat for VGS = 2V and VBS =−3V , assuming that the
substrate doping is N= 1017 cm−3 .
7-5) A silicon MOSFET (nI = 1010 cm-3, s/e0 = 11.9 and ox/0 = 3.9) is
scaled by reducing all dimensions by a factor of 2 and by increasing the
doping density of the substrate by a factor of 4. Calculate the ratio of the
following parameters of the scaled device relative to that of the original
device:
a. The transconductance gm at VGS - VT = 1V.
b. The gate capacitance
c. The threshold shift when increasing the reverse bias VBS of the source-
bulk diode from 1V to 3V.
d. The breakdown voltage of the oxide.
346
7-6) Consider the MOSFET circuit shown in figure below. The MOSFET
has VTN = 1V and Kn = 25 A/V2. Calculate the quiescent point (IDS,
VDS) and the trans-conductance (gm) of the MOSFET. Take the
modulation parameter  = 1V-1.
7-7) Calculate the AC voltage gain of the following MOSFET circuit.

The AC output is taken from drain to ground (across R3). Repeat for the
case when a source resistance of 1k is inserted in the same circuit.
Hint: Draw the AC equivalent circuit. Replace the MOS with the
appropriate small signal model and then calculate Av = (vds/vgs).
7-8) If the substrate of the MOSFET shown in problem 7-6 is connected

to a 5V reverse bias (instead of being grounded), what would be the effect
on the voltage gain?
7-9) Laboratory Assignment

In this practical assignment, you will characterize the current-voltage
characteristics of an N-channel MOSFET. In order to do this, you may
use the virtual laboratory WebLab, from MIT Microelectronics. The
WebLab server is available at http://ilab.mit.edu/. The N-channel
MOSFETs is labeled “nMOSFET” (2N7000). This exercise involves
three phases: (i) characterization of the devices, large and small signal
parameter extraction, (ii) using the measurements to choose bias voltages
for a common collector amplifier to meet amplifier specifications, and
(iii) using the measurements to determine small signal model parameters.
When you are done with good results, download the data to your PC for
more analysis. Write a report which describes what the measured data
should look like and gives a short overview of the relevant equations.
347
Photocopy the following page, read the assessment carefully and answer
on the page. Carry out the required measurements, and comment if there
exist a discrepancy between the measured and calculated values. Don't
forget to write your name and ID.
348
7-17. References:

Inc., 1st edition, 1985.
[2] Jacob Millman, Christos C. Halkis, “Integrated Electronics, Analog

and Digital circuit and systems”, Tata McGrow-Hill publishing Company
Limited, New Delhi, 1991.
[3] M. Bohr, “MOS Transistor: Scaling and Performance Trend”,

Semiconductor International, pp.75-78, June, 1995.
[4] Y. Taur and T. H, Ning, “Fundamentals of Modern VLSI Devices”,

Cambridge University Press, 1998.
[5] S. M. Sze, Semiconductor Devices. Physics and Technology. J.


Oxford, 2004.
[7] Semiconductor Industry Association, “International Technology

Roadmap for Semiconductors”, ITRS 2009, 2010.
349
350
Semiconductor Power
Devices
Contents:
8-1. Overview and Learning Objectives

8-2. Bipolar Power Devices
8-2.1. Power PIN
i. PIN operation & I-V Characteristics
ii. PIN Switching Characteristics
8-2.2. Power BJT
i. Safe Operating Area (SOA)
ii. Emitter Current Crowding
iii. Kirk Effect
iv. Switching Times & Switching losses
v. Packaging
8-2.3. Power Darlington Transistors
8-2.4. Thyristors
i- Thyristor Structure & Operation
ii- Thyristor I-V Characteristics
iii- Thyristor Fabrication Techniques
iv- Thyristor Packaging
v- Thyristor Testing
vi- Thyristor Application Circuits
vii- Other Thyristor Devices
8-2.5. Diac and Triac
8-2.6. GTO
i- GTO Basics
ii- GTO Structure
iii- GTO Operation
351

iv- GTO Switching Circuits

v- GTO Safe Operating
82.7. Integrated-Gate Thyristor (IGT)
8-3. MOSFET Power Devices
8-3.1. DMOS
8-3.2. LDMOS
8-3.3. VMOS and UMOS
8-3.4. MCT
8-3.5. IGBT
i. IGBT Structures
ii. IGBT Operation
iii. IGBT I-V Characteristics
iv. IGBT Circuit Models
v. IGBT Switching Characteristics
vi. IGBT Ratings
8-4. Switching Performance of Power Devices
8-5. Protection of Power Devices
8-6. Packaging & Thermal Considerations
8-7. Applications of Power Devices
8-7.1. Rectification (AC-DC Conversion)
8-7.2. Inverters (DC-AC Conversion)
8-7.3. Converters (DC-DC Conversion)
8-7.4. Cycloconverters (AC-AC Conversion)
8-8. Comparison of Power Devices & Vacuum Tubes
8-9. Summary
8-10. Problems
8-11. References
352

Semiconductor Power
Devices
8-1. Overview and Learning Objectives
Power semiconductor devices are the heart of power electronic circuits.
They have widespread applications in three major consumer markets:
automotive, entertainment (locomotive) and in power supplies and
regulators of household appliance. Engineers working in power
electronics need a basic knowledge of power devices, their operation,
capabilities and limitations. In this chapter, we summarize the operation
concepts and limitations of the major power semiconductor devices.
On completion of this Chapter, the student will be able to
1. Distinguish between, cut off, active, and saturation region operation

of a power device.
2. Draw the input and output characteristics of a power device and

explain their nature.
3. List the salient constructional features of a power device and

explain their importance.
4. Draw the output characteristics of a power device and explain the

applicable operating limits under Forward and Reverse bias
conditions.
Know the phenomena dominate the switching of power devices,
Draw and explain the turn-on & turn-off characteristics of power

devices,
Interpret manufacturer datasheets and ratings of a power device,
Differentiate between different packages of power device,
Know how to design and make use of power semiconductor devices in

basic applications of power electronics (e.g., rectifiers, inverters, and
converters).
353

As shown in the following figure, the power semiconductor devices can

be divided into two main categories based on number of terminals: two-
terminal devices and three-terminal devices.
Fig. 8-1(a). Basic types of semiconductor power devices
Power devices can be also classified into bipolar-based devices (like

power BJT and thyristors), and MOSFET-based devices (like Power
MOSFET and DMOS). In addition, there exist a category of power
devices which combines a bipolar transistor with a MOSFET (like
IGBT). However, the bipolar power devices are the traditional power
devices because of their capability to provide high currents and high
blocking voltages. In this chapter, we present the fundamentals of these
devices, with emphasis on their power ratings (breakdown voltage
maximum current, safe operating area, etc) and switching characteristics.
354

8-2. Bipolar Power Devices

The bipolar-based power devices include power diodes, power bipolar
transistors, Darlington transistors, thyristors, which are also called
silicon-controlled rectifiers (SRC) and triacs, a complementary thyristor
structure suitable to control AC power.
These power devices, however, are required to carry up to several Kilo

Amperes of current under forward bias condition and block up to several
Kilo Volts under reverse biased condition. These extreme requirements
call for important structural changes in power devices, which
significantly affect their operating characteristics.
Fig. 8-1(b). Trends of power Devices
8-2.1. Power PIN Diode

The PIN diode is the same as a PN diode but with the addition of an
intrinsic layer between the P- and the N-layers. As we have seen so far in
Chapter 2, of this book, this intrinsic layer provides a high breakdown
voltage capability of the device. The power versions of the PN junction
diode have broad applicability in power electronics. Besides the usual
breakdown voltage and high current capabilities, the other main
consideration in selecting a PIN diode is their switching characteristics in
general and their reverse recovery time in particular. Therefore, we
content ourselves in this section to discuss these parameters, which are
specific for the power version of PIN diodes.
355

i. Power PIN Structure

The following figure shows the structure of PIN diode, which may be
made of silicon or silicon carbide (SiC). The P-N junction is formed by
defusing a heavily doped P+ region into an epitaxial N-layer, which is
deposited on a heavily-doped N+substrate.. This P-type region acts as the
anode and the N+ as cathode. Impurity atom densities in the heavily
doped cathode and anode are approximately of the same order of
magnitude (1019) while that of the epitaxial layer (also called the drift
region) is lower by several orders of magnitude (10 14). This drift region
withstands the depletion region in reverse bias and is flooded with
carriers in high forward bias.
Fig. 8-2(a). Structure of a power PIN diode and one of its packages.
The PIN diode is usually fabricated with silicon technology. However,

recent successful devices have been fabricated from SiC. The SiC is an
IV–IV semiconductor and possesses many outstanding properties, such as
wide bandgap, high breakdown electric field strength (approximately one
order of magnitude higher than Si), high thermal conductivity, high
saturation drift velocity, high thermal stability. These properties are
attractive for high-power, high-frequency, and high-temperature
applications. In fact, the SiC has a high electric field strength, so that the
layer thickness of the active region of SiC power devices can be made
thinner (by a factor of 10) than that of Si devices with a similar
breakdown voltage. In addition, the doping level in the SiC layer can be
made higher, by two orders of magnitude than that in Si.
356

Owing to the thinner base and higher doping level, a greatly reduced on-
resistance (by two orders of magnitude) can be realized to SiC compared
to Si devices.
ii. PIN Operation & I-V Characteristics

In the following analysis, we assume a one-dimensional PIN structure,
with homogenous doping in its three regions and abrupt junctions. We
adopt the regional approach and assume constant transport parameters
(carrier mobility, diffusion constant, and lifetime), in each quasi-neutral
regions. In steady state, the voltage across the PIN diode is the sum of the
junction voltage plus the i-region drop.
VAK = VP + VM + VN (8-1)
Fig. 8-2(b). Doping profile of a power PIN diode.
The voltage drop across junctions and the forward current can be obtained
by solving the continuity equation inside the drift region, where excess
carriers defuse and recombine. As we'll see in the next paragraph, the
spatial distribution of excess carrier concentrations (n and p) in the drift
region is almost flat and several orders of magnitude higher than the
thermal equilibrium carrier density of this region..
A. PIN in Forward Bias

If we neglect recombination currents, the continuity equation in the drift
region can be reduced to the following diffusion equation:
357

(8-2a)
where Da = Dp Dn /(Dp+Dn ) is the ambipolar diffusion constant and La=

√(Dah) is the ambipolar diffusion length of charge carriers (electrons and
holes) and is their lifetime at high level injection.
The solution of this equation has the form:
(8-2b)
After applying the boundary conditions of current continuity at both the

PIN junctions, we can find the constants C1 and C22, such that the
electron and hole concentrations become:
(8-2c)
with
(8-2d)
The following figure depicts the carrier concentration in the quasi-neutral

regions of the PIN diode.
Note that if the width of the drift region is less than the diffusion length
of carries, the spatial distribution of excess carrier density in the drift
region will be fairly flat and several orders of magnitude higher than the
thermal equilibrium carrier density of this region.
358

Fig. 8-3(a). Distribution of charge carriers in a power PIN diode, in forward bias.
The voltage drop components (Vn, Vp and Vm) can be found from the
charge carrier and electric field distributions, as follows:
(8-3a)
(8-3b)
After substituting the boundary values n(±d), we get:
(8-3c)
As for the i-region drop, it can be found from the electric field, as
follows:
359

(8-4a)
After substitution, we get:
(8-4b)
The total current (J) can be also calculated from the carrier distribution
(from the drift and diffusion components) as follows:
(8-5a)
with
(8-5b)
The next figure (8-4) depicts the forward I-V characteristics of the PIN
diode. The effect of recombination and carrier scattering on the carrier
distribution is depicted on the same figure. The following figure shows
the forward I-V characteristics of a real silicon PIN diode at 25C.
360

Fig. 8-3(b). Forward I-V characteristics of a PIN diode, according to the above
analysis and taking the recombination and scattering effects into account.
Fig. 8-3(c). Forward I-V characteristics of a PIN diode.

361

B. PIN Operation in Reverse Bias

The applied reverse voltage is supported by the depletion layer formed at
the P-N metallurgical junction. The depletion layer spans the entire drift
region and is in contact with the cathode. However, due to very large
doping density of the cathode, penetration of drift region inside cathode is
negligible. Electric field strength inside the drift region of both these type
of diodes at break down voltage is shown in figure 8-3. The DC blocking
voltage (VB) is the maximum direct voltage that can be applied in the
reverse direction across the device for indefinite period of time. Under
reverse bias condition only a small leakage current (less than 100mA for
a rated forward current in excess of 1kA) flows in the reverse direction.
Fig. 8-4. Electric field distribution across a power PIN diode.
Remember that the critical electric field for breakdown (C) in Si is given
by:
C (Si) = 4010 ND1.8
From the geometry of the depletion region, the corresponding punch-

through breakdown voltage for the drift region is then:
VB = C WD - ½ eNDWD2/s
362

Fig. 8-5. Variation of the reverse current a PIN diode with ambient temperature,
at 25V reverse bias..
ii. PIN Switching Characteristics

Power Diodes take finite time to make transition from reverse bias to
forward bias condition (switch ON) and vice versa (switch OFF).
Behavior of the diode current and voltage during these switching periods
are important due to the following reasons.
Severe overvoltage /overcurrent may happen during diode switching.
Voltage and current exist simultaneously during switching operation

of a diode. Therefore, every switching of the diode is associated with
energy losses. At high switching frequencies this may contribute
significantly to diode heating and eventual damage.
363

(a) (b)
Fig. 8-6. Switching characteristics of a PIN diode. Both turn-on (Left) and Turn-off
(right) voltages and current waveforms are shown..
PIN diodes are often used in circuits with di/dt limiting inductors. The
rate of rise of the forward current through the diode during turn-on has
significant effect on the forward voltage drop characteristics. A typical
turn-on transient is shown in figure 8-5(a). This is a typical turn-on
behavior of a power diode assuming controlled rate of decrease of the
forward current. It is observed that the forward diode voltage during turn-
on may reach a high value (Vfr) compared to the steady slate value. In
some power converter circuits, where a freewheeling diode is used across
an asymmetrical blocking power switch this transient over voltage may
be high enough to destroy the main power device. The so-called forward
recovery voltage (Vfr) is given as a function of the forward di/dt in the
manufacturer’s data sheet. Typical values lie within the range of 10-30V.
Forward recovery time (tfr) is typically within 10us. Figure 8-5(b) shows
a typical turn-off behavior of a power diode assuming controlled rate of
decrease of the forward current
As shown in the above figure, the switching characteristics of the PIN

diode have the following features:
 The diode current does not stop at zero, instead it grows in the
negative direction to a peak reverse recovery current (Irr), which can
be comparable to IF.
364

 In many power electronic circuits, this reverse current flows through

the main power switch in addition to the load current. Therefore, this
reverse recovery current has to be taken into account when selecting
the switching device.
 Voltage drop across the diode does not change appreciably from its
steady state value till the diode current reaches reverse recovery level.
In many power electric circuits this may create an effective short
circuit across the supply. Also in high frequency switching circuits
(like SMPS), if the time period td is comparable to switching cycle
qualitative modification to the circuit behavior is possible.
 Towards the end of the reverse recovery period if the reverse current
falls too sharply, stray circuit inductance may cause dangerous over
voltage (Vrr) across the device. It may be required to protect the diode
using a snubber RC network.
During the period ts large current and voltage exist simultaneously in the
device. At high switching frequency this may result in considerable
increase in the total power loss.
Important parameters defining the turn off characteristics are, peak

reverse recovery current (Irr), reverse recovery time (trr), reverse recovery
charge (Qrr) and the dI/dt rate. The dI/dt rate (sometimes, called the
snappiness factor S) depends mainly on the structure of the diode (drift
region width, doping lever, carrier lifetime). Other parameters are
interrelated and also depend on S. Manufacturers usually specify these
parameters as functions of dIF/dt for different values of IF. Both Irr and
Qrr increases with IF and dIF/dt while trr increases with IF and decreases
with dIF/dt.
365

8-2.2. Power BJT

High power bipolar transistors are conceptually similar to usual bipolar
transistors, we presented in chapter 3. The main difference is that the
active area of the device is higher, resulting in a much higher current
handling capability. The following figure shows some of the famous
packages of power BJT's. Power BJTs also have a thick and low-doped
collector region with extremely low doping, down to 1013 cm-3, to obtain
blocking voltages as large as 10kV. As a result, one finds that the
structure needs to be redesigned to manage the power losses and to avoid
the current crowding and Kirk effects.
Fig. 8-7. Photographs of some packages of power BJT's
i. Safe Operating Area of a Power BJT

The following figure shows the typical output characteristics (IC versus
VCE) of an NPN power BJT. A power BJT exhibits Cutoff, Active and
Saturation regions in its output characteristics similar to a small-signal
BJT. In fact output characteristics of a Power BJT in the Cutoff and
Active regions are qualitatively identical to a signal level transistor. In the
cut off region (IB ≤ 0) the collector current is almost zero.
The maximum voltage between collector and emitter under this condition
is termed maximum forward blocking voltage with open base (IB =0) and
is denoted by VCEO. For all practical purpose this is the maximum voltage
that can be applied in the forward direction across a power transistor. This
blocking voltage can however be increased to a value VCBO by keeping
the emitter terminal open. In this case IB<0. In the active region the
current gain (β) remains fairly constant up to certain value of the collector
current (called the Webster current), after which it falls off rapidly.
Manufacturers usually provide a graph showing the variation of β as a
function of the collector current for different temperatures.
366

Fig. 8-8. Output characteristics and safe-operating area (SOA) of a power BJT.
This graph is useful for designing the base drive of a power BJT.
Typically, the value of the DC current gain of a power BJT is much
smaller compared to their small signal counterpart. At higher levels of
collector currents the allowable active region is further restricted by a
potential failure mode called the second breakdown voltage. It appears
on the output characteristics of the BJT as a drop in the VCE at large
collector currents.
The collector voltage drop is often accompanied by significant rise in the

collector current and a substantial increase in the power dissipation. This
dissipation is not uniformly spread over the entire volume of the device
but is concentrated in localized regions. This localized heating is a
combined effect of the non-uniformity of the collector current density
across the device, which leads to the formation of current filaments by a
positive feedback mechanism. Once current filaments are formed, the
thermal runaway quickly takes the junction temperature beyond the safe
limit and the device is destroyed.
367

ii. Emitter Current Crowding

The current crowding is a typical problem in large area devices. It can be
avoided by using inter-digitized base structure, as shown in the following
figure, to uniformly (almost) distribute the base current. In fact, the large
area BJT can have a very non-uniform current distribution due to the
resistance of the base layer. Since the base current is applied through the
thin base layer, there can be a significant series resistance. This resistance
causes a voltage variation across the base region. This voltage variation in
turn causes a variation of the emitter current density. This effect is
minimal in the center of the emitter-base diode and strongly increases
toward the edges. In extreme cases, this effect causes the emitter current
to crowd at the very edges of the emitter-base diode. The parameters
involved in this phenomenon include the sheet resistance of the base
layer, the emitter current density and the current gain in the device.
Fig. 8-9(a). Emitter current crowding in power bipolar transistors. Here the case of
double-sided base contact.
The characteristic length, sp, can be obtained from a distributed model

similar to that of a metal contact to a thin semiconductor layer.
sp = √( rE.Area / Rs,B ) = √(Vt / JE.Rs,B ) (8-6a)
where rE is the small signal emitter resistance, Rs,B is the sheet resistance
of the base and JE is the emitter current density. This analysis is only
valid if the emitter current density close to uniform.
368

The emitter current density in a BJT can only be consider close to

uniform when the emitter stripe width is less that the characteristic length
in the case of a one-sided base contact or less than twice the
characteristics length in the case of a double sided base contact or:
WE ≤ 2 sp (8-6b)
The corresponding value of the base resistance for a uniform emitter

current distribution equals
RB = Rs.WsE. /12 LsE (8-6c)
for a double-sided base contact, which effectively has the resistance of

two sections with half the emitter stripe width connected in parallel. A
series of narrow emitter fingers with alternating base contacts is therefore
typically used in large area power device, resulting in the characteristic
inter-digitated structure, as shown in figure 8-8(b).
Fig. 8-9(b). Power bipolar transistor, with inter-digitized base
369

iii. Kirk Effect in Power BJT's

The Kirk effect is avoided by increasing the collector doping density.
However, for devices with a very high blocking voltage, this may not be
an option. Power BJTs therefore are operated at rather low current density
of 100 A/cm2 since the lower current density reduces the power
dissipation per unit area and eliminates the Kirk effect.
Large currents – up to 1000 A – are obtained by making a large area

device. Silicon BJTs dominate the power device market, in part because
of the low cost of large area silicon devices and the high thermal
conductivity of Si compared to GaAs. Silicon carbide (SiC) has been
hailed as the perfect material for high-power BJTs. The higher thermal
conductivity (3x) and breakdown field (10x) compared to silicon give it a
clear performance advantage. The high saturation velocity (3x compared
to silicon) also shifts the onset of the Kirk effect to high current densities.
iv. Switching Times & Switching Losses in Power BJT's

In a power electronic circuit the power transistor is usually employed as a
switch i.e. it operates in either cutoff (switch OFF) or saturation (switch
ON) regions. We have already described the switching characteristics of a
BJT in Chapter 3. We examine here the switching performance of power
BJT's, when they are connected to an inductive load.
Fig. 8-10(a). Switching circuit of a power bipolar transistor, with inductive load
370

A. Turn On characteristics of a Power BJT

From the description of the basic operating principle of a power transistor
presented in the previous sections it is clear that minority carriers must be
moved across different regions of a power transistor in order to make it
switch between cut off and saturation regions of operation. The time
delay in the switching operation of a power transistor is due to the time
taken by the minority carriers to reach appropriate density levels in
different regions. The exact level of minority carrier densities (and
depletion region widths) required for proper switching is determined by
the collector current and biasing collector voltage during switching, both
of which are determined by external circuits. The rate at which these
densities are attained is determined by the base current waveform.
Therefore, the switching characteristics of a power transistor is always
specified in relation to the external load circuit and the base current
waveform as shown in figure 8-10, which shows a clamped inductive
switching circuit with a flat base drive.
The switching wave forms shown in figure 8-10(b) are the idealized
version of the actual waveforms that will be observed in a clamped
inductive switching circuit as shown in figure 8-10(a). Some simplifying
assumptions have been made to draw these waveforms. These are
The load inductor has been assumed to be large enough so that the load
current does not change during turn-ON period.
 Reverse recovery characteristics of the diode (D) has been ignored.

 All parasitic elements have been ignored.
Before t = 0, the transistor (Q) was in the OFF state. In order to utilize the
increased break down voltage (VCBO) the base-emitter junction of a power
transistor is usually reverse biased during OFF state. Under this condition
only negligible leakage current flows through the transistor. Power loss
due to this leakage current is negligible compared to other components of
power loss in a transistor. Therefore, it is not shown in figure 8-10(b).
The entire load current flows through the diode and VCE is clamped to VCC
(approximately). In order to turn the transistor ON at t = 0, the base
biasing voltage VBB changes to a suitable positive value. This starts the
process of charge redistribution at the base-emitter junction. The process
is akin to charging of a capacitor. Indeed, the reverse biased base emitter
junction is often represented by a voltage dependent capacitor, the value
of which is given by the manufacturer as a function of the base-emitter
reverse bias voltage.
371

Fig. 8-10(b). Switching-on waveforms of a power BJT, with inductive load
The rising base current that flows during this period can be thought of as
this capacitor charging current. Finally at t = td the base-emitter junction
is forward biased. The junction voltage and the base current settles down
to their steady state values.
372

During this period, called the turn-ON delay time no appreciable collector
current flows. The values of IC and VCE remains essentially at their OFF
state levels. At the end of the delay time (td ON) the minority carrier at
the base region quickly approaches its steady state distribution and the
collector current starts rising while the diode current (Id) starts falling. At
t = tdON + tri the collector current becomes equal to the load current and id
becomes zero. At this point, the diode D starts blocking reverse voltage
and VCE becomes unclamped. The time interval tri is called the rise time of
the transistor. At the end of the rise time the diode D regains reverse
blocking capacity. The collector voltage VCE which has so far been
clamped to VCC because of the conducting diode D starts falling towards
its saturation voltage VCE (sat).
The initial fall of VCE is rapid. During this period the switching trajectory
traverses through the active region of the output characteristics of the
transistor. At the end of this rapid fall (t fv1) the transistor enters quasi
saturation region. The fall of VCE in the quasi saturation region is
considerably slower. At the end of this slow fall (tfv2) the transistor enters
hard saturation region and the collector voltage settles down to the
saturation voltage level VCE(sat) corresponding to the load current IL. The
turn-ON process ends here. The total turn-on time is given by:
tSW (ON) = td (ON) + tri + tfv1 + tfv2. (8-7a)
Power loss occurs at all time during the operation of a power transistor.
However, the collector leakage current is usually negligibly small and
power loss due it can be safely neglected in comparison to the power loss
during ON condition. Power loss occurs during turning ON a Power
transistor due to simultaneous existence of non-zero VCE and ic during tri,
tfv1, and tfv2. The energy lost during these periods is called the turn-ON
loss and given by the area under the power curve in figure 8-10(b). The
average turn-ON loss is obtained by dividing this area by (tri + tfv1 + tfv2).
For safe turn-ON this average power loss must be less than the limit set
on the maximum. Similar restriction with respect to second break down
should also be observed.
The turn-ON time can be reduced by increasing the base current.

However large base current increases the quantity of excess carrier in the
base and collector drift region which has to be removed during turn-Off.
As will be seen later this increases the turn-OFF time. The turn-ON delay
time can however be reduced by boosting the base current at the
beginning of the turn-ON process.
373

This can be achieved by connecting a small capacitance across RB. This

increases the rate of rise of VBE and iB. Therefore, turn-ON delay time
decreases. However, in steady state iB settle downs to a value determined
by RB and VBB and no adverse effect on the turn-OFF time is observed.
In figure 8-10 (b) the reverse recovery current of D has been neglected. If
this current is not negligible then for safe turn ON operation the sum of
the load current and the diode reverse recovery current must be less than
the maximum IC rating of the transistor. Thermal and second break down
limits must also be observed.
It should be noted that there is some power loss at the base-emitter

junction as well. This power loss depends on the current gain of the
transistor during hard saturation. Since current gain reduces during
saturation (typically 5 to 10) this power loss may become significant.
Manufacturers usually provide the values of td (ON), tri, tfv as functions of
ic for a given base current and case temperature.
B. Turn Off Characteristics of a Power BJT

During turn-OFF a power transistor makes transition from saturation to
cut off region of operation. Idealized waveforms of several variables in
the clamped inductive switching circuit of figure 8-10(a) during the turn-
OFF process of Q are shown in figure 8-10(c). The turn OFF process
starts with the base drive voltage going negative to a value -VBB. The
base-emitter voltage however does not change from its forward bias value
of VBE(sat) immediately, due to the excess, minority carriers stored in the
base region. A negative base current starts removing this excess carrier at
a rate determined by the negative base drive voltage and the base drive
resistance. After a time ts called the storage time of the transistor, the
remaining stored charge in the base becomes insufficient to support the
transistor in the hard saturation region. At this point the transistor enters
quasi saturation region and the collector voltage starts rising with a small
slope. After a further time interval trv1 the transistor completes traversing
through the quasi saturation region and enters the active region. The
stored charge in the base region at this point is insufficient to support the
full negative base current. VBE starts falling forward –VBB and the negative
base current starts reducing. In the active region, VCE increases rapidly
towards VCC and at the end of the time interval trv2 exceeds it to turn-on
the diode (D). VCE remains clamped at VCC, thereafter by the conducting
diode. At the end of trv2 the stored base charge can no longer support the
full load current through the collector and the collector current starts
falling. At the end of the current fall time tfi the collector current becomes
zero and the load current freewheels through the clamping diode.
374

Fig. 8-9(c). Switching-off waveforms of a power BJT, with inductive load
The turn-OFF process of the transistor ends at this point. The total turn-
OFF time is given by:
ts (OFF) = ts + trv1 + trv2 + tfi (8-7b)
375

As in the case of turn-on, considerable power loss takes place during turn-
off due to the simultaneous existence of IC and VCE in the intervals trv1, trv2
and tfi. The last trace of figure 8-10(c) shows the instantaneous power loss
profile during these intervals. The total energy last per turn off operation
is given by the area under this curve. For safe turn off the average power
dissipation during trv1 + trv2 + tfi should be less than the power dissipation
limit set by the forward bias safe-operating area (FBSOA) corresponding
to a pulse width greater than trv1 + trv2 + tfi.
Turn-OFF time intervals of a power transistor are strongly influenced by

the operating conditions and the base drive circuit. Manufacturers usually
specify these values at a given collector current, as functions for given
positive and negative base currents.
C. Switching Losses in a Power Transistor

It has been mentioned in the earlier sections that energy loss takes place
in a power transistor during each switching operation. Instantaneous
power loss during switching can be calculated and plotted. The areas
under power curves indicate the energy loss during switching (ON and
OFF). Indicating these areas as EON and EOFF during turn-ON and turn-
OFF operations respectively one can write.
(8-8a)
Where VCEf1 is the value of VCE at the end of the interval tfv1 . Similarly
(8-8b)
If the switching frequency of the transistor is fSW, then the average

switching power loss is given by
(8-8c)
In this section, we considered inductive load switching. However, if the

load is resistive. the freewheeling diode D will not be used. In such a case
the collector voltage (VCE) and collector current (ic) will fall and rise
together. Other characteristics of the switching process will remain the
same. The switching power loss in this case will also be substantially
lower. This case is described in Chapter 3.
376

8.2.3. Power Darlington Transistors

Darlington transistors contain two transistors connected in an emitter-
follower configuration, while sharing the same collector contact. This
structure can be fabricated with the same technology as a single BJT as
shown in Figure 8-11. The key advantage of the Darlington configuration
is that the total current gain of the circuit equals the product of the current
gain of the two devices. The disadvantage is the larger saturation voltage.
Since the two devices share the same collector, the saturation voltage of
the Darlington pair equals the forward bias voltage of transistor Q2 plus
the saturation voltage of transistor Q1. Since the forward bias voltage
(VBE1+VBE2) is much larger than the saturation voltage, the saturation
voltage of the Darlington pair is also significantly larger. This larger
voltage results in larger on-state power dissipation.
Fig. 8-11. Darlington transistor structure a) equivalent circuit b) device cross-section
377

8-2.4. Thyristor
The silicon-controlled rectifier (SCR) or thyristor has four alternating n-
type and p-type layers as shown in figure 8-12. Thyristors are typically
made of silicon. The advantage of the structure is that it provides a high
power handling capability, high blocking voltage and high gain with a
very low on-state resistance.
Fig. 8-12. Structure of a thyristor, one its circuit symbol.
i- Thyristor Structure & Operation (2-Transistor Model)

The operation of the device is best explained by considering the
equivalent circuit, shown in figure 8-13. It consists of two bipolar
transistors, an NPN transistor, TR1, and a PNP transistor, TR2. The P-
type base layer of transistor TR1 is also the collector layer of transistor
TR2, while the N-type base of transistor TR2 is also the collector of
transistor TR1.
Fig. 8-13. Two-transistor model of a thyristor

378

In the off-state of a transistor, the collector current Ic is related to emitter

current IE as follows:
IC = αIE + ICBO (8-9a)
where α is the common-base current gain and ICB0 is the common-base

leakage current of collector-base junction of the transistor. For transistor
TR1 in figure, the emitter current IE is equal to the anode current Ia and IC
is equal to the collector current IC1. Therefore, for TR1, we have:
IC1 = α1 Ia + ICBO1 (8-9a)
Here, α1 is the common-base current gain of TR1 and ICBO1 is the common-
base leakage current of TR1. Similarly, for transistor TR2, the collector
current IC2 is given by
IC2 = α2 Ik + ICBO2 (8-9b)
where α2 is the common-base current gain of TR2, ICBO2 is the common-

base leakage current of TR2 and Ik is the emitter current of TR2. The sum
of two collector currents is equal to the external circuit current Iα entering
at anode terminal. Therefore Ia = IC1 + IC2 and we can write:
Ia = α1 Ia + ICBO1+ α2 Ik + ICBO2 (8-9s)
When gate current is applied, then Ik = Ia + Ig . Substituting this value of

Ik we get
Ia = α1 Ia + ICBO1+ α2 (Ia + Ig ) + ICBO2 (8-9d)

or
Ia = α2 Ig + ICBO1 + ICBO2 / [1- (α1+ α2)] (8-9e)
For a silicon transistor, the current gain α is very low at low emitter
current. With an increase in emitter current,  builds up rapidly. With
gate current Ig = 0 and with thyristor forward biased, the sum (α1+ α2) is
very low and the forward leakage current is more than ICBO1 + ICBO2. If, by
some means, the emitter current of two component transistors can be
increased so that α1+ α2 approaches unity, then Ia would tend to become
infinity thereby turning-on the device. Actually, external load limits the
anode current to a safe value after the thyristor begins conduction. The
methods of turning-on a thyristor, in fact, are the methods of making α1+
α2 to approach unity.
379

There are various methods to turn-on (trigger) a thyristor, namely:
(i) GATE Triggering : With anode positive with respect to cathode and
with gate current IG = 0, the anode current, is equal to the forward
leakage current, somewhat more than ICBO1 + ICBO2. In this condition, the
device is in the forward blocking state. Now, assume a sufficient gate-
drive current, which is greater than a threshold value (called the firing
current, IGT) is applied. This gate-drive current will provide the base
current IB1 of TR1. With the establishment of emitter current IE1=Ik of
TR1, current gain α2 of TR2 increases and base current IB1 causes the
collector current IC1 =β1 IB1=β1 Ik to flow. The amplified current IC1
serves as the base current IB2 of TR2. With the flow of IB2, the collector
current IC2= β2 IB2 = β1 β2 IB1 begins to flow. Currents IB2 and IC2 lead to
the establishment of emitter current IA of TR2 and this causes current gain
α2to rise as desired. Now current IG + ICI = (1 + β1 β2) IG acts as the base
current of TR1 and therefore its emitter current Ik = ICI + IG . With the rise
in emitter current, the current gain α2 of TR2 increases and this further
increases IC2. This regenerative positive feedback process will continue
until the sum of current gains α1+ α2 reach to unity. As a consequence, the
device is turned ON, and anode current begins to grow towards a very
large value, which will be limited only by the external load. Even if the
initial gate current IG is removed, the feedback process will continue. This
allows the thyristor to be fired (turned-on) by pulse triggering. Therefore,
the thyristor is a latching device. After thyristor is turned on, all the four
layers are filled with carriers and all junctions are forward biased. Under
these conditions, thyristor has a low resistance and enters the on-state.
(ii) Forward-voltage triggering: If the forward anode to cathode voltage

is increased, the collector to emitter voltages of both the transistors are
also increased. As a result, the leakage current at the middle junction J 2 of
thyristor increases, which is also the collector current of TR2 as well as
TR1 With increase in collector currents IC1 and IC2 due to avalanche
effect, the emitter currents of the two transistors also increase causing the
sum of current gains α1+ α2 to approach unity. This leads to switching on
of the device by positive feedback action. The forward-voltage, which
turns-on the thyristor is greater than a critical value, called the breakover
voltage, may be destructive and should therefore be avoided. An
important consideration, one has to slowly ramp up the applied supply
voltage to avoid the so-called dV/dt effect. The rapid increase of the
applied voltage causes a displacement current proportional to the
capacitance of the junctions (IA =Cj.dV/dt), and this current could provide
a temporary base current in TR1 and TR2, which may trigger the thyristor
to the on-state. 380

ii- Thyristor I-V Characteristics

Figure 8-4, depicts the thyristor I-V characteristics. As shown in figure,
thyristors have three operation modes:
1. Forward blocking mode -- Voltage is applied in the forward direction,

but the thyristor has not yet been triggered into conduction, as long as
the applied voltage is smaller than the breakover voltage (VAK < VBO)
2. Forward conducting mode -- The thyristor is triggered into conduction
by a gate current greater than a threshold value (IG>IGT). The thyristor
remains conducting unless its current is not reduced below the holding
current (IH).
3. Reverse blocking mode -- Voltage is applied in the reverse direction
that would be blocked by a diode
A very attractive feature of a thyristor is that it can be scaled easily to

very large area devices even if that causes a significant variation of lateral
resistance though the thin and lowly-doped base and collector regions. As
one applies a current to the gate electrode, the thyristor would be locally
triggered. The turned-on region would then spread laterally throughout
the structure without a need for an additional gate current.
Fig. 8-14. Thyristor characteristics
381

Example 8-1
Consider a power thyristor with uniformly doped cathode, P-base, N- drift
and P+ anode regions. The N+ cathode has a doping of 2x1019 cm-3 and
thickness of 10um. The P-base has a doping of 2x1017 cm-3 and thickness
of 20um. The N- drift region has a doping concentration of 5x1013 cm-3
and thickness of 300um. The P+ anode has a doping of 2x1019 cm-3 and
thickness of 50 um. Ignore bandgap narrowing and Auger recombination.
Use an ambipolar diffusion constant Da of 15 cm2/s for the on-state
calculations. The structure has linear cell geometry with an emitter width
of 0.5cm and length of 1cm.
(i) What is the blocking voltage capability for the device?
(ii) What's the on-state current for the device at a forward bias of 1V?
Solution
The blocking voltage capability for the thyristor structure is limited by
open-base breakdown voltage of the P-N-P transistor. The breakdown
voltage can be obtained by the following procedure (like Example 6-1).
(i) As the anode voltage is increased, the base-transport factor and
multiplication coefficient increase until the current gain becomes unity at
the breakdown voltage. Using the parameters for the structure in this
problem, the blocking voltage capability is found to be 2080V. At this
anode voltage, the base transport factor is 0.844 and the multiplication co-
efficient is 1.18.
(ii) The on-state voltage drop for a thyristor is given by:
The value for parameter d is (WP + WN)/2 = 160 um. The diffusion length
is 122 microns for a lifetime of 10 microseconds in the P-base and N-base
regions. The function F(d/La) is 0.279 at a (d/La) value of 1.31 for this
structure. The on-state current density for this thyristor structure is found
to be 284 A/cm2 at an on-state voltage drop of 1V. Using the device area
of 0.5 cm2, the on-state current is found to be 142A.
382

The following listing depicts the SPICE netlist of a typical 600V

thyristor, using the two-transistor model.
* SCR Model, 600 Volt 16 Amp

* TERMINALS: A G K
. SUBCKT BTW38 1 2 3
QP 6 4 1 POUT OFF
QN 4 6 3 NOUT OFF
RF 6 4 400K
RR 1 4 266K
RG 6 3 24
RGS 2 6 .2
DF 6 4 ZF
DR 1 4 ZR
DG 6 3 ZG
.MODEL ZF D (IS=6.4F IBV=300U BV=600 RS=60K)
.MODEL ZR D (IS=6.4F IBV=300U BV=800)
.MODEL ZG D (IS=6.4F IBV=300U BV=5)
.MODEL POUT PNP (IS=6.4P BF=1 CJE=19.4N TF=228N TR=59.5U)
.MODEL NOUT NPN (IS=6.4P BF=100 RE=10M RC=10M
+ CJE=19.4N CJC=3.89N TF=228N TR=59.5U)
.ENDS
iii. Thyristor Fabrication Technology

The following figure, 8-15, shows the cross section of two practical
thyristor structures, namely: the symmetric and asymmetric thyristors.
The asymmetric thyristor is characterized by what is termed the emitter

shorts in cathode and anode sides. It can be seen from the diagram that
both the cathode and anode connections connect to N+ and the P regions
in the case of the cathode and the P+ and N regions on the case of the
anode. The short between the P and N regions has adds a resistance
parallel to the emitter-base junctions. This has many useful effects
including reducing carrier lifetime, avoiding the dV/dt effect and
improving the transient response.
The level of doping varies between the different layers of the thyristor.
The cathode is the most heavily doped. The gate and anode are the next
heavily doped. The lowest doping level is within the central n type layer.
This is also thicker than the other layers and these two factors enable a
large blocking voltage to be supported. Thinner layers would mean that
the device would break down at lower voltages.
383

The anode of the thyristor is usually bonded to the package since the gate
terminal is near the cathode and needs to be connected separately. This is
accomplished in such a way that heat is removed from the silicon to the
package.
Fig. 8-15(a). Thyristor symmetric structure
Fig. 8-15(b). Thyristor asymmetric structure, with emitter shorts.
384

iv. Thyristor Packages

The following figure depicts some of the famous thyristor packages.
Fig. 8-16. Photograph and schematic of some thyristor packages.
385

v. Thyristor Testing
One can use a simple multimeter to test SCRs quite effectively. The first
procedure is to check the diode action between the gate and cathode
terminals of the SCR. This test is just like what you have done in the case
of testing a silicon diode (see testing a silicon diode). Now put the
multimeter selector switch in a high resistance position.
Connect the positive lead of multimeter to the anode of SCR and negative
lead to the cathode. The multimeter will show an open circuit. Now
reverse the connections and the multimeter will again show an open
circuit. Then connect the anode and gate terminals of the SCR to the
positive lead of multimeter and cathode to the negative lead. The
multimeter will show a low resistance indicating the switch ON of SCR.
Now carefully remove the gate terminal from the anode and again the
multimeter will show a low resistance reading indicating the latching
condition. Here the multimeter battery supplies the holding current for the
triac. If all of the above tests are positive we can assume the SCR to be
working fine.
Fig. 8-17(a). Testing of a silicon controlled rectifier (SCR) using a multimeter
The following figure depicts another method for testing an SCR. Almost
all types of SCR can be checked using this circuit. The circuit is just a
simple arrangement demonstrating the basic switching action of an SCR.
Connect the SCR to the circuit as shown in diagram and switch S2 on.
The lamp must not glow. Now press the pushbutton switch S1 on and you
can see the lamp glowing indicating the switch on of SCR.
386

The lamp will remain on even if the push button S1 is released (latching
process). If the above checks are positive then the SCR is fine.
Fig. 8-17(b). Testing circuit for a silicon controlled rectifier (SCR)
vi. Thyristor Application Circuits

The high-volume production techniques of thyristors had made them
available at low price so that almost any electrical product can benefit
from thyristor control. A look at the fundamentals of SCR phase control
shows how this is possible. Phase control is the most common form of
thyristor power control. The thyristor is held in the off condition such that
all current flow in the circuit is blocked by the thyristor. Then the
thyristor is triggered into an ―on‖ condition by the control circuitry.
The following figure illustrates voltage waveform and shows common

terms used to describe thyristor operation. Delay angle is the time during
which the thyristor blocks the line voltage. The conduction angle is the
time during which the thyristor is on.The following figure depicts one of
the classic thyristor applications in power control, such as motor speed
control.
387

Fig. 8-18(a). Thyristor control circuits.
Fig. 8-18(b). Thyristor application as a motor speed controller.
388

Fig. 8-18(c). Motor conduction current at different positions of the control

potentiometer.
vii. Other Thyristor Devices

The thyristor has many variant devices, such as
 Silicon Controlled Rectifier (SCR)

 Breakover Diode (BOD) , which is a gateless thyristor triggered by
avalanche current, and used in protection applications
 DIAC, two back-to-back BOD’s
 Light Activated SCR (LASCR)
 Triode for Alternating Current (TRIAC)— A bidirectional switch,
 Amplifying Gate Thyristor- Power SCR triggered by a sensitive SCR
 Amplifying Gate TRIAC -Power triac triggered by a sensitive triac
 Gate Turn-Off thyristor (GTO)
o MOSFET Controlled Thyristor (MCT)
 Static Induction Thyristor (SITh) or Field Controlled Thyristor (FCTh)
containing a gate structure that can shut down anode current flow.
389

LASCR structure does not contain a gate electrode. Instead the PNPN
structure is locally illuminated with photons whose energy exceeds the
bandgap energy of the semiconductor. The photo-generated current then
acts as the gate current, which triggers the thyristor.
Fig. 8-19. Symbols of different thyristor devices
8-2.5. DIAC and TRIAC

The diode AC switch (DIAC) and the triode AC switch (TRIAC) are very
similar to thyristors. Both are used in AC powered systems and therefore
respond similarly to positive and negative applied voltages. The circuit
symbols and layer structures are shown for both devices in Figure 8-20.
The DIAC consists of a two gate-less PNPN structure connected in

parallel and back-to-back to each other. This device, therefore, acts like
an open circuit until the threshold voltage is reached after which the
device acts as a short. To make a DIAC, an N+ region is added to the
front and the back of a PNPN structure.
The triode AC switch (TRIAC) also contains the same vertical structure
as a DIAC. In addition a contact is made to the P-type gate of the npnp
structure as well as the n-type gate of the pnpn structure. This additional
gate contact allows lowering the threshold for latching for both positive
and negative applied voltages applied between terminal 1 and terminal 2.
390

The figure 8-19 illustrates voltage waveform and common terms used to
describe triac operation. Delay angle is the time during which the triac
blocks the line voltage. Note that the triac can conduct in both half cycles
of the AC line voltage. Thus, the triggering may be applied during both
the half cycles, to turn on the triac and make the triac conduct.
Fig. 8-20. Circuit symbol and device cross-section of a Diode AC switch (DIAC) and
a Triode AC switch (TRIAC).
Fig. 8-21. Triac symbol and I-V characteristics
The following figure depicts one of the classic applications of triacs and
diacs, in power control, such as light dimmers. The circuit shows how
such elements can be used in light intensity control.
391

Fig. 8-22. Triac control circuit.
Fig. 8-23(a). Application of a triac and a diac in a light dimmer.
392

Fig. 8-23(b). The triac conduction current at different positions of the dimmer control
The circuit shown in Figure 8-24 is used to set the speed of a low-power
induction motor, such as those which can be found in fan applications.
Capacitors C1, C2 and C4 are used to filter the noise coming from triac
commutations. C1 and C4 capacitors have to be from Y2 technology,
whereas C2 has to be from X2 technology.
393

Fig. 8-24. Application of a triac in speed control of a small induction motor.
8-2.6. Gate-Turn Off Thyristor (GTO)

The Gate Turn-Off Thyristor, GTO is a variant of thyristor. Rather than
the gate being used to turn the thyristor on, within a gate turn-off
thyristor, GTO, the gate pulse turns the device off. These gate turn-off
thyristors are useful in a number of areas, particularly within variable
speed motor drives, high power, inverters and similar areas. Although
they are not nearly as well known as the more standard forms of thyristor,
the gate turn off thyristor, is now widely used as it is able to overcome
many of the disadvantages of the traditional thyristor. As a result the gate
turn-off thyristor is used in virtually all DC to AC and DC to DC high
voltage conversion units. The first thyristors were developed in the mid-
1950s and established their place in the market as a high current high
voltage switch. The gate turn-off thyristor, GTO was not developed until
later and only entered the market around 1973.
i. GTO Basics
The gate turn off thyristor is behaves somewhat differently to a standard
thyristor which can only be turned on and cannot be turned off via the
gate. The gate turn off thyristor, GTO can be turned-on by a gate signal,
and it can also be turned-off by a gate signal of negative polarity. The
device turn on is accomplished by a "positive current" pulse between the
gate and cathode terminals.
394

As the gate-cathode behaves like PN junction, there is a relatively small

voltage between the terminals. The turn on phenomenon in GTO is
however, not as reliable as that of a standard thyristor and small positive
gate current must be maintained even after turn on to improve reliability.
ii. GTO Structure

Like the standard thyristor, the gate turn-off thyristor is a four layer
device having three junctions. Again the layers are p-n-p-n with the
outside p layer providing the anode connection, and the outside n layer
providing he cathode connection. In order to attain high emitter
efficiency, the cathode layer is highly doped to give an n+ region. This
has the drawback that it renders the junction nearest to the cathode with a
low breakdown voltage - typically 20- 40V.
The doping level of the p region for the gate is graded. This is to provide
good emitter efficiency for which the doping level should be low, while
providing a good turn off characteristic for which a high doping level is
needed. The gate electrode is often inter-digitated to optimize the current
turn-off capability. High current devices, i.e. 1000A and above may have
several thousand segments which are all connected to the common gate
contact.
Fig. 8-25. Structure of a GTO and its circuit symbol.
395

Another key parameter for a gate turn-off thyristor is the maximum

forward blocking voltage. This is determined by the doping level and
thickness of the n type base region. As many devices may need to block
voltages of several kilovolts, the doping level of this region needs to be
kept relatively low.
GTO thyristors are available with or without reverse blocking capability.

Reverse blocking capability adds to the forward voltage drop because of
the need to have a long, low doped i-region. GTO thyristors capable of
blocking reverse voltage are known as Symmetrical GTO thyristors,
abbreviated S-GTO. Usually, the reverse blocking voltage rating and
forward blocking voltage rating are the same. The typical application for
symmetrical GTO thyristors is in current source inverters.
Thyristors, which are incapable of blocking reverse voltage, are

considered as asymmetrical GTO thyristors, abbreviated A-GTO. They
typically have a reverse breakdown rating in the tens of volts. A-GTO
thyristors are used where either a reverse conducting diode is applied in
parallel (e.g, in inverters) or where reverse voltage would never occur
(e.g, in switching power supplies or DC choppers). A-GTO thyristors can
be fabricated with a reverse conducting diode in the same package. These
are known as Reverse Conducting GTO (RCGTO).
iii. GTO Operation

Many aspects of the Gate turnoff thyristor, GTO are very similar to that
of the ordinary thyristor. However, the GTO can be turned-on by a gate
signal, and can also be turned-off by a gate signal of negative polarity.
Turn on is accomplished by a positive current pulse between the gate

and cathode terminals. As the gate-cathode behaves like PN junction,
there will be some relatively small voltage drop between the terminals.
The turn on phenomenon in GTO is however, not as reliable as an SCR
(thyristor) and small positive gate current must be maintained even after
turn on to improve reliability. The turn-on power losses of a GTO are
given by the following expression:
PON-State = J.(Eg/e) +J.(3/8)Vt.exp(3VB/2La c) (8-10)
where J is the current density, Eg is the bandgap, La =√(Da.a) is the am-

bipolar diffusion length,a = n+p is the high injection lifetime of
carriers, c is the critical field and VB is the breakdown voltage
396

VB =  (Na+Nd).c2 / 2eNaNd (8-11)
The first term in equation (8-10) corresponds to the loss due to the
voltage drop across the junction, and the second term corresponds to the
voltage drop due to on-state specific resistance in the lower base region.
Turn off is accomplished by a negative voltage pulse between the gate

and cathode terminals. Some of the forward current (about 1/3 to 1/5) is
stolen and used to induce a cathode-gate voltage which in turn induces
the forward current to fall and the GTO will switch off (to off state).
iv. GTO Switching Circuits

The GTO is used in switching applications because of its rapid turn-off
capability feature. The GTO has low on-state conduction losses and high
voltage blocking capability making it suitable for high-power switching
applications. The main applications are in variable speed motor drives,
high power inverters and traction machines. The following figure shows a
typical GTO switching circuit.
Unlike the insulated gate bipolar transistor (IGBT), the GTO requires
external devices to shape the turn-on and turn-off currents to prevent
device destruction.
During turn on, the device has a maximum dI/dt rating limiting the rise of
current. This is to allow the entire bulk of the device to reach turn on
before full current is reached. If this rating is exceeded, the area of the
device nearest the gate contacts will overheat and melt from over current.
The rate of dI/dt is usually controlled by adding a saturable reactor. Reset
of the saturable reactor usually places a minimum off time requirement on
GTO based circuits.
During turn off, the forward voltage of the device must be limited until
the current tails off. The limit is around 20% of the forward blocking
voltage. If the voltage rises too fast at turn off, not all of the device will
turn off and the GTO will fail, often explosively, due to the high voltage
and current focused on a small portion of the device. Substantial snubber
circuits are added around the device to limit the rise of voltage at turn-off.
Resetting the snubber circuit usually places a minimum time requirement
on GTO circuits.
The total switching losses are given by:
397

Pswitching = (Eon + Eoff).fs (8-12)
The total power losses are hence given by:
Ptotal = Pswitching + Pon-state (8-13)
where the conduction losses are given by equation (8-10).
Fig. 8-26. .Switching circuit of GTO
Fig. 8-27. Typical switching waveforms of a GTO
398

GTO thyristors suffer from long switch off times, whereby after a long
tail time where residual current continues to flow until all remaining
charge from the device is taken away. This restricts the maximum
switching frequency to about 1 kHz. It may however be noted that the
turn off time of an equivalent SCR is ten times that of a GTO. Thus
switching frequency of GTO is much better than SCR.
Table. 8-1. Comparison of an SCR and GTO of same ratings (600V, 350A).
Parameter Description GTO Thyristor

ton, Turn-on time, 8 µs, 2 µs,
Igon at Gate current 2A 200 mA
toff Turn-off time 150 µs 15 µs
VT-ON On state voltage drop 3.4 V 1.5 V
A distributed buffer gate turn-off thyristor (DB-GTO) is a thyristor with

additional PN layers in the drift region to reshape the field and increase
the blocking voltage in the off state. Compared to a typical PNPN
structure, this thyristor would be a PN-PN-PN type structure.
Fig. 8-28. Photograph of a GTO module
399

8-2.7. Integrated-Gate Control Thyristor (IGCT)

An IGCT is a special type of thyristor similar to a GTO. They can be
turned on and off by a gate signal, have lower conduction loss as
compared to GTOs, and withstand higher rates of voltage rise (dv/dt),
such that no snubber is required for most applications. The structure of an
IGCT is very similar to a GTO thyristor.
In an IGCT, the gate turn off current is greater than the anode current.
This results in a complete elimination of minority carrier injection from
the lower PN junction and faster turn off times. The main difference is a
reduction in cell size, plus a much more substantial gate connection with
much lower inductance in the gate drive circuit and drive circuit
connection. The very high gate currents plus fast dI/dt rise of the gate
current means that regular wires cannot be used to connect the gate drive
to the IGCT. The drive circuit PCB is integrated into the package of the
device. The drive circuit surrounds the device and a large circular
conductor attaching to the edge of the IGCT die is used. The large contact
area and short distance reduces both the inductance and resistance of the
connection. The IGCT has much faster turn-off time than the GTO's
allows them to operate at higher frequencies—up to several of kHz for
very short periods of time. However, because of high switching losses,
typical operating frequency up to 500 Hz. The main IGCT applications
are in variable frequency inverters, drives and traction.
400

8-3. MOSFET-based Power Devices.

The MOSFET-based power devices include LDMOS, VMOS, and IGBT.
Power MOSFET’s are typically used in portable electronics and
automotive applications. The input impedance of power MOSFET is
extremely large, so given a very small control currents, relatively large
currents can be switched between ON and OFF states. Thus, resistance is
an important parameter for a power MOSFET, which can be written as
(8-13)
where RS, RD are the resistance associated with the source contact and the
drain contact respectively, and RCH is the channel resistance. In linear
region of operation, RCH can be written as
(8-14)
Therefore, if the current in any cell begins to increase, the resulting

temperature rise will increase the on-resistance, thus limiting the current.
8-3.1. DMOS
DMOS stands for Double-diffused Metal Oxide Semiconductor. The
following figures depict the DMOS transistor structure and circuit symbol
Fig. 8-29. DMOS structure and currents

401

Fig. 8-30. DMOS detailed structure and circuit symbol.
8-3.2. LDMOS
The Laterally Diffused MOSFET (LDMOS) is an asymmetric power
MOSFET designed for low on-resistance and high blocking voltage.
These features are obtained by creating a diffused p-type channel region
in a low-doped n-type drain region. The low doping on the drain side
results in a large depletion layer with high blocking voltage. The channel
region diffusion can be defined with the same mask as the source region,
resulting in a short channel with high current handling capability. The
relatively deep p-type diffusion causes a large radius of curvature at the
edges, which increases the breakdown voltage.
A typical structure is presented in Figure 8-31. The device can be

fabricated by diffusion as well as ion implantation. The p-type region is
formed first, followed by shallow p+ and n+ regions. The n+ regions
provide both source and drain contact regions. The p+-region contacts the
p-type body, which is typically shorted to the source, thereby eliminating
the body effect.
The LDMOS structure combines a short channel length with high

breakdown voltage as desired for high power RF amplifiers in numerous
applications. This device is currently the device of choice for RF power
amplifiers in base stations of wireless communications systems as well as
numerous UHF and L-band power amplifiers in broadcast,
communication and radar systems. The following figure depicts the
LDMOS transistor parasitics and circuit model.
402

Fig. 8-31. LDMOS structure
Fig. 8-32. Power MOS parasitic components and equivalent circuit

403

8-3.3. VMOS and UMOS

The VMOS transistor, which looks like a V-shaped groove, is a vertical
MOSFET with high current handling capability as well as high blocking
voltage. It consists of a double diffused N+P layer, which is cut by a V-
shaped groove as shown in Figure 8-33. The V-groove is easily fabricated
by anisotropic etching a (100) silicon surface using a concentrated KOH
solution. The p+ groove is then coated with a gate oxide, followed by the
gate electrode. As the V-groove cuts through the double diffused layer, it
creates two vertical MOSFETs, one on each side of the groove. The
combination of the V-groove with the double diffused layers results in a
short gate length, which is determined by the thickness of the p-type
layer. The vertical structure allows the use of a low-doped drain region,
which results in a high blocking voltage.
Fig. 8-33. UMOS and VMOS structures
Another alternate structure is the UMOS structure. A vertical trench is

etched though the double diffused layer, again resulting in two vertical
MOSFETs. These vertical structures can further be combined with the
HEXFET layout. This layout resembles a honeycomb structure in which
the hexagonal areas are source areas, while the gate metal is located on
the perimeters
404

8-3.4. MOS Controlled Rectifier (MCT)

There exist two recent technologies to reduce the driving gate trigger
current requirements of classic thyristor devices, namely:
1- MOS-gated thyristor (MGT) and

2- MOS Controlled Thyristor (MCT).
The MOS-gated thyristor uses a MOSFET to turn-on through the upper

(PNP) transistor of a normal thyristor structure. Since a MOSFET
requires negligible current to drive, this makes the thyristor as a whole
very easy to trigger.
MOS controlled thyristor (MCT) is a voltage controlled fully controllable

thyristor. The MCT is similar in operation with GTO thyristor, but it has
voltage controlled insulated gate. As shown in figure 8-35(b), the MCT
has two MOSFETs in its equivalent circuit. One is responsible for turn-on
and the another is responsible for turn-off.
Positive voltage on gate terminal with respect to cathode turns the

thyristor into on state. Negative voltage on gate terminal with respect to
anode (which is close to cathode voltage in on state) turns the thyristor
into off state.
Fig. 8-34. Equivalent circuit of the MOS gated thyristor (MGT), left, and MOS
controlled thyristor (MCT), right.
405

Fig. 8-35. Structure of the MOS controlled thyristor (MCT)
8-3.5. Insulated Gate Bipolar Transistor (IGBT)

The Insulated Gate Bipolar Transistor (IGBT) is a semiconductor device
with four alternating layers (P-N-P-N) that are controlled by a metal-
oxide-semiconductor (MOS) gate structure. The device structure is
referred to as the insulated-gate transistor (IGT), the conductivity-
modulated field-effect transistor (COMFET) and bipolar-mode MOSFET.
It has three terminals called Collector (C), Gate (G) and Emitter (E).
Fig. 8-36. Generic structure of insulated gate bipolar transistor (IGBT).
406

As shown in figure 8-31, the IGBT combines the high input impedance of
a MOSFET with the high current handling capability and high blocking
voltage of a BJT in a simple structure. The main advantages of IGBT
over a Power MOSFET and a BJT are:
o It has a very low on-state voltage drop due to conductivity modulation
and has superior on-state current density. So smaller chip size is
possible and the cost can be reduced.
o Low driving power and a simple drive circuit due to the input MOS
gate structure. It canbe easily controlled as compared to current
controlled devices (thyristor, BJT) in high voltage and high current
applications.
o Wide safe operating area (SOA). It has superior current conduction
capability compared with the bipolar transistor. It also has excellent
forward and reverse blocking capabilities.
The main drawbacks are:

o Switching speed is inferior to that of a Power MOSFET and superior
to that of a BJT. The collector current tailing due to the minority
carrier causes the turn-off speed to be slow.
o There is a possibility of latchup due to the parasitic PNPN thyristor
structure inherent within the device structure.
The applications for the IGBT were initially restricted by its slow
switching speed and latch-up phenomena. However, it was demonstrated
by Baliga and Goodman et al. in 1983 that the switching speed could be
increased by electron irradiation. Successful efforts to suppress the latch-
up of the parasitic thyristor and the scaling of the voltage rating of the
devices allowed the introduction of commercial devices in 1983.
Complete suppression of the parasitic thyristor action and the resultant
non-latch-up IGBT operation for the entire device operation range was
achieved in 1984. Products of non-latch-up IGBTs were first
commercialized by Toshiba in 1985. Once the non-latch-up capability
was achieved in IGBTs, it was found that IGBTs exhibited very rugged
and a very large safe operating area. It was demonstrated that the product
of the operating current density and the collector voltage exceeded the
theoretical limit of bipolar transistors (2x105 W/cm2). The IGBT is
suitable for many applications in power electronics, especially in 3-phase
drives with high dynamic range control and low noise. It also can be used
in Uninterruptible Power Supplies (UPS), Switched-Mode Power
Supplies (SMPS),
407

i. IGBT Basic Structure

The basic structure of a typical N-channel IGBT is shown in Figure 8-22.
This is one of several structures possible for this device. It is evident that
the silicon cross-section of an IGBT is almost identical to that of a
vertical Power MOSFET except for the P+ injecting layer. It shares
similar MOS gate structure and P wells with N+ source regions. The N+
layer at the top is the source or emitter and the P+ layer at the bottom is
the drain or collector. It is also feasible to make P-channel IGBTs and for
which the doping profile in each layer will be reversed. IGBT has a
parasitic thyristor comprising the four-layer NPNP structure. Turn-on of
this thyristor is undesirable.
Some IGBTs, manufactured without the N+ buffer layer, are called non-
punch through (NPT) IGBTs whereas those with this layer are called
punch-through (PT) IGBTs, as shown in figure 8-37. The presence of this
buffer layer can significantly improve the performance of the device if the
doping level and thickness of this layer are chosen appropriately.
Fig. 8-37. Non-punch through (NPT) and punch-through (PT) IGBT structures
ii. IGBT Operation

Despite physical similarities, the operation of an IGBT is closer to that of
a power BJT than a power MOSFET. It is due to the P+ drain layer
(injecting layer) which is responsible for the minority carrier injection
into the N-drift region and the resulting conductivity modulation. Based
on the structure, a simple equivalent circuit model of an IGBT can be
drawn as shown in Figure 8-33.
408

The following figure depicts a cross section of a typical IGBT showing

the internal connection of MOSFET and bipolar device. The additional
P+ region creates a cascade connection of a PNP bipolar transistor with
the surface n-channel MOSFET. This results in a lower forward voltage
drop compared to conventional MOS in high blocking voltage devices.
Fig. 8-38. Symmetrical structure and equivalent circuit of the IGBT.
The electrons originating from the N+ source flow laterally underneath

the gate and then flow down in the buried N-type region, thereby
supplying the gate current of the PNP BJT. Since the gate current is
provided locally, the emitter current will be concentrated around the same
area. Note that under typical operation the collector is grounded while a
positive voltage is applied to the emitter. Therefore this device can be
connected in a switching circuit just like an NPN BJT with the distinction
that no gate current is required to maintain the on-state current.
A. Forward-Blocking and Conduction Modes

When a positive voltage is applied across the collector-to-emitter terminal
with gate shorted to emitter, the device enters into forward blocking mode
with junctions J1 and J3 are forward-biased and junction J2 is reverse-
biased. A depletion layer extends on both-sides of junction J2 partly into
P-base and N-drift region. An IGBT in the forward-blocking state can be
transferred to the forward conducting state by removing the gate-emitter
shorting and applying a positive voltage of sufficient level to invert the Si
below gate in the P base region. This forms a conducting channel which
connects the N+ emitter to the N--drift region. Through this channel,
electrons are transported from the N+ emitter to the N--drift. This flow of
electrons into the N-drift lowers the potential of the N--drift region
whereby the P+ collector/ N--drift becomes forward-biased.
409

Under this forward-biased condition, a high density of minority carrier

holes is injected into the N--drift from the P+ collector. When the injected
carrier concentration is very much larger the background concentration, a
condition defined as a plasma of holes builds up in the N--drift region.
This plasma of holes attracts electrons from the emitter contact to
maintain local charge neutrality. In this manner, approximately equal
excess concentrations of holes and electrons are gathered in the N-- drift
region. The excess carrier concentrations drastically enhance the
conductivity of N--drift region. This mechanism of conductivity rise is
referred to as the conductivity modulation of the N--drift region.
B. Reverse-Blocking Mode
When a negative voltage is applied across the collector-to-emitter
terminal shown in figure 8-39, the junction J1 becomes reverse-biased
and its depletion layer extends into the N--drift region. The break down
voltage during the reverse-blocking is determined by an open-base BJT
formed by the P+ collector/ N--drift/P-base regions. The device is prone
to punch-through if the N--drift region is very lightly-doped. The desired
reverse voltage capability can be obtained by optimizing the resistivity
and thickness of the N—drift region.
iii. IGBT IV-Characteristics

The plot for forward output characteristics of an NPT-IGBT is shown in
Figure 8-34. It has a family of curves, each of which corresponds to a
different gate-to-emitter voltage (VGE). The collector current (IC) is
measured as a function of collector-emitter voltage (VCE) with the gate-
emitter voltage (VGE) constant. A distinguishing feature of the
characteristics is the 0.7V offset from the origin. The entire family of
curves is translated from the origin by this voltage magnitude. It may be
recalled that with a P+ collector, an extra P-N junction has been
incorporated in the IGBT structure. This P-N junction makes its function
fundamentally different from the power MOSFET.
The transfer characteristics of the IGBT are defined as the variation of

ICE with VGE at fixed values of VCE. A typical transfer characteristic is
shown in Figure 8-35. The gradient of transfer characteristic at a given
temperature is a measure of the trans-conductance (gm) of the device.
410

Fig. 8-39. Output I-V characteristics of the IGBT
Fig. 8-40 Transfer I-V characteristics of an IGBT

411

iv. IGBT Circuit Models

Rather than using a device physics-based model, SPICE simulates IGBTs
using Macromodels, a method that combines an ensemble of components
such as FETs and BJTs in a Darlington configuration. An alternative
physics-based model is the Hefner model. Hefner's model was introduced
in 1988 and was later extended to a thermo-electrical model.
v. IGBT Switching Characteristics

The switching characteristics of an IGBT are very much similar to that of
a Power MOSFET. The major difference from Power MOSFET is that it
has a tailing collector current due to the stored charge in the N--drift
region. The tail current increases the turnoff loss and requires an increase
in the dead time between the conduction of two devices in a half-bridge
circuit. The Figure 8 shows a test circuit for switching characteristics and
the Figure 9 shows the corresponding current and voltage turn-on and
turn-off waveforms. The tested IGBTs are connected with a gate voltage
switched from +15V to 0V. To reduce switching losses, it is
recommended to switch off the gate with a negative voltage (-15V).
Fig. 8-41. Switching circuit of an IGBT
The turn-off speed of an IGBT is limited by the lifetime of the stored

charge or minority carriers in the N--drift region which is the base of the
parasitic PNP transistor. The base is not accessible physically thus there
is no external means to sweep out the stored charge from the N-drift
region to improve the switching time.
The only way the stored charge can be removed is by recombination

within the IGBT. Traditional lifetime killing techniques or an N+ buffer
layer to collect the minority charges at turn-off are commonly used to
speed-up recombination time.
412

The turn-off energy Eoff is defined as the integral of (IC .VCE) within the
limit of 10% VCE rise to 90% IC fall. Eoff plays the major part of total
switching losses in IGBT.
The turn-on energy Eon is defined as the integral of (IC .VCE) within the
limit of 10% ICE rise to 90% VCE fall. The amount of turn-on energy
depends on the reverse recovery behavior of the freewheeling diode, so
special attention must be paid if there is a freewheeling diode within the
package of the IGBT.
Fig. 8-42. Switching characteristics of an IGBT
vi. IGBT Ratings

In this section we provide the definition of the IGBT device parameters,
so that the designer can predict with accuracy its behavior in a specific
application.
Collector-to-Emitter Breakdown Voltage (BVCES). This parameter

guarantees the lower limit of the distribution in breakdown voltage.
Breakdown is defined in terms of a specific leakage current and has a
positive temperature coefficient (listed in the table as BVCES/DT) of
about 0.63V/°C. This implies that a device with 600V breakdown at 25°C
would have a breakdown voltage of 550V at -55°C.
413

Emitter-to-Collector Breakdown Voltage (BVECS). This rating

characterizes the reverse breakdown of the collector-base junction of the
PNP. The relevance of this specification can be better understood as
follows. When an IGBT turns-off and current is transferred to the diode
across the complementary device, the turn-off di/dt in the stray
inductance, which is connected in series with the diode, generates a
reverse voltage spike across the IGBT. This reverse voltage is typically
less than 10V. This reverse voltage can cause breakdown in the junction.
Collector-to-Emitter Saturation Voltage (VCE(on)). Being the key rating

to calculate conduction losses, this value is supported in data sheets by
plots that provide a detailed characterization in temperature, current and
gate voltage.
Gate Threshold Voltage (VGE(th)). This is the range of voltage on the

gate at which collector current starts to flow. The variation in gate
threshold with temperature is also specified (VGE(th) / Tj). Typically the
coefficient is -11 mV/°C, leading to a reduction of about 1.4V in the
threshold voltage at high temperature.
Forward Transconductance (gFE). This parameter is measured by

superimposing a small variation on a gate bias that takes the IGBT to its
100°C rated current in "linear" mode.
Zero-Gate-Voltage Collector Current (ICES). This parameter guarantees

the upper limit of the leakage distribution at the rated voltage and two
temperatures. It complements the BVCES rating seen above.
Switching Times (td, tr, tf). Switching times provide an indication of

switching losses. They also provide a useful guideline to establish the
appropriate dead-time between the turn-off and subsequent turn-on of
complementary devices in a half bridge configuration and the minimum
and maximum pulse widths. The switching times for a simple IGBT are
defined with reference to the switching test circuit in the previous section.
For a simple device, they are defined as follows:
Turn-on delay time: 10% of gate voltage to 10% of collector current

Rise time: 10 to 90% of collector current
Turn-off delay time: 90% of gate voltage to 90% of collector current
Fall time: 90 to 10% of collector current.
414

It should be remembered that IGBTs, like power MOSFETs, do not have

a storage time. The turn-off delay is due to the Miller effect.
Switching Energy (Eon, Eoff, Ets). These parameters allow the designer to
calculate the switching losses, without worrying about the actual current
and voltage wave shapes, the tail and the quasi-saturation.
415

8-4. Switching Performance of Power Devices

Power device are usually employed as switching elements in various
power conversion applications. A power semiconductor switch can either
conduct a current when it is turned ON or block a voltage when it is
turned OFF by appropriate control signals. The time that it takes to
change the conductivity of a power device is also reduced to the
microsecond level compared with the millisecond level of a mechanical
switch. By employing this kind of switch, a properly designed electrical
system can control the flow of electric energy, shaping the electricity into
desired forms. Parameters describing the performance of a power
conversion system include reliability, efficiency, size, and cost. The
power switch plays an important role in determining these system-level
performances. Generally, the following parameters are important for any
semiconductor switch designed for power conversion applications:
1. Maximum conduction current capability

2. Maximum blocking voltage capability
3. Thermal capability
4. Forward voltage drop during ON and its temperature dependency
5. Leakage current in the OFF state
6. Safe Operating Area (SOA)
7. Switching times during both turn-on and turn-OFF
8. Capability to stand dV/dt when the switch is OFF or during turn-OFF
9. Capability to stand dI/dt when the switch is ON or during turn-on
10. Controllable dI/dt or dV/dt capability during switching
11. Ability to withstand both high current and high voltage
12. Switching losses
13. Control circuit power requirement and complexity
The above items can be further divided into three categories: static,
dynamic, and control parameters. Items 1 to 6 relate to the static
performance of a switch. Both current and voltage ratings describe the
power handling capability of a switch. For a certain application, devices
with higher current and voltage ratings are more robust to transient over-
current and voltage due to switching transitions or circuit faults,
increasing the system level reliability. Lower forward voltage drop and
leakage current lead to a lower power loss, which is good from the energy
efficiency and the thermal management point of view. Good thermal
capability, which refers to the thermal resistance from the device to
ambient and the maximum temperature the device can withstand, allows
the device to operate at its full power rating instead of being limited by
the thermal management.
416

For power semiconductor devices, the safe operating area (SOA) is

defined as the voltage and current conditions over which the device can
be expected to operate without self-damage. SOA is usually presented in
transistor datasheets as a graph with VCE versus IC , as shown in figure 8-
38; the safe area referring to the area under the curve. The SOA
specification combines the various limitations of the device — maximum
voltage, current, power, junction temperature, second breakdown — into
one curve, allowing simplified design of protection circuitry.
Any combination of collector current and voltage below the line can be
tolerated by the transistor.Often, in addition to the continuous rating,
separate SOA curves are plotted for short duration pulse conditions (1 ms
pulse, 10 ms pulse, etc.). The safe operating area curve is a graphical
representation of the power handling capability of the device under
various conditions. The SOA curve takes into account the wirebond
current carrying capability, transistor junction temperature, internal power
dissipation and secondary breakdown limitations
Fig. 8-42.Illustration of the safe operating area (SOA) of a typical power device
(power BJT here).
As we'll see in the next sections, there are two types of SOA; namely:
Reverse bias safe operating area (RBSOA) is SOA when turning the
device into the off-state.
Forward bias safe operating area (FBSOA) is SOA when turning the
device into the on-state.
417

Items 7 to 13 are related to the dynamic performance of a switch. Short

transition times are required to increase the switching frequency and
reduce the switching loss. The latter is caused by the overlap of current
and voltage on the switch.
The current/voltage of the switch overlaps; hence, its switching losses are
approximately proportional to the switching times. Item 8 describes the
external dV/dt immunity of the device. In a system, the switch is
generally exposed to a complex electromagnetic environment. However,
the state and the operation of the switch should only be controlled by its
control command instead of the environment. When the switch is in the
OFF state or during turn-off operation, the switch should stay OFF or
continue its turn-off process no matter what the external dV/dt across its
anode and cathode (or collector/emitter) is.
Similarly, there is a dI/dt requirement when the switch is ON or during

the turn-on transition. Devices with a large cell size such as the GTO
thyristor have lower dI/dt limitations because of the longer time required
for uniform current distribution.
While a good switch should be able to withstand severe dynamic voltage

and current changes, it should also be able to resist acceptable levels of
electromagnetic interfering (EMI) noise. This requires the control of dI/dt
and dV/dt capabilities of the switch. A typical turn-on operation of a
switch in a power system is associated with a turn-OFF process of
another switch (or diode). The dI/dt is generally determined by the turn-
on switch and shared by the turn-off switch, which may not be able to
withstand the high dI/dt. For example, a diode has a turn-off problem and
high turn-off dI/dt may overstress it.
In order to protect these associated devices effectively, the maximum

turn-on dI/dt should be limited. Similarly, a typical turn-OFF operation of
a switch in a power conversion circuit is associated with a turn-on process
of another switch (or diode). The dV/dt is generally determined by the
turn-OFF switch and shared by the turn-on switch, which may not be able
to withstand the high dV/dt. The maximum dV/dt of the active switch
should be limited to protect the associated switches. Both dV/dt and dI/dt
controls normally require a device to possess a forward-biased safe
operation area (FBSOA). The FBSOA defines a maximum V−I region in
which the device can be commanded to operate with simultaneous high
voltage and current. The device current can be controlled through its gate
(or base) and the length of the operation is only limited by its thermal
limitation. 418

Devices with FBSOA normally have an active region in which the device
current is determined by the control signal level. It should be noted,
however, that dI/dt control in practice means slowing down the transient
process and increasing the turn-on loss.
During a typical inductive turn-off process, the voltage of a switch will

rise and its current will decrease. During the transition, the device
observes both high voltage and high current simultaneously. Figure 8-43
depicts the typical voltage–current trajectory of an inductive turn-OFF
process. The current of the device stays constant while its voltage rises.
Its current begins to decrease once its voltage reaches its nominal value.
The voltage spike is caused by the dI/dt and stray inductance in the
current commutation loop.
Fig. 8-43. I-V trajectory during switching-OFF of a typical power device
On the I–V plane of the device, the curve that defines the maximum
voltage and current boundary within which the device can turn off safely,
is referred to as the reverse-biased safe operation area (RBSOA) of the
device. Obviously, the RBSOA of a device should be larger than all its
possible turn-off I–V trajectories. Devices without a large enough
RBSOA need an external circuit (such as an auxiliary soft-switching
circuit or a dV/dt snubber) to shape their turn-off I–V trajectories to a
smaller one to ensure safe turn-off operation. However, a dV/dt snubber
increases the system size and cost. The turn-off operation conducted
without a snubber is called snubberless turn-off or hard turn-off, whereas
a process with the help of a snubber is called snubbered turn-off.
419

During the turn-on transition, a switch will also observe both high voltage
and high current simultaneously. Figure 8-44 depicts the typical voltage–
current trajectory of an inductive turn-on process.
The voltage of the device stays constant while its current increases until it
hits the nominal current level of the device. The current overshoot is due
to the reverse recovery of an associated diode (or a switch). A device
without a large enough FBSOA needs an external snubber circuit to help
its I–V trajectory. The stress on the device can be significantly reduced
with the turn-on snubber. The ability of a switch to limit its maximum
current regardless of the voltage applied is an effective method to limit its
instant power. A device with FBSOA capability normally has self-current
limiting capability and, hence, can survive a short-circuit fault for a short
time as determined by its thermal limitation.
Fig. 8-44. I-V trajectory during switching-on of a typical power device
Finally, it should be noted that any test circuit for measuring switching
performance of power devices, has to satisfy two fundamental
requirements:
1. It must simulate the switching conditions as they are encountered in a
practical application, i.e., a clamped inductive load with continuous
current flow.
2. It must reflect the losses that are attributable to the IGBT, and must be
independent from those due to other circuit components, like the reverse
recovery of the freewheeling diode.
420

8-5. Protection of Power Devices

In practice it is very difficult to design a protection circuit that will work
under all conditions, and it is left up to the design engineer to weigh the
likely fault conditions against the complexity and cost of the protection.
The most common form of device protection used with bipolar junction
transistors senses the collector-emitter current with a low-value series
resistor; the voltage across this resistor is applied to a small auxiliary
transistor that progressively 'steals' base current from the power device as
it passes excess collector current. This approach is effective but not
bullet-proof.
Power devices usually make use back diodes for protecting them from
back EMF, when connected to inductive loads. This type of diode is
generally known as a Freewheel diode. The Freewheel diode is used to
protect solid state switches such as power transistors and MOSFET's from
damage by reverse battery protection as well as protection from highly
inductive loads such as relay coils or motors, and an example of its
connection is shown below. Every time the switching device above is
turned ON, the freewheel diode changes from a conducting state to a
blocking state as it becomes reversed biased. However, when the device
rapidly turns "OFF", the diode becomes forward biased and the collapse
of the energy stored in the coil causes a current to flow through the
freewheel diode. Without the protection of the freewheel diode high di/dt
currents would occur causing a high voltage spike or transient to flow and
possibly damaging the switching power device
Fig. 8-45. Power device protection by a freewheel diode.

421

In high-voltage and high power systems, the isolation of high-voltage

systems, from the low voltage control circuits is accomplished by opto-
couplers or optoisolators. Opto-isolators pair an infrared LED with a
photosensor, which allows current to flow when it detects light from the
LED. Below is an example circuit of an optoisolator. Optocouplers, are
sometimes integrated inside the power device itself, e.g., in light activated
thyristors (LASCR).
Fig. 8-46. Power device protection by a freewheel diode.
422

8-6. Packaging & Thermal Considerations

The power device, which is mounted on a carrier, should be sealed and
molded into a package. Packaging protects the device from moisture, dust
and other types of contamination. The packages also make it easier to
install it in various types of equipment. The shape of the external
packaging system depends on the number of terminals and the power
dissipation as well as the environmental operating conditions. In high
power devices heat dissipation is a crucial issue. The maximum power
dissipation P that a power semiconductor device can tolerate at a given
ambient temperature TA is given by:
TJ  TA TJ  TA
P  ( 8-15)
 JA  JC  CA
where TJ is the maximum allowed junction temperature (about 125 °C for

Si and more for wide gap semiconductors), JA is the thermal resistance
between junction and ambient air. Also, JC is the thermal resistance
between junction and case and CA is the thermal resistance between case
and ambient air. The thermal resistance is measured in °C/Watt.
Evidently, the thermal resistance JA and hence the maximum power that
can be dissipated (in the form of heat) depends on the package material
and the presence of a heatsink. As the performance characteristics of
semi-conductor devices varies as a function of its temperature, it is
necessary to choose the package type (and a heat sink, if necessary)
which suits fine the destined application. Particularly, in power devices,
the die attachment is exposed to facilitate its connection to an external
heat sink.
Fig. 8-47(a). Packaging of a power device or power IC, using Power Pad.
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The following figure shows the different temperatures, which are

important for characterizing the package of a power device and its
thermal behavior.
Fig. 8-47(b). Power device mounting on a board or on a heatsink, and the

significance of different temperatures.
The thermal resistance (θ or Theta) is also a common method of

characterizing the packaged devices and their thermal performance. For a
semiconductor device, thermal resistance indicates the steady state
temperature rise of the die junction above a given reference for each watt
of power (heat) dissipated at the die surface.
The most common examples are Theta-JA (junction-to-ambient), Theta-

JC (junction-to-case), and Theta-JB (junction-to-board). Knowing the
reference (i.e. ambient, case, or board) temperature, the power, and the
relevant theta value, the junction temp can be calculated.
Theta-JA is commonly used with natural and forced convection air-

cooled systems using components mounted on epoxy-glass PCBs. Theta-
JC is useful when the package has a high conductivity case mounted
directly to a PCB or heatsink. And theta-JB applies when the board temp
adjacent to the package is known.
In additional to the theta thermal resistance, the psi-JB (junction-to-

board) and psi-JT (junction-to-top) thermal parameters are useful. For a
device powered up on a printed-circuit board (PCB), these psi's provide a
correlation between junction temperature and the board temperature or
"top of package" temperature. The term "psi" is used to distinguish these
from "theta" thermal resistances since not all heat is actually flowing
between the points of temperature measurement with the psi parameter.
They're not true thermal resistances for this reason.
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The common thermal design parameters are as follows:

• TJ = Die Junction Temperature, °C
• TC = Package Case Temperature, °C
• TB = Board Temperature Adjacent to Package, °C
• TT = Top of package Temperature at center, °C
• TA = Ambient Air Temperature, °C
• θJA (Theta-JA) = Thermal Resistance Junction-to- Ambient, °C/W
• θJC (Theta-JC) = Thermal Resistance Junction-to-Case, °C/W
• θJB (Theta-JB) = Thermal Resistance Junction-to-Board, °C/W
• ΨJB (Psi-JB) = Junction-to-Board Parameter, °C/W
• ΨJT (Psi-JT) = Junction-to-Top (of Package) Parameter, °C/W
• P = Power dissipated by device, Watts
Out of the above parameters, there exist five main metrics, which are
usually given in data sheets. The five thermal metrics of a device package
are summarized in table 8-2. Also Table 8-3 contains some information
about standard packages and their thermal characteristics.
Table 8-2. Summary of the five thermals design metrics.
Thermal Symbol Definition Formula Usage Formula

Metric
Theta-JA θJA θJA = (TJ – TA) / P TJ = TA + (θJA * P)
Theta-JC θJC θJC = (TJ – TC) / P TJ = TA + (θJC * P)
Theta-JB θJB θJB = (TJ – TB) / P TJ = TA + (θJB* P)
Psi-JB JB JB = (TJ – TB) / P TJ = TB + (JB* P)
Psi-JT JT JT= (TJ – TT) / P TJ = TB + (JT* P)
Note that θJA indicates ease of heat flow through the total of all paths
between die junction and ambient air. Also, θJ C indicates ease of heat
flow between die junction and case (either package top or bottom). For
packages with an exposed metal pad (e-pad) on the underside that will be
soldered to matching land on an epoxy-glass PCB, the total θJA is:
θJA = θJC + θCA
where θCA term is the case-to-ambient resistance, which is controlled by

the printed circuit board (PCB). For packages with a power pad (e-pad)
that will be mounted to a heatsink, the total θJA through this path is:
θJA = θJC + θCS + θSA

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Here, θCS (case-to-sink) term is controlled by the thermal grease or

mounting pad between the package and heatsink. For instance, to
determine theta-JA, we need TJ, TA, and P. If TJ = 80°C, TA =25°C, and
P=1W, then θJA = (80°C - 25°C) /1W =55 °C/W. With θJA, TA and the
power dissipated P known, then
TJ = TA + (θJA * P).
Example: 8-3:
If Theta-JA = 55°C/W and the application board has similar construction
as the thermal test board, then a 1st order approximation of TJ in the
system can be made. Assuming TA = 35°C in the system and steady state
power of the device is P = 0.6W, then:
TJ = = TA + (θJA * P) = 35°C + (55°C/W * 0.6W) = 68°C
Fig. 8-47(c). Illustration of different types of thermal resistances.
Table 8-3. Electronic devices & Integrated circuits standard packages.
Package No of pins Nature Thermal resistance JA

(ºC/W)
TO-3 2 Metal can 45
TO-5 8, 10,12 Metal can 150-300
TO-39 3 Metal can 185
TO-86 14 Ceramic, Flat pack 165, 300
TO-92 3 Plastic (transistor) 200
TO-116 14 Ceramic, Plastic DIP 100, 200
TO-220 3 Plastic Power 65
TO-601 14 Metal can 160
426

8-7.Applications of Power Devices

There are so many applications of power devices in our daily life. The
topic which is concerned with power devices and their applications is
called power electronics. Power electronics refers to control and
conversion of electrical power by power semiconductor devices wherein
these devices operate as switches. In fact, the advent of silicon-controlled
rectifiers led to the development of the area of power electronics. Prior to
the introduction of SCRs, mercury-arc rectifiers were used for controlling
electrical power. Once the SCRs were commercially available, the
application area spread for many fields such as power supplies, drives,
aviation electronics, and inverters.
Power electronics has applications that span the whole field of electrical
power systems, with the power range of these applications extending
from a few VA/W to several MVA / MW.
The main task of power electronics is to control and convert electrical

power from one form to another. The four main forms of conversion are:
 Rectification (AC to DC conversion),

 Inverters (DC-to-AC conversion),
 Converters (DC-to DC conversion) and
 Cycloconverters (AC-to-AC with different frequency conversion).
The term "converter" is the term that is used Power Electronics to refer to
a power electronic circuit that converts voltage and current from one form
to another. These converters can be classified as:
 Rectifier converting an AC voltage to a DC voltage,

 Inverter converting a DC voltage to an AC voltage,
 Chopper or a switch-mode power supply that converts a DC to DC,
 Cycloconverter and cycloinverter converting an AC to AC.
8-7.1. Rectification
Rectifiers can be classified as uncontrolled and controlled rectifiers, and
the controlled rectifiers can be further divided into semi-controlled and
fully-controlled rectifiers. Uncontrolled rectifier circuits are built with
diodes, and fully-controlled rectifier circuits are built with SCRs. Both
diodes and SCRs are used in semi-controlled rectifier circuits.
427

There are several rectifier circuit configurations. The popular rectifier

configurations are listed below.
 Single-phase semi-controlled bridge rectifier,

 Single-phase fully-controlled bridge rectifier,
 Three-phase three-pulse, star-connected rectifier,
 Double 3-phase, 3-pulse star-connected rectifiers with inter-phase,
 Three-phase semi-controlled bridge rectifier,
 Three-phase fully-controlled bridge rectifier and
 Double three-phase fully-controlled bridge rectifiers with IPT.
Apart from the configurations listed above, there are series-connected and
pulse rectifiers for delivering high power output.
Power rating of a single-phase rectifier tends to be lower than 10 kW.

Three-phase bridge rectifiers are used for delivering higher power output,
up to 500 kW at 500 VDC or even more. For low voltage, high current
applications, a pair of three-phase, three-pulse rectifiers interconnected by
an inter-phase transformer (IPT) is used. For a high current output,
rectifiers with IPT are preferred to connecting devices directly in parallel.
There are many applications for rectifiers. Some of them are:
 Variable speed DC drives,

 Battery chargers,
 DC power supplies and Power supply for a specific applications.
The following figure depicts a 3-phase-rectifier, using thyristors. The gate

control signals are not shown for simplicity.
Fig. 8-47. Application of power devices in rectification (AC-DC conversion).

The circuit shown is a 3-phase-rectifier, using thyristors.
428

8-7.2. DC-to-AC Conversion

The converter that changes a DC voltage to an alternating voltage is
called an inverter. Earlier inverters were built with SCRs. Since the
circuitry required to turn the SCR OFF tends to be complex, other power
semiconductor devices such as bipolar junction transistors, power
MOSFETs, insulated gate bipolar transistors (IGBT) and MOS-controlled
thyristors (MCTs) are used nowadays.
Currently only the inverters with a high power rating, such as 500kW or
higher, are likely to be built with either SCRs or gate turn-OFF thyristors
(GTOs). There are many inverter circuits and the techniques for
controlling an inverter vary in complexity. Some of the applications of an
inverter are listed below:
 Emergency lighting systems,

 AC variable speed drives,
 Uninterrupted power supplies, and
 Frequency converters.
The following figure depicts a full-bridge inverter, using IGBT’s. The

gate control signals are not shown for simplicity.
Fig. 8-48. Application of power devices in inverters (DC-AC conversion). The circuit
shown is a full-bridge inverter, using IGBT’s.
8-7.3. DC-to-DC Conversion

When the SCR came into use, a DC-to-DC converter circuit was called a
chopper. Nowadays, an SCR is rarely used in DC-to-DC converters.
Either a power BJT or a power MOSFET is normally used in such
converters and they are called switch-mode power supplies (SMPS).
429

A switch-mode power supply (SMPS) can be of one of the following

types:
 Step-down switch-mode power supply,

 Step-up chopper,
 Flyback converter or
 Resonant converter.
The typical applications for a switch-mode power supply or a chopper

are:
 DC power supply.
 Battery charger and
 DC drive
The following figure depicts a flyback DC-DC converter, using power

MOSFET. The gate control signals are not shown for simplicity.
Fig. 8-49. Application of power devices in a flyback converter (DC-DC conversion).

The circuit shown is a flyback converter, using power MOSFET.
8-7.4. AC-to-AC Conversion

A cycloconverter or a cycloinverter converts an ac voltage, such as the
mains supply, to another ac voltage. The amplitude and the frequency of
input voltage to a cycloconverter tend to be fixed values, whereas both
the amplitude and the frequency of output voltage of a cycloconverter
tend to be variable. On the other hand, the circuit that converts an AC
voltage to another AC voltage at the same frequency is known as an AC-
chopper. A typical application of a cycloconverter is to use it for
controlling the speed of AC traction motor and most of these cyclo-
converters have a high power output, of the order of a few megawatts
(MW) and SCRs are used in these circuits.
430

Fig. 8-50. Application power devices in cycloconverters (AC-AC conversion)
In contrast, low cost, low power cycloconverters for low power, AC

motors are also in use and many of these circuit tend to use triacs in place
of SCRs. Unlike an SCR, which conducts in only one direction, a Triac is
capable of conducting in either direction. It may be noted that the use of a
cycloconverter is not as common as that of an inverter and the so-called
cycloinverter is rarely used.
431

8-8. Comparison of Power Semiconductor Devices & Vacuum Tubes

Now, we’ll shed some light, with flavor of history, on the vacuum tube
power devices, which are still in use nowadays.
In fact, electron tubes not only continue to see practical use in certain
applications, but perform their tasks better than any solid-state device yet
invented. In some cases the performance and reliability of electron tube
technology is far superior. In the fields of high-power, high-speed circuit
switching, specialized tubes such as thyratrons and krytrons are able to
switch far larger amounts of current, far faster than any semiconductor
device designed to date. The thermal and temporal limits of
semiconductor physics place limitations on switching ability that tubes --
which do not operate on the same principles -- are exempt from.
In high-power microwave transmitter applications, the excellent thermal

tolerance of tubes alone secures their dominance over semiconductors.
Electron conduction through semiconducting materials is greatly

impacted by temperature. Electron conduction through a vacuum is not.
As a consequence, the practical thermal limits of semiconductor devices
are rather low compared to that of tubes.
Tubes are also able to operate at far greater temperatures than equivalent
semiconductor devices. This allows tubes to dissipate more thermal
energy for a given amount of dissipation area, which makes them smaller
and lighter in continuous high power applications. Another decided
advantage of tubes over semiconductor components in high-power
applications is their reproducibility. When a large tube fails, it may be
disassembled and repaired at far lower cost than the purchase price of a
new tube. When a semiconductor device fails, there is generally no means
of repair.
Tubes are potentially cheaper to produce as well, because they are less
complex in their manufacture than semiconductor components, although
the huge volume of semiconductor device production greatly offsets this
theoretical advantage. Semiconductor manufacture is quite complex,
involving many dangerous chemical substances and necessitating super-
clean assembly environments. Tubes are essentially nothing more than
glass and metal, with a vacuum seal. Physical tolerances are "loose"
enough to permit hand-assembly of vacuum tubes, and the assembly work
need not be done in a "clean room" environment as is necessary for
semiconductor manufacture.
432

Tubes also possess the distinct advantage of low drift over a wide range
of operating conditions. Unlike semiconductor components, whose
resistance, junction voltages, and capacitances may change substantially
with changes in device temperature and other operating conditions, the
fundamental characteristics of a vacuum tube remain nearly constant over
a wide range in operating conditions, because those characteristics are
determined primarily by the physical dimensions of the tube's structural
elements.
One modern area where electron tubes enjoy supremacy over

semiconductor components is in the professional and high-end audio
amplifiers. The tube amplifiers are preferred over transistor amplifiers
because of the specific distortion produced by tube circuits.For these
reasons, electron tubes will never be obsolete, but will continue to serve
in niche roles, and to foster innovation for electronics engineers.
433

8-9. Summary
In this chapter, we summarized the operation concepts of the major

semiconductor power devices. Power semiconductor devices are used in
commutation applications (as switches or rectifiers), in power electronic
circuits, such as switch mode power supplies (SMPS) and uninterruptable
power supplies (UPS).
Power devices can be classified into bipolar-based devices (like power

BJT and thyristors), MOSFET-based devices (like DMOS) and devices
that combine a bipolar transistor with a MOSFET (like MCT and IGBT).
Bipolar power devices are the traditional power devices because of their
capability to provide high currents and high blocking voltages. The power
diode and power MOSFET operates on similar principles to their low-
power counterparts, but they are able to carry larger amounts of current
and typically are able to support larger reverse-bias voltages. In addition,
their structural are often designed to accommodate the higher current
density, higher reverse breakdown voltage and higher power dissipation.
434

The important parameters of Power semiconductor devices can be

summarized in the following points:
Breakdown voltage: Often there is a trade-off between breakdown
voltage rating and on-resistance, because increasing the breakdown
voltage by incorporating a thicker and lower doped drift region leads
to higher on-resistance.
On-resistance: Higher current rating lowers the on-resistance due to
greater numbers of parallel cells. This increases overall capacitance
and slows down the speed.
Switching times (Rise time and Fall time) for switching between on
and off states.
Safe-operating area (SOA) and "latch-up" consideration
Thermal resistance: This is an extremely important parameter from
practical design point of view. Semiconductors do not perform well at
elevated temperature but due to large current conduction, all power
semiconductor devices heat up. Therefore they need to be cooled by
removing that heat continuously. Packaging and heatsinks provide a
means of removing heat from the device.
PIN Diode
The PIN diode is the same as a PN diode but with the addition of an
intrinsic layer between the P and N layers. This intrinsic layer provides a
high breakdown voltage capability under reverse bias. The properties
introduced by the intrinsic layer of the PIN diode make it suitable for a
number of applications where ordinary junction diodes are less suitable.
435

Advantages of the PIN diode:

Inexpensive
Does not require control
Disadvantages of the PIN Diode:
Has a reverse recovery time which contributes to power loss
Power BJT
The BJT is an older technology. Switching power supply applications for
BJTs include switching voltages over 600V at frequencies upto 20kHz.
Due to conductivity modulation effects, the BJT can exhibit lower ON-
state collector-emitter voltage (VCEsat) than the drain-source voltage across
a comparable MOSFET. The BJT conduction state is controlled by the
level of current injection into the base terminal.
436

Advantage of the power BJT:

Lower ON- state voltage than power MOSFET’s upto 600V.
The slow switching speed helps to minimize EMI generation,
eliminating the requirements for input EMI filtering.
Disadvantages of the power BJT:

Substantial control current required, resulting in efficiency issues,
Substantial turn-off storage time resulting in slow switching times
and therefore relatively slow maximum switching frequencies.
Silicon-Controlled Rectifier (SCR)

The silicon-controlled rectifier (SCR) or thyristor is essentially a
Shockley PNPN diode with an extra terminal added. This extra terminal
is called the gate, and it is used to trigger the device into conduction
(latch it) by the application of a small voltage. Thyristors are typically
made of silicon. The advantage of the structure is that it provides a high
power handling capability, high blocking voltage and high gain with a
very low on-state resistance.
The thyristor has three basic states:

Reverse blocking: In this mode or state the thyristor blocks the
current in the same way as that of a reverse biased diode.
Forward blocking: In this mode or state the thyristor operation is
such that it blocks forward current conduction that would normally be
carried by a forward biased diode.
Forward conducting: In this mode the thyristor has been triggered
into conduction. It will remain conducting until the forward current
drops below a threshold value known as the "holding current."
As shown in their I-V characteristics, SCRs are unidirectional current

devices, useful for controlling DC only. If two SCRs are joined in back-
to-back parallel fashion, we have a new device known as the TRIAC.
437

Most applications of the SCR are for AC power control. If bidirectional

circuit current is required, multiple SCRs may be used, with one or more
facing each direction to handle current through both half-cycles.
Advantages of the SCR:

Operating characteristics lends the SCR to phase control of AC power
and for crowbar applications.
Lowest cost per kVA of all power semiconductor switches.2
Large power handling capability.
Disadvantages of the SCR:

Substantial minority carrier charge storage time, limiting the
maximum switching frequency to about 400 Hz.
Gate Turn-Off Thyristor (GTO)

The GTO thyristor is similar to the SCR but can be turned off through
application of negative current to the gate electrode. This turn off
capability expands the areas of applications to include not only phase
control of AC line power, but also variable speed motor drive and
inverters. Additionally, the GTO is able to switch somewhat faster than
the SCR. SCRs and GTOs share the same equivalent schematics (two
transistors in positive-feedback). This allows a smaller gate current to
exert a greater degree of control over conduction from cathode to anode.
The key capability of the GTO is its ability to be turned-off by the use of
the gate electrode on the device.
438

The GTO turn-off is achieved by applying a negative bias to the gate with
respect to the cathode. This extracts current from the n-base region. The
resulting voltage drop in the base starts to reverse bias the junction and
thereby stopping the current flow in this transistor. This then stops the
injection into the p-base region and this prevents current flow in this
transistor. The GTO is used in areas where the standard thyristor cannot
be used. Accordingly the GTO is a useful tool for many applications.
Power MOS
The MOSFET-based power devices include LDMOS, VMOS, and IGBT.
Power MOSFET’s are typically used in wireless portable electronics and
automotive applications.
439

Insulated-Gate Bipolar Transistor (IGBT)

The IGBT, is a three terminal hybrid of the BJT and power MOSFET.
Internally, the drain of an N-channel power MOSFET sinks current from
the base of a PNP BJT. Therefore, the IGBT has a high impedance input
similar to a MOSFET. It also has a collect-emitter output which has a
large breakdown voltage and a low on state voltage as in a BJT. IGBT
technology has been greatly improved, resulting in shorter turn off delay
times compared to the BJT.
Advantages of the IGBT:
Voltage controlled, high input impedance device, easier than current
control of BJT.
For devices with higher voltage ratings, the on state voltage is much
lower than that of a comparable MOSFET.
Power handling capability is ten times better than power MOSFETs
or BJT’s
Shorter delay times relative to the BJT, about 300nS to 1500nS.
Disadvantages of the IGBT:

Have a current tail turn-off characteristic which results in longer delay
times relative to the power MOSFET.
440

Most of the above power semiconductor devices are made of silicon.

However, some wide-gap semiconductor materials (such as silicon
carbide SiC) have been investigated for the development of high-power
high temperature devices.
The advantages of SiC compared to Si have been exploited by the device

manufacturers. These advantages result in the improved system
performance.
441

8-10. Problems
8-1) What is/are the basic purpose(s) of the silicon-controlled rectifier?

1. To function as a switch
2. To function as a regulator
3. To function as a rectifier
4. All of the above
8-2) Fill in the blank(s) with the appropriate word(s)

a) Doping density of the emitter of a Power BJT is several orders of
magnitude ______________ than the base doping density.
b) Collector drift region is introduced in a Power BJT to block
_______________ voltage.
c) Doping density of the base region in a power BJT is
________________.
d) Power BJT has ________________ DC current gain compared to
signal level transistors.
e) In a Power BJT multiple, narrow finger like distributed emitter
structure is used to avoid emitter ___________________
8-3). Which of the following advantages, if any, does a vacuum electron

tube have over a power semiconductor device?
1. It can handle more power at higher frequencies
2. It has a longer life
3. It is more economical
4. None of the above
8-4). When compared to an electron tube, the semiconductor device has

which of the following limitations?
1. The semiconductor is more sensitive to temperature
2. The semiconductor is used only in radar equipment
3. The semiconductor is difficult to adapt to commercial products
4. Each of the above
8-5) At some potential, as you increase the reverse bias voltage on a

semiconductor device, the reverse current increases very rapidly. What
electronic term is given to this voltage potential?
1. Breakdown voltage
2. Reverse-bias
3. Forward-bias
4. Thermal runaway
442

8-6) The SCR is equivalent to what electronic device?

1. Diode 2. Tetrode
3. Thyratron 4. Beam power tube
8-7) Once an SCR is turned on by a positive pulse of current applied to

the gate lead, what action turns the SCR off?
1. Removing the positive pulse from the gate lead
2. Inserting a negative pulse of current on the gate lead
3. Reducing the anode current to a value below holding current
4. Increasing the anode current to a point that saturate the SCR.
8-8) What is the total number of terminals in a TRIAC?

1. One 2. Two
3. Three 4. Four
8-9) What is the main difference between the TRIAC and the SCR?
1. The SCR requires a higher input voltage than the TRIAC
2. The TRIAC requires a higher input voltage than the SCR
3. The TRIAC controls and conducts current during both AC half cycles,
while the TRIAC controls and conducts currents during only one half
4. The SCR controls and conducts current during both AC half cycles,
while the SCR controls and conducts currents during only one half
8-10) Complete the space with one of the following choices:

1.The ________ can be externally programmed to turn on at a desired
anode-to-gate voltage level.
A. UJT B. PUT
C. SCR D. SCS
2. The ________ can conduct current in either direction and is turned on
when a breakover voltage is exceeded.
A. SCR B. Diac
C. SCS D. Triac
8-11) You need a very efficient thyristor to control the speed of an AC fan
motor. A good device to use would be
A. 4-layer PNPN diode. B. PUT.
C. Triac. D. BJT.
443

8-12) You need to design a relaxation oscillator circuit. The most likely
device to use might be
A. SCR. B. UJT.
C. Triac. D. 4-layer diode.
8-13) You have the schematic diagrams of several circuits. Which of

these circuits most likely use a Triac?
A.oscillator B. AC motor control
C. programmable oscillator D. amplifier
8-14) Consider the two-transistor model of a thyristor. Derive an

expression for the forward anode current, in terms of the two-transistor
current amplification factors (1 +2).
8-15) Derive an expression for the turn-off time of a GTO, in terms of the
switching voltage levels, and its internal physical parameters.
8-16) Check True or False for the following phrases:

i. The anode-to-gate voltage can be used to turn the PUT on or off.
A. True B. False
ii. In an SCR-based half-wave phase-control circuit, a diode is connected
in series with the AC source.
A.True B.False
iii. The SCR is a device that can be triggered off by a pulse applied to the
gate.
A.True B.False
8-17) Which of the following is (are) the advantage(s) of VMOS over

MOSFETs?
A. Reduced channel resistance B. Higher current and power ratings
C. Faster switching time D. All of the above
444

8-11. References
[1] S. M. Sze and G. Gibbons, ―Avalanche breakdown voltages of abrupt

and linearly graded p-n junctions in Ge, Si, GaAs, and Ga P,‖ Appl. Phys.
Lett., vol.8, p.111, 1966.
[2] S.K. Ghandhi, Semiconductor Power Devices, John-Wiley Sons,

New York, 1977.
[3] A. K. Temple, MOS-Controlled Thyristors--A New Class of Power

Devices", IEEE Transactions on Electron Devices, Vol. ED-33, No. 10,
Oct. pp. 1609-1618, 1986,
[4] A. Nakagawa et al., "Safe operating area for 1200-V non-latch-up

bipolar-mode MOSFETs", IEEE Trans. on Electron Devices, ED-34,
pp.351-355, 1987.
[5] Paolo Antognetti, Giuseppe Massobrio ―Semiconductor Device

Modeling with SPICE,‖ McGraw-Hill, New York, 1988, 2nd Ed. 1993.
[6] B.K. Bose, ―Evaluation of modern power semiconductor devices and

future trends of converters,” IEEE Transactions on Electron Devices,Vol.
28, pp. 403 – 413, 1992.
[7] W.E. Doherty and R.D. Joos, ―PIN Diodes Offer High-Power HF
Band Switching‖, , Microwaves & RF, Vol 32, No 12, pp 119-128,1993,
[8] A. Duncan and John Gower, Power MOSFETs - Theory and

Applications, 1995.
[9] Ned Mohan, Tore M. Underland, and William P. Robbins, Power

Electronics, 2nd Edition, New York, John Wiley & Sons, 1995.
[10] Vítězslav Benda, John Gowar, Duncan Andrew Grant, Power

semiconductor devices: theory and applications, John Wiley- Sons, 1999.
[11] B. Jayant Baliga, Modern Power Devices, PWS, Boston, 2000
[12] Robert W. Erickson, Dragan Maksimovic, Fundamentals of Power

Electronics, 2nd Edition, Norwell, Kluwer Academic Publishers, 2001.
[13] S. M. Sze, Semiconductor Devices. Physics and Technology. John

Wiley, 2nd edition, 2002.
445

[14] B. Jayant Baliga, Power Semiconductor Devices, PWS publishing

Company, Boston. 2004

Oxford, 2004.
[16] Reid L. Sprite, "Power Semiconductors: The BJT, MOSFET, and

IGBT", December, 2004.
[17] Stefan Linder, Power Semiconductors, EPFL Press, 2006
[18] Yong Perry Li, "Why Consider a BJT over a MOSFET?", Electronic
Engineering Times, 2010.
[19] Josef Lutz, Heinrich Schlangenotto, Uwe Scheuermann, Rik De

Doncker, Semiconductor Power Devices: Physics, Characteristics,
Reliability, Springer, 2011.
446

Microelectronic & Nanoelectronic Devices Appendix
Appendices
Appendix A List of Symbols

Appendix B SPICE Model of P-N Junction Diode
Appendix C SPICE Model of a BJT
Appendix D SPICE Model of a JFET
Appendix E SPICE Model of a MOSFET
Appendix F SPICE Model of an IGBT
629
630
Appendix A: List of Symbols

Symbol Description Units
A Area m2
c Speed of light in vacuum m/s
C Capacitance per unit area F/m2
CFB MOS Flatband capacitance per unit area F/m2
Cj Junction capacitance per unit area F/m2
Cox Oxide capacitance per unit area F/m2
Dn Electron diffusion constant m2/s
Dp Hole diffusion constant m2/s
E Energy Joule
E Electric field V/m
Ea Acceptor energy Joule
Ec Conduction band energy of a semiconductor Joule
Ed Donor energy Joule
EF Fermi energy (thermal equilibrium) Joule
Eg Energy bandgap of a semiconductor Joule
Ei Intrinsic Fermi energy Joule
Ev Valence band energy of a semiconductor Joule
Evacuum Electron energy in vacumm Joule
f(E) Distribution function (probability density function)
Fn Quasi-Fermi energy of electrons Joule
Fp Quasi-Fermi energy of holes Joule
gc(E) Density of states in the conduction band per unit m-3J-1
energy per unit volume
gv(E) Density of states in the valence band per unit energy m-3J-1
per unit volume
Gn Electron generation rate m-3s-1
Gp Hole generation rate m-3s-1
h Plank's constant Js
ħ Reduced Plank's (= h /2) Js
I Current A
J Current density A/m2
Jn Electron current density A/m2
Jp Hole current density A/m2
kB Boltzmann's constant J/K
l Mean free path m
L Length m
631

Ln Electron diffusion length m
Lp Hole diffusion length m
m Mass kg
m0 Free electron mass kg
me* Effective mass of electrons kg
mh* Effective mass of holes kg
n Electron density m-3
ni Intrinsic carrier density m-3
n(E) Electron density per unit energy and per unit volume m-3
n0 Electron density in thermal equilibrium m-3
ni Intrinsic carrier density m-3
N Doping density
Na Acceptor doping density m-3
Na- Ionized acceptor density m-3
NB Base doping density m-3
Nc Effective density of states in the conduction band m-3
NC Collector doping density m-3
Nd Donor doping density m-3
Nd+ Ionized donor density m-3
NE Emitter doping density m-3
Nv Effective density of states in the valence band m-3
p Hole density m-3
p(E) Hole density per unit energy m-3
p0 Hole density in thermal equilibrium m-3
pn Hole density in an n-type semiconductor m-3
q electronic charge C
Q Charge C
Qd Charge density per unit area in the depletion layer C/m2
of an MOS structure
Qd,T Charge density per unit area at threshold in the C/m2
depletion layer of an MOS structure
Qi Interface charge density per unit area C/m2
R Resistance Ohm
Rn Electron recombination rate m-3s-1
Rp Hole recombination rate m-3s-1
t Thickness m
tox Oxide thickness m
632

T Temperature Kelvin
Un Net recombination rate of electrons m-3s-1
Up Net recombination rate of holes m-3s-1
v Velocity m/s
vth Thermal velocity m/s
Va Applied voltage V
VB Base voltage V
VC Collector voltage V
VD Drain voltage V
VE Emitter voltage V
VFB Flatband voltage V
VG Gate voltage V
Vt Thermal voltage = kB T/ e V
VT Threshold voltage of an MOS structure V
VTN Threshold voltage of an NMOS structure V
VTP Threshold voltage of an PMOS structure V
w Depletion layer width m
wB Base width m
wC Collector width m
wE Emitter width m
wn Width of an n-type region m
wp Width of a p-type region m
x Position m
xd Depletion layer width in an MOS structure m
xd,T Depletion layer width in an MOS structure at m
threshold
xj Junction depth m
xn Depletion layer width in an n-type semiconductor m
xp Depletion layer width in a p-type semiconductor m
 Transport factor
 Current gain
 Body effect parameter V1/2
E Emitter efficiency
n Excess electron density m-3
p Excess hole density m-3
633

Qn,B Excess electron charge density in the base C/m2
ox Dielectric constant of the oxide F/m
s Dielectric constant of the semiconductor F/m
n Electron mobility m2/V-s
p Hole mobility m2/V-s
 Charge density per unit volume C/m3
Resistivity m
ox Charge density per unit volume in the oxide C/m3
 Conductivity m-1
n Electron lifetime s
p Hole lifetime s
 Potential V
B Barrier height V
F Bulk potential V
i Built-in potential of a p-n diode or Schottky diode V
s Potential at the semiconductor surface V
M Workfunction of the metal V
MS Workfunction difference between metal V
semiconductor
S Workfunction of the semiconductor V
 Electron affinity of the semiconductor V
634
Appendix B: SPICE Model of a P-N Junction Diode
General Form
D<name> <anode> <cathode> <model name> [area value]
Examples
DCLAMP 14 0 DMOD D13 15 17 SWITCH 1.5
Model Form
.MODEL <model name> D [model parameters]
Description The diode is modeled as an ohmic resistance (RS/area) in

series with an intrinsic diode. Positive current is current flowing from the
anode through the diode to the cathode
The following table contains the model parameters for the P-N junction
diode model. Note that the diode current is considered to have an
additional component, due to recombination in the space charge region:
  V     Vd  
I d  I o exp  d  
  or exp 
1 I   1 (B-1)
  .VT     r .VT  
635
Table B-1. Diode Model parameters
Name Symbol Description Unit Default

Is Io Reverse saturation current A 10-14
N  emission coefficient 1
Isr Ior recombination current parameter A 0
Nr r emission coefficient for Ior 2
Rs Rs Ohmic resistance  0
Cj0 Cj0 zero-bias junction capacitance F 0
M M grading coefficient 0.6
Vj Vj junction potential V 0.7
Fc Fc forward-bias depletion capacitance coefficient 0.5
Cp Cp linear capacitance F 0
Tt  transit time s 0

Bv VB reverse breakdown voltage V
Ibv IBv current at reverse breakdown voltage A 0.001
Kf Kf flicker noise coefficient 0
Af Af flicker noise exponent 1
Ffe Ffe flicker noise frequency exponent 1
Temp T device temperature 27
Xti Xti saturation current exponent 3
Eg Eg energy bandgap eV 1.11
Tnom To temperature of parameters extraction 27
Area A default area for diode 1
636
APPENDIX C : SPICE Model of JFET

General Form
J<name> <drain node> <gate node> <source node> <model
name> +[area value]
Examples
JIN 100 1 0 JFAST J13 22 14 23 JNOM 2.0
Model Form
.MODEL <model name> NJF [model parameters]
.MODEL <model name> PJF [model parameters]
Model The JFET is modeled as an intrinsic FET using an Ohmic

resistance (RD/area) in series with the drain, and using another ohmic
resistance (RS/area) in series with the source. Positive current is current
flowing into a terminal.
637
Table C=1. JFET Model Parameters
PARAMETERS DESCRIPTION UNITS DEFAULT

AF flicker noise exponent 1
ALPHA ionization coefficient -1 volt 0
BETA transconductance coefficient amp/volt2 1E-4
BETATCE BETA exponential /°C 0
temperature coefficient
CGD zero-bias gate-drain p-n farad 0
capacitance
CGS zero-bias gate-source p-n 0
capacitance farad
FC forward-bias depletion 0.5
capacitance coefficient
IS gate p-n saturation current amp 1E-14
ISR gate recombination current amp 0
parameter
KF flicker noise coefficient 0
LAMBDA channel-length modulation 1/volt 0
M gate p-n grading coefficient 0.5
N gate p-n emission coefficient 1
NR emission coefficient for isr 2
PB gate p-n potential volt 1.0
RD drain ohmic resistance ohm 0
RS source ohmic resistance ohm 0
T_ABS absolute temperature °C
T_MEASURED measured temperature °C
T_REL_GLOBAL relative to current temperature °C
T_REL_LOCAL relative to AKO model °C
temperature
VK ionization knee voltage volt 0
VTO threshold voltage volt -2.0
VTOTC VTO temperature coefficient volt/°C 0
XTI IS temperature coefficient 3
638
APPENDIX D : SPICE Model of BJT

General Form
Q<name> < collector node> <base node> <emitter node> [substrate
node] <model name> [area value]
Examples
Q1 14 2 13 PNPNOM
Q13 15 3 0 1 NPNSTRONG 1.5
Q7 VC 5 12 [SUB] LATPNP
Model Form
.MODEL <model name> NPN [model parameters]
.MODEL <model name> PNP [model parameters]
.MODEL <model name> LPNP [model parameters]
Arguments and Options

[substrate node] is optional, and if not specified, the default is the ground.
[area value] is the relative device area and has a default value of 1.
Description The bipolar transistor is modeled as an intrinsic transistor

using ohmic resistances in series with the collector (RC/area), with the
base (value varies with current, see Bipolar Transistor
Equations), and with the emitter (RE/area).
639
Table D-1. BJT model parameters

AF flicker noise exponent 1.0
BF ideal maximum forward beta 100.
BR ideal maximum reverse beta 1.0
CJC base-collector zero-bias p-n farad 0.0
capacitance
CJE farad base-emitter zero-bias p-n 0.0
capacitance
CJS (CCS) substrate zero-bias p-n farad 0.0
capacitance
EG bandgap voltage (barrier eV 1.11
height)
FC forward-bias depletion 0.5
capacitor coefficient
GAMMA epitaxial region doping factor 1E-11
IKF (IK) corner for forward-beta high- amp infinite
current roll-off
IKR corner for reverse-beta high- amp infinite
current roll-off
IRB current at which Rb falls amp infinite
halfway to
IS transport saturation current amp 1E-16
ISC (C4) base-collector leakage amp 0.0
saturation current
ISE (C2) base-emitter leakage amp 0.0
saturation current
ISS substrate p-n saturation amp 0.0
current
ITF transit time dependency on Ic amp 0.0
KF flicker noise coefficient 0.0
MJC (MC) base-collector p-n grading 0.33
factor
MJE (ME) base-emitter p-n grading 0.33
factor
MJS (MS) substrate p-n grading factor 0.0
640

NC base-collector leakage 2.0
emission coefficient
NE base-emitter leakage 1.5
emission coefficient
NF forward current emission 1.0
coefficient
NK high-current roll-off 0.5
coefficient
NR reverse current emission 1.0
coefficient
NS substrate p-n emission 1.0
coefficient
PTF excess phase @ 1/(2·TF) degree 0.0
QCO epitaxial region charge coulomb
factor
RB zero-bias (maximum) base ohm 0.0
resistance
RBM minimum base resistance ohm RB
RC collector ohmic resistance ohm 0.0
RCO epitaxial region resistance ohm 0.0
RE emitter ohmic resistance ohm 0.0
TF ideal forward transit time sec 0.0
TR ideal reverse transit time sec 0.0
TRB1 RB temperature coefficient °C-1 0.0
(linear)
TRB2 RB temperature coefficient °C-2 0.0
(quadratic)
TRC1 RC temperature coefficient °C-1 0.0
(linear)
TRC2 RC temperature coefficient °C-2 0.0
(quadratic)
TRE1 RE temperature coefficient °C-1 0.0
(linear)
TRE2 RE temperature coefficient °C-2 0.0
(quadratic)
TRM1 RBM temperature °C-1 0.0
coefficient (linear)
TRM2 RBM temperature °C-2 0.0
coefficient (quadratic)
641

T_ABS absolute temperature °C
T_MEASURED measured temperature °C
T_REL_GLOBAL relative to current °C
temperature
T_REL_LOCAL relative to AKO model °C
temperature
VAF (VA) forward Early voltage volt infinite
VAR (VB) reverse Early voltage volt infinite
VJC (PC) base-collector built-in volt 0.75
potential
VJE (PE) base-emitter built-in volt 0.75
potential
VJS (PS) substrate p-n built-in volt 0.75
potential
VO carrier mobility knee voltage volt 10.0
VTF transit time dependency on volt infinite
Vbc
XCJC fraction of CJC connected 1.0
internally to Rb
XCJC2 fraction of CJC connected 1.0
internally to Rb
XTB forward and reverse beta 0.0
temperature coefficient
XTF transit time bias dependence 0.0
coefficient
XTI (PT) IS temperature effect 3.0
exponent
642
APPENDIX E : SPICE Model of MOSFET

General Form:
M<name> <drain node> <gate node> <source node>
+ <bulk/substrate node> <model name>
+ [L=<value>] [W=<value>]
+ [AD=<value>] [AS=<value>]
+ [PD=<value>] [PS=<value>]
+ [NRD=<value>] [NRS=<value>]
+ [NRG=<value>] [NRB=<value>]
+ [M=<value>]
Examples
M1 14 2 13 0 PNOM L=25u W=12u
M13 15 3 0 0 PSTRONG
M16 17 3 0 0 PSTRONG M=2
M28 0 2 100 100 NWEAK L=33u W=12u AD=288p AS=288p +
PD=60u PS=60u NRD=14 NRS=24 NRG=10
Model Form
.MODEL <model name> NMOS [model parameters]
.MODEL <model name> PMOS [model parameters]
Description The MOSFET is modeled as an intrinsic MOSFET using

ohmic resistances in series with the drain, source, gate, and bulk
(substrate). There is also a shunt resistance (RDS) in parallel with the
drain-source channel
The simulator provides six MOSFET device models, which differ in the
formulation of the I-V characteristic. The LEVEL parameter selects
between different models as follows.
LEVEL=1 Shichman-Hodges model (see reference [1])

LEVEL=2 geometry-based, analytic model (see reference [2])
LEVEL=3 semi-empirical, short-channel model (see reference [2])
LEVEL=4 BSIM model (see reference [3])
LEVEL=5 (No longer supported.)
LEVEL=6 BSIM3 model version 2.0 (see reference [7])
LEVEL=7 BSIM3 model version 3.0 (see reference [8])
643
Table E-1. MOSFET model parameters
Parameter Description Unit Default

AF flicker noise exponent 1
CBD zero-bias bulk-drain p-n farad 0
capacitance
CBS zero-bias bulk-source p-n farad 0
capacitance
CGBO gate-bulk overlap farad/meter 0
capacitance/channel length
CGDO gate-drain overlap farad/meter 0
capacitance/channel width
CGSO gate-source overlap farad/meter 0
capacitance/channel width
CJ bulk p-n zero-bias bottom farad/meter2 0
capacitance/area
CJSW bulk p-n zero-bias sidewall farad/meter 0
capacitance/length
FC bulk p-n forward-bias 0.5
capacitance coefficient
GDSNOI channel shot noise coefficient 1
(use with NLEV=3)
644

IS bulk p-n saturation current amp 1E-14
JS bulk p-n saturation amp/meter2 0
current/area
JSSW bulk p-n saturation sidewall amp/meter 0
current/length
KF flicker noise coefficient 0
L channel length meter DEFL
LEVEL model index 1
MJ bulk p-n bottom grading 0.5
coefficient
MJSW bulk p-n sidewall grading 0.33
coefficient
N bulk p-n emission coefficient 1
NLEV noise equation selector 2
PB bulk p-n bottom potential volt 0.8
PBSW bulk p-n sidewall potential volt PB
RB bulk ohmic resistance ohm 0
RD drain ohmic resistance ohm 0
RDS drain-source shunt resistance ohm infinite
RG gate ohmic resistance ohm 0
RS source ohmic resistance ohm 0
RSH drain, source sheet resistance ohm/square 0
TT bulk p-n transit time sec 0
645
646
APPENDIX F : SPICE Model of IGBT

General Form
Z<name> <collector> <gate> <emitter> <model name [AREA=<value>]
+ [WB=<value>] [AGD=<value>] [KP=<value>] [TAU=<value>]
Examples
ZDRIVE 1 4 2 IGBTA AREA=10.1u WB=91u AGD=5.1u KP=0.381
Z231 3 2 9 IGBT27
Model Form
.MODEL <model name> NIGBT [model parameters]
Description The equivalent circuit for the IGBT is shown below. It is

modeled as an intrinsic device (not as a subcircuit) and contains five DC
current components and six charge (capacitive) components. An overview
of the model equations is included below.
647
Imos = MOSFET channel current

IT = anode current
Icss = steady-state (bipolar) collector current
Ibss = Steady-state base current
Imult = avalanche multiplication current
Rb = conductivity modulated base resistance
b = ambipolar mobility ratio
Dp = diffusion coefficient for holes
W = quasi-neutral base width
Qeb = instantaneous excess carrier base charge
Qb = background mobile carrier charge
ni = intrinsic carrier concentration
M = avalanche multiplication factor
Igen = (bipolar)collector-base thermally generated current
si = dielectric permittivity of silicon
q = electron charge
Wbcj = base (bipolar) to collector depletion width
Table F-1: Parameters of IGBT Model

AGD gate-drain overlap area m2 5.0E-6
AREA area of the device m2 1.0E-5
BVF avalanche uniformity factor none 1.0
BVN avalanche multiplication exponent none 4.0
CGS gate-source capacitance per unit area F/cm2 1.24E-8
COXD gate-drain oxide capacitance per unit F/cm2 3.5E-8
area
JSNE emitter saturation current density A/cm2 6.5E-13
KF triode region factor none 1.0
KP MOS transconductance A/V2 0.38
MUN electron mobility cm2/(V·s) 1.5E3
MUP hole mobility cm2/(V·s) 4.5E2
NB base doping 1/cm3 2.E14
TAU ambipolar recombination lifetime sec 7.1E-6
THETA transverse field factor 1/V 0.02
VT threshold voltage V 4.7
VTD gate-drain overlap depletion V 1.E-3
threshold
WB metallurgical base width m 9.0E-5
648
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Fundamentals of Electronic Devices & Circuits (from A to Z)

Book · January 2010

Muhammad Hamza El-Saba

Advanced Electronic Engineering Encyclopedia (AEEE) View project

Modelling & Numerical Simulation of Superconductors View project

The user has requested enhancement of the downloaded file.

Prof. Dr. Muhammad EL-SABA

Copyright © 2001-2010, by the author. All rights reserved.

1st Edition 2001

Reproduction or translation of any part of this work, without permission

This book gives an introduction to electronic devices. The book covers

A proper background in undergraduate-level quantum mechanics,

Prof. Dr. Muhammad EL-SABA

CHAPTER 1: Introduction to Electronic Devices 1

1-1. Energy Band Theory in Solids 3

CHAPTER 2: P-N Junctions 43

2-1. Chapter Overview & Learning Objectives 45

2-17. Chapter Assessment 127

CHAPTER 3: Bipolar Junction Transistor 131

3-1. Chapter Overview and Learning Objectives 133

3-16. Other BJT Structures 189

CHAPTER 4: Metal-Semiconductor (M-S) Contacts 211

4-1. Chapter Overview & Learning Objectives 213

CHAPTER 5: Junction Field Effect Transistor (JFET) 245

5-1. Chapter Overview and Learning Objectives 247

CHAPTER 6: Metal-Oxide-Semiconductor (MOS) Structure 269

6-1. Chapter Overvieew & Learning Objectives 271

CHAPTER 7: MOS Field Effect Transistor (MOSFET) 301

7-1. Chapter Overview & Learning Objectives 303

CHAPTER 8: Semiconductor Power Devices 351

8-1. Overview and Learning Objectives 353

8-2.2. Power BJT 366

Chapter 9: Memory Devices 447

9-1. Overview and Learning Objectives 449

Chapter 10: Low-dimensional Structures & Quantum Devices 509

10-1. Introduction & Learning Objectives 511

Chapter 11 Nanowires, Nanotubes and NanoDevices 547

11-1. Overview & Learning Objectives 549

Chapter 12: Spintrobic Devices 601

12-1. Overview & Learning Objectives 603

12-3.2. Bir-Aranov-Pikus (BAP) Mechanism 608

Introduction to Electronic Devices

1-1. Energy Band Theory in Solids

Upon completion of this Chapter, students should:

Understand the fundamentals of solid-state physics, such as the energy

2-1. Energy Band Theory in Solids

1-1.1. Energy Levels and Energy Bands in Solids

As the electron clouds of individual atoms are overlapped, the height of

Figure 1-2 shows the development of the one-electron energy bands in

1-1.2. Conductors and Insulators

An electric current is made up of the flow of free electrons. This means

Metals are all conductors of electricity, and a number of other substances

Fig. 1-4. Classification of solids into conductors, semiconductors and insulators.

1-2, Intrinsic & Extrinsic Semiconductors

Figure 1-5. Illustration of the covalent bond

The density of the quasi-free electrons in a semiconductor is called the

1-2.1. N-type and P-type Semiconductors

It is also possible to place elements with only three electrons in their

Fig. 1-6. Types of semiconductors.

Fig. 1-7. Doping elements.

1017 [atom / cm3 ]

1-2.2. Majority and Minority Carriers