US006014735A

Ulllted States Patent [19] [11] Patent Number: 6,014,735

Chennupaty et al. [45] Date of Patent: Jan. 11, 2000

[54] INSTRUCTION SET EXTENSION USING 5,845,102 12/1998 Miller et a1. .......................... .. 712/211
PREFIXES
OTHER PUBLICATIONS

[75] Inventors: $231372: kalllzcgulsilszfkmg; Visual Instruction Set (VIS) User’s Guide, Sun Microsys
Shreekant S- ’Thakkar gin of port’land terns, Version 1.1, Mar. 1997, pp. i—xii, 1—127.
Oreg ’ ’ AMD—3D Technology Manual, Advance Micro Devices,
' (AMD), Feb. 1998, pp. i—x, 1—58.
[73] Assignee: Intel Corporation, Santa Clara, Calif. _ _
Primary Examiner—W1ll1arn M. Treat
_ Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor &
[21] Appl. No.. 09/053,391 Zafman LLP
[22] Filed: Mar. 31, 1998 [57] ABSTRACT
[51] Int. Cl.7 ...................................................... .. G06F 9/30 _ _ _
[52] U S C] 712/210 The present invention discloses a method and apparatus for
,' ' ' '''''''''''' '''''''" encoding an instruction in an instruction set Which uses a

[58] Fleld of Search """""""""" 221102’ pre?x code to qualify an existing opcode of an existing
’ ’ ’ instruction. An opcode and an escape code are selected. The
. escape code is selected such that it is different from the
[56] References Clted pre?x code and the existing opcode. The opcode, the escape
U.S. PATENT DOCUMENTS code, and the pre?x code are combined to generate an
5353 420 10/1994 Z _d_
, , a1 1 ..................................... ..
712/210 instruction code Which uniquely represents the operation
- -

5,572,206 11/1996 Miller et a1. .. 341/51 performed by the msmlcnon'

5,619,666 4/1997 Coon et a1. ..... .. 712/208
5,822,559 10/1998 Narayan et a1. ...................... .. 712/214 20 Claims, 5 Drawing Sheets

{- P500

BYTE = Z-BYTE
ESCAPE

BYTE = Z-BYTE BYTE : OTHER

ESCAPE ESCAPE
CODE

V 5565 " B545 B535 ‘ B530

I I I I

DECODE SECOND
DBEYSOEDLFSTSIEW BYTE AS REGULAR DigggigicliwD DECODE AS OTHER DECODE AS oNE
INSTRUCTION WITH INsTRucTIoNs BYTE INSTRUCTION
INSTRUCTION TYPE 1 PREFIX AS QUALIFIER INSTRUCTION TYPE 0

A Y Y Y Y
U.S. Patent Jan. 11,2000 Sheet 1 0f5 6,014,735

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U.S. Patent Jan. 11,2000 Sheet 3 0f5 6,014,735

r- 300

310
,/
INSTRUCTION BUFFER

IN To IN+7 IN To IN+7
IK TO IK+7 IK T0 IK+7
| IM TO IM+7 |
| I
| |
| PREFIX AND -\ 320 |
| ESCAPE |
: DETECTOR :
| |
| |
| |
| |
| V |
| |
| DECODER -\ |
| ENABLE 330 |
: cIRcuIT :
| |
| |
| 340 |
| |
| V I |
| |
| |
: OPCODE DECODER :
| |
| |
| |
L. _______________________________ _ _ _I

TO uINSTRUCTION QUEUE

FIG. 3
U.S. Patent Jan. 11,2000 Sheet 4 0f5 6,014,735

REGULAR
ONE BYTE
DECODER

430

432

REGULAR
PREFIX
DECODER

434

REGULAR
ESCAPE
DECODER

436

I N S T CH o N
TYPE 0
DECODER

438
NEW
INSTRUCTION
TYPE 1
DECODER
 6,014,735
1 2
INSTRUCTION SET EXTENSION USING FIG. 1 is a diagram illustrating one embodiment of a
PREFIXES computer system 100 in accordance With the teachings of the
BACKGROUND OF THE INVENTION present invention.
1. Field of the Invention FIG. 2 is a diagram illustrating a format of an instruction
200 in according to one embodiment of the invention.
This invention relates to microprocessor systems. In
particular, the invention relates to instruction set extension FIG. 3 is a diagram illustrating a circuit 300 to decode the
using pre?xes. instruction according to one embodiment of the invention.
2. Description of Related Art FIG. 4 is a diagram illustrating the pre?x and escape
Microprocessor technology has evolved over the years at 10
detector 320, the decoder enable circuit 330, and the opcode
a fast rate. Advances in computer architecture and semicon decoder 340 according to one embodiment of the invention.
ductor technology have created many opportunities to FIG. 5 is a ?oWchart illustrating a process P500 to
design neW processors. There are typically tWo options for perform instruction decoding using pre?xes according to
designing neW processors: (1) de?ning a completely neW one embodiment of the invention.
architecture, and (2) extending the current architecture to
accommodate neW features. Each option has both advan 15
DESCRIPTION OF THE PRESENT INVENTION
tages and disadvantages. HoWever, When a processor has
captured a signi?cant market segment, option (2) offers A method and apparatus for extending an instruction set
many attractive advantages. The main advantage of extend using pre?xes is disclosed. The method uses a set of existing
ing the current architecture is the compatibility With current pre?x codes to de?ne a neW set of instructions. The method
and earlier models. The disadvantages include the problems provides a fast and ef?cient mechanism to decode the neW
of getting out of the constraints imposed by the earlier instruction set.
designs. In the folloWing description, for purposes of explanation,
NeW processors involve neW features in both hardWare numerous details are set forth in order to provide a thorough
and softWare. A neW processor based on existing design understanding of the present invention. HoWever, it Will be
typically has an additional set of instructions that can take 25 apparent to one skilled in the art that these speci?c details
advantage of the neW hardWare design. HoWever, extending are not required in order to practice the present invention. In
an instruction set by adding a neW set of instructions is a other instances, Well knoWn electrical structures and circuits
challenging problem because of the constraints in the encod are shoWn in block diagram form in order not to obscure the
ing of the instructions.
present invention. In the folloWing description, the notation
When an instruction set is originally developed, the 0>< indicates the number that folloWs is in hexadecimal
typical approach is to encode the instructions With a mini
format.
mum number of bits to leave room for future expansion.
HoWever, as the architecture evolves and becomes more and FIG. 1 is a diagram illustrating one embodiment of a
more mature, more and more instructions are de?ned. processor 110 in accordance With the teachings of the
Eventually, there Will be a point Where there is no more 35 present invention.
space for encoding the instructions. The processor 110 represents a central processing unit of
One solution to the problem is to eliminate some of the any type of architecture, such as complex instruction set
older instructions. HoWever, this solution reduces the com computers (CISC), reduced instruction set computers
patibility to the earlier processors. SoftWare Written for the (RISC), very long instruction Word (VLIW), multi-threaded
earlier processors may not Work for the neW design. Another or hybrid architecture.
solution is to narroW the neW instruction set to only a group FIG. 1 illustrates that the processor 110 includes a decode
of selective instructions to accommodate the little room left unit 116, a set of registers 114, an execution unit 112, and an
in the available opcode table. The solution results in poorer internal bus 111 for executing instructions. Of course, the
performance because it sacri?ces many advanced features processor 110 contains additional circuitry, Which is not
offered by the neW design. Yet, another solution is to de?ne necessary to understanding the invention. The decode unit
45
a set of neW opcodes Which is different than the existing 116, registers 114 and execution unit 112 are coupled
opcodes. The problems With this solution include the com together by the internal bus 111. The decode unit 116 is used
plexity of the decoding circuitry Which occupies a large chip for decoding instructions received by processor 110 into
area and may not scale Well With the processor frequency. control signals and/or microcode entry points. In response to
Therefore there is a need in the technology to provide an these control signals and/or microcode entry points, the
ef?cient method for extending an instruction set Without execution unit 112 performs the appropriate operations. The
increasing hardWare complexity. decode unit 116 may be implemented using any number of
SUMMARY OF THE INVENTION different mechanisms (e.g., a look-up table, a hardWare
The present invention discloses a method and apparatus implementation, a PLA, etc.).
for encoding an instruction in an instruction set Which uses 55 The decode unit 116 is shoWn including an instruction set
a pre?x code to qualify an existing opcode of an existing 118 for performing operations on scalar and packed data.
instruction. An opcode and an escape code are selected. The The number format for these operations can be any conve
escape code is selected such that it is different from the nient format, including single-precision, double-precision,
pre?x code and the existing opcode. The opcode, the escape and extended ?oating-point numbers, signed and unsigned
code, and the pre?x code are combined to generate an integers, and non-numeric data. The instruction set 118
instruction code Which uniquely represents the operation includes an existing instruction set 118a, a neW instruction
performed by the instruction. set 118b. In particular, the instruction format of the instruc
tion set includes a pre?x 118C.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the invention Will become 65
Instruction Format
apparent from the folloWing detailed description of the FIG. 2 is a diagram illustrating a format of an instruction
invention in which: 200 according to one embodiment of the invention. The
 6,014,735
3 4
instruction 200 includes a pre?x ?eld 210, an opcode ?eld The escape code provides an extension to the instruction
220, and operand speci?er ?elds (e.g., modR/M, scale set. For example, the escape codes 0><D8 through 0><DF are
index-base, displacement, immediate, etc.). The operand used to indicate that the opcode that folloWs belongs to the
speci?er ?elds are optional and include a modR/M ?eld 230, ?oating-point unit. The decoder Will pass the opcode to the
an SIB ?eld 240, a displacement ?eld 250, and an immediate ?oating-point decoder. In one embodiment, a tWo-byte
?eld 260. escape code, 0><0F, indicates that the opcode that folloWs
The pre?x ?eld 210 includes a number of pre?xes. In one de?nes a neW instruction set. Although the escape code
embodiment, the pre?x ?eld 210 includes up to four alloWs enlargement of the instruction set further, the addi
pre?xes, each pre?x is one byte. The pre?x ?eld 210 is tional number of opcodes is still limited.
optional. For the extended neW instruction set, hoWever, the The combination of the pre?x and the escape code pro
pre?x ?eld is required to encode the neW instructions. vides a signi?cant enlargement of the opcode table to alloW
The opcode ?eld 220 speci?es the operation. For the additional neW instruction sets. This combination uses the
extended neW instruction set, the opcode ?eld 220 is com existing pre?x codes to de?ne a completely neW set of
bined With the pre?x ?eld 210 to de?ne an operation. In one instructions, in addition to the instruction set created by the
embodiment, the opcode ?eld 220 may include one or tWo escape code. By using the existing pre?x codes, the decod
15
bytes. ing circuitry for the existing instruction set remains essen
The combination of the pre?x ?eld 210 and the opcode tially the same. Although the decoding circuitry Will have to
?eld 220 creates a number of different types of instruction be modi?ed to accommodate this combination, the modi?
set. For illustrative purposes, FIG. 2 shoWs only ?ve types cation is merely a modular add-on With minimal changes to
of instructions: a regular one-byte instruction 212, a regular existing design.
instruction With pre?x as quali?er 214, a regular escape The opcodes of some or all of the neW instructions may
instruction 216, a ?rst neW instruction type 222, and a be the same as the opcodes of the existing instructions. By
second neW instruction type 224. As is knoWn by one skilled using the same opcodes With the pre?x and escape codes to
in the art, other types of instruction can be similarly de?ned. de?ne a brand neW set of instructions, the decoding circuitry
The regular one-byte instruction 212 includes regular is much less complex than having a completely neW set of
instructions With one-byte opcodes. The regular instruction 25 opcodes for the neW instruction set.
With pre?x as quali?er 214 includes regular instructions In one embodiment, the repeat pre?x 0><F3 is used to
Which use the pre?x as a quali?er for the opcode. For de?ne a neW instruction set. Other pre?xes can be similarly
example, a string instruction may use a REPEAT pre?x to used. Furthermore, pre?xes can still be used in the tradi
repeat the string instruction by a number of times speci?ed tional role of enhancing the opcode or qualifying the opcode
in the count register or until a certain condition is met. The under some operational condition. For example, the address
pre?x used in instruction 214 does not add a completely neW siZe pre?x can still be used to affect the neW instruction With
meaning to the opcode that folloWs. Rather, the pre?x is memory operand.
merely used as a quali?er to qualify the opcode With The folloWing are examples of the neW instruction set
additional conditions. As Will be explained later, the use of using pre?xes and escape codes.
the pre?x in the instruction 214 is markedly different from 35 Instruction Opcode (in Hex) De?nition
that in the instruction 224. The regular escape instruction
216 is a regular instruction that escapes to other types of ADDPS OF, 58 Packed single FP add
instruction. For example, in one embodiment, a ?oating ADDSS F3, OF, 58 Scalar single FP add
point coprocessor escape code 0><D8 through 0><DF indi CMPPS OF, C2 Packed single FP compare
cates that the opcode that folloWs should be interpreted as CMPSS F3, OF, C2 Scalar single FP compare
DIVPS OF, 5E Packed single FP divide
coprocessor instructions. DIVSS F3, OF, 5E Scalar single FP divide
The ?rst neW instruction type 222 (or the neW instruction MAXPS OF, 5F Packed single FP maximum
type 0) is a neW instruction that is part of the neW instruction MAXSS F3, OF, 5F Scalar single FP maximum
MINPS OF, 5D Packed single FP minimum
set to be added to the existing regular instruction set. The MINSS F3, OF, 5D Scalar single FP minimum
neW instruction type 0 uses a special escape code, called a 45
MOVUPS OF, 10/11 Move unaligned Packed single FP
tWo-byte escape code. In one embodiment, the tWo-byte MOVSS F3, OF, 10/11 Move scalar single FP
escape code is 0><0F. For the instruction 222, the opcode that MULPS OF, 59 Packed single FP multiply
MULSS F3, OF, 59 Scalar single FP multiply
folloWs the 2-bye escape code should be decoded as a neW SUBPS OF, 5C Packed single FP subtract
instruction. The second neW instruction type 224 (or the neW SUBSS F3, OF, 5C Scalar single FP subtract
instruction type 1) uses the pre?x as part of the opcode.
Unlike the instruction 214 Where the pre?x merely quali?es
the opcode that folloWs, the instruction 224 uses the pre?x In the above examples, the instruction set Without the
to de?ne a completely neW instruction. The use of the pre?x pre?x 0><F3 relates to operations on packed data, While the
together With the escape code enlarges the instruction instruction set With the pre?x 0><F3 relates to operations on
opcode table Without signi?cant changes in the decoding 55 scalar data.
circuitry. In addition, no neW opcodes are used so that there In one embodiment, the set of pre?x codes are: an address
is room for neW instructions in the future. Examples of these siZe pre?x code (0x67), an operand siZe pre?x code (0x66),
instructions Will be given later. a segment override pre?x code (0><2E, 0x36, 0><3E, 0x26,
0x64, 0x65), a repeat pre?x code (0><F3), a repeat While
Examples of Instruction Pre?xes and Escape Codes equal pre?x code (0><F3), a repeat While not equal code
Instruction pre?xes are originally developed to enhance a (0><F2), and a lock pre?x code (0><F0). As is knoWn by one
set of instructions. For example, the repeat pre?x is devel skilled in the art, the exact codes for these pre?xes are
oped to repeat a string instruction. The repeat pre?x codes implementation-dependent, the above pre?x codes are
are 0><F3 (REP, REPE) and 0><F2 (REPNE). The pre?x does merely for illustrative purposes. Furthermore, not all the
not de?ne a neW meaning for the opcode that folloWs. It 65 pre?x codes are available for encoding the neW instruction
merely de?nes additional operational conditions for the set. Some pre?xes may result in illegal mode or may not be
opcode. recogniZed.
 6,014,735
5 6
Instruction Decoding Using Pre?xes corresponds to the condition Where the instruction bits IN to
FIG. 3 is a diagram illustrating a circuit 300 to decode the IN+7 match the pre?x code but the instruction bits IK to IK+7
instruction. The circuit 300 includes an instruction buffer do not match the 2-byte escape code. Therefore this condi
310, a pre?x and escape detector 320, a decoder enable tion corresponds to an opcode using the pre?x as a quali?er
circuit 330, and an opcode decoder 340. The pre?x and of a regular instruction.
escape detector 320, the decoder enable circuit 330, and the The ESC1 signal is used as the EN3 signal. This signal is
opcode decoder 340 form a portion of the decode unit 116 asserted When the instruction bits IN to IN+7 match the
in FIG. 1. ?oating-point escape code. Therefore this condition corre
The instruction buffer 310 stores the instructions fetched sponds to a ?oating-point opcode of a regular instruction.
from the external memory. Typically, the instruction buffer 10
The ESC2A signal is used as the EN4 signal. This signal
310 is implemented as an instruction cache. For illustrative
purposes, an instruction is assumed to comprise three bytes: is asserted When the instruction bits IN to IN+7 match the
The ?rst byte corresponds to IN to IN”, the second byte 2-byte escape code. Therefore this condition corresponds to
corresponds to IK to IK+7, and the third byte corresponds to an opcode of a neW instruction type 0.
IM to IM+7, Where IN to IN”, IK to IK+7, and IM to IM+7 refer 15
The AND gate 424 asserts the ENS signal When the PRFX
to the bit positions of the instruction Word. and ESC2B signals are asserted. This condition corresponds
The pre?x and escape detector 320 receives the instruc to the condition Where the instruction bits IN to IN+7 match
tion bits IN to IN”, IK to IK+7, and detects a set of prede?ned the pre?x code and the instruction bits IK to IK+7 match the
pre?xes and/or escape codes used as part of the neW instruc 2-byte escape code. Therefore this condition corresponds to
tion set. The values of these pre?xes are selected so that they an opcode of a neW instruction type 1.
are the same as those pre?xes that are used for the regular The opcode decoder 340 includes a regular one-byte
instruction set. The decoder enable circuit 330 combines the decoder 430, a regular pre?x decoder 432, a regular escape
results of the pre?x and escape detector 320 to generate decoder 434, a neW instruction type 0 decoder 436, and a
enable or select signals to the individual opcode decoder. neW instruction type 1 decoder 438. These decoders essen
The opcode decoder 340 receives the instruction bits IN to tially perform the decoding functions for the instruction as
25
IN”, IK to IK+7, and IM to IM” and performs the decoding speci?ed by the instruction opcodes in instruction bits IN to
function for the individual types of instructions. IN+7 and IK to IK+7. Although these decoders are shoWn in
FIG. 4 is a diagram illustrating the pre?x and escape separate blocks, in practice the decoding of these instruc
detector 320, the decoder enable circuit 330, and the opcode tions are combined.
decoder 340. For illustrative purposes, it is assumed that FIG. 5 is a ?oWchart illustrating a process P500 to
there is one 0><F3 pre?x, and tWo escape codes, the 0><D8 perform instruction decoding using pre?xes.
0><DF and 0><0F.
At START, the process P500 enters block B510 to decode
The pre?x and escape detector 320 includes 4 AND gates
the ?rst byte, or the instruction bits IN to IN”. Then the
410, 412, 414, and 416. The AND gates 410, 412, and 414 process P500 enters block B515 to determine if the ?rst byte
match the instruction bits IN to IN+7 With the corresponding 35
pre?x code and escape code. The AND gate 410 matches the is a valid pre?x code (e.g., 0><F3). If NO, the process P500
enters block B520. If YES, the process P500 enters block
instruction bits IN to IN+7 With the pre?x code, 0><F3, and B550.
generates a signal PRFX. The signal PRFX is asserted if the
instruction bits IN to IN+7 represent the pre?x 0><F3. The At block B520, the process P500 determines if the ?rst
AND gate 412 matches the instruction bits IN to IN+7 With byte is a 2-byte escape code. If NO, the process P500 enters
the escape code, 0><D8-0><DF, and generates a signal ESC1. block B525. If YES, the process P500 enters block B540. At
The signal ESC1 is asserted if the instruction bits IN to IN+7 block B525, the process P500 determines if the ?rst byte is
represent the escape code 0><D8 to 0><DF. The AND gate 414 other escape code (e.g., ?oating-point escape code). If NO,
matches the instruction bits IN to IN+7 With the 2-byte escape the process P500 enters block B530 to decode the ?rst byte
code, 0><0F, and generates a signal ESC2A. The signal as a one-byte regular instruction. If YES, the process P500
45
ESC2A is asserted if the instruction bits IN to IN+7 represent enters block B532 to obtain the second byte and then to
the 2-byte escape code 0><0F. The AND gate 416 matches the block B535 to decode the second byte as other regular
instruction bits IK to IK” With the 2-byte escape code, 0><0F, instructions (e.g., ?oating-point instructions). The process
and generates a signal ESC2B. The signal ESC2B is asserted P500 then terminates.
if the instruction bits IK to IK+7 represent the 2-byte escape At block B540, the process P500 obtains the second byte
code 0><0F. As is knoWn by one skilled in the art, other logic and enters block B545 to decode the second byte as a neW
gates can be employed to perform the matching or decoding instruction type 0 (e.g., packed data instructions). The pro
of the instruction bits IN to IN+7 and IK to IK+7. cess P500 then terminates.
The decoder enable circuit 330 receives the PRFX, ESC1, At block B550, the process P500 decodes the second byte,
ESC2A, and ESC2B signals to generate the enable signals to 55 or the instruction bits IK to IK+7. The process P500 then
the individual decoders. The decoder enable circuit 330 enters block B560 to determine if the second byte is a 2-byte
includes a NOR gate 420, an AND gate 422, and an AND escape code. If NO, the process P500 enters block B565 to
gate 424. decode the second byte as an opcode of a regular instruction
The NOR gate 420 asserts the EN1 signal When all the With the pre?x as a quali?er. If YES, the process P500 enters
PRFX, ESC1, and ESC2A are negated. This condition block B570 to obtain the third byte and then block B575 to
corresponds to the condition Where the instruction bits IN to decode the third byte as a neW instruction type 1 (e.g., scalar
IN+7 do not match a pre?x, a ?oating-point escape code, and instructions). The process P500 then terminates.
a 2-byte escape code. Therefore, the instruction bits IN to The present invention provides an ef?cient method to
IN+7 correspond to an opcode of a one-byte regular instruc encode a neW instruction set using existing pre?xes. The
tion. 65 present invention therefore alloWs the neW instruction set to
The AND gate 422 asserts the EN2 signal When the PRFX be as large as necessary Without complicating the instruction
signal is asserted and the ESC2B is negated. This condition decoder.
 6,014,735
7 8
While this invention has been described With reference to code (0x66), a segment override pre?x code (0><2E, 0x36,
illustrative embodiments, this description is not intended to 0><3E, 0x26, 0x64, 0x65), a repeat pre?x code (0><F3), a
be construed in a limiting sense. Various modi?cations of the repeat While equal pre?x code (0><F3), a repeat While not
illustrative embodiments, as Well as other embodiments of equal code (0><F2), and a lock pre?x code (0><F0).
the invention, Which are apparent to persons skilled in the art 10. The method of claim 7 Wherein the escape code is
to Which the invention pertains are deemed to lie Within the 0><0F.
spirit and scope of the invention. 11. The method of claim 7 Wherein the ?rst operation is
What is claimed is: a scalar operation.
1. A method for encoding a ?rst instruction in an instruc 12. The method of claim 8 Wherein the second operation
tion set, the instruction set using a pre?x code to qualify an
is a packed data operation.
existing opcode of an existing instruction, the method com 13. An apparatus for decoding an instruction code issued
prising: from an instruction buffer, the instruction code having a
selecting a ?rst opcode; plurality of ?elds, the apparatus comprising:
selecting an escape code, the escape code being different a pre?x detector coupled to the instruction buffer to
15
from the pre?x code and the existing opcode; and
receive the instruction code and to detect if a ?rst ?eld
combining the ?rst opcode, the escape code, and the of the instruction code matches a pre?x code;
pre?x code to generate a ?rst instruction code, the ?rst
instruction code uniquely representing a ?rst operation an escape detector coupled to the instruction buffer to
performed by the ?rst instruction. receive the instruction code and to detect of a second
2. The method of claim 1 further comprises: ?eld of the instruction code matches an escape code;
and
combining the ?rst opcode and the escape code to gen
erate a second instruction code, the second instruction an opcode decoder coupled to the instruction buffer to
code uniquely representing a second operation per receive the instruction code and to translate one of the
formed by a second instruction. 25 ?rst ?eld, the second ?eld, and a third ?eld of the
3. The method of claim 1 Wherein the pre?x code is one instruction code into a decoded instruction code.
of an address siZe pre?x code (0x67), an operand siZe pre?x 14. The apparatus of claim 13 further comprises:
code (0x66), a segment override pre?x code (0><2E, 0x36, a decoder enable circuit coupled to the pre?x detector and
0><3E, 0x26, 0x64, 0x65), a repeat pre?x code (0><F3), a the escape detector to generate enable signals to enable
repeat While equal pre?x code (0><F3), a repeat While not the opcode decoder.
equal code (0><F2), and a lock pre?x code (0><F0). 15. The apparatus of claim 13 Wherein the pre?x code is
4. The method of claim 1 Wherein the escape code is 0><0F.
one of an address siZe pre?x code (0x67), an operand siZe
5. The method of claim 1 Wherein the ?rst operation is a
scalar operation. pre?x code (0x66), a segment override pre?x code (0><2E,
6. The method of claim 2 Wherein the second operation is 0x36, 0><3E, 0x26, 0x64, 0x65), a repeat pre?x code (0><F3),
35
a packed data operation. a repeat While equal pre?x code (0><F3), a repeat While not
7. Amethod for decoding an instruction code, the instruc equal code (0><F2), and a lock pre?x code (0><F0).
tion code having a plurality of ?elds, the method compris 16. The apparatus of claim 13 Wherein the escape code is
ing: 0><0F.
determining if a ?rst ?eld matches a pre?x code; 17. The apparatus of claim 13 Wherein the opcode decoder
translates the third ?eld into a ?rst decoded instruction code
if the ?rst ?eld matches the pre?x code, determining if a
if the ?rst ?eld matches a pre?x code and the second ?eld
second ?eld matches an escape code; and
matches the escape code, the ?rst decoded instruction code
if the second ?eld matches the escape code, translating a uniquely representing a ?rst operation performed by a ?rst
third ?eld into a ?rst decoded instruction code, the ?rst instruction.
45
decoded instruction code uniquely representing a ?rst 18. The apparatus of claim 13 Wherein the opcode decoder
operation performed by a ?rst instruction. translates the second ?eld into a second decoded instruction
8. The method of claim 7 further comprises: code if the ?rst ?eld matches the escape code, the second
if the ?rst ?eld does not match the pre?x code, determin decoded instruction code uniquely representing a second
ing if the ?rst ?eld matches the escape code; operation performed by a second instruction.
if the ?rst ?eld matches the escape code, translating the 19. The apparatus of claim 17 Wherein the ?rst operation
second ?eld into a second decoded instruction code, the is a scalar operation.
second decoded instruction code uniquely representing 20. The apparatus of claim 18 Wherein the second opera
a second operation performed by a second instruction. tion is a packed data operation.
9. The method of claim 7 Wherein the pre?x code is one
of an address siZe pre?x code (0x67), an operand siZe pre?x * * * * *