POSTAL udy Course 2018 Computer Science & IT Objective Practice Sets el pms] Contents SI. Topic Page No. 4. Basies of Digital Logie 2 2. Boolean Algebra and Minimization Techniques 6 3. Logic Gates and Switching Circuits 12 4. Combinational Logie Circuits 8 5. Sequential Logie Crouts 23 6. Registers a 7. Counters 2 MADE ERSY India Bese Instiote for ES GATE & PES oa aan eaeiesiT roy Q4 Let 2,4, ; ...a;4) be the binary representation of an integer b. The integer bis divisible by 3 (@) The difference of alternates sums, ie. (a+ ayt.) ~ (8,+2y+...) is divisible by 3 (©) The number of ones is divisible by 3 (©) The number of ones is divisible by 3, but not by 9 (@) The number of zeros is divisible by 3 Q2 Convert (3121.121), to base 3? (@) 10022100 (b) 22001.100 (©) 22001101 (a) 10022.110 3. (10110011100011110000), in base 32 are (@) 2214716 (®) 1192831 (o) 11976 (@ 11142316 G4 (22), +(101),~ (20), = (x), +(4),., where x > 4 The value of x is (a) 6 (4 © @e Q.5 The hexadecimal representation of (667), is @ (Ay, (0) (078), ©) O70, (0) GA, Q.6 Convert 10010011 (BCD code) into binary. The value of obtained in binary will be equal to, in decimal Q.7_ Inaparticular number system having base 8. (V4i)g = 5,9- The value of ‘" is Q.8 The number of 18 in the binary representation of (@ * 4096 + 15» 256 + 5 + 16 + 3) are @s 9 © 0 12 Q9 The decimal value 0.25 (@) is equivalent to the binary value 0.1 ore Era Basics of Digital Logic (©) is equivalent to the binary value 0.01 (€) is equivalent to the binary value 0.00111 (@) cannot be represented precisely in binar Q.10 The binary equivalent of the decimal numb: 0.4375 is, (@) 00111 (©) 0.1011 (©) a1100 (@) 0.1010 Q.11 Two numbers ~48 and -23 are added using 2's complement. The 2's complement of the result Using 8 bit representation is. (@) 10141001 (b) 01000111 (© o1t01010 = (a) 11100111 Q.12 A number Nis stored in a 4-bit 2% complement tepreseniationas alalals] E-bit register and alter a fow itis copied into a operations, the final bit pattern is [asTas @ 1 [@ [1 ‘The value of this bit pattern in 2's complement representation is given in terms ofthe original number in Nas 2Ne1 (b) 32a,-2N-1 (8) 2N+t Q.13.4 number in 4-bit two's complement representation is X, X,X, X,, This number when stored using 8-bits wil be @) 0000 XXX, X WNT %GX XH ©) KKK (©) yRsoXsXoXoXMo Q.14 What range of decimal integers can be represented by mbit tw representation? ‘8 complementfa MADE EASY (@) -(2")t0 + (21-1) (©) ~(2" + 1)t0+ (2-1) (©) -(2")t0 + (2-1) 8) -2™)10+ 21) Q.15 The greatest negative number which can be stored in computer that has &-bit word length and uses 2's complement arithmetic is (@) 286 (b) -255 (©) -128 (@) -127 Q.16 Result of the subtraction with the following unsigned decimal numbers by taking the 10's complement of the subtrahend. 1753-8640 (@) 3113 (©) 10393, (c) -6887 (@) 3113 Q.17 Number (+46.5),.canbe represented asafoating point binary number with 24 bits. The normalized fraction mantissa has 1 bits and the exponent has 8 bits. The mantissa of the number is. (@) 0101110100000000 (©) 1001410100000000 (©) 0000011000000000 (@) 0000000001011101 sics of Digital Logic 1 @ 2 © 3 @ 4 @ 5. 12, @ 13, ©) 14 @ 15. © 16. 21. @ wwnmadeeasy.in Postal Study Course BIE] [MADE Ensy Digital Logic | .18 Given that (E08),, compliment of Yis (@) 244 (0) 6264 (ABA) = ¥. The radix 8's (o) 1514 (@ 3251 Q.19 4-bit2's complement representation of a decimal number is 1000, The number is .20 Which of the following statement is incorrect for the range of n bits binary numbers? (@) Range of unsigned numbers is Oto 2"— 1 (©) Range of signed numbers is -27-* + 1 to antag (©) Range of signed 1's compliment numbersis -2r4 4 110201 (@) Range of signed 2s compliment numbers is =20 "tot 4 Q21 Let A= 1111 1010 and B= 0000 1010 be two B-bit 2s complement numbers. Their product in 28 complement is (a) 11000100 (b) 1001 1100 © 19100101 (a) 11010101 @ & © 9% (>) 10 @ 11. (©) 17. ©) 18 (@ 20. Objective Practice Sts& coormpene tainennttt EXSEIIELY Basics of Digital Logic 1 aca man ie (@) Consider 10101011 % % % % % % A & Number of 1 in even places = 1 Number of 1 in odd places = 4 The diference (4 1)is dividable by 3 binary number 10101011 = 171 (decimal no. is divisible by 3) (c) 3121 = 3x 4341x424 2x 4h e 1x4? = 217 O12t=tx4t42x 4241 x42 = 0.990 aan a a —|o 2001), 0.9003 = 1.17 0.17x3 = 051 051 x3 = 183 (0.101 (22001.101), $0 (217.990),5 @ To convert to base 8, we group in 3's, because 2-8 To convert to base 16, we group in 4's because 2216 To convert to base 32, we group in 5's because 28 = 32, Grouping in 88, from the right we getthe answer. So 10119 01110 O0111 10000 (a) (22), + (101),~(20), = (04 + (st 4x24 2x4 41x38 +04 1x3-[5x2+ Opa s ext (1x4 yu = 842+941-[W]art4 = 10+10-10=x44 3 ax44 3 x26 fgimabe Ensa famnAce ersu (a) Octal number 657, Binary representation of 657, 00041011114 Hexadecimal representation of (657), = (1AFy (93) fs 10010011 + 101105 9) (6) squaring both side, (ai)? = (5)? A, = Bp (4B+ io = (25ho = B=6 (c) 3°4096 + 18256 + 5°16 +3. As we can see that 4096 = 2'haveone 1 256 = 2haveone1 16 = 2¢have one 1 Hence, they only remain as same in number of ‘Vs and when any other number is multiplied by themselves, the number of 1's is only the count of the number of 1's in other mutiplicant, 3 - on 15 - 1111 5 - 0101 3 - on - Correct option is (c) 10 1's )- (b) (025), 025 x2 x 056 TT 0 (0.25),0=(0.01}, www.madeeasy.in10. (a) (04375), i 2 2 2 Cay 1 i t ° ' 1 0) 080 x2 (0.4375},, ={0.011 1, FD Hence (ais corectooton 1 1 11. (b) (489+ C28)9 ~48 "17010000 -23__()11107001 7i___ 10117001 2s complement of a 2's complement number is. the number itself Here answer -71 is in 2's complement. 2s complement of 10111001 is01000111 12. (a) Given number is [4 [a [a [a] in 2's complement form. We know that in2's complement form. Ifwe copy MSB any number of times the number remains unchanged, $0, 838 a, = 8; 2 8,8, dy = N When we left shift a number by 1 bit then itis muitiped by 2, 50, 2,52, a, a,0 = 2N Now, a, a4 2, 4,041 =a, aga a, 1 =2N41 13. (0) Suppose we have to represent a number +5 and Bin 2's compiement representation using &-bits 00000101 -8= 11111011 (Using 2s complement) From the above example we conclude that when X, XX, Xp number will be stored in 2's complement method using 8-bit will be X, XX, XX XXX wuwmadeeasy.in Postal Study Course RUE] 16, 17, 18. 19. 20. 21. ig mabe easy Digital Logic | (c) 1753 +1360 “BIS + 10% complement -6667 (a) As 485 = (1011101), 0101110100000000 90000110 mantissa exponent (c) (€08),,-(ABF),, = (340), (340), = (001101001100), 1514), 7scompliment = (6263), @’scompliment = (6263), + 1 = (6264), (8) 1000 MSB is 1 s0, -ve number fe 2s complement for magnitude. ont (c) Range of signed 1's compliment number is 20-14 Hott (a) A= 11111010 Sinee MSB is 1 hence no. is negative Le. - (00000110) 00000110) A=46 B = 00001010, there is no. 2's complement representation for positiveno, B = +10 AxB = 10x(-6)=-60 Binary representation of -60 = 00111100 Now take 2's complement = 11000100 Objective Practice Setsa4 a2 as as YA Boolean Algebra and ores Minimization Techniques ‘A Boolean expression (A,B, Cs represented i inits pictorial form as shown below. The function aa Cee fA, B, Chis 1 a an o}t = ® of = : ife 14] 4 (@) BC +80+80 () BD+H84CD (a) (AC+ AC +B) (co) BD+ 80 +CD (d) BD+BD'+CD (©) (BA+oya+ oy] Q.5_ The switching expression corresponding to KA, BCD) = ¥(0,3,4,7.8) and ¥(10,14 12,1 where d : don't care (@) (aBc+ ABC) (@ CD+86 —() Coo The maximum number of Boolean expressions ae a that can be formed for the function Ax, y, 2) @:6 For the following Boolean equation, the value of A, Band C wil be AB+AC=1, AC+B = 0 © [A+e+CyA+ 8+] 2 satistying the relation f(x,y, (9,2) is (@) 441 ©) 1,10 @ 6 (b) 256 © 0.0,1 (@ 0,0,0 © () 72 oe e Q.7 The kmap for the boolean function F of 4 Match column-| with columnIt boolean variables is given below where A, B, Column Column C are don't care conditions. What values of A, (a) (488)8(89Q) 1.(40Q 8, C will result in the minimal expression? (AB AC+ EC BIAFBIOIA+O wz 0001 1 10 (©) (Ao B0(BOO) 3.ABe AC oo] 0] 0 (0) A¥(80Q) 4(A@O) of of 4 5. AC @ AC alate Codes wl o|o AB Cc oD | @4 3 1 2 (@) A=B=C=1 (0) B=C=1;A 3 4 1 2 (©) A=C=1;B=0 d) A=B=1;C=0 2 3 1 2 Q8 The well known fibonacci numbers are 11.23 @4 3 5 2 58 13... Let the boolean variables a, b and o gether represent a 3-bit non-negative binary number (that is, not in 2s compliment representation) Which of the following functions implement the K-map shown below?(a mMaoe EAS Let c be the least significant bit (that is, write the number as abc). Let F be a boolean variable that indicates whether the number represented by a, b, cis a Fibonacci number. (F=1 ifitis fibonacci number and 0 otherwise), Determine the minimized sum of product formula for F. (a) Feac+be (oe) Fedbede () Faab+ be (@) none of these Q.9 The Boolean Expression B@E is a simplified version of expression: ABE + BODE + BCDE + ABDE + BODE + then which of the following choice is correct 1. don't care conditions don't exist 2. don't care conditions exist 3. d (16, 18, 20, 23, 27, 29) is the set of don't ‘care conditions 4. d( 16, 20, 22, 27, 29)is the set of don't care conditions (@) tony (©) 2and 4 only DE (b) Zand only (6) Data insufficient Q.10 Boolean expression A+B 40+ A+B+C + AB +C-+ ABC reducesto @a (bo) 8 oc (d) A+B+C Q.11 The minimized expression for the given K-map (X: don't care) is 4a oo oso eo] o[o]+]1 oto |x] x 1 [x ole x[x[a x[alx ehh (@) Asie (b) B+ AC © C+4B (9) ABC Q.12 The biack box in the below figure consists of a minimum complexity circult that uses only AND, OR and NOT gates. The function fix, y, 2) = 1 whenever x, y are different and 0 otherwise. tn addition the 3 inputs x,y, Znever contain the same value. Which one Of the following equations leads to the correct design for the minimum complexity circuit? ae cceid 2018] (]MADE ERsy Digital Logic | 7 y— Black Box (a) xy 4x7 (xyz +ayz 2.13 Find the correct function forthe following kmap ac 20, oo 1 10 oo or 1 10 wl s}ofo]+] m)z]o]o]7 Moya) xtyz @xytyerz (@) ACE+BCE+ACDE (0) CE+8CE+CDE (©) Ae+E+BCE (@) CE+CDE+8CD Q.14 Minimal POS obtained trom Y= Em(0, 2,3, 6,7) +d (8, 10, 11, 15) (@) AC+8D (©) (AC+ 8B) (b) A(C-+By8+C) (d) None of these Q.16 IY = ABO+ AB+8C then dual and compliment of Yare respectively (@) (ABC +AB)-(8+C) and [Gra+0)+ A+ ay] 2c (&) [(4+8+0+A4-8)]-BC and [asc+ @+B)]-B6 (© [@¥B+O)+AB)]-6+0 ana (ABC + AB)-BC (o) [7B0+4+B] BC ana [\4+8+0)+28]-20 Q.16 The logic function f = (e-7]# CF y) isthe same as (@) fexey (0) f=xoy (© fexty (d) None of these Objective Practice Sets [J| Computer Science & IT aes 2o8] GIMAOE EASY .17 The boolean expression A + BC equals Q.20 Consider a four variable K-map shown below: (@) (A+B)(A+C) (0) (A+ B)(A+ 0) oo no (©) (A+ 8) (A+C) (d) None ot these oo} 1} 4 1 | Q.18 The SOP form af given function 7 a ] y=(A+B++0)-(A+8) is may date wl] | [a ABCD + AB it ‘The total number of all possible Non Essential Prime implicants (NEPIs) is, @ © ABCD + AB (©) y= 7aCB+ AB @6 5 (8) y= ABC + AB 4 @3 Q.19 Which of the following functionsimplements the 21 Consider a 3 variable function 4P, Q, A) having Kamaugh map shown below? min terms representation as, Q AP, Q, Ry = Em (3, 5,6, 7) Se How many minimum NAND gates required to ealefetele implement above expression? i @ 2 (0) 3 nfotafrto wfelt[afo os @6 @ AB+CD (0) DIC+A) (©) AD+AB ——(@) (C+ DG + DK A+B) EXE boi Functions We 2 Oe oe ye CO OC On 8G) 6. oC) 10. (b) 11. @ 12 @ 13 &) 14 () 15. @ 16 () 17. &) 18 @ 19. (b) 20. (0) 21. (@) Logie Functions 1. 272 [Ray ee Representing the graph in K-map 22 8) Yaw 4A 8. C)= B+ AC+AC wR os a ta8.0-(6raesac) eH too, _fetteroeet +s DED §4.8,.0)=[BArGATO] volte [ras |_ foseroor 2. (a) tro femeroort For every combination of, zthe function value remains same for input 5.2 Effectively there are only four rows forthe truth table of the function x,y. 2) -. Total Boolean expressions possible is 2* = 16. (ZF objective Practice sets §g MADE EASY wir madeeasyinG2MADE EASY PRES 2078] 3. (a) (Aone(Be0) = (A@BY\B@C)+(A@B\BOC) = (AB + ABKABC + BC)+(AB+ ABYBC+ BC) = ABC + ABC + ABC + ABC = AC(B+B)+AC(B+B) (AC+AC)=ASC (a) matches with (4) AB® AC + BC= AB@AC This is concensus law in XOR algebra, (®) matches with (3) (A+8)9(A+0) Option (a) matches with (2). A+ (BOC) 4 (c) co BS x fo 00] 0 co of lt t ny = &+co=ced (ce) From AC+B from AB+AC = 1 and B=0 38 AC=1=A=Oand C= Thus(A, BO) (0,0, 1) 10, Qamade Easy Digital Logic | 7. (@) For minimal expression Zoo 1 1 10 wr oof of o [ao al olaiio " ° 10 ° For A= eT Itwall give the minimal expression. (b) Fibonacci numbers are: 1, 1,2,3,5,8. Fibonacci numbers with 3 digits in its binary representation are 1 001 2 010 3 011 5 104 using K-map we can get minimized SOP formula, (c) @\ DE De oe oF A, Bex [1] a4 1 Bo| x x] aft 1 ecl_[x[4 scl [a[4 a{_ | 1[x a|_ [ah] Only (c) option satisties the required condition, (b) AvB+O0+ Av B+ C+A+B4C+ABe = A.B-C+ABC+ABC+ABC = AB(E+C)+AB(C+C) B+ AB = BIA+A)=8 fusing x +2 =] Objective Pace Sts| Computer Science & IT 11. (a) 4a 3X00 or | ot ape why The expression is Y= A+BC 12. (a) xy 2 thy.2) Oa Oogiee 10 0ort 1 So, Fisy.2) = HZ + Rye + 472+ x92 Hy +2) +97 +2) = HtW 13. (b) Bop ot 1 30 ps8 op 0 of en ods al a 0 wd a ace sat) 4 +1) [tee F= CE+CDE+80E 14. (b) 48 o_o 110 co] + [0 a wl 1] 1folal = Aic+5y6+c) 19. (0) Y= ABC+AB+8C Dual of ¥ Ya Gra O- AFB) 6+0) = [FBO AB] 8+0) Objective Praciee Sets 16. 17, 18, 19, 20. (mabe Easy ggmMApE ensy Compliment of ¥ (ABC-+AB) +80 = (ABC + AB). BC = (ABC + AB) -BC ) = EWE &y)-Ey) = G+ y(e+7) = ay tey or (x-7)+(F-y)=@, complement of @is. © ©) A+ BCrepresents the distributive law which can be expanded as A+ BC=(A+B)-(A+C) (a) (AvB+0+0) (A+B) = (A+B+C+D)++B) = ABCD+A (b) Solving the given k-map we have () wo om ©Group-() > NEPI + BB Group) »NEPI> AB Group) + NEPI + ABC: Groupv) +» NEPI-> ACD Group{v) > NEPI> ABD Group-(vi) + NEPI > BCD Group-(vil) + NEPI> ABC wurumadeeasy.in 24 [Mabe Easy G3MBBE SASS MOSM 2075) Digital Logic | (@) Realization of 'Y’ by using only NAND gates is given as below: vee = (PRYPQ+ QR) PR+FO=OR PR+PQ+QR -. Minimum # NAND gates required = 6. Objective Practice Setsa2 If propagation delay of NOT gate is 10 nsec, AND gate is 20 nsec and X-OR gate is 10 nsec. If Ais connected to Vagat t= 0, then waveform for output Vis vt oe bes e, PoE t $b ns ¥ o4 : rT) ” { @ 4 —-—) ee The circuit shown below is to be used to implement the function Z= fA, 8) = A+B.The values of fand J are as as a6 reece Logic Gates and Switching Circuits (@) 1=0andJ=8 (©) 1=BandJ=1 () f= 1andv=8 (@ 1=BandJ=0 fA, 8) =T1M(@, 1,2 term) (@) NORgate (©) NAND gate (©) OR gate (@) a situation where output is independent of input 3) represents (Mis The minimum number of NAND gates required to implement the boolean function ABCDE + ABCD + ABC + AC + Cis (@) 0 4 4 7 ‘The Boolean expression corresponding to the given circuit Le (@) isindependent of A (b) isan inconsistency (@) isa tautology (@) none of these The output fof the given circuit is @o (AMADE ERSY Q.7_ The given mutipiexer diagram can be expressed In canonical SOP form. Ifa function is defined as flw, x, y, 2) then what will be the number of rminterms in canonical SOP form? Do pA 8 Consider a 7 input EXNOR gata shown inthe Foueboow i—\ oe ' : —/, The seven not EXNOR gate ets 2 (@) Oddfunction —(b) Even function (6) Identity function (a) Both (b) and (c) Q.9_ Minimum number of 2-input NOR Gates required {to implement the function. Q.10 Which of the following expressions is not t=As[B+C(8+ AC) equivalent to #7 (a) xNAND x (b) xNOR x (© xNAND1 (d) xNOR 1 Q.11 A positive level logic digital circuits shown below D=p>- The negative level ogic digital crcuttfor the given circuit is @ aaa L>- (6) > ‘ostal Study Course PRE] (gmnoe Easy Digital Logic | (6) All of these Q.12 Consider Y= A@A@ASASASASAGABA then ¥is equivalent to: (@) 10RA () 1NOR A (0) AEXORO (@) AANDA Q.13 Identity the logic function performed by the circuit shown in the given figure ey) y > (©) exclusive NOR (a) NOR (@) exclusive OR (©) NAND Q.14 The following circuit can be represented as: @c ©) 14.8, (@ aeRc @1 BO, 1, 2,8, 4,5,6,7) @.15 Consider the logical functions given below. 1A, B, C) = 22,3, 4) ({4, 8, C)=n(0, 1,3. 6,7) f f. & If Fis logic zero, then maximum number of possible minterms in function f, are __ 1 Q.16 Consider a 3-bit number A and 2 bit number B are given to a multiplier. The output of multiplier ig realized using AND gate and one bit full adders. If minimum number of AND gates required are Xand one bit full adders required are Y, then X+ Y= a Multi c 5 Mater | Objective Practice Sets© | Computer Science & IT Q.17 For the circuit shown in figure the Boolean expression for the output Yin terms of inputs P, Q, Rand Sis Opp! aoe @) PrO+A+S () PORS © P+B)+F+3) (P+Q(R+9 Q.18 Astate diagram of alogic which exhibits a delay in the output is shown in the figure, where Xis the do not care condition, ox, 101 The logic gate represented by the state diagram is (@) XOR (©) AND Q.19 The output Y in the circuit below is always "1" () oR (@) NAND (@) two or more of the inputs, P, Q, Rar (©) two or more of the inputs P, Q, Rare "1" (©) any odd number of the inputs P, Q, Ris (6) any odd number of the inputs P, Q, Ris * Q.20 A digital circuit which compares two numbers Ay Ay A; Ay, B, By 8, 8, is shown in figure. To get output Y= 0, choose one pair of correct input numbers (EY objective Practice Sets Postal Study Course EUHE] G3 MADE Ensy MADE EASY BA BA BA BA Hao : D 0 {@) 10101010 (@) 0101, 0101 (©) 010,010 (d) 1010, 1011 Q.21 The circuit given in figure is to be used to implement the function Z=/(A,6)=A+B What are the values that should be selected for Tand J? q J A @i=0u=8 OT B @i=BJ=1 @T Q.22 Consider the circuit diagram given below ~ Dp. Em, 1,2,3) Em(O.2, 4,6) Ifthe boolean function f,is dual off, then the boolean function ‘fis @ Em, 1,2,3,4,5,6.7) (©) Em(0, 1,2,3,6,7) ©) Em, 1,2,3,7) (@) None of theseMADE EASY Cia Logic Gates and Switching Circuits 1% 2%) 3 @ 4 @ 5 11. @) 12.) 13. ©) 14 @ 17. 22. (a) Postal Study Course PUHE] @ 6 @ 7 ® & @ 10. @ (b) 18. () 19. () 20. @) 21. Oo) PEDEEIIIE oa%c cates and switching circuits 1. (b) 10ns = Minimum number of NOR gate required =9 (d) A 8 10. Letx = 0 then ONOR1= O#¥ Lets = 1 then 1NOR1 = O2¥ Hence, (d) is the reauired option. (a) " ‘The negative level logic citcuitis a dual circuit of positive level logic circuit, Using dual logic gates, it can be shown that the and (c) are all same in circuits in option (a), (t operation. Objective P Sets Postal Study Course BXEE| G3 mane easy 12. (b) Y= ABABA) BIACA OABA BABA) Note: A@A= 0 A@A=1 Y= A@0@0@0@0=Ae0 Hence Y= AEXORO Hence (b) is correct option. 13. (b) {sy fx 9) Ew CFM = rey y y= T= iy Therefore the above circuit performed exclusive NOR gate. 14. (a) From the given diagram we can see that Property: CC= COC=1 18. (6) f(A, B, ©) = 22,3, 4) if, B.C) = w(0, 1,3, 6,7) = 312, 4,8) For function fio be zero: (A, B,C) = [F(ABLC) 9 EA. B, Cj = £0, 1,3, 5,6, 7) Maximum minterms possible are 6 16. (9) Az a a a 8 _ bb AxB= ab ab ab ba ba ba | ba, (@b.+abjab,* bala, aq 6 GG, MADE EASY www.madeeasy.inMADE EASY PRA 2078] Number of AND gates required (X) = 6 24. (b) Number of one bit full adders required (Y) = 3 X+Y = 64+3=9 id i a > 17 % ‘As we can see clearly output must be A+B - which can be abtained only by making J = B andi=1 AB Q a 7 > 0 0 7 So, that J+ A=1 and f =(A+8)1 +8 la Hence (b) is corect option 1 0 1 22, (a) it o f= Fa+F GOR) if any one ofthe input is zer0, outputs ogic 1 _— Otherwise output is logic ‘0’, which represents = fatty + Ole) the NAND gate. Fyt ty tthe +t 19. (b) fy hd Take two or thee input’ then we always get f, = 1m (0.2, 4.6) * i Fg = Em(1,3,5,7) Take two or three input zero then we always get 0’ hence option ‘bis true and output f= Em(1,3,5,7) +Em(4,5,6,7) + Y = PQ*PR+AO 3:0 (0,2, 4) Em (0,1, 2, 3, 4, 5, 6, 7) 20. (d) in EX-NOR gate, if odd number of inputs are 1 tore tort, a9 then outputs zero, wwwimadeeasy.in G@MADE EASY Objective Practice Setsaa a2 as a4 Find the simplified boolean expression fx.y.z.W) forthe below 8 : 1 MUX we i, oy tls —! ol ot? 1) Pn sety (@) syexztaweyw ) x7 + pws 32432 (c) Fy +az+20+ yw (0) sync 2+ yw If-x number of 4 x 1 multiplexers, y number of 2x 1 multiplexers and z number of 16 x 1 multiplexers are needed to impliment a 128 x 1 ‘multiplexer, then which of the following can be value of (x + y + 2)? (Hint: Use exactly two16 x 1 multiplexers ie., 2=2) @) 5 () @ (©) 10 (a) Allof these For ambit carry look ahead adder the gate count (0? +9n) 2 (? +6n) 2 Find the boolean expression Bin the digital circuit given bek (o) () ote [+ 0 (oiterence) subvacter st a (e-0)-0 | + aaron) as as a7 as oa Combinational Logic Circuits (@) ab+bo+a0 (©) ab+bo+ca (©) ab+Bo+ca (@) ab bo+ca AA 1-bitfull adder takes 20 ns to generate carryout bit and 40 ns for the sum bit. What is the maximum rate of addition per second when four ‘-bitfull adders are cascaded? @ 0 (©) 125x107 (©) 625x108 @ 0 ‘The Boolean expression f(a, b, c)in ts canonical form for the decoder circuit shown belowis (a) mM(4,6) (©) Em(4,6) (©) Bm(0, 1,2,3,8.7) (@) TMC, 1,2,3,5) Consider the combinational circuit below has TT fee ol | | oe ee py ! : “ The output of the combinational circuit How many half adders are required to realize the following 4 functions? f=A@Becag ato an a1 f= ABC +(A+B)C 4, = ABC @ 2 4 3 5 Let x,, ¥, and 2, are the sign bits of a number x, y and result z. The overflow condition if C,. be the carty into sign bit (8) BVeCn2 + HIE y-2 (0) BYeCoa + %VeCr-2 () 5 VeCn2+ MY En-2 (@) none of these ‘A combinational circuit outputs a digit in the form of 4 bits. 0 is represented as 0000, 1 by 0001... 9 by 1001, A combinational circuit is to be designed which takes these 4 bits as input and output 1 if the digit > 5 and 0 otherwise, if only AND, OR and NOT gates may be used, what is the minimum number of gates required? (a) 2 () 3 (4 (5 Minimum number of 2 x 1 multiplexers required to realize the following function f= ABC + ABC ‘Assume that inputs are available only in true and boolean constants 1 and 0 are available, fa) 1 (b) 2 3 7 The circuit shown below converts (Here @ is XOR) tp re | % oO, 0, o (2) Binary to gray (0) Binary to excess 3 (0) Excess Sto gray (2) Gray to binary 4 4) h LAS 2018] Digital Logic | 4 Q.13 Consider the following multiplexer: o— {0 wuxl-=r S10 ux | h 7 R The value of output function 'g’ is, (@ PO+PR (0) PO+PR (© PR+PO (@) None ot these Q.14 Minimum number of NAND gates required to implement Sum in hal-adder circuit is @ 2 ) 3 4 @s Q.18 The number of full and hait-adder required to add 16 - bit numbers is (@) Bhall-addors, 8 fulladders {b) 1 halt-adder, 15 full-adders (0) 16half-adders, 0 ful-adders (0) 4halt-adders, 12 fulladders Q.16 A4 x 1 muttiplexer is used to implement 3 inout boolean function as shown in the below figure, The F(A, B, Chis = FAB.) @) 0.4.5.6) (0) 2(3.4,5,6) (c) 10, 4,5, 6) (@) 7(3, 4,5, 6) (@mMAbe Ensy Objective Practice Sets KE)| Computer Science & IT Q.17 The circuit below represents function X(A, 8, C, Dyas: h ° 1 he tik of —s ts as | . ABE @) (3.8.9, 10) (0) E(3,8, 10, 14) (©) (0, 1,2,4,5,6,7, 11, 12, 13, 15) (@) (0, 4,2, 4,5,6, 7, 10, 12, 13, 15) Q.18 Consider the following statements. ‘Ad : 16 decodercan be constructed (with enable input) by: 1, using four 2: 4 decaders (each with an enable input) only using five 2 : 4 decoders (each with an enable input) only using two3 : 8 decoders (each with an enable input) only using two3:8 decoders (each with an enable input) and an inverter. Which of the statements given above is/are correct (@ 2anda (©) only (©) 2and4 (@) None otthese Q.19 A3+10-8 decorder's shown below: pe 7 |, bes bs wow —2 8 output a b—2 abi Enable Signal Allthe output lines of the chip will be high, when all the inputs 1, 2 and 3 w (EY objective Practice sets Postal Study Course FUE] Da MACE EASY (@) arehigh; and G,, Gare tow (6) are high; and G, is low, Gis high (©) are high; and G,, G, are high (@) ate high: and G, is high, G, is iow Q.20 Consider the circuit given below wal yt ans a4 Max [—Y i ~ 1! Doc Which of the following statements is true for ¥. (@ Y= CD+Dc(A+8)+Cos () ¥ =CD+DO(A+B)+CDS (8) ¥=0D+O+C\AFB)+C+ Q.21 The logic function f(A, B, C, D) implemented by the circuit shown below is oy (@) Diae@c) (b) DiAac) (©) DiA@a) (@ DiAeB) Q.22 The function realized by the circut shown infigure is © MADE EASY wwwmadeeasy.inMADE ERSS [RESTS 2078] Digital Logic | *! 2.23 In the folowing circut, S,, S, and S, are select Which ofthe folowing combinations of inputs to lines and X, to X, are input lines. S, and X, are I fy fgand I, of te MUX will realize the sum S? LSBs. The output Yis 1 — —" ocr feet AN & s 5, y (@) indeterminate (6) ASB (© ASB (6) C(ASB)+C(A@B) Q.24 Consider the cirouit given below. .28 Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be 2, Q=00 For aninput sequence X= 1010, the respective ‘output sequence will be Ifthe decimal input is 92 then ¥, « corresponds i iB eaanascae a DP 0.25 Minimum line to 16 ine decoders required to tsSenex ea ¢ realize @ line 10256 ine decoder are : ay @s 8 ole f ov @ 6 > Q.26 Consider the logic circuit given below. The eal minterms in F(A,B,C,D) are Q.29 A new two input fip flop is designed as shown ao 0 in figure. The table shows the characteristic table ax Lrasco, of the A-Bflipstop, et AS Te 6 ope | o (@) Em(1, 3.5.6.7, 11,14 ‘fo fa (0) Em (6, 7,8, 12, 14, 15) stata (©) Em(G,6,7,8, 11, 12, 14, 18) ——— (@) Em(G,6,7,9, 11, 12, 14, 18) J convinaon- 4 Q.27 Figure shows a 4 0 1 MUX to be used to 8 a Ko implement the sum $of a 1-bit full adder with inputbits Pand Qand the carry input C,, The combination logic is | www.madeeasy.in G3 MADE EASY Objective Practice Sets Fat}| Computer Science & IT © 2.30 A digital circuit which compares two numbers A.A, Ayand 8, B, By is shown in figure YY_Y Y To obtain output ¥ = 1, the valid combination is (@) 010,111 (b) 010, 101 (©) 101,110 (@) 101,011 Q.31 Atwo bit magnitude comparator circuitis shown below. ose [J] : Pia> 8) A Am aa=5, RA< 6) a- The logic circuit for ris Objective Practice Sets Postal Study Course EDIE (@mnAde Easy MADE ERSY t=D5 =D aD a oa) > D>, @ Q.32 Consider the waveforms given below: ouput (2) Ghock—p Lo2 —— om lp tock —$} wunw.madeeasy.inMADE EASY [EEEIEN combinationat Logic circuits 1 @ 2 @ 8 (bo) 4. {o) 5. pes) et et a gee eh 20. (d) 21. (b) 22. (b) 23. (b) 25. 31. (a) 32. (co) Combinational Logic Circuits 1. (@) Funetion table for multiplexer is x y z 7 0 0 0 w | oy] 0 7 7 0 T 0] 0 0 7 1 7 7 0 0 7 i 0 i 7 1 1 a 0 1 1 i 1 Total Four Quads fis yz.) = a taz 2 2. (a) 128 395 4x1 Multiplexers 16% 1 Multiplexers = 1 2x1 Multiplexers wey 47=924142=35 Option (5) and (c) not possible. [Note: Many values can exist for. + y+ 2] “wirwamadeeasy.in Postal Study Course EXHH| (mabe Easy Digital Logic | @ 6 () & © % © 10 &) &) 16 @ 17. @ 18 © 19 (©) 26. () 27. (©) 29. (d) 30. (o) 3. (b) For n-bit carry look ahead adder inst Total #AND gates = MO+D , Total #OR gate: Total #XOR gates Total gate count = “+? nentntn _ (2 +9n) 2 4. (c) Order of subtraction is (ob) - 2 (cele es are | ena Borrow (B) = TBa+cba+Eba+cba be oo or 0 o [aor 1 4 B= Tareb+ba 5. (a) Given, Ty = 20ns T, = 40ns GEGeaTecl 8. cs Computer Science & IT Te, =40ns Tg, =(40+20)ns=60ns | 4 full adders Te, = (60+20)ns = 80 ns {are cascaded Ta, =(80+20) ns = 100 ns Final sum result will take 100 ns Rate of addition 10 toons . (c) The given 3 x 8 decoder is a active low output. Each output represents a maximum term when activated with enable I © = O,then EN=1 The outputs Dy, D,, D, and Dy are active and outputs D,, D,, D, and D, are inactive ‘Output of OR gate is (M, + 1 + M, Cutput of AND gate is (M, M,) = TIM(4, 6) fa,b,0) = TIM4,6) fab) = TIM(, 1,2,3,5,7) fa, b,0) = Xnt4,6) (c) = ABC + ABC =(AB + AB)C (AgBic ABC +(A+B)C = ABC + ABC ABC Single Half Adder —> SSD aesnoe [)—sum=a8 Objective Practice Sets Postal Study Course PXE| Gg maoe Easy OS MADE EAsy To realize the four given equations ABOC=f, aac 10. (b) We need output 1 when input 6, the required boolean expression can be obtained using K- map W820 01 1 10 oo] of ooo TIMP? (ATW wlls Ta [a [ a) y = A+BD+8C = A+B(C+0) oi o = 3 gates are required 14, (b) t= ABc+ABC = AB(C +0) = AB with 2 > 1 multiplexer offense 7 wnwmadeeasy.inG3 MADE EAS! 13. (a) +0P +AP)+0P OUR +OQ\A+P)+OP G\AR + OR = AP +QF)+0P GRP +P (GR +Q)P (+R) (O+0)(Q+ R)=Q+ A) (Q+R)P = PO+PR 14, (c) Expression for sum in half adder is AB+AB=A@Band minimum number of NAND gates requited for EX-OR Gate are “4. Hence correct option is (c). 16. (a) 20. 2 17. (a) ‘The given circuit represents the implementation of four variable function using 8 : 1 MUX here. O as taken as the fourth ifp and A, 8, C act as select lines. ea] oa re] ae Boletstel@leela| i o 11 /Ols[71O/ |] is (weno ]ofoj}o}i}ololo Em(3,8, 9, 10). 18. (©) 4:16 decoder using only 2: 4 decoders: Output Postal Study Course BOIE 4:16 decoder using two 3:8 decoders and an 19. QamAde EASY Digital Logic | inverter: wmf Output (b) Outputs are active low, so all the output lines of the chip willbe high, when chip will be disabled ie, G=Oand G =1 (a) f = DAC+AC) "Objective Practice sets 322. 23. 24, 28. 26. cs | Computer Science & IT Postal Study Course FLEE G3mnAvde Ensy ©) = AGB +805 +0 Fe ABC+ABC+ABC+ABC = AB+B)CD Fs AC(B+B)+AC(8+8) +(a+AoaoB + Ac+ac COA + A\(B +B) F=A@C © = ABCD = ABCD + ABCD Fioating input is accepted by GATE logic gate eee) ica +ABCD + ABCD Hence § MA,B,C,D) = E43, 6,7,.8, 11, 12, 14, 15) co S]5 5 ]¥ bo) 5 1|B/A Tholtfa Sst ‘4 1[ol1|1p 2 7 a[a tht fo Tt] 1 1 Tf fo} 27. (6) Y=A@B For a4: 1 mux (219) 1 Decimal input = 92 A BCD = 10010010 ‘ fol ar Output of Gray code converter ion = 11011011 | | Y, corresponds to J, with (S,,...S,) is 11011011), AB 19 Fe1,AB +1,A8+1,AB +1,A8 (0) epee Numbers of 4 x 16 decoders required Lf 256 Fut 0 ‘or 16 Erle +t=17 s-AdBec where sum of full adder is = A® B@ C (3) Truth table of Full adder a—fo 4 i eae S| S1@ [cameo] sum ‘mst nf? |e es o | o Wo | . 2 1+] 0 Y= AC+BC CEE f= ¥D+CD nf 4 } (AC + BC)D + CD Objective Practice Sets (@mAde EnsyO3 MADE ERsy 28. (0011) Q(t+1) =D, AT Qy(t+ 1) = Q,(NOX (1) Qy(t+ 1) =D, OQy(t+ 1) = QHH@.Q,(0 (2) M9 = Alt) +(Gw9-X) cu WO = Q()+QO+X (3) State table: 5 [eae | NenSae a, Cm Oy a com ons [rate core om aithe sa silanated of+[s[+ olt al oa ool ect Oc [ope fet. 4+ ]4 oppo pepo Fe State diagram: ony ont 31 1" 32, From state diagram output sequence is 0011 for input sequence 1010. 29. (d) a Z[« ° | + [4 ° 1 | 0 1 o | o 1 o Li x e wa 1 ue 1 (3MADE EASY Postal Study Course EXE) Digital Losic | ——) ee ==) (b) gut ‘A3sinput XNOR gate acis as an odd function Y=A,@8, 94,0804, @B, =1 sing definition of XOR the valid combination is A,A, Ay = 010 and B, B, By = 101 (a) Expression of 'F from logical deduction is Ra AoB, +(A: @B2)AB, Rean be implemented by AND-OR logic. () By checking all the options, Option (c) correctly matches.era ia 5 Sequential Logic Circuits CHAPTER Q.1_ Consider the digital circuit shown in below figu The average propagation delay of each NAND gate in the clock generator circuit is 10s. The frequency of the clock signal is MHz, Q.2 Consider the counter shown below J unter is 001, then after how many minimum number af clack pulses the initia If the initial state of the state is reached? Q.3 In the following figure consisting of JHK flip flop assume the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be Os 11k Ge (@) 010000 (b) 011001 (6) 010010 (© o10101 Q.4. Consider the following circuit consisting of D flp flops.G2MADE EASY PREM EMecnd 2073] Digital Logic The circuit generates a sequence. Initially al fp flops are cleared. The generated sequence after all the flip flops have been changed from their initial value is (@) cortt10 (b) 111010 (©) cont (@) 11010 If the initial state Q,QjQ, = 110, atter how many clooks it gat back same value? @ 5 6 7 @3 Q.6 An X-Y'lip-fop, whose characteristic table is given below, is to be implemented using a JK flip-flop. This can be done by making x LY [Ons | a) 1 a 10 | G, 1/1 0 @) J=XK=P () J=X.K=¥ () J=VKeR @ J=¥.K Q.7 Assertion (A): D-Hip-Flops are used as butfer register. Reason (R): D-lip-Flops are tree from "race-eround” condition (@) Both A and R are individually true and R is the correct explanation of A (b) Both A and Rare individually rue but Fis not the correct explanation of A (c) Ais true but R is false (d) Ais false but R is true Q.8 The JK flip-flop shown below is initially reset, so that Q = 0. If a sequence of four clock pulses is then applied, with the Jand K inputs as given in the figure, the resulting sequence of values that appear at the ‘output Q starting with its initial state, is given by 4 (@) 01011 (b) 01010 (©) 00110 (d) 00108 BBDE EnSy Objective Practice Sets| Computer Science & IT PES os] 9 MADE EASY 8 Analyse the sequential circuit shown below in Codes: figure. Assuming that intial state is 00, determine A BCD what inout sequence would lead to state 11? @3 244 ay [pee ooo 7 a oy (1 3 4 2 Da | @) 2 4 3 1 la t« Q.11 The input A and clock applied to the D flip-flop cu: a oe are shown in figure below. The output G is ato axp | «-D—t: fa) 1-1 ©) 1-0 (c) 0-0 (d) State 11 is unreachable Q.10 Match List-1 (Logic circuitftunction) with Listell (Circuit realization) and select the correct answer 12 An XY flip flop, whose Characteristic Table is, Using the code given below the lists: ° ® “ given below is to be implemented using a u-K List! fk A. Dflp-op Oded B. Thip-fop x [Y ] On C. Exclusive OR Oo D. Haltadder of1], a List pe be] oe 1 pute | outputs This can be done by making tp @ J=XK= — (0: J=Y,K=X @) Ja¥.K=Xx ya 2 EL | oupus .13 A J flip-flop can be implemented by T fp Tple ef 2 flop. Identity the correct implementation. voit 3 outs @ De Che ofS K | riptep a Inputs Supa Dy YD 2. 4, me D! © an na K coaaaaaaas MADE EASY [SJ Objective Practice SetsG@ MADE EAsy ° Diy = ceux (cD aame eT, @ Ax .14 For the circuit shown below, the counter state (Q,Q,) follows the sequence ig 4 CLK, | (2) 00,01, 10, 11, 00 (©) 00, 01, 10, 00, 01 (©) 00,01, 11, 00, 01 (d) 00, 10, 11, 00, 10 Q.18 The outouts of both the fp-ops Q, and Q, in the figure shown below are initialized to 0. The sequence generated at Q, upon application of clock signal is (@) 01110. (©) oor. (b) 01010, (@) oreo, Q.16 Consider the following synchronous counter made up of JK, Dand TFlip-Fiops, 7 abo afr 3 6 | UJ cK. Find the modulus value of the counter, pt www.madeeasy.in Postal Study Course BE) [3 made Easy Digital Logic | 0.17 Inthe following JK tip-top we have J= @ and = 1. Assuring the tlip-lop was intial cleared and then clocked for 6 pulses, the sequence at the Qoutput wil be tex ot ux (@) 010000 (b) 011001 (©) 010010 (@) 010101 Q.18 The inital state of MOD-16 down counteris 0110. Atter 37 clock pulses, the state of the counter willbe 2.19 In clocked RS flip-loo, the output remains as previous output until (@) R=0,S=1 © R=1,8=0 () cP=0 (@) R=1,8 1 Q.20 An XY tlip-tiog, whose characteristic table is given below, is to be implemented using @ JK fip-iop. X LY [On _o oT 4 o{tlo, 7 0 |G, Tp o This can be done by making (@) JX K= () Jak. K=Y © J=¥K=X Oda V.Kax Q.21 Amod-2.counter followed by a mod-5 counter is {@) same as a mode-§ counter followed by @ mod-2 counter (b) adecade counter (6) amod-? counter (d) none ofthese .22 Inthe following sequential circuit, the intial state (before the first clock pulse) of the circuit is 0,0, = 00. The state (0,0), immediately after the 383° clock pulses, SeesJ Computer Science & IT PRESEN T2015) GIMACe EASY j = . (@) 00, 01, 10, 11, 00. CSI (b) 00, 01, 10, 00, 07 6 fa (e) 00,01, 11, 00,01 fe att | (a) 00, 10, 11,00, 10 ou 4 ——_] @.24 For the folouing characteristic table using XY @m wo flip-flop, the characteristic equation Qit + 1) = 10 1 a XTY [Ot+9 @.28 For the circuit shown below, the counter state titel (Q,Q,) follows the sequence 7 an <4 lop om ladle! Gro} Tyee rae 2) YU)+ RAW) (0) FAM) + XQKE) ox] —— J ©) FQQ+RAG — @) YAQ+xXaQ LEEEEIEH sequential Logic circuits Se eee Oo) at) Or ee ee) 011) 10) it (a) 12. (b) 13. (b) 14. (@) 16 (@) 18 () 19. ) 20. (@) 21. ©) 22 (oy) 23. (co) Sequential Logie Circuits 4. (10) The modulus value of te counteris x Here the clock generatorisaringoscilator circuit So, aller six clock pulses the counter reaches 72M its intial state umber of logic gates propagation delay of each 3. @ ea For JK pop N=5:t,4= 10n5 0,,,= JO, +RQ, — because K= 1 always (given) BxBicton * OME = in this case, Q,, , = JO, 2. (6) ft The given digtal crcut is a asynchronous up 90 240) =10-=1 andnow J-0h-0 counter aK Q, =O; =07=0 and now J =, Q, = JG, =10=1 and now J=G,=0 Q =U, =07=0 andnow J= Q,=uG, =10=1 Thus the sequence of output will be = 010101 (EY objective Practice sets fg mabe easy eenG3MBDE EASY RSet Digital Logic | 4 xy Qe 00) esteem Ome ent aifo o |@ to} 1 1 1G, ri) 0 1/0 1) tpoltjors whichis true | ( io 14 Riis pont at i op have baer eee Changed rom teen aise a The generated sequence is 1 1010 Ga 5. (a) Q,0,=00 For JK lp flop Then, z= OOF ea " x= 0; wewill get ee get QR! = 10 + O50; =] +a3a .x= Dis only in option (c). Similarly for next state ee we need input x = 0. Yt = 08GB +0-03 =03-OB Hence for output state 1 1; input is 00. a 9. (0) Now 4. Dilip flop QR = 10 ical o yah QLQLO} = (0+1.1) (0.0) (141.0) = 101 -| ox OROBOZ = (0+0.1)(1.1) 041.1) <011 kd} QRQBOR = (144.0) (1.0)(0+0.1) = 100 2. Tilip flop QfQsO = (0+0.1)(0.1)(141.0) = 001 : J QHQSOR = (1+0.0)(1.1) (040.1) = 110 eel Aiter 5 clocks, it will get back same value. 3 kK 8 6. (d) XY Oy, 3. Exclusive OR Oo 1 ° 1 a, 1 0 Qe 1 1 0 The JK flip-flop can be implemented by making J=7, K=x 7 (mane easy Objective Practice Sets| Computer Science & IT ENOTES) GGMADE eEAsy 4. Half adder Now, assuming Tto be an output, we solve it in s——} terms of J, K, Q, inputs. This gives the definition > sum s . ‘of the logic to be applied on the Tinput. Also, observing the given options, we solve for om T using a maxterms map instead of using a minterms map, as shown below: So option is 2, 3, 4,1 Is right. 10. (a) Dilip-top changes its output according to input ‘and clock pulse applied to it. The flip lop shown in figure is positive edge triggered so the output modifies at every positive edge of clock Yr ko, KG, KG, Ka, according tothe input T= (J+Q))-(K+0,) 11. (¢) The circuit corresponding to this expression is X-Ytruthtable J-K truth table ‘given option (b). XT¥TQn] [TKT Qn 13. (b) ofol 1] fofora, D, = A, = QoQ, olita,| folipo = (2, Q,) 00-701 > 10-00-01. 1{0[ a, auto 14. (a) tafe] bit Excitation table QMO ITRTXTY, oO] 0 [Olx[xfi o| 1 [ifx[x[o TL 0 [e[t[1]x cue! T|_7_|x[o[o|x Initially Q, = Q,= Truth table of uk: Z K a 0__ [Previous state i a a 1 1 ‘To make (X— ¥) FF using (J~ K) FF, (J) should be (Y) and (X) should be (%), 12. (b) To obtain a JK flip-flop from a Titip-tlop, we frst construct the characteristic table of JK tlip-lop; and then obtain the excitation values for the T Case-1: 1 clock pulse flip-flop as shown below: a o 7 1 a Q, = 0, G,=10,=0,0,=1 Tx fe ee] +] $0, d= 1, K,=Oand J,=0, K, cele elo oi |o ole SG =1Q=0 omrecansto{ 30} 0 1 | 1 f= sstatn . ea) tie ff o ae) Fabac ase 1a = 0, G=1 (2 objective Practice Sets MADE Esy _—___ wanmmadeeasyinGa MADE EASY So j= t= So, Qf=1, Q=1 (new values of Q, and Q,) Case-2: Q=1, Q=00 0, K,= 1.5 0, Qy=1 (new values of Q, and Q,) So, the sequence willbe 01100. 3, Ky 16. (8) Consider characteristic equation of 4K Fip-Fiop: (a Consider characteristic equation of D —Fiip-Flop: Qy.1= 2 Qy.1 = & (ii) Consider characteristic equation of T- Flip-Flop: Qqys = TRQy ner = OQ, (iit) Using equations (i), (i) and (it) Present State ‘The number of used states = 5 : Modulus value of the counter = 5 wuw.madeeasy.in ee kee ed 2018] 16. 17. 18. 19. fg made Easy Digital Logic | 2 So, the Sequence at the Q output will be 010101 (0001) 87 = 16x 245 Alter 37 clock pulses, the state of MOD-16 DOWN counter will be five states below the present state, 01106) -0101(-5) 007 (bo) Truth table of clocked RS flip-flop is: (a a a 0 Ona 1 a, 9 On i Qn4 ° Qn4 1 [Reset (.2.0) 0 1 Set (i¢.1) Invalis 0 0 1 1 0 0 1 1 4a cong aos0Kx The JK flip-flop can be implemented by making Jay K Objective Practice SetsComputer Science & IT TESEeae 20s) GIMADE EASY 22. (b) = D, = A, Dy= OQ, o 3 (Q,Q,)00 +01 > 10-400501 ° 1 23. (c) ‘ Using K-map 0 Which is true mye ort 2 20. (a) ntho po We can replace the positions of counters as etn shown in Figure = moa a | {mod == ef mos a | t+ 1) = YO)+XA0) 21. (b) (EY ovjecti Practice Sets MADE EASY wuwmadeeasy.in¢ Registers Cro Q.1 Asixbitright shift register is intialized to a value of 100000, Minimum number of clock pulses needed to produce 101 101 from the given initial value is | a a a Q; a O fa) 3 {b) 4 © 5 (d) 6 2. Forthoiial state of 000 the uncon performed by the arangemertfthe Kipp inthe given igure is OF aq—p a} a 3} |x, alte aft! cof (0) Shit Register (&) Mod-sCourier (6) Mod Courter (@) Mod-2 Courter Q.3. Three shift registers are initialized and are connected as shown below, having a common clack. The contents of register-A after 10 clock pulses is Register A Register 8 Lote. + Te eo f - f ] 4 AB-bit shiftlett shift register and a D fliptlop is shown in the figure are synchronized with the same clock. The Dilip-lop is intially cleared. The circuit acts as tock SECC coxp > a 1| Computer Science & IT (@) Binary 10 2's complement converter (b) Binary to Gray code converter (€) Binary to 1's complement converter (@) Graytobinary converter Q5 Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with Input I Shear t| shit opete 2 Shit Reger | Clack Output A 4 bit data 1011 is applied to the shift register 4. What is the minimum number of clock pulses required to get same input data at output are with same clock? @n © 18 &) 12 @ 14 Q.6 A decimal number ‘58’ is stored in a register. After performing one right shit operation on this, the content ofthe register is, @) 00111010 (b) 0001 1101 (©) 01140100 (a) 11000101 Q7 The initial contents of the 4 bit serial-in-parallel- out right-shift Register shown in igure below, is 0110. After three clock pulses are applied, the contents of the shift Register will be cK seralia (@) 0000 (©) 1010 (b) o101 (@ 11 Q.8 Consider the following statements regarding registers and latches: (EY objective Practice Sets Postal Study Course EDIE ag a.t0 at at2 (emave easy OamrAbe erasy 1. Registers are made of edge-triggered FFs, whereas latches are made from level- triggered FFs. 2, Registers are temporary storage devices whereas latches are not 3, A latch employs cross-coupled feedback connections. 4, Aregister stores a binary word whereas a latch does not. ‘Which of the statements given above are correct? (@) tand2 (b) 1and3 (©) 2and3 (@) Band 4 Which of the following capabilities are available ina Universal Shift Register? 4. Shift loft 2. Shift right, 3, Paralielload 4, Serial add Select the correct answer from the codes given below (@) 2and 4 only © t.2and4 (b) 1,2and3 (@) 1.3and4 The content of a 4-bit register is initially 1101 The register is shifted six times to the right with the serial input being 101101. Whatis the content of register after six shifts @ ‘101 (o) 1011 (© 1001 (@ 110 ‘The shift register shown in figure is initially loaded with the bit pattern 1010, Subsequently the shift register is clocked, and with each clock pulse the patiern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position (MSB). After how many clock pulses will the content of the shift register become 1010 again? Clock Serial Input Prrir Match List| with Listl and select the correct, answer using the codes given below the lists: wuw.madeeasy.in35 MADE EASY List-II Codes: A B.C (ea o) 3 1 2 eo a 1 2 2 [EEE resisters 1 @) 2 ©) 4 ) 5 2%) 14 © 1. (0) Letthe output of XNOR gate is ¥ howot Digital Log Q.13 A Sit ripple counter uses JK flipflops. If the propagation delay of each fliplop is 50 n sec, then what will be the maximum clock frequency that can be used in megahertz? Q.14 Ann stage ripple counter can count up to (2 (b) 2-1 (a © 2- 6) 7 © 8 tb) 9 () 10. wb) CLK TY] O5, Q Minimum five clock pulses are required to get the sequence 101101 2. (c) Given figure is a Jhonson counter, so maximum possible states in output wll be 2n, where nis the number of fiplops. Initial state = 000 wuw.madeeasy.in Objective Practice Sets|. Computer Science & IT SEs 2013) Gs MADE ERSY Present state Next state 2 4 @ Qa 2 ae 0 0 Oo 0 o 41 o 0 4 o 4 1 : o 4 1 1 1+ Gditferent states 1 1 1 1 1 ° 1 1 ° + 9 0 1 0 0 0 o 0 Hence, option (c)is correct. 3. (1011) 6. (b) Register A and Register-B are taken together to ~~ 7 form a cyclic register. So, contents in Register-A ie —e worn t01dh reappears after 7-clock pulses. YAW [Glock Pulse [Register A Contents Fim aie = goo1 1101 7 TOTO in 8 | ont 8) ° (i) $Rlatch is shown below: 10 1014 4, (b) ° The output of XOR gateis 2= 0, ,@ b,andithis ‘output shift the register to left, initially 2 = 0. Alter 18\clock 2= 0, ®0 = by 2 Alter 2° clock 2= b, ® by 7 @ Ps Alsich employs cross-coupled f ne eee ene Almich employs crose-oupled feedback ee (i) Registers are made of edge-tiggered FFs, 5. (b) whereas latches are made from level 3180 so triggered FFs. tot LLL 2. ©) I Universal shift register features parallel inputs, Le out parallel outputs. It performs both functions shift oe left and shit right a faeteer] =e * goon} cooe [Croats ae e 388] bene 01 5 1oo0| 008 . apo é ii oot oo8 9 Lon i Sotto tte + spr t0n s fod + LS ive: . * mt 0 ono x | pak 1 fein | Minimum no. of clock pulses required = 12. (Sy objective Practice Sets G3MADE EAsy winumadeeasy.inGSEMBDE EASY PRES 2078) Digital Logic | " 12. (b) 2 a, a, Shift register: Serial to paraiol data conversion m % soratinpar=[1]o[ 1] 0] or eg? Counter: Frequency civision y, rl os Decoder: Addressing in memory chips Es, 13. (667) T23x60nsec [cikpuise [a @ a Tz 150nsec Araaea nari Tun = 150806 ee veto? Spezia bac = MOE = 6.67 ite ahs foors 150 a [ooos ae eas 14. (0) 806 o10 0 An nstage ripple counter can count up to the 1C7 1010 binary value represented by the m-bits. Oft+ 1) = A498 0,19 © 0,0) wommadeeasy.in G3 MADE EASY Objective Practice SetsvA Cro Q.1 Counterisa (@) Combinational Circuit (b) Sequential Circuit (¢) Both (a) and (b) (2) None ofthese 2 Ifa counter having 10 flip flops is intially at 0, ‘what count wilt hold after 2060 pulses. (@) coo0001000——(b) 0000001110 (©) 0000011100 (a) 0000001100 Q.3 How many decade counters are necessary to implement a devide by 1000 counter and divide by 10,000 counter? (@ 10 (e) 100 (o) 1000 3 Q.4 The counter shown in figure is built with 4-7 flipflops. The flipflops can be reset asynchronous when R = 0. The logic required to realize a mmodulo-14 counter is, @yY Q5 In figure, initially Q = A = B= 0. After three clock triggers, the states of Q, A and Bwill be respectively is recall Counters Q.6 By using two T-tip-fiops we wish to design a synchronous counter having 2-bit random sequence are: 00+ 10-> 11-01 +00 1 +e} ac | {ise er| el For the design of counter, involved logic gates G, and G, respectively are (@) Ex-OR and NOT gate (0) Ex OR and ExNOR (©) NOTandEx-NOR (@) NOTand AND Q.7_ Number of flip-flops that would be required to build Mod-19 counter i QB _Fortheintia state of 000, the function performed bythe arrangement ofthe LK Tip-fop inthe given figure is fa Sf a | sg Our—ol A gO g Or — —| (@) Shift Register (b) Mod-3 Counter (c) Mod-6 Counter (@) Mod-2Counter 9 A4-bitsynchronous UP counteris holding a state (0101. What will be the count after 27" clock pulse? (@) o101 (©) 0001 141 (@) 0000 Q.10 Consider a two bit counter which implements the sequence 0-2-3-1-0, thenMABE EASY [ERS 2078) Digital Logic | 413 @ xX=@6a). Y= () X=Q,eQ, (© X=Q4Q,, Y= (@ X=Q,0Q, ¥ Q.11 Acounter made up of Tfipflops with a feedback circuit is shown below. What is the modulus value of the counter? (Counter is initialy with state 0000) "Fahy Q.12 Two counter circuits, counter-1 and counter-2 are shown below with their clock frequencies as BOktiz and 40kHz respectively Up at—_fo_ afb a a at a J tal fal Clock ei Counter’ 4 feats 2, 6, Clock Counter? If f,and f, are frequencies at outputs Q, and Q, respectively, then what is the value of (f,/ )? Q.13 The divide by N counter as shown in igure. If intially Q, = 0, Q, = 1, Q, = 0. What isthe value of N? — bo a JO, 21K can} icin rs oak @s (0) 6 ©3 @4 wonwimadeeasy.in (gmMabE Easy MaDe Easy Objective Practice Sets| Computer Science & IT Q.14 A 3. ripple counter uses J-K flip-flops. If the propagation delay of each flipflop is 50 n sec, then whet willbe the maximum clock frequency that can be used in megahertz? Q.15 Apuise train witha frequency of 1 MHzis counted using a module 1024 ripple counter built with J- K flip-flops. For proper operation of the counter, the maximum permissible propagation delay per flip lop stage is, @) t0nsec (0) 100nsec (© 1000nsec —(@) 100 sec Q.16 The following counter has umber of states Ga Se —> “ly «fed ax. Q.17 Aswitch-ail ring counter consisting of 5-FFs. If this counter has P-states and it counts maximum. decimal number Q the correct values of Pand Q respectively are (@) P=32,Q=32 © P=10,Q=31 (0) P=32,Q=31 @ P=5,0=16 Q.18 Figure shows a mod-K counter, Here K is equal Q.19 The initial state of MOD-16 down Alter 37 clack pulses, the state of the counter will be Q.20 Match List with List-I and select the correct answer using the codes given below the lists: List List A. Shiftregisior 1. Frequency division B. Counter 2, Addressing in memory Postal Study Course EEE] Ga made ERmsy Codes: A eC @ 3 2 1 ) 3 1 2 @ 2 1 8 @ 1 2 2 Q.21 A Sit ripple counter uses JK flipflops. If the propagation delay of each flitlop is 80 n sec, then what will be the maximum clock frequency that can be used in megahertz? Q.22 Consider the following synchronous count made up of JK, D and T Flip-Flops, 7 oj}— a}—{r a] te Cte ox—_t__f Find the modulus value of the ter. .23 If Q,is output and initial state is Q,Q= 00, the circuits cul} (@) Divide by two counter (b) Divide by three counter (©) Divide by four counter (@) Nodivision happens Q.24 The below figure shows a mod-N counter, The value of Nis chips —_ ©. Decoder 9. Sorial to parallel data conversion (EF objective Practice sets Gmade eEnsy www.madeeasy.infa] MADE EASY 1 243 @ 4 @ 6 15, (b) 17. (©) 20. (b) 23. (b) 24. 2. (a) It completes one cycle in 1024 pulses and two cycles in 2048 pulses and 2060 ~ 2048 = 12. Binary representation of 12 is 0000001 100. 4. (a) Hore in given counter crit Ris preset and“@ cuiputis connected as lock. So, aNAND-ate isused as combinational logic cicul Mod-14 =1110 The logic requitedis ¥ = 0,0; 0,0, ¥=0,0,2;0, 5. (110) 4K flip-flop is in toggle mode so alter every clock pulse outout Qtoggles. So output Qwill be as +s + +O, and Qis input te MOD-3 counter then | after 3 clock pulses of input clack there are 2 ++ve edge of clock input Q so output of counter goes to2= (10), So, AB= 10 So, Q, Aand Brespectivelyis 110 6. (b) The given random sequence is, (Q, Q, = 00> 10-4 11-401 500...) wwwmadeeasy.in Postal Study Course EXEE Gamaode easy Digital Logic | o & © & @ 0 @ 13. @ © First of all we write @ state table as: Present State Wont Sate] Gm Gin | Gant Groot rr 1 octet 1 + if 4 0 340 oo oat (Eschaton Tate] = 7; [1 a o 1 4 ° ° 1 From the above state table and excitation table we get, T= 00, +0;0, =, 80, =0, 0, T, = Q,(BeNOR}Q, 0 Again, 7, = 0) +0,0;=0,60, F, = Q(-OR)Q, «ii Since, T, [| > EXOR gate ac Te [Gj] > Ex-NOR gate 7. (8) As 8. (c) Given figure is a Jhonson counter, so maximum possible states in output willbe 2n, where nis the number of flip-flops. 32. ieea ea pie Poko bak Objective Pace Set| Computer Science & IT Initial state = 000 Present state Next stato 222 244 00 0 0 Ot 00 1 0 1 4 oO 4 1 4 44 6 diferent states. 13. ttt 4 40 11 0 + 00 10 0 0 0 0 Hence, option (ea correct. 9. (d) After every modulus the initial state will repeat hence after 16 clock pulses the counter holds the same state i. decimal 5 The remaining clock pulses 27 - 16 = 11, sothe final state Is 11 + 5 = 16. For this counter 16 means 0000 10. (a) x y—fo, 2, 14. oxy | oo 0 0 ° 4 1 3 4 1 > 10+ 20> 00 est) 2a = 15, So, only 1 state = It is mod ~ 2 counter a) Countert is a twisted ring counter BokHz 2x4 12. =10kHe [SJ Objective Practice Sets Thee acd 2018] (mabe Ensy G3 Ape ERs Counter 2s a ring counter fx LOH so te tO kH TOK (a) QB = Jyh + 08 = OFS +QFOH = 07 QP" = OP +, OF = OO? +Q2Q? = a3 Of" = J.B +K,08 = OF Of +Ohaz Initial state = Q, Q, Q, decimal 010 clockpusei> 0 01 4 Clockpulse2> 100 4 clockpuise3> 1 10 © 6 clockpuses9 i 1107 clockpuse5> 0 1 1 3 clock puise6 > 0 0 1 axis of system clock puise7 > 1 0 0 4 Here 5 states appeared so the value of N= 5. (6.67) T23x50nsec or Tz 150nsec Trin = 150RS€C tx10® ac = y5q” = 867 MHZ Since loading is synchronous type, for every niipble to load, one clock pulse is needed. No.of clock pul ‘Operation LSB nibble writen 7 ‘4 56 nibble ead 1 MS nibbe writen | 4 MSBnibbioread | Total clock pulses = 1+ 441+4=10 (b) Pulse train frequency = 1 MHz = 1 pulse takes = 10 sec ‘And so, maximum propagation delay permissible through all stages = 10° sec. Now because the ripple counter in question is modulo 1024 ripple 10° cyclesisec www madeeasy.incounter => it will be n bit ripple counter with 10, so there will be 10 stages 024,i.e.n= inthe counter. So the maximum permissible propagation delay per flip lop stage 108 “Uy 7 100% 10 sec 100n sec. MADE EASY [RM 2078) o Myo oT : : ; : oY ; “Lo : So, state diagram of the counter will be 2. Ithas 3-states, 17. (0) The switch-tall ing conteris nothing but a twist ring counter or Johnson counter. With n-FFs, the total number of possible states = 2n=2x5=10 P210 Also with rFFs the maximum count by this Nag = (BN (31)i0 18. (3) Itis 2 mod-3 counter (00 + 01 -> 10 + 00) So, K=3 www.madeeasy.in - GEMaDE EAs Digital Logic | 19. (0001) ST = 16x2+5 Alter 37 clock pulses, the state of MOD-16 DOWN counter will be five states below the prosent state. 011016) ~0101(-5) 007 20. (b) Shift register: Serial to parallel data conversion Counter: Frequency division Decoder: Addressing in memory chips 21. (6.67) Tz 3x50nsec = 150nsec Tan = 1501880 tx10? la * “fgg” 7 887 Mz 22. (5) Consider characteristic equation of J-K Flip Flop: Qoy.s = Jay + KQany J= QiK=1 > Qsys= A Oy (i) Q)=1 > Qy 1) =0 = Qyyy= Oy Consider characteristic equation of D Flip-Flop: Qu D Ons = a) Consider characteristic equation of Flip-Flop: Our = TO Qy Ou = OQ (it) Using equations (i), (i) and (ii) a ale a % opi oo | sfo 0 7 ofs 0 4 ifo 0 0 ofo 1 0 sto 44 ool oe si[o 1 0 €19-—~((0)}—~61) Cy ‘The number of used states “. Modulus value of the counte Objective Practice Sts® | Computer Science & IT sstal Study Course PEE O3MADE EASY 23. (b) 24. (c) GK ] [Oe aS, y= Qy Ky = 1 and Jy =G,Ky=1 apoyo | a J nilols|]a ERs hie oy m2iilo 0 - 1 - 11/0 0 halol|o] + for 1 sto 4 majo 1 1 141 1414 0f [ns]s] 0 fo | o io to 0 Fromihe above or every ckppuises.Q, giving _ 1 oye. So, divide by 3 counter. CE ctiecive Practice sets (omabe ensy _oeieaddeanyin