Q1

module main;
reg [3:0] A;
reg [3:0] B;
reg sel;

wire [3:0] out_sum_diff;

wire [3:0] carry;
wire [3:0] borrow;
Mux_Adder_Subtractor g1(A,B,sel,out_sum_diff,carry,borrow);
initial
begin
$monitor(" A=%b\n B=%b\nTotal=%b\n\n carry=%b borrow=%b
",A,B,out_sum_diff,carry[2],borrow[2]);

sel =0;
A = 4'b1101;
B = 4'b0100;
#100;

sel =1;
A = 4'b1001;
B = 4'b0100;

end
endmodule
module Mux_Adder_Subtractor(a,b1,cin,out_sum_diff, carry,borrow);
input[3:0] a,b1;
input cin;
output [3:0] out_sum_diff;
output [3:0] borrow;
output [3:0] carry;
wire [3:0] sums;
wire [3:0] diff;
//subtractor

wire [3:0] w;
not n1(w[0],b1[0]);
FullAdder h1(diff[0],borrow[0],a[0],w[0],1'b1);
not n2(w[1],b1[1]);
FullAdder h2(diff[1],borrow[1],a[1],w[1],borrow[0]);
not n3(w[2],b1[2]);
FullAdder h3(diff[2],borrow[2],a[2],w[2],borrow[1]);
not n4(w[3],b1[3]);
 FullAdder h4(diff[3],borrow[3],a[3],w[3],borrow[2]);

//adder
FullAdder g1(sums[0],carry[0],a[0],b1[0],1'b0);
FullAdder g2(sums[1],carry[1],a[1],b1[1],carry[0]);
FullAdder g3(sums[2],carry[2],a[2],b1[2],carry[1]);
FullAdder g4(sums[3],carry[3],a[3],b1[3],carry[2]);

mux_4bit fu(sums,diff,cin,out_sum_diff);

endmodule

module FullAdder (s,cout,a, b, c);

input a, b,c;
output s, cout;
assign s= a ^ b^c;
assign cout= (a & b) | (c&(a^b));
endmodule

module Full_Subtractor(D,B,X,Y,Z);
output D, B;
input X, Y, Z;
assign D = X ^ Y ^ Z;
assign B = ~X & (Y^Z) | Y & Z;
endmodule
module mux_4bit ( a ,b , sel, dout );

output [3:0]dout;

input [3:0]a ;
input [3:0]b ;
input sel ;

assign dout = sel ? b : a;

endmodule

Q3

module 8x1_mux_using_2_4x1_mux{O,s,i);
input [7:0]i;
input[2:0]s;
output O;
mux a ({s[1:0]},{ i[3:0]},w1);
mux a1({s[1:0]},{ i[7:4]},w2);
not n(w3,s[2]);
and an(w4,w1,w3):
and an1(w5,w2,s[2]):
nor n1(o,w4,w5):
endmodule

module mux( sel, in, out );

input[1:0] sel;
input[3:0] in;
output out;
reg output;
always @( sel or in )
begin
if( sel == 0)
out = in[0];
else if( sel == 1)
out = in[1];
else if( sel == 2)
out = in[2];
else if( sel == 3)
out = in[3];
else
out=1’bX
end
endmodule

Q4

module d3x8( output [7:0] d ,input [2:0] a, input e );

wire x,y,z;
not g1(z,a[0]);
not g2(y,a[1]);
not g3(x,a[2]);
and g4(d[0],x,y,z,e);
and g5(d[1],x,y,a[0],e);
and g6(d[2],x,a[1],z,e);
and g7(d[3],x,a[1],a[0],e);
and g8(d[4],a[2],y,z,e);
and g9(d[5],a[2],y,a[0],e);
and g10(d[6],a[2],a[1],z,e);
and g11(d[7],a[2],a[1],a[0],e);
endmodule
module d4x16(out, in,e);
output [15:0] out; input [2:0] in; input e;
d3x8 d1(out[7:0],in[2:0],e);
d3x8 d2(out[15:8],in[2:0],~e);
endmodule

Q5

1. module pr_en ( input [7:0] a,  
2.                input [7:0] b,  
3.                input [7:0] c,  
4.                input [7:0] d,  
5.                input [1:0] sel,  
6.                output reg [7:0] out);  
7.   
8.    always @ (a or b or c or d or sel) begin  
9.       if (sel == 2'b00)  
10.          out <= a;  
11.       else if (sel == 2'b01)  
12.          out <= b;  
13.       else if (sel == 2'b10)  
14.          out <= c;  
15.       else  
16.          out <= d;  
17.    end  
18. endmodule