COMSATS UNIVERSITY ISLAMABAD

Department of Computer Sciences

LAB REPORT 2

Subject:
Digital Logic Design

Submitted to:
Ms. Kiran Nadeem

Submitted by:
Sharjeel Shahid SP19-BSE-104
Shazif Rizwan SP19-BSE-105
Shoaib Naseer SP19-BSE-106

DATE: 25-feb-19

Table 2.9: Observation Table for OR gate

 INPUTS OUTPUT

𝑨 𝑩 𝑭

0 0

0 1

1 0

1 1

Proteus Simulation:

Post Lab Tasks

Task 01: Simulate NAND, XOR and XNOR gates in Proteus software, by using only NOR gates.
Verify their truth tables.

NAND gate using NOR gate:

Truth Table:

A B OUTPUT
0 0 1
0 1 1
1 0 1
1 1 0

XOR gate using NOR gate:

Truth Table:

A B OUTPUT
0 0 0
0 1 1
1 0 1
1 1 0

XNOR gate using NOR gate:

Truth Table:

A B OUTPUT
0 0 1
0 1 1
1 0 1
1 1 0

Critical Analysis:

In this lab we implemented Boolean functions using logic gates by which we can form
any logic gate by interconnecting several logic gates of another type.
This involves connecting of one logic gate’s output to another gate’s input and involves
using AND, OR, NAND and NOR gates.
We created several logic gates using only NAND and NOR gates.