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PWM Methods
PWM Methods
CHAPTER 3
MODULATION TECHNIQUES
3.1 INTRODUCTION
where VrR ,VrB and VrY are R-phase, Y phase and B phase reference voltages
41
Figure 3.1 Reference signals of the three phase sinusoidal PWM technique
Figure 3.2 Carrier signal of the three phase sinusoidal PWM technique
42
The output pulse applied to the gates, through switch control device
for switches. The upper limbs connect the positive DC supply to the loads and
the lower limbs connects the negative DC supply to the loads through the
inverter connected in series.
43
Figure 3.4 Three phase SPWM control circuit output gate control signal
44
Frequency-modulation ratio = Fc / Fr
𝑉𝑑𝑐
Vry1 = (MI)(√3)
2
𝑉𝑃𝑛
Vfn = (3.1)
𝑛(𝑅1 𝐶)𝐹𝑟
𝑉𝑃1 𝑉𝑃1
Vf1 = (𝑅 = 𝑉𝑟 → (𝑅1 𝐶)𝑉𝑟 (3.3)
1 𝐶)𝐹𝑟 𝐹𝑟
47
In Equation 3.3, it has been shown that the ratio Vp1 / Fr remain
constant until the DM output Vp becomes a square wave of frequency Fr = Frb
at which point
4
Vp1 = 𝑉𝑆 (3.4)
𝜋
The Equation 3.5 is obtained from the Equations 3.3 and 3.4
4
𝑉𝑃1 𝑉 4𝑉𝑆
𝜋 𝑆
= = (𝑅1 𝐶 )𝑉𝑟 → 𝑅1 𝐶 (3.5)
𝐹𝑟 𝐹𝑟𝑏 𝜋 𝑉𝑟 𝐹𝑟𝑏
Δ𝑉 𝑅1
= (3.6)
Δ𝑉𝑆 𝑅2
2
𝑇𝑟𝑚 = (3.7)
𝑁𝑐𝑚
𝑇𝑟𝑚 2𝛥𝑉 𝛥𝑉
= → 𝑇𝑟𝑚 = 4𝑅1 𝐶 (3.8)
2 𝑉𝑆 /𝑅1 𝐶 𝑉𝑆
Substituting the Equation 3.6 in Equation 3.8
𝑅2 𝑅2 𝑇𝑟𝑚
𝑇𝑟𝑚 = 4𝑅1 𝐶 → = (3.9)
𝑅3 𝑅3 4𝑅1 𝐶
𝑅2 1
= (2𝑅 (3.10)
𝑅3 1 𝐶𝑁𝐶𝑀 )
4 × 12
R1 C = = 3.2 × 10−3
2 × 10 × 2𝜋 × 76
𝑅2 103
= = 0.01
𝑅3 (2 × 3.2 × 1500)
and improved delta modulation. This section first discusses about the delta
modulation. Secondly, it discusses about improved delta modulation.
(a)
(b)
Figure 3.7 Delta modulation circuit and related waveforms (a) Block
diagram of the delta modulation controller (b) Typical
reference, carrier and DM output waveforms
50
𝑆𝑐2 −𝑆𝑟2
𝐹𝑠𝑤 = (3.11)
4𝛥𝑉.𝑆𝑐
1 𝑆
𝐷𝑅 = (1 + 𝑟) (3.12)
2 𝑆𝑐
𝑉𝑟 = 𝑉𝑚 sin 𝜔𝑡 (3.13)
𝑆𝑟 = 𝜔. 𝑉𝑚 Cos 𝜔𝑡 (3.14)
𝑉𝑃 ±𝑉𝑑𝑐𝑡
𝑆𝑐 = = (3.15)
𝑅𝐶 𝜏
where Vdct is the DC rail voltage and τ is the time constant of the integrator.
Substituting the Equation 3.13 and 3.14 and 3.15 in the Equation 3.11. The
switching frequency Fsw can be determined as
2
𝑉𝑑𝑐𝑡 −(𝜏.𝜔.𝑉𝑚 cos 𝜔𝑡)
𝐹𝑠𝑤 = (3.16)
4𝜏.𝛥𝑉.𝑉𝑑𝑐𝑡
Substituting the Equations 3.13, 3.14 and 3.15 in the equation 3.12.
The switching frequency DR can be determined as
51
1 𝜏.𝜔.𝑉𝑚 cos 𝜔𝑡
𝐷𝑅 = (1 + ) (3.17)
2 𝑉𝑑𝑐𝑡
2
𝑉𝑑𝑐𝑡
𝐹𝑠𝑤 = (3.18)
4𝜏.𝛥𝑉
1
𝐷𝑅 = (3.19)
2
The Equations 3.18 and 3.19 imply that the switching frequency
and duty ratio of the delta modulator are constant value for a constant
reference voltage.
From Figure 3.8 (a) the slope of the carrier waveform of the
improved delta modulation (Sci) is given by
𝑉𝑃 −𝑉𝑟 ±𝑉𝑑𝑐𝑡− 𝑉𝑟
𝑆𝑐𝑖 = + 𝑆𝑟 = + 𝑆𝑟 (3.20)
𝑅𝐶 𝜏
Substituting Equation 3.20 into the Equations 3.11 and 3.12, the
switching frequency Fswi and duty ratio DRi of the improved delta modulation
controller can be derived and expressed as:
2
𝑉𝑑𝑐𝑡 −𝑉𝑟2
𝐹𝑠𝑤𝑖 = (3.21)
4𝜏.𝛥𝑉.𝑉𝑑𝑐𝑡
52
1 𝑉𝑟
𝐷𝑅𝑖 = (1 + ) (3.22)
2 𝑉𝑑𝑐𝑡
For a sinusoidal reference signal, the Equations 3.13 and 3.14 can
be substituted into 3.21 and 3.22 and the following equation can be obtained
2
𝑉𝑑𝑐𝑡 −(𝑉𝑚 sin 𝜔𝑡)2
𝐹𝑠𝑤𝑖 = (3.23)
4𝜏.𝛥𝑉.𝑉𝑑𝑐𝑡
In this IDM, the variation range of duty ratio DRi can be increased
due to the inverse proportional relationship between the magnitude of the
input reference signal and the slope of the carrier signal. That is an increase in
the reference signal magnitude will reduce the slope of the carrier signal and
decrease in the reference signal magnitude will increase the slope of the
carrier signal. Because of the increment in the carrier signal slope, the
integrator takes longer time to complete the integration. So the output carrier
signal needs more time to change its output status. Hence the duty ratio of the
IDM can be expanded to increase the output voltage.
(a)
(b)
(c)
Figure 3.8 Improved delta modulation and its waveforms (a) Block
diagram of the improved delta modulation (b) reference
signal and IDM output gate pulse (c) improved delta
modulation output gate pulse and integrated feedback signal
with variable slope
54
The error between the reference sine voltage signal and feedback
signal is allowed to oscillate within an upper limit and lower limit of the
defined window, equally above and below the reference sine voltage signal in
the hysteresis comparator. The two limits intersecting points determine the
state of the PWM output IDM switching function VP. This is shown in
Figure 3.8 (c) by PSIM simulated results.
3.5 SUMMARY