Unit: STA-241 Static Timing Analysis TVLSIGURU Static Verification Flow TVLSIGURU Functional Im lieSLACK ANALYSIS — Data Path Types TIVLSIGURU PAT snput Port > REG pag: a66 > Res PATER REG 9 Output ort PATA :Input Port > Oupur tot Timing exceptions TIVLSIGURU Timing exception includes the following:+ False Path- Use the set_faise_path command to specity a logic path that exists in the design but should not be analyzed. Setting a false path removes the timing constraints on the path, + Multiple Cycle Path - Use the set_mutticycle_path ‘command to specify the number of clock cycles required to propagate data from the start to the end of the path. + Min/Max Delay - Use the set_max delay and ‘sot_min_delay commands | override the default setup and hold constraints with specific maximum and minimum time values. Setup/Hold Analysis (in he absence of timing exceptions) Setup/Hold Analysis (nthe absence of tiing exceptions) Setup check - vets tha the dats launched trom FF at ie=0 arives at the D input of FF2 in imo or ho capture edgo at imo=10. the data takos too ong o ave, itis eporad a8 a setup violation. *Hold check - vos tha! the data launched ftom FF1 at time 0 doesnot ‘get propagated so soon that it gets captured at FF2 atthe cock edge time 0: the data aves too soon, lis reported as a hold lao. TIVLSIGURUTiming Verification of Synchronous Designs TIVLSIGURU Static Timing Verification of FF2: Setup Fr1/etk¥r2/0 wreak Fri/eik rr2/o wezjeie Four Sections in a Timing Report report_timing uariplnts er tclaiag adyetsigqead f1p-fiop locked by cit) aS Tagg. PF stniog day trgoered flap-Fep chocwa by 8) {me See neO he eget ci a TIVLSIGURU The Header sarglss Pr calgary cn yc) str ta ar oo — capture clock “Report is: for setup TVLSIGURU Data Arrival SectionTVLSIGURUTT ‘DIVLSIGURU Summary - Slack report_timing eran treim one eropen titi ceca EQS ad elt Taersgeas up-top shies oy 8)” lest ik (ing som mya SS.Fro rar PAE TVLSIGURU PrimeTime Terminology ‘Stack s the diterence between dala arial anc required, eras} —. ae TIVLSIGURUrere est seman e Be ae ef cn er fee eer ree TIVLSIGURU Example Eraeko Ty 2 max pe Hh 8 typ, = 40ns, ty = 20ns Tw2 tout by Ty >40120= 60 TIVLSIGURU ExampleCe > fatten" ate Ty 2 max topp + MAX tpyyy + ty TVLSIGURU Example Tove Ta Ty 2 max tpg + MAX tux thsTIVLSIGURU Example Paths fom Q1 901: Noe Pats from Q1 £02: Ty > ma pp Mya 20-410~ 305 Ty Em ore MI yvo 206124 10~42n8 Paths fom Q210 QI: Ty 2 aX ese Hoe * Tou = 25+ 10-4 $= 40.08 Paths fom Q2 10 Q2: Ty 2 Ma pyre FM Hayy ye 25°12 1047 ns Tw247 earns TIVLSIGURU Clock Network Reports For each clock, report REAL skew ptsTIVLSIGURU Detecting timing violations — CASE 1 (2) Hold time for clocks is 1.5 ns Determine i there are any timing violations inthis design haownaeh taunts ora TIVLSIGURU Detecting timing violations —(2) Hold time for clocks i 1.5 8 (0) Clock nw delay for Capture flop is of 3.72 ns and source top is 0 ns. Determine if there are any timing violations inthis design oee1 *——Oeky in} = 5s ——+ ore ‘akzomnare ckowhe TIVisiGuRU Example (Etfect of cock skew on clock rate) Clock © shewed ser Cl pe lel ee a ie ee ee o rm r— —— = cr « mj cr oe ora ore Ty =man Typ + mAN toe hy Ty 2mm Thyp FAX toe Hein (if lock ot skewed ie, yy 0) —_ielock skewed ety * 0) TAVLSIGURUCock stewes ater ‘Ty 2 mae Thy + Eye “Ey (Glock ot skewed, ie gy 0) Ty 2 man Thy + MH Eog + fy ty (Gelook skewed, 12, oy 9) TIVLSIGURU Sumnoaty of menu clack regency cnlenltoen(€2 skewed ater CL: Ty 2 max They MAX Key by iM ty (€2 skewed before C1: Ty > ax Typ +e ty ty FM ty TAVLSIGURU False Path Paths through whict From the example above: "The delay of the longest path from ‘i to ‘outs 8 and not 10! should not be propagated >the paths [n-A-CE-out] and [i-8-C-0-out] are non-sensitizable since they require contracting values on ‘en’ TIVLSIGURU Multi —- Cycle PathsSeats toe stein ore ck ee Soros tora es oe Sei Sra ito pn chxamphg oman wc 5 Taal from Gecko edge aarp poet 300 + From he above example wit MCP cena eee eavcegar sah ten, Mow costo. ae orang cP ere can by meer een gia eat a tac eng hoot TVLSIGURU Multi - Cycle Paths (contd.) TIVLSIGURU Specify Timing Assertions (2)‘om o 15 30 sara i W a cee oO 15 30 etree cock CI ! tee 55 25 355 seemmnce ft oon a os aa enc cost cmon 0 1 a sedan 55 205 355 TIVLSIGURU Negedge Triggered Registers: Setup Time — what happenst Froblem r/o hl tine» Ss Gio = Ops f6rS80; Pra/olk TVLSIGURUmiyen wd wa hppesto Ny tour eee roti etme «50: lone em chocoptrseo: }' = FFL= 10p5 ; rr2/oik HO 2s; TAVLSIGURU Timing Report for Hold ene ae eae {lning ed: trinyras fip'tiop shoaked by CD Saree taaeciaig”TIVLSIGURU Setup Definition - Summary Data must become valid and stable at least one setup time before being captured by flip-flop. © Shh =a oi iba T= Hold Definition - Summary Data remains stable for a minimum time as required by capture flip-flop. (Hold Check) £21 [Sy a Al a aia ne = 0TVLSIGURU Estimating Rnet and Cnet Pre-layout = Extraction data of already routed designs are used to build a lookup table called the wire load model = WLMis based on the statistical estimates of R and C based on “Net Fanout” Wire Load Model (RC) Estimated RCs are represented as wire load model TIVLSIGURU Cell Delay Calculation'= Cell delays are calculated from a Non Linear Delay Model (NLDM) table in the technology library 1 Tables are indexed by input transition and total output load for each gate ‘carbeayins) TIVLSIGURU Net Delay Calculation = Net delay is the “time-of-flight” due to the net's RC 1= Net's RC is obtained from wire load model for pre-layout design — oat Roet — CnotTIVLSIGURU Output Transition Calculation '= There is another NLDM table in the library to, calculate output transition ‘= Output transition of a cell becomes the input transition of the next cell down the chain TIVLSIGURU What About Negedge Triggered Registers? ox l ee a te: 1 PETE f= el TVLSIGURU What About Multi-Frequency Clocks? visicuRU What About Interface Paths: Input Ports? Bal Ports ofthe design,TIVLSIGURU What About Interface Paths: Output Ports? You speciy the path requredtime atthe output ports ofthe design TIVLSIGURU Interface Paths in a Timing Report: OutputTAVLSIGURU Interface Logic Models (ILM) {+ Enbl orchin STA dice mentary and CPU usage fr cp ove araals + Ofer tg eit econ bo Os re ropes Backanotton rd const es aac aro wien Scant «Bent Vig accuracy bozaso aco log no abated 1 rastnoel geerton tine «nin aeponget + Sanchange oa, dv, operating condos, parses, SOF, onan thui generating he madeTIVLSIGURU PVT —- PROCESS/VOLTAGE/TEMPERATURE PROCESS : ‘As L increases, process becomes slower and delay increases. TIVLSIGURU PVT - PROCESS/VOLTAGE/TEMPERATURE — (contd) VOLTAGE : Why we wil see voltage variations. Asvoltage creases, the celaysof the ele ecreases maTVLSIGURU PVT — PROCESS/VOLTAGE/TEMPERATURE — (contd) “Temperature: Why to model temperature variations. Temperature TVLSIGURU Problem = Given corner data below, which combinations are expected to lead to worst and best gate delays? + Process + Siow+ Typical + Fast + ener + 09v * 10v ea + Temperature + 0c +210 + 1056 TIVLSIGURU Clocks a ex ex as vous be Dena eng yi at opr inher + Peres 1 Stvaruneeainy Overview= In this era of high performance electronics, timing continues to be a top priority and designers are spending increased effort addressing IC performance. ‘= Two Methods are employed for Timing Analysis: + Dynami¢ Timing Analysis + Static Timing Analysis TVLSIGURU Dynamic Timing Analysis ‘= Traditionally, dynamie simulator has been used to verity the functionality and timing of an entire design or blocks within the design. ‘= Dynamic timing simulation requires vectors, a logle simulator and timing information. With this methodology, input vectors are used to ‘exercise functional paths based on dynamic timing behaviors for the chip or block. ‘= Dynamic simulation is becoming more problematic because of the difficulty in creating comprehensive vectors with high levels of coverage. "= Time-to-market pressure, chip complexity imitations in the speed and capacity of traditional simulators are all motivating factors for ‘migration towards stalic timing techniques.TIVLSIGURU Static Timing Analysis (STA) = STAisan exhaustive method of analyzing, debugging and validating the timing performance of a design ‘First, a design is analyzed, then all possible paths are timed and ‘checked against the requirements. = Since STAs not based on functional vectors itis typically very fast land can accommodate very large designs (multimillion gate designs). '= STAs exhaustive in that every path in the design is checked for timing violations. 1 STAdoes not verity the functionality of a design. Also, certain ‘design styles are not well suited for static approach. For instance, ‘dynamic simulation may be required for asynchronous parts of a design and certainly for any mixed-signal portions. TIVLSIGURU Static Ti ig Analysis (STA) ‘STA consists of three major steps: ‘Break down the design ino timing paths (R-R, PLR,PLPO & P-PO). ely ofeach path is calculated 1 Allgath delays are checked agaist timing constrains to see itis met sSTAadvantage + Speed (orders of magnitude faster than dynamic simulation) 5 Capacty tohanding ful chip 1 Exhaustive timing coverage 1 Vectors are not required STA disadvantage This possimste too conservative)+ Reports false paths ‘= Flow Inputs: Gateovel Voriog * Constants (SD) 1 Bitracted nes (SPEF) + Ubrates (liberty format - ib) TIVLSIGURU Analysis Modes + Semiconductor device parameters can vary with condtions such as {abrication process, oparating temperature, and power supply voltage, + The STA tool supports three analysis modes: ‘+ Single operating candtion single set of delay parameters is used forthe ‘hole cc, based on one sot of proces, temperature, and volage ‘concione + Min Max (86-0) oporating condition - simultaneously chocks the cect for ‘ho two exreme operating conctions, minimum and maximum. For soup ‘checks, uses maximum delae for al paths. For hold nooks, R Uses ‘minim lays + On-chip-ariation mode - conservatvatratonal analysis that allows both ‘mismam and maximum delays o apply io diferent paths a the same tine. Fora setup choc, fuses maximum delae for to launch lok path and. ala path, and minimum dolays forthe caplre clock path, For ahold chock, {t'usce minimum dlays forthe launch lok path ard data path, and ‘maximum dolys forthe capture dock path, TIVLSIGURU Single Operating Condition lSingle set of delay parameters for the whole clrcult, based on ‘one set of process, temperature, and voltage conditions. Hold Setupstrate -orge seperenm are Sold SET Try tts eoecaed WORST ea sou TVLSIGURU Best case/Worst case Analysis ‘Simultaneous checks of extreme operating conditions, minimum and ‘maximum, ‘For setup checks, it uses maximum delays forall paths. {For hola checks, i uses minimum delays for al paths. On-Chip Variation AnalysissConservativerTraditional analysis that allows both minimum and ‘maximum delays to apply to iferent paths atthe same time. Fora setup check, uses maximum delays for the launch clock path and data path, and minimum delays for the capture clock path Fora hold cheok, it uses minimum delays forthe launch clock path and éata path, and maximum delays forthe capture clock path stable -onhron TIVLSIGURU Derating ‘sMinimum and Maximum delays can be adjust by specie factors to ‘model th effects of operating conditions. This agjustment of calculated ‘dolays's called derating.. 1 Derating affects the delay and slack values reported by report_timing. setTimingDerate -max early 0.8 tate 1.05 setTimingDerate-min early 1.0 -lato.tTIVLSIGURU TIVLSIGURU Clock Reconvergence Pessimism Removal (CRPR) ¥en launching and capturing clock share common path the omumon ath aay te a Gay wi daar asian 10 both setup and hold analysis. ‘CRPR can be used to remove this pessimism. eastern Saget tag shore cee earners pesinem ne TIVLSIGURU Multiple Cycle Setup Multiple Cycle Setup sf datas launched every 3 cycles, thon sotupis checked against the {hird rising edge (0.7) and holds checked against next sing edge (whichis CLK at 6.50, '=STA too! veriis thatthe data launched by the setup faunch edge is ‘ot captured by the previous capture edge. So the default hold check for‘mult-eyole setup is capture edge minus one. TVLSIGURU Multiple Cycle Hold 'Tho number attr the -old option specifies the numberof cycles to ‘move the hold check backward from the default postion implied by the setup check. ‘A postive number moves the check backward by the specified number of cycles, Speciying zero does not change the hold check time. TVLSIGURU CCS & NLDMDifference Hetwcen CCS and NLM What is CCS and NLDM: {CCS stands for Composit Current Sourse Model and NLDM stands for ‘Non-Lineae Delay Mode, Bath CCS & NLDM are delay models used i ining analyze Difference between OCS & NLDM SNLDM woes voltage source for driver modeling “eCS utes acurent source for driver modeling Why prefer CCS to NLDM: “The sues with NLDM moselngs that, when the drive resistance RD bocomes much les than Znet(network load impedance), then ideal condition arses Le Vout-Vin, Which simple in praetical conditions So with NLDM modeling parameters ike the cll el aleulation, skew taleulation wal be insecurate That the reason why we prefer CCS to NLDM. TIVLSIGURU