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    (Chen, 1992)-Threshold Voltage and C-V Characteristic of SOI MOSFET Related to Si Film Thicness Variation on SIMOX Wafer

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    (Chen, 1992) - Threshold Voltage and C-V Characteristic of SOI MOSFET Related To Si Film Thicness Variation On SIMOX Wafer

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    Threshold Voltage and C-V Characteristics of SOI MOSFET’s Related to Si Film Thickness Variation on SIMOX Wafers Sian Chen, Student Member, IEEE, Ray Solomon, Tung-Yi Chan, Ping K. Ko, Member, JEEE, and. Chenming Hu, Fellow, EEE “Absract—C-V characteristics of fully depleted SOI MOS- T's have been studied using a technique to measure silcon- thickness using a MOSFET. The tec diferent back-gate voltages, and only a large-area transistor "required. Using this technique, SO1 film thickness mapping was ‘made on a finished SIMOX wafer and a thickness variation of ‘£180 A was found. This thickness variation cases as much 25 1100 mY variation in the device threshold voltage, The sllicon- film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for fully de- pleted device. C-V measurements ofthe back-pate device yields the buried-ovide thickness and parasite eapacitances. The ef- fects of GIDL (Gate-Induced Drain Leakage) current on C-V characteris are also discussed, 1. Iwrropucniow KIMCON-ON INSULATOR OD technology is a promising candidate for future VLSI as the quality of $01 material continues to improve. Thin (less than 1000 A) SOI film thickness is important for minimization of shor-channel effects and elimination of current kinks in SOI MOSFET’s [1], [2]. Film thickness influences al the clectrical parameters of SOI devices, such as threshold voltage and subthreshold swing. Nonuniformity in the SOL film thickness results in nonuniform characteristics, ¢5- pecially threshold voltage, Accurate determination of both the silicon-film thickness and the buried-oxide thickness is essential for device design and modeling, There have been a number of studies on SOI film thickness measure- ‘ment techniques such as spectroscopic reflectometty [3], [4], spectroscopic ellipsometry [5], [6], and electrical methods {7]-[12]. SOI MOS capacitor ate also studied (13), 114) In this paper, we will present a thorough study of SOL MOSFET's threshold voltage and C-V characteristics re- lated to Si-film thickness variation on SIMOX wafers, as Manuscript eeived February 26, 1992; revised April 9, 1982. Tit project wat suppored by SRC and AFOSRISED andes Contract P9620. ECopst The rove o ths paper wa ranged by Asoxine Bor R Chen, PK. Ko, and C. Ho ate with the Deparment of Blesticl Engiceing nd Computer Scenes, Unies of alfa erly ener 1 Slonion wih tet Corporation, Su TY. Chanis with Cypress Semicond TERE Log Nemte 920 Cas, CA 94050, ne CA S13. well as the frequency dependences of C-V characteristics, A simple and accurate technique for measuring the sili con-film thickness based on the C-V characteristics was used based upon our earlier work [12]. Using this tech- nique, we were able to determine the SOI film thickness uniformity across a completely processed wafer, and the thickness variation was correlated with the threshold volt- age variation. The SOI film doping concentration ean also be estimated from the correlation between film thick- nesses and threshold voltages. From C-V measurement fon a back-gate SOI device we can also determine the bur- jed-oxide thickness and parasitic capacitances. The var- ious parasitic capacitances due to the buried oxide are modeled. The effects of GIDL (Gate-Indueed Drain Leak- age) current on the C-V measurement characteristics was also studied, ML, Sete C-V Mernon ror MeAsuRixe SOI Pita “Tmickness ‘The SOI devices used in this study were a” polysilicon gate n-channel MOSFET's and p* polysilicon gate P-channel MOSFET's fabricated using a modified sub- ‘iicrometer CMOS technology on SIMOX (Separation by IMplanted OXygen) wafers. The SIMOX wafers were im- planted with a high dose of oxygen ions (10"* em) at 200 keV and subsequently annealed at 1230°C, The SIMOX wafers were thinned by thermal oxidation and subsequent etching of the oxide layer. The NMOS thresh old boron implant dose is 2 10" em”? and the PMOS threshold phosphorus implant dose is 10 em 7, The MOSFET’s used in this study are non-LDD devices. Lat- ral isolation is obtained by LOCOS. The polysilicon-gate thickness, gate-oxide thickness, and buried-oxide thick- ness are 2500, 118, and 3600 to 4000 A, respectively Transistors with W'= 50 jm, L = 50 jum were used to ‘measure SOI film thickness. Device with dimensions as small as W = 10 wm, L = 1 wm can also be used with reasonable accuracy. The HP4275 LCR meter was used to perform the high-frequency C-V measurements, Illustrated in Fig. 1(a) and (b) are the concepts behind this C-V technique for measuring the SOI film thickness fora fully depleted MOSFET [12]. The area of the MOS- FET is suficiently large so it can be described by a one- dimensional model and two-dimensional effects can be ig- .0018:938392503.00 © 192 REE ‘Cipaciunce ie meaoed betwen gate and soured The icon fs) ‘Sly depicted (©) HF C-Y eusuremene on SOV MOSFET wth tno Stern bck sae bins. From he diference betreen Gey stl Cy SOV fim thickness Zea be ound nored. From our experience, transistors with W = 50 um, L = 50 ym, and W = 10 um, L = 10 ym give the same thickness results. This is easy to understand since the sil- icon film thickness is about 1000 A, which is 1% of 10 am, L = 10 um device and 0.04% of W = 50 ym, = $0 pimdevice. Drain and source are tied together and, ‘ade voltage is applied between source/drain and the gate. ‘An ac signal is applied to the gate and the substrate is ac grounded. The large high-frequency capacitance is mea- sured between the gate and the source/drain with different back-gate voltages Vag applied. We can either invert the front channel oF the back channel to measure the front gate oxide capacitance Cyax, OF Cys the front gate ox- ‘ide capacitance Cox in series with depleted silicon film capacitance Cs,. From the difference of those two capac- itances the SOI film thickness Ts, ean be calculated. It is also noticed thatthe value of gate to source/drain overlap parasitic capacitance Coa is small (less than 0.2% of Guax for the devices we used), The details of this tech nique are reported in [12] ‘The inversion-layer capacitance is not considered inthis technique. It can be shown that it has negligible effets in strong inversion [5]. Also, the correction is consistent forall the measurements. Therefore, the measured rela- tive thicknesses among devices are the same. The mag- nitude of the inversion-layer thickness is then calculated, From [15], the empirical form of inversion-layer capaci tance Cy, versus electrical field Ey. is expressed as fol- lows: 8.5 oer T+ exp [40 Exon — 0.39) o Here Cy, is in microfarads per square centimeter and Exon in megavolts per centimeter. The electrical field for the front gate is therefore 2,5 MV /em at Voos = 3 V and that forthe back gate is 1.87 MV/cm at Vag = 75 V. Using (1), the values of Gy are calculated. It is found that the thicknesses of inversion capacitances are 5 A for the front gate and 7A. for the back gate, respectively, ‘They are obviously negligible even for very thin SOL film thickness UI, SIMOX Siticon-FILM THICKNESS AND TugeshoLn-VouTace UNIFORMITY A. Silicon-Film Thickness Uniformity SOL-film thickness uniformity across a wafer has been ‘4 major concem to manufacturers as well as to users of SIMOX wafers, Its important to know the silicon-layer thickness as well as its variation across a wafer for mod- cling and process control, SOI-flm thickness and doping ‘concentration variation across a wafer can result in thresh- ‘old-voltage variation, which in tum can cause other prob- lems. Due to the silicon-thickness variation, itis even possible that within one wafer, some devices are fully de- pleted while others are not, and therefore kinks may ap- pear in some I-V characteristics Due to the simplicity of the C-V technique, it can be used to measute the film thickness variation across a whole ‘wafer and to estimate the doping concentration variation at the same time. The time required for obtaining each point is less than I min, We will report the measured SOI film thickness variation across a SIMOX wafer and cor- relate it to the threshold-voltage variation, Experimental results of threshold voltage dependence on silicon-film thickness are reported for SOL MOSFET’s for the first It is found thatthe silicon-film thickness varies from 680 t0 1005 A for a 4-in wafer. This agrees with the specifications of +150 A provided by IBIS, the manu- facturer of those SIMOX wafers. The same experiments were done for p-channel SOI MOSFET’s on the same wafer and a similar thickness and distribution was ob- tained. This further confirms the validity of the above C-V technique. As shown in Fig. 2, a three-dimensional plot of the measured SOI-flm thickness reveals the to: ography of the SIMOX wafer. A systematic pattem in the thickness variations seems to exist, and the thickness change is more global than local. This suggests that the silicon-film thickness change within one die (usually less than I em X 1 em) is less than 100 A, However, the silicon-flm thickness might change by 300 A for differ- tent dies within one 4-in wafer. Tis is very important knowledge for analog as well as digital circuit designers. B. Correlation Between Si Thickness and Threshold Voltage Te threshold voltage is measured at 10 A per unit W/L at Vo = 50 mV with zero back-gate voltage. A threshold-voltage distribution is plotted in Fig. 3 for Tsi From NMOS Fig. 2. Thee-dimensonl pot of the SOLSim thickness on finished SIMOX water said fom CV tehnigus for chao device, Stee ‘els wer baie fom C1 ecg for penne device, [Namber of Devices ‘Threshold Voltage (¥) ig. 3 channel SOI MOSFET thresol-voliage dsributon of « fo ‘aed SIMOX wafer. Vs ca bes large ss 120 do te kas NMOS and Fig. 4 for PMOS SOI MOSFET’. The fairly large threshold voltage spreads reflect the silicon-film thickness spread and might be a concer for circuit per- formance and subthreshold currents, ‘The correlation between the measured threshold volt- ‘ages and the measured SOI film thicknesses are shown in 5. The threshold voltage increases with increasing lm thickness as expected. From Lim, Fossum [16] and Haond [11], the threshold voltage ofa fully depleted ‘SOI MOSFET is given by 2. 1 Vig + 265 ~~ (Yyg Yi Vln + 2m — 5A = (Ya Vy _ o CoCoox 2s) wees Where V{ and Vjg are the front threshold and back-gate voltages, Vy and Viy are the front gate and back gate flatband voltages, Cox, Cpox. and Cs, are front and back- ate oxide and depleted silicon-film capacitances, Q, is the area charge density in the depleted silicon film. Qy= -GNsTa oF +9NpT @ [Number of Devices | ‘Threshold Voltage (¥) Fig. 4. pchanel SO! MOSFET thesbol-olge disibuion of «Sn tibed SIMOX water ‘Threshold Voltage: SOK Thickness (A) Fig. $. Measured wchane SO! MOSFET held voltae versus ex ‘uted scm thiknes of he save devi. The Score anf a ted Te dpi ocean 3% 1 ean mans ‘elton width is 900 A The spend ia forte same Ts apy te ‘ptead in he doping conection scons the wae ‘This equation applies to n-channel and p-channel devices, where Nj and Np are the p-type body and n-type body doping concentration and Ty, isthe SOL-film thickness Since buried (or back gate) onde thicknesses tpisily range from 3600 to 4000 A, andthe siigon-flm thick. ness of interest isunder 1000 A and eq/tox = 1.9/3.3 Ca. >> Caous we have Garo Goon Cox(Cs + Cuox) Cox [Equation (2) can be written for an n-channel SOI MOS- FET ® Via + 265 ~ Woo ~ Vin ~ 265) Gow, aNaTs Cox * Cox In the case that the film is not fully depleted or Ts, > Xow the threshold voltage is given by + © Vi = Vig + 2g + NeXoras Cox . one = [2224] o aM In (5) we see a linear dependence of threshold voltage ‘on SOI-film thickness with slope proportional to the dop- ing concentration for a fully depleted device. The thresh ‘old voltage becomes independent of silicon thickness in (5) when Ta. is larger than Xpyeqx- The dependence of Vrg and ¢p on N, is neglected for approximation, This only induces a very small error in N, estimation because Vrg and dy are very weak functions of N,. From (5) and Fig. 5, which show the correlation between the measured threshold voltages and the measured SOI film thicknesses. for an n-channel device, doping concentration N, can be calculated from the slope of V/ versus Ts. The doping. ‘concentration obtained from the n-channel slopes is about 1.3 x 10" em”, as shown by the solid line. This doping concentration is little lower than the 2 x 10!” em”? cal- culated from the boron-implant dose divided by the film thickness 7;,. This can be explained by the fact that not all the implant ions end up in the silicon film. After the gate oxidation, part ofthe implanted boron will end up in ‘oxide due to boron segregation, thereby lowering the dop- ing concentration in the silicon film. The same correlation is shown in Fig. 6 fora p” poly-gate p-channel SOI MOS- FET on the same wafer. The negative threshold voltage increases linearly with increasing Si-lm thickness as ex pected. The slope indicates Np = 1 x 10"” em”, and is in good agreement with the phosphorus-implant dose di vided by film thickness, ie., 1-1 x 10'” em’. Inthe ease of the phosphorus, the segregation coefficient is larger than I reversed and phosphorous piles up at the interface. ‘The spread in Vy for a given Ts, for n-channel devices in Fig. 5 suggests additional eauses for V; variation. One possible explanation involves the fluctuation in the sub- sirate doping concentration. Another possible reason is due to the variation in back-gate flatband voltage caused bby the variation in the buried oxide thickness. Ifthe vari ation is attributed to the fluctuation in the doping concen- tration, it i estimated that for the n-channel device, the doping concentration varies between 0.8 x 10" and 2 x 10” cm”. However, itis not clear why p-channel de- vices exhibit a much tighter distribution for the threshold voltages. IV. Back: iat SOL C-V CHARACTERISTICS AND PARASITIC CAPACITANCES. One major advantage of SOI MOSFET’s over bulk MOSFET’s is the much lower parasitic capacitance. The Dburied-oxide thickness and parasitic capacitance are, therefore, parameters of interest. The parasitic capaci- tances depend on the SOI material, process technology, and the device layout. We can measure the capacitance between the back gate and source/drain at different front- gate bias voltages. From this C-V measurement, infor- ‘mation regarding buried-oxide thickness and different parasitic capacitances can be extracted. ‘The schematic configuration of an SOI n-channel MOS- FET was shown in Fig. 7 with p-type substrate fabricated with a LOCOS isolation technique. Capacitance is mea- os | — ten & oo | pus stemne i 3 an eet Boe SOL Thickness (A) Fig. 6. Mensur pchanne! 9O1 MOSFET threo voltage verus ex {fed alco fm hicks The heel relation fas pote. The lope avers coping concentration of about 1 10" et * The much lighet pend inthe nes lauonship tween Yan T sage a {ping mae usfonn i PMOS case tan in he NMOS ewe. Fig. 7. Schematic contgution of an chal SOI MOSFET with type ‘abut comidenne the pars capusor Coon the capetance Of ihe turd oxide blow device chanel ses, Cyogy ithe eapttance of the bred ene below the ne saureldun wed Cone fhe capcance ‘the sorcefaan mc pas wth combination of Bred oxo eld des and LTO (Low-Tenperatoe Onde), Cu Coy ad Cy ae depletion sured between back gate and sourceldrain. Cyox is the buried-oxide capacitance corresponding to the effective device channel atea when there is an inversion layer pres~ cent at the back channel. Cspox isthe buried-oxide eapac- itance under the n° source and drain. Crox isthe capac: itance due to the source and drain metal contact pad which is over buried oxide plus field oxide plus LTO oxide. Coy, Cop, and Cpy are depletion capacitances in the p-type sub- strate. They are equal to zero when the buried oxide/sub- strate interface isin accumulation, ‘The C-V characteristics of a W = $0 wm, L = SO um n-channel SOI MOSFET are shown in Fig. 8 between source/drain and back gate with front-gate voltage at Vo = 0, -0.5, and ~1 V. This observed C-V curve can be explained as follow. At positive high Vagos, the back-gate voltage Vac is higher than the back-channel threshold voltage (about 15 V), so there is an n” inversion layer at the back channel as shown in Fig. 7. The bottom buried oxide interface and the p-type substrate is in eccurmula- tion. So the capacitance measured is Camax = Crox + Csv0x + Cros: ® acoe(PF) gate with iret rope as Yo, When Vagos is lower than the back-transistor threshold voltage, the n” inversion layer disappears. Cyy is mea- sured at this point as the sum of Cspox and Cron Cn = Crox + Crvox: o ‘The Cayiax to Cp transition occurs at different Vagus for Ve ='0, ~0.5, —1 V because the back-gate threshold voltage is a function of front-gate voltage Vc. The differ cence between Cpieax tnd Cp: is Cyox. from which we can determine the buried-oxide thickness Fox Whos _ Coax ~ Cae Trox co) From the equation above, bured-oxide thicknesses from 3600 1 4000 A. were obtained. This i in good agreement ith TEM results as well as specifications given by the SIMOX manufacturer. When the back-pate voltage drops further, the lightly doped p-type substrate underneath the sourceldrain N* region and source/drain metal pad be- comes depleted and the measured capacitance value Cyxqy is Capon in series with Cp, while Crox isin series with os. Cp can be expressed as Csv0xCnr_ Covox + Con —LroxCos rox + Cos It is worth mentioning that, similarly to the front-gate case, if a positive front gate voltage Vis applied, an in- version layer will form atthe front channel and the silicon will be depleted. The measured capacitance Cys, will be Cs Caoxs and Coy in series plus Conan Cova ay Cso0x Con Cas, [ome Coy * GiGhox + Crox Cor + CC «2 From the difference of Cys, and Cpyay we ean obtain Cy and, therefore, the SOI silicon-flm thickness Ts, since the substrate doping concentration and Cp, are known. Good agreement was found between the Ts, thick- ness measured with this method and the results of using the front-gate C-V method described in Section II. But W/=56/50,Toen 1158 (oF) Seas Neos") Fig. 9. CV menaremen ale with ick a votge Vg rng from {0b ww0'V formchunel MOSFET. At sal Vy, eC sal Ce tothe sence a an nvr yer athe back chante. The Cy Teas larger negative Voy sdf holes geterated by the GIDL. cent. the method described here is more prone to error since it involves more data reduetion steps. V. Discussion A. The Effects of GIDL Current on C-V ‘The proper choice of the back- and front-gate voltages are important parameters needed to yield meaningful and acceptable C-V characteristics. The back-gate vollage Vac has to be high enough to ensure that @ strong inversion layer is formed at the back channel, so that the capaci- tance ean be measured between front-gate and back-chan- rel inversion layer. An additional problem occurs when insufficiently high Vgq i used, due to the limited hole generation rate and GIDL (Gate-Induced Drain Leakage) current, This can be explained as follows ‘As shown in Fig 9, if back-gate voltage Vqq is lower than the back-channel threshold voltage, there is no 1" inversion layer formed at the back channel, and the ca- pecitance measured is merely the parasitic capacitance Coaea: With Vag. = 35 V, which is larger than the back- ate threshold voltage, an n° layer is formed at the back channel and the measured capacitance is Cyan, which is the front-gate oxide capacitance in series with fully de- pleted silicon-film capacitance as given in {12, eq. ()) ‘At more negative Voos, e-B.. Vops = 2 V. there is no accumulation layer at the front channel due to lack of holes. Instead, Veps causes the back-gate threshold volt- age to increase, e:g., to 40 V and larger than Vag, and the bback-channel inversion layer disappears. With the disap- pearance of the back-channel inversion layer, the mea- sured capacitance drops to the parasitic capacitance Cran as shown in Fig. 9 ‘The capacitance increases at even larger negative Vens ddue to GIDL (Gate-Induced Drain Leakage) current from band-to-band tunneling [17], [18]. A high vertical field exists between sourve/drain and front gate in the overlap region when Veos = ~5 V, and valence-band electrons tunnel to the conduction band leaving holes which flow 10 the floating body. This allows an accumulation layer to form at the front channel eliminating the influence of front Ta ga ow Ceos( oF) 4 > ° 5 Yoox") Fig. 10. C-V measurement rests with bck ate voltage Vac range fom T3510 fo pokane! MOSFET Ve on the back-gate threshold voltage V$, Therefore, the inversion layer reappears at the back channel causing the capacitance to rise again. Similar results were obtained for p-channel device with negative back-gate bias volt- ages as shown in Fig. 10. GIDL current was measured as a drain current with 50-m V drain voltage at gate voltage range from 0 to ~5 V with different back-gate voltages. This bias situa- tion is similar to that for the C-V measurements above. Direct measurements of GIDL current shows that the GIDL current indeed appears at the same Vc as the rise of capacitance, thus supporting the above scenario. GIDL. effects appear at lower Vans and at higher Vag, because Vag enhances the field between drain and the front gate, B. Limitation of this Method One limitation of the C-V technique described in Sec- tion II is thatthe SOI film has to be fully depleted. This condition is obviously satisfied when the silicon-film thickness is less than Xpyyax. The technique actually ‘works even if Ty, is larger than Xpasax a8 long as itis thinner than 2Xpygqx, and Ve is Scanned from a positive value (> ¥) to a negative value (for n-channel device) This is explained in Fig. 11 ‘As shown in Fig. 11(a), ifthe film thickness is between Xowax and 2Xpwax, With Vo > Vrand Vag = +75 V, both the front channel and the back channel are in inver: sion. The whole silicon film is fully depleted because the bband bends at both the front and back interfaces. When Vp is scanned to below V>,€.8., Ve = —2 V as shown in Fig. 11(b), the front inversion layer electrons flow into source and drain. The silicon film remains depleted since there is no source of holes to neutralize the depletion layer space charge for many minutes. Hence, the C-V tech- nique is still applicable. Ifthe device is exposed to light or Vg is scanned from a negative value, the equilibrium shown in Fig. 11(¢) exists, and the C-V technique will work. C. Frequency Response The frequency used was 100 kHz for the high-fre- quency C-V measurements. At higher frequencies, a fre- Vacersv © Fig. 11, The CY echnigue works fr sion im hikes up 62a ete Vag = +78 V. a) version layer exits athe rot cane sad te te ion fm is ly deplored with Vo = 1 2V.() Ye Senne fom {S7o =2'V, doe to ited bole geseron rate no ncuron yet fond on th rt chanel se whole sl fly epee. fe) Equlam condition shieved when Vest fom neato the vce Isexponied light Accumulation ayer formed a the fron Canela ‘het iso fly deed. quency dependence is observed for the SO yam x 50 ym large-area device when only the drain is probed, as shown in Fig. 12 fora p-channel MOSFET, The capacitance val- tues measured were smaller than those at higher fre- quency. This result occurs because at negative gate volt age, holes which have lower mobilities cannot diffuse from the p* source/drain to the center of the long channel fast enough in response to the high-frequency signal. The frequency dependence of Cx is shown in Fig. 12. ‘The highest usable frequency can be estimated from the RC time constant of the MOSFET channel, For a p-chan- nel MOSFET, the characteristic frequency is 1 _ mle = V9] 2aRC Dsl where R is the channel resistance and C is the gate oxide capacitance. So the longer the channel, the smaller the mobility, the lower will be the usable frequency. In prac- tice, the small-signal frequency used should be less than L aa Ceos( oF) Veoel") Fin. 12, Frequency dependence due w the nied hole obit ad RC Time constant for lre-ae -canel device. one tenth of f, 19 avoid error due to frequency depen- dence. The smaller the [Vo ~ Vr| value, the lower will be the required frequency. As shown in Fig. 12, the smaller the voltage Vans, the more derivation inthe capacitance value for 1 MHz from the capacitance value for 100 kH2. Prob- ing both source and drain shortens the length the holes have to travel from L to L/2. When a back-gate voltage Voc of =75 V was applied, similar frequency depen- ences are still observed. This is because the threshold voltage of the front channel has been increased by the back-gate bias (to more positive) |Vq ~ Vrl. and thus f Ihave increased. The fact that the hole mobility is in ‘ereased also helps to increase frequency f, as the vertical field is reduced. VIL. Sustany ‘Thinner SOL film thickness is required for the minim’ zation of short-channel effects and elimination of the cur- rent kinks in SO] MOSFETs. Nonuniformity in SO-film thickness can result in nonuniformities in those character- istics and the threshold voltage. In this paper, a simple C-V technique for measuring SOL-film thickness across the finished wafers was described. Using this technique, ‘SOl-film thickness mapping was performed on SIMOX wafers which shows a silicon-flm thickness variation of £150 A. The variation in threshold voltage is correlated to the variation in film thickness. AckNowLepament ‘The authors wish to thank Ms, E. Rosenbaum for help- ful discussion regarding frequency dependence of C-V measurement, ReveReNces U1 LB, Colinge, “Resuction of kik fst i til SOI MOS FETs" BBE Blecron Device Letts 9,02, p97, 1988 (2) Suton ataor Teomsiop” Matenale mo VES)" Dot (3) Te amis and 1 P-Calinge,"Thicknes determination fo oncom inelaorsniturs," Eston fet to 2800239 1336, toi 12] SN. Bunker, P. Sowa, MM. Safacon, an S. P. Tobi, Nona stl of siieor- onlin wafers.” Appl Ph eres 50, no 26,9 1800, 198, 151 1 Narayan, 8.9. Kio Voda and R. Maagkonds, “Formation tnd ondesuctvechuactercation of fon vont ico on tsarlayen App Phy Let vl Sty no Sep. M3, 198) 1 Foren #6 Anche, Oi 8. Maile {ned by iphone oxygen mplaniaton wing spectroscope: lip. Somat. Japp Phos 829.8 3, 1987. 171 3st a's Thomas, "An ccc! method to mesure SOL i, 986 181 Dla, F, Van de Wisk, PG. A. Jesper, and M. Had ‘eases of inal capucuoce af SOl MOSFETs, IEEE Elecrron Device Lt ol. ST 907 p20, 1900 19) oe ans pte apices of S01 MOSFET Mesures, [00] D:Ver At Zavracky, NC. Baden and NK. Cheon, A simple tes IEEE Blecron Device Let, ol 12-0. 4. 193. (Hn) MC Hiond and M. Tack, “Rapid lect messes of back Ie antic ln theknes nap SO CMOS process." EE Tras lecron ences ol 3803 p64, DL 112] 1 Chen, Re Solomon, T= Chan, PK KO, and C. Hu, “A CV techie for measrig thin SO hs thee," EE Eleron De- Vice der ol 12, 8.9.43, AUB BT 103) Drlndr anf Van Se Wile, ""A new aati model for te ‘hoteminal MOS capacitor on SOI saben,” IEEE Elston De 1141 158. se and 8: Crtibeans, “Ascutewebigu for CV mes Siemens on SO stuctures excoding yrs eapucane eect TEE tlecrron Desice Let ol EDL, no. p53, 86 tis) MES. Lisp: ¥- Chl, PK. Koy and 6. Ho, “Invenintaer ‘paciance and moby of ery thn pate-oxde MOSFET." IEEE ‘han: Eecron Dries, 01 ED33, 90, 3p 4091986, ti HR Liman 6 Foca Theil het tin som 1171 TeGhen TY. Ghat -€, Chen, PK, Ko, and C Hu, Sabres ‘down din leakage cartel In MOSFET. TREE Elecon Device eval EDL p55, 1987, tis) Tv. Chan, Chen, BK. Ko, and C. Hu, “The pct of gt {nace dna eng corent on MOSFET scaling." n EDM Teh, an Chen (58) was torn in Chin, Sept ier 1063 He wenned the BS gi fot the UUniserty of Econ Science an Teehology 1 China (UESTC) sn 1964 a the MS depree In let engineenng from te Unive of Calor, Beksey In 1988. rom TH to 1886 fe worked on hih-e uoney GaAs MESPEs a UESTC and Hebei SCmncondatr lait of Chin. fn he sme of 198. he worked on plyslicon hi-fi tan ore at Xerox Palo Ao Reseach Cnt, Hee

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