Eaoevices 12- and 14-Bit Hybrid Synchro/ Resolver-to-Digital Converters SDC/RDC1740/1741/1742 FEATURES Ineernal aolating Transformers Miinary Temperature Range ‘Taree Accurney Options 14Bit or 128i Resolution igh, Continuous Tracking Rate :32Pin Welded Matal Package Heemetealy Sealed Ratiometre Conversion Laver Timed ~ No External Adjustment ‘Three State Latched Outputs [APPLICATIONS Flight inatrumantation Systems Mattary Servo Control Systems [Atilary Fire Control Systems ‘Avion Systeme ‘Antanna Monitoring Robotics Engine Controlters (Coordinate Conversion ‘ie Transformation ‘CHE Machine Tooling Process Control GENERAL DESCRIPTION ‘The SDORDCI7AMI74U/I7I2 are hybrid 14 o¢ 12-bit coot- nous tracking syachro or resolves to digi contre conse {i 3-pin welded tet pacage. Tre coe ofthis hybrid the tnarenicn proves is performed by 2 monolithic IC manafae= tured in Analog Devices propritary BIMOS It proces that ‘combines the edvatages of CMOS lope and bipolar high ast- acy linn cc on the same chip. Tera aig ico tramfonmers ar ued te provide ra oan ofthe signal and reference inputs, The Io 12 digital word is ina thre fate digital form avaiable in two byes Using separate EN- ‘ABLE taps fr the most significant andthe lest ‘giant 6 o 4 bits ot ely simplifies muliperng of more_ ‘her one device ono single data bus, but aio enables the IN- [IBY input tobe sed witout inteopting the operon of the tracking np. The converters are hemeticaly xed a ‘pin welded meal package. REV.A loro ured by Analog Dan eleva ba aca and ‘ait oeear norecponaby esos by Soaoa So ‘eters raungerenn fps fer ih otha pa Serer erie. he heonan avid Uy mponon TRL ery ptet opens ot Arlog Dev. FUNCTIONAL BLOCK DIAGRAM S = Pr a Pe eee ee MODELS AVAILABLE oe ‘The tre scbroveoverco digi cooveters described in this ir shet ifr primarily inte areas of resohuton, sxuricy and dye performance at flows: Model SDCI740XYZ isa 1¢-bie converter with an over a> acy of 5,3 ae minutes and a resltion of 13 are minutes. Model SDCITSIXY2 is 12-9 converter with an over ac racy of 15.3 ae minutes and a reslution of 5.3 ae mints Model SDCIT@IXYZ it 212. converer with an oven ac troy of 28.5 ar minster and a reslutin of 5.3 ac minute Each model bas wo opening tempers range versions, thot coverag the industrial emperarare range (0 10 +70C) andthe lary temperate cane (88°C to» 125°C). The XYZ cade ‘eins the option a fallow: (X) sigue the operating temper ure range, (Y eiiies the reference frequency, (2) gies the signal and rfereace voltage weber twill acept synchro ‘x rsler format. To ensue a high level of reality ech coo ‘ever ecies tingeotpecap vt inspection, environmental ‘crening and Ria ect test iar temperate range devices and those proceed wo high rebbity serening standards (suffi B) receive further levels of testing and screening fo ensue high levels of elabiiy. More Jnformaton about the option coves is given unde the beading (Ordering Infra, (ne Technology Way, #0. Box 108, Norwood, MA 62062-8108 ‘Tar errraee0a Fer: 6179288003 Tw: 710/386-4677 Went Const Cont ‘Aue aera ansesose 15/6677SDC/RDC1740/1741/1742—SPECIFICATIONS pcs 2 wa mn sce Pramas ‘spompcie | SDORDCI | SDURDCITG | Unie CONVERT PERFORMANCE nines 233.8 sissmm | =tSmm | wenn Tack Hae ne {itn | = ecttee [a j= ie [ouwesa | ome) | Sign & Refers Freqeny : : | ARepeaabity of Psion up J * | ise ei 19, * Le SIGNAL INPUT inreDANCE 7 caus 0V Sigal 20 : : ao | Reine Toner 26 | + B60 Sal 7 : : hae ‘ 1. Sgt Es : : Py ‘ ABFERENCE INPUTS 1 ae tenes Voge ways | + . Vim | Se Onkiag Reese Inpece Ibias | TS Re wo : : | an | Retive Tore 29 | 4 ave hs Ie : | in ‘ ACCELERATION CONSTINT_| 5007 Ta = =e [Se ia TARGESTEPRERONGE | Slop wor = ae | FS esate | 1S tors | Sam * me _ | ispereow POWER ENE | E aie a |: mt | Quen cian | 1,4 Wee Bopsen [+ : mh | Quam Gedin | 13 vlew Sop S6mat : SA | Oise Genin | 13 Lane i v | : | | 2 min : : va | yas ha arm : : Vee ray : : wh | Negcbev ms apt Loe) : : [ea | vaseav ie ‘ENABLE AND DISABLE TIME = = = i 7 aT 1 See Lwctor [+ : ehunmr | + : | Tine Dea Sabie oer | | ‘equi Cea | | aniar 0 ma : : * ‘ ar ourraT T ‘seme civ Lagi Hah when vee pain pt gi. Time "aie poe Sm ke hg = po om waa sop : : = ‘ cn : : cl : \ ome : : = ‘ Let Pin : : Tm. ‘ Diora oorraTs cana se Lees | | i Tn Hh dai . : a Loge Low 4m |. . 1s Lot mas Le Rev.ASDC/RDC1740/1741/1742 Peer SBCADGI® | SUCADCIa | SDCRDCIG | Uais | Comment Rows ‘SreRATING TEMPERATURE RANGE ‘Opi SYZ ow+m ‘ : j= Open YZ tess | ‘ i ‘BIMENGTONS Treaoa | + . [a tear 7 (aaeoeny | * ‘ so | Ison weet 02 aa = + Bau : : pas Notes ‘spill ove he preity spe St) £10 pl nd esate vin) Nga reference a ‘ane drm (5 38 poe py moan, =O ron ee age. eat a pi saber spin (6 in SDRC, ‘io edwin rb ome pe pe yl lad pag eg. ‘Conan yd ‘Speen ene SDORDCI. "Spero tes SDORDCTI Sperm io ang ou Nt ABSOLUTE MAXIMUM RATINGS +¥4' w GND. 17280 de =Vj0 GND SSiasv ee SVE W@GND ees vas Referee lput Hl to GND. “50V de Reference Input LO 10 GND -350V de (Common Mode Range VISV ms SI, $2, $3, 4 GND. [350 de ‘Any Logical Input to GND oave +%, ‘ORDERING INFORMATION For fll definition, the converter part umber shoud be suf: ‘ized by an opin code. Al he standard options and the ‘option codes ae shown belo. For options not shown, please ‘nasi Analog Deis, soc WA XY ZB TL High-Ret Processing eon wees ay ee $2Smt i Corer] Sy ee ees ne re Zod Signal 26V Reference 26V. Rewer Z=4 Signal 118V Relernce 26V. Resolver Y=1_aOOle Reference Frequency Yes 26kIls Reference Freuency 1742=12.Bit Reston, 285 ae min Accuracy X-4 -S8C 10 +128C Operating Temperature Range X=5 010 +71 Operating Temperature RasgeSDC/RDC1740/1741/1742 PIN CONFIGURATION PIN FUNCTION DESCRIPTION Pla Maemoaie wen [O |» Te Be F470) Parallel outpt dt is. | ol M2 Bi avanH) =O @|--- 1s REFLO Ing pin for he etree is 20 8|~ ie REFHI aH faa 17 SLORNC ——_| és int for Rear | 7 Spe, Ne yh pon, nos =O @ [ars » SyaceiReseinpu sil =O dette © |= wos 1] Q EL © me n ONC No Connection. =(6 ola n Ne No Conesin ory @| B case Sos be connect 6 OY GND. #+|@ O|- 4 Ne Ne Coneton wen ("| @|> 2 ENABCET. —_| ENABLE enierste60r¢ =1o ole tet nico Be orem] © e+ 6 FNABLER | ENABLE Wertin ste ene ween] © @ |ucmres signe bs Lp Hp ct ops dr — roa eh impedance st; 8 “seems Logic Low presents the data in the ~2seee uch wt out pe fees ust a7 BUSY ‘Converter busy. A Logic High pods he expat . thes are bn weed ad Bit Number. ee data should not be transferred. ead orn 2 NAT ‘Logic Low inhibit the dat 2 saa trate om the cost the : 4s.) suet aches ; itso yo Main pose power py ‘ $0 oven over spt sound 7 28125 xe ee 7 od ay ain erie power > om Lagi ome ® oasie a ours Raseie vara | 00m 3 toes 16.58 fr 170) oa ‘Table L Bit Weight Table‘SDC/RDC1740/1741/1742 zs ‘Figure 1 Functional Diagram ofthe SDCIROCT740/1741/1742 ‘THEORY OF OPERATION In the sachre-toigal convener configuration, the vires cho ouput thsld be connesed to SI, $2 and 83 0 the unt tnd the Scott T troeformer pai wil convert thes signals ino reselver format, Vi=K Bpsin wtsind (SIN) VyeK Epain wtcoed (C05) where i the angle of the nacho sat Inthe reolveto-igtalcoaverterconigurco, the wire ‘esaver output should be connected 1 SI, $2, $2 and S4 onthe (i andthe transformers will at purely a la. “To undead the conversion proces, the sie thatthe cut ret word wate of he up-down counter is ‘Via ipl by COS6 and Vs mule by SING te: K Ep sin wt sia cos > nd K Ep sin ot 08 in 6. ‘These signals re subtracted by the ero aplier gve: K Ee in ut (sin 8 con 6 ~e0s sin 6) oe KEpsinatsin 6-4) A plas texstive detec, integrator and vlge conte ‘ilor (VCO) form a cloed lop sytem which seks w nll 1=8). Te dita utp (counter), then represents the ‘synchoreselver sft angle 6 within the specified acuncy of the eouverer. INHERIT nerUT ‘The INFIBTT logic input onl inhibits the dae wranser rom the up-down counter tothe output latches and therefor, does ‘ot imerrape the operetion ofthe tracking lop. Relig tbe AIRRTBTT euromatally generates 2 busy pls orf the ‘ouput da ENABLE inrurs ‘The ERABLE inputs deceive the sate ofthe ontput data. A Lage High aie eum ia oh sce condition, and appiain of 2 presets tain the tces to the outpt pins. ENABLE Mt enti the root sigan: & bis while ENABLE L, enables the least sig rican 4 te (6 bie ia the SDOIRDCI740) The operon of the ENABLE inp sno elect onthe conversion proces DATA TRANSFER ‘ata tater canbe acomplihed sing ithe he INET ‘ut othe ening edge, postive to mepuive trancion of he BUSY pulse ouput. “The daa wil be aid 40s after the aplication ofa Logic Lo tothe INRTBTT pat. Tiss reaardless ofthe ie whee the [INHIBIT is applied and allows tine fran active busy pulse to ‘ear, By vsing the ENABLE M and ENABLE L inputs he two byes of a canbe wansferred afer whic the INHIBIT. ‘hood be returned to Lape Hi ste to enable te output Tees to be update. eb Figure 2. Timing Diagram‘SDC/RDC1740/1741/1742 BUSY OUTPUT “The valid ofthe ouput dats is indice by the ste ofthe ‘BUSY ouput. When the input tothe converters changing, the Signal appearing on the BUSY outpace of pulses "TIL lve: A BUSY i inte each tne he input moves by sn stalog equivalent of an LSB andthe internal counter is incremented or decremented o the INHIBET input seemed. “Typically the with of the BUSY pule is Ons during be p= tin dts output updaces. The aig de, pose © negative transition, ofthe BUSY pulse indies that the poison date tut bes been updited and is ready for anter (ata ali). ‘The maximum load onthe BUSY ouput wing the tring edge of the BUSY pas? TTL eds. CONNECTING THE CONVERTER “The power mpply voltages conneced 10 +V, and ~V, pias sould be = 15V and mast not be evened. The digg sapoly Vit connected 0 +50. Inia sagged tht + paral cumbintion of 0.14F ceramic aod 64, F deco capacitor is paed from each of he ‘ve supply pins to GND. “The pin marked CASE i connered eetialy tthe case tnd should be kent «convenient zero vat poten in the oem. “The gia ouput it taken from Pia 1 hough Pin 12 for the SDORDCI74V/I742 and Pn throught Pin 14 fo the ‘SDOARDCI740 where Pin | is the MSB. “The reference connections are made to REF HI and REF LO. Inthe cave oft syro, the sgn reconnected to SI, S2 and ‘3 according wo the following convention: Eyres Enron sa ot in Egy" Exvonin i ot sin (04120) Byasy* Exxon in wc in (04240) For a recive, the sigals are connected to SI, 82, $3 and St scoring to the fllwing convention: Equsr-Envosnin in ota Esee=Enoazo Bt ot cm 8 “The BUSY, INHIBIT and ENABLE pis should be connected a described under the heading Data Traster. RESISTIVE SCALING OF INPUTS ‘A fearare of thee converter i tht the signa and reference inp can be reise sealed to accommodate any change of imp egal and reference volnges. “This means tha sandard coaver cn be used with a peron- sly card in poems where 4 wide range of iaput und reference ‘ages re encountered Note: Th necurcy ofthe conver wil be alee by the ‘matching scarce of resos used fr ere saing “Tocalelnte the values of the external suing reso in the cae of x sychre converter ad 111K pe extra vt of sig! insets wih SL, SP and S3 and 1k0 pe ena vl of reference in ein with RET In the cae of a resolver cover, {8442.22 in serio with SU and S2 per exc vot of signal and Tet pe extra vot f reference in srs with RH [DYNAMIC PERFORMANCE ‘The tranafer function of the convene i given blow. Figure 3. Transter Function of ‘SDOmDCT740/1741/1762 pen lop gsi: wr K1esh cS (se oop in Sour tw” Lest, tee, £255 RR Made SDORDCI740 Where +5600 Tizoo. Treoonss “The gin and phase diagrams are shown in Figures 4 and 5. Mode SDORDCI7AI742 Ties ‘The fain and phase diagrams are shown in Figures 6 and 7 [ACCELERATION ERROR ‘Aen coercing» pe 2 sp drs ot {hfe any ost ig, however ei sn na eer de ‘oot, Th tion! err canbe eed a he ‘sede cmatKy of he ee. ape Aceon Ke ar “Te pune sd denoninnor av thse ui K, es bet ene mainun sori, ely tee eo mene {on mminum sein intern ofS tins he Ky fave The foliving an eampe van the Ky fhe sbcino. Acconci, $400 sein se = OH ars Rev.SOC/RDC1740/1741/1742 ‘an = 7° * aT) = * ny mo Figure 4. SOORDCI740 Gain Plot Figure & SDORDC1741/1742 Gain Piot ee i ce Herpes ee - ‘RELIABILITY ae ee . eet ee eters i Seer os : SS eens enn ae gers eer [ Ses eee oer rece i Seb mape ead Figure 8. SOCROCI74081/42 MTBF Curve EVA‘SDE/RDC1740/1741/1742 OTHER PaoUucTS ‘Many ober hybrid produc concerned with he convenin of ‘ochre dat are manufactured by Analog Devices, ome of hich are ltd below. you have any questions shout out [rodacts or require edie aboot te we for parila app “The O5C17S8 ina hybrid sinlotine power tcilator which can provide a mazimam pore output of 1.5 wats over a frequency ‘age of Ot 10K ‘The DRCI76S tod DRCI746 ae 14- and 16 naturelbiary ached cup hybrid igh resolver convert. The ncurn des ulale wre £2 and 4 ar mine, andthe ourp can sp By IVA 7V ras,