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Asynchronous Counter - Sani Irwan Salim
Asynchronous Counter - Sani Irwan Salim
CHAPTER 2 Counter
- A counter is a sequential logic circuit consisting
of a set of flip-flops which can go through a
sequence of states.
COUNTER
1 2
Introduction (continue)
Counters
Counters are formed by connecting flip-flops
together
Types of counter are;
Asynchronous counter Synchronous counters Asynchronous
Clock pulse is applied to Also known as ripple counter
(Ripple counter)
each FF simultaneously The first flip-flop is driven by external clock while the
The output of one FF drives successive flip-flops by the output of preceding flip-flop
the input of the next one
High Speed
Slow speed
3 4
Introduction (continue)
Synchronous
All flip-flops are simultaneously driven by common clock
Asynchronous counter
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9 10
Timing diagram for 2-bit asynchronous binary counter Binary state sequence for 2-bit asynchronous binary counter
Four clock pulses are applied, assume initially all LOW The counter is in up sequence (Q1 is MSB, Q0 is LSB)
Q0 (LSB) is always toggle at positive-edge clock (J and K are HIGH) Count from 0 to 3 in binary sequence
Q0 is reciprocal of Q0 The term ‘recycle’ refers to the transition from final state to original state
Q1(MSB) is toggle at positive-edge of Q0 Therefore, 2-bit asynchronous counter has four state and consists of two FF
At 4th clock pulse, the counter is recycle to its original state (both FF are LOW)
11 12
A 3-bit Asynchronous Binary Counter A 3-bit Asynchronous Binary Counter (continue..)
Draw 3-bit asynchronous up counter using J-K FFs Tabulate the state sequence for 3-bit asynchronous up counter
13 14
It limits the rate at which the counter can be clocked and creates decoding problems.
The maximum cumulative delay in a counter must be less than the period of the clk
waveform. 15 16
Exercise: A 4-bit Asynchronous Binary Counter
Disadvantages of asynchronous
counter (continue) Draw the timing diagram for 4-bit asynchronous up counter given below
Eg: If you look closely at the figure below, for a short period of time (50ns) right after
state 011, you see that state 010 occurs before 100. This is obviously not the correct
binary counting sequence and while the human eye is much too slow to see this
temporary state, our digital circuits will be fast enough to detect it. These erroneous
count patterns can generate what are called glitches in the signals that are produced
by digital systems using asynchronous counters. In spite of their simplicity, these
problems limit the usefulness of asynchronous counters in digital applications.
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19 20
Asynchronous MOD counter Changing the MOD number
(continue) Determine the MOD number of the counter in
Example Fig. 6-6(a). Also determine the frequency at the
A photocell and light source combination is used D output.
to generate a single pulse each time an item
Ans.) Mod-14 ripple counter, 30/14 = 2.14 kHz
crosses its path. The counter must be able to
count as many as 1000 items. How many FFs are
required?
ans.) 2n = 1000
n = log1000/log2
= 10 FFs
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Construct a MOD-10 counter that will count from Each flip-flop provides an output waveform
0000 through 1001. that is exactly half the frequency of the
waveform at its CLK input.
In any counter, the signal at the output of the
last flip-flop (i.e; the MSB) will have a
frequency equal to the input clock frequency
divided by the MOD number of the counter.
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Frequency Division (continue) Example
E.g: in a MOD-16 counter, the output from the last FF will
have a frequency of 1/16 of the input clock frequency.
Thus, it can also be called a divide-by-16 counter.
Likewise, a MOD-8 counter has an output frequency of 60-Hz signal is fed into a Schmitt-trigger, pulse-shaping circuit
1/8 the input frequency; it is a divide-by-8 counter. to produce a square wave.
60Hz square wave is then put into a MOD-60 counter, which
is used to divide the 60-Hz frequency by exactly 60 to produce
a 1-Hz waveform.
1-Hz waveform is fed to a series of counters, which then count
Ss, Ms, Hs, and so on. How many FFs are required for the
MOD-60 counter?
6 FFs
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Counters can be designed to have a number of states in their sequence that is Timing diagram and binary state sequence for decade counter
less than the maximum of 2N. This type of sequence is called a truncated
sequence.
For example, asynchronous modulus ten (MOD-10) counter or decade counter
0 1 0 1
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Asynchronous Decade Counter Exercise
Exercise
Modify MOD-10 asynchronous counter to have MOD-12 and draw the timing
diagram (1100)
0 0 1 1 1. What is the difference of operation between
asynchronous and synchronous counter?
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31 32
Answer:
Synchronous counter
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Truth table
circuit
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Types of synchronous counter Design step for synchronous up counter
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Design step for synchronous up counter Design step for synchronous up counter
(continue) (continue)
Step 2: Fill in the truth table Step 3: Generate k-map
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Up counter using T flip-flop Up counter using JK flip-flop
Using JK flip-flop
Using T flip-flop
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Design a counter to produce 3-bit binary counter using J-K FF Design a counter to produce 3-bit binary counter using J-K FF
State diagram State and excitation tables K-maps
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Design of Synchronous Counter Exercise 2 Design of Synchronous Counter Exercise 2 (continue..)
Design a counter to produce 3-bit binary counter using D FF Design a counter to produce 3-bit binary counter using D FF
State diagram State and excitation tables K-maps
Q0 Q0 Q0
PRESENT NEXT STATE FLIP-FLOP INPUTS Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1
STATE
00 0 0 00 0 1 00 1 0
Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
01 0 1 01 1 0 01 1 0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0 11 1 0 11 1 0 11 1 0
0 1 0 0 1 1 0 1 1 10 1 1 10 0 1 10 1 0
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
D2 map D1 map D0 map
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0
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47 48
Synchronous mod-counter Synchronous mod-counter (continue)
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Design MOD5 synchronous counter using D FF Design MOD5 synchronous counter using D FF
State diagram State and excitation tables K-maps
Q0 Q0 Q0
PRESENT NEXT STATE FLIP-FLOP INPUTS Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1
STATE
00 0 0 00 0 1 00 1 0
Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
01 0 1 01 1 0 01 1 0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0 11 0 0 11 0 0 11 0 0
0 1 0 0 1 1 0 1 1 10 0 0 10 0 0 10 0 0
0 1 1 1 0 0 1 0 0
1 0 0 0 0 0 0 0 0
D2 map D1 map D0 map
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0
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Design of Synchronous Counter Exercise 3 (continue..) Design of Synchronous Counter Exercise 4
Design MOD5 synchronous counter using D FF Design MOD5 synchronous counter using T FF
Counter implementation State diagram State and excitation tables
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Design of Synchronous Counter Exercise 4 (continue..) Design of Synchronous Counter Exercise 4 (continue..)
Design MOD5 synchronous counter using T FF Design MOD5 synchronous counter using T FF
K-maps Counter implementation
Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1
00 0 0 00 0 1 00 1 1
01 0 1 01 0 1 01 1 1
11 1 1 11 1 1 11 0 1
10 1 1 10 0 0 10 0 1
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Exercise Topic:
Design a 3 bit synchronous counter for the Up/down counter or bidirectional counter
sequence 0642 using Cascaded counter
a) D flip-flop Asynchronous cascaded counter
b) T flip-flop Synchronous cascaded counter
c) JK flip-flop Counter decoding
Decoding glitches
Strobing technique
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Up/Down Synchronous Counter (bidirectional counter) Up/Down Synchronous Counter design procedure
• Bidirectional counters, also referred to as UP/DOWN counters, are capable of Eg: Design a 2 bit up/down counter using T flip-flop based on the
progressing in either direction through any given count sequence. Recall that in
state diagram below. Assume up = 1 and down = 0.
general, bidirectional counters can be reversed at any point in their count
sequence. Answer:
• Capable to count in either direction through a certain sequence
• For example 3-bit up/down synchronous counter
Able to count from 0 to 7 or 7 to 0
Cascaded Counters Cascaded Counters (continue)
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Answer:
Overall modulus = 10 x 8 =80 = mod-80 counter
Frequency at B = fin/80 = 250Hz
• 64
Cascaded Counters (continue) Cascaded Counters (continue)
1 = (1x106)/10n
n = log (1x106)/log10
n = 6 decade counter
Answer:
(a) the overall modulus for the 3 counter configuration is 8 x 12 x 16
= 1536 = mod-1536
(b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x
5 = 1400 = mod-1400
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67 68
Counter Decoding (decoding a counter) Counter Decoding (decoding a counter)
• Example: to decode binary state 6 (110) of a 3 bit Example: A 3-bit counter with active-HIGH decoding of
binary counter. When Q2=1, Q1=1 and Q0=0, a HIGH count 2 and count 7.
appears on the output of the decoding gate.
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Occurs to
(a) Asynchronous counter – propagation delay due to ripple effect
(b) Synchronous counter – propagation delay from the clock to the Q
output of every flip-flop Figure: Outputs with glitches
Solution to eliminate glitches Example without glitches
Exercise 1
Design a 3 bit up/down counter using JK flip-flop based on the
state diagram below. Assume up = 1 and down = 0.