Lab Assignment 4

Enhanced Priority Encoder

1 Specifications
An enhanced-priority encoder returns the codes of the highest and second-
highest priority requests. The input is the 10-bit r signal, in which the r[9] has
the highest priority and r[0] has the lowest priority. The outputs are fst and
snd, which are the 4-bit binary codes of the highest and second-highest priority
requests, respectively. The input and output signals are
• input:
∗ r: 10-bit input request
• output:
∗ fst: 4-bit output, the binary code of the highest priority request
∗ snd: 4-bit output, the binary code of the second-highest priority
request
An output becomes “1111” when there is no active request.

2 Lab Tasks
a) A “normal” 10-to-4 priority encoder outputs the code of the highest priority
request (can be coded by one conditional signal assignment statement). Use it
as the basic building block to construct the enhanced priority encoder. Derive
a top-level conceptual diagram of the enhanced priority encoder. The diagram
should contain 3 to 6 blocks.
b) Derive Verilog code according to the top-level conceptual diagram. The
module declaration of this design is:
module e n h a n c e d p r i o ( output [ 3 : 0 ] f s t , snd ,
input [ 9 : 0 ] r ) ;

The lab manual is exclusively for the students of the University of Engineering and Tech-
nology, Lahore.
©2020 UET Lahore.

1
Proper header and comments should be included. In the comments, indicate
the correspondence between Verilog statements and blocks.
c) Use the testbech (tb enhanced prio.v) to simulate your Verilog code.
d) Develop a proper “layout” and “format” for the simulated waveform. To
get full credits, the input and output signals should be properly arranged and
represented in proper format (r in binary and fst and snd in unsigned decimal)
so that the simulation result can be easily understood, as shown below. Do a
screen capture of the simulated result.

3 Instructions
a) Prepare a report for everything that you have done in “Lab Tasks”. The
report should include the following:

• Answer to all the questions.

• Top-level conceptual diagram of the enhanced-priority encoder.
• Verilog code for all the modules that you have developed for this lab

• A snapshot of ModelSim simulation waveform (you must include your

registration number on the top right side of snapshot)
b) The collaboration between students is encouraged, but blind copying or shar-
ing the simulation and report is not allowed. I can randomly ask a student during
the teams meeting session to explain about his/her work. If you are unable to
explain anything in your work, it will be assumed you have copied it and you
may be awarded a zero grade for the lab. So make sure you know everything
that you have done. I am least concerned about how you have learnt something
as long as you have learnt it well.