Lab Assignment 3

Combinational Circuits
(Structural Modeling)

Suppose, your boss asks you to design a circuit which takes two 2-bit numbers
X and Y and outputs 1-bit F as described below:

 0 if X > Y
F = don0 t care if X = Y
1 otherwise


where comparison is for the decimal equivalent of X and Y.

1 Lab Tasks
a) Write down the truth table of the circuit.
b) Use K-map technique to minimize the logic. Write down all prime and
essential prime implicants of the function.
c) Write Verilog code for the circuit using structural modeling (using primitives
such as AND, OR, etc., gates).
d) Write testbench code for the circuit and test the circuit by simulating on
ModelSim.

2 Instructions
a) Prepare a hand-written report for everything that you have done in “Lab
Tasks”. The report should include the following:
• Answer to all the questions.
• A snapshot of ModelSim simulation waveform (you must include your
registration number on the top right side of snapshot)
The lab manual is exclusively for the students of the University of Engineering and Tech-
nology, Lahore.
©2020 UET Lahore.

1
 • Scan your hand-written work by any scanner mobile application and attach
the Modelsim simulation waveform with it to make a one .pdf file that you
will submit. Make sure the hand-writting is neat and easy to understand
with no cutting and overwritting.
b) The collaboration between students is encouraged, but blind copying or shar-
ing the simulation and report is not allowed. I can randomly ask a student during
the teams meeting session to explain about his/her work. If you are unable to
explain anything in your work, it will be assumed you have copied it and you
may be awarded a zero grade for the lab. So make sure you know everything
that you have done. I am least concerned about how you have learnt something
as long as you have learnt it well.