Scribd Logo
Upload

Welcome to Scribd!

  • Test Case

    Uploaded by

    Kiss 002
    14 views3 pages
    The document contains configuration details for an ESPI clock including minimum and maximum input and output delays and clock edge transitions for various ESPI ports. It defines an ESPI clock source and divides it by 1 before connecting to the GPPC_G_21_ESPI_CLK port.

    Original Description:

    scrap

    Original Title

    test case

    Copyright

    © © All Rights Reserved

    Available Formats

    XLSX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document contains configuration details for an ESPI clock including minimum and maximum input and output delays and clock edge transitions for various ESPI ports. It defines an ESPI clock source and divides it by 1 before connecting to the GPPC_G_21_ESPI_CLK port.

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    14 views3 pages

    Test Case

    Uploaded by

    Kiss 002
    The document contains configuration details for an ESPI clock including minimum and maximum input and output delays and clock edge transitions for various ESPI ports. It defines an ESPI clock source and divides it by 1 before connecting to the GPPC_G_21_ESPI_CLK port.

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 3

    Hi this is Murali

    This is second line

    create_generated_clock -name ESPI_CLK_pad -master_clock [get_clocks espi_io_tx_gated_rosc_side_clk] -add -source [get_p


    set sod_espi_ 3640
    set sod_espi_ -2840
    this is between line
    set sid_espi_m 15310
    set sid_espi_m 690
    set tran_espi_ 15310
    set tran_espi_ 690
    Label port_nameclock nameinput external delay clock edge Transition Comments
    min max min max
    IN ESPI_CSBESPI_CLK_ ${sid_espi ${sid_espi clock_fall ${tran_esp${tran_espi_max}
    IN ESPI_CSBESPI_CLK_ ${sid_espi ${sid_espi clock_fall ${tran_esp${tran_espi_max}
    IN ESPI_CSBESPI_CLK_ ${sid_espi ${sid_espi clock_fall ${tran_esp${tran_espi_max}
    IN ESPI_CSBESPI_CLK_ ${sid_espi ${sid_espi clock_fall ${tran_esp${tran_espi_max}
    IN ESPI_IO_0ESPI_CLK_ ${sid_espi ${sid_espi clock_fall ${tran_esp${tran_espi_max}
    IN ESPI_IO_1ESPI_CLK_ ${sid_espi ${sid_espi clock_fall ${tran_esp${tran_espi_max}
    IN ESPI_IO_2ESPI_CLK_ ${sid_espi ${sid_espi clock_fall ${tran_esp${tran_espi_max}
    IN ESPI_IO_3ESPI_CLK_ ${sid_espi ${sid_espi clock_fall ${tran_esp${tran_espi_max}
    Label port_nameclock nameoutput external delayclock edge Transition Comments
    min max min max
    OUT ESPI_CSBESPI_CLK_ ${sod_espi${sod_espirise
    OUT ESPI_CSBESPI_CLK_ ${sod_espi${sod_espirise
    OUT ESPI_CSBESPI_CLK_ ${sod_espi${sod_espirise
    OUT ESPI_CSBESPI_CLK_ ${sod_espi${sod_espirise
    OUT ESPI_CSBESPI_CLK_ ${sod_espi${sod_espirise
    OUT ESPI_IO_0ESPI_CLK_ ${sod_espi${sod_espirise
    OUT ESPI_IO_1ESPI_CLK_ ${sod_espi${sod_espirise
    OUT ESPI_IO_2ESPI_CLK_ ${sod_espi${sod_espirise
    OUT ESPI_IO_3ESPI_CLK_ ${sod_espi${sod_espirise
    _side_clk] -add -source [get_pins pargpcom0/espi_io_top_1/espi_io_top1/espi_link_io_top1/clock_gen/output_clk] -divide_by 1 [get_por
    put_clk] -divide_by 1 [get_ports GPPC_G_21_ESPI_CLK]

    You might also like