LiU-ITN-TEK-A--10/047--SE

6-9 GHz Low-Noise Amplifier

Design och Implementering
Mohammad Billal Hossain
2010-06-14

Department of Science and Technology Institutionen för teknik och naturvetenskap

Linköping University Linköpings Universitet
SE-601 74 Norrköping, Sweden 601 74 Norrköping
 LiU-ITN-TEK-A--10/047--SE

6-9 GHz Low-Noise Amplifier

Design och Implementering
Examensarbete utfört i Electronics
vid Tekniska Högskolan vid
Linköpings universitet

Mohammad Billal Hossain

Handledare Adriana Serban

Examinator Adriana Serban

Norrköping 2010-06-14
Upphovsrätt

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© Mohammad Billal Hossain

6-9 GHz Low-Noise Amplifier Design and Implementation

Mohammad Billal Hossain

June 14, 2010

Preface
This report is the result of Master of Science Thesis carried out at the Department of
Science and Technology (ITN) in Linköping University.

I would like to take a chance to thank the people who have helped and encouraged
me during this Master Thesis work. First of all, I want to express my gratitude to
Adriana Serban, for giving me the opportunity to perform my Master Thesis at ITN
department and for being my supervisor. This thesis work could not have been
accomplished without her guidance and full assistance. I would also like to thank
professors in ITN department Shaofang Gong, Magnus Karlsson and Allan Huynh
for their suggestion and comments.

i
Abstract
Low-noise amplifier design (LNA) is a critical step when designing a receiver front-
end. For the broadband technologies and particularly ultra-wideband (UWB) system,
designing the LNA becomes more challenging. This master thesis mainly focuses on
the LNA design for the European UWB recommendation, i.e. LNA covering the 6 - 9
GHz spectrum. Moreover, better understandings of the design process in correlation
with the implementing of the LNA on a printed circuit board (PCB) were expected.

The LNA was manufactured, assembled and measured with network analyzer. This
report presents a complete functional design of an UWB LNA.

ii
List of Abbreviations
ADS Advanced Design System
BPFs Bandpass Filters
BW Bandwidth
CAD Computer Aided Design
EDA Electronic Design Automation
EMI Electromagnetic Interference
EIRP Equivalent Isotropically Radiated Power
FCC Federal Communication Commission
FM-UWB Frequency Modulation UWB
GaAs Gallium Arsenide
HBTs Hetero-junction Bipolar Transistors
HEMTs High Electron Mobility Transistors
JFETs Junction Field Effect Transistors
LNA Low-Noise Amplifier
MC-UWB Multi Carrier UWB
MW Microwave
NF Noise Figure
OFDM Orthogonal Frequency Division Multiplexing
PSD Power Spectral Densities
RF Radio Frequency
RFI Radio Frequency Interference
RFID Radio Frequency Identification
RSC Radio Spectrum Committee
SMDs Surface Mount Devices
S-parameters Scattering Parameters
UMTS Universal Mobile Telecommunication System
UWB Ultra-wideband
VSWR Voltage Standing Wave Ratio
WPAN Wireless Personal Area Network

iii
List of Figures
Figure 2- 1 Diagram of band allocation [7]
Figure 2- 2 FCC emission limit for outdoor UWB communications [3]
Figure 2- 3 FCC emission limit for indoor UWB communications [3]
Figure 2- 4 Spectrum of the Main Interfering Communication Standards for UWB
Communication System [11]
Figure 2- 5 Skin depth area of a wire [13].
Figure 2- 6 Electric equivalent circuit representation of the resistor [15].
Figure 2- 7 Absolute impedance value of a 500 ohm thin-film resistor as a function of
frequency [15].
Figure 2- 8 Electric equivalent circuit for a high frequency capacitor [15].
Figure 2- 9 Absolute value of the capacitor impedance as a function of frequency
[15].
Figure 2- 10 Distributed capacitance and series resistance in the inductor coil [4].
Figure 2- 11 Equivalent circuit model of the HF inductor [15].
Figure 2- 12 Frequency response of the impedance of an RFC [15].
Figure 2- 13 Biasing effect of n-channel JFET [21]
Figure 2- 14 IV characteristic of FET [23].
Figure 2- 15 GaAs MESFET [5]
Figure 2- 16 HEMT [16]
Figure 2- 17 High frequency FET model [22]
Figure 2- 18 Segment of transmission line expressed with distributed parameters R,
L, C and G, where all parameters are given in terms of unit length [4].
Figure 2- 19 Terminated transmission line at location z=0.
Figure 2- 20 (a) Microstrip line; (b) end view of microstrip line [9].
Figure 2- 21 Line voltages reference to the load end [21]
Figure 2- 22 Smith Chart.
Figure 2- 23 Parametric representation of the normalized resistance r [15].
Figure 2- 24 Parametric representation of the normalized reactance x [15].
Figure 2- 25 Smith chart by combining r and x circles for Γ ≤ 1 [15].
Figure 2- 26 Reflection coefficient: A = (0.8-j1.6), angle BOC=-55.5 degree [21].
Figure 2- 27 T network connected to the base-emitter input impedance of a bipolar
transistor. Assuming Z 0 = 50 ohm and f c = 2 GHz [15]
Figure 2- 28 Computation of the normalized input impedance of the T network
Figure 2- 29 Two-port network [15].
Figure 2- 30 Two port scattering network with source and load [21]
Figure 3- 1 RF receiver using a heterodyne architecture [5].
Figure 3- 2 Thermal noise [7]
Figure 3- 3 Shot noise [7]
Figure 3- 4 Representation of noise by input noise generators [7].
Figure 3- 5 Simplified single stage amplifier [3]
Figure 3- 6 Eight possible two components networks [3].
Figure 3- 7 Impedance effects of series and shunt connections of L and C [3].
Figure 4- 1 Minimum noise figure, associated gain vs. frequency characteristics [3].

iv
Figure 4- 2 ADS Simulation setup for the I-V characteristic using electrical model of
NE3512S02.
Figure 4- 3 Simulated I-V Characteristic of NE3512S02.
Figure 4- 4 I-V Characteristic of NE3512S02 according to data sheet [3]
Figure 4- 5 Simulation setup for the Electrical and S-Parameter model of
NE3512S02.
Figure 4- 6 S-Parameters are estimated using Electrical (Thick line) and S-Parameter
model (Thin line) at the Q-point (ID = 20 mA and VDS = 2 V).
Figure 4- 7 Fixed-bias Configuration [7]
Figure 4- 8 Self-bias Configuration [7]
Figure 4- 9 Active-bias Configuration [8].
Figure 4- 10 Layout component of footprint for the transistor (NE3512S02) and three
types of packages such as 0402, 0603 and 0805.
Figure 4- 11 Different layout components of via hole model and ADS via model.
Figure 4- 12 ADS set-up for via simulation.
Figure 4- 13 Reflection coefficients for different via models.
Figure 4- 14 Impedance vs Frequency. Solid line represents for ATC100A101
(100pF) and dot line for ideal 100 pF capacitor [11] .Figure 4- 14 Impedance vs
Frequency. Solid line represents for ATC100A101 (100pF) and dot line for ideal 100
pF capacitor [11] .
Figure 4- 15 Insertion loss (S21) of ATC100A101 (100 pF) capacitor [11].
Figure 4- 16 Kemet COG ceramic capacitor model schematic [12].
Figure 4- 17 Kemet X7R ceramic capacitor model schematic [12].
Figure 4- 18 Murata Monolithic ceramic SMT Capacitor model [12].
Figure 4- 19 CAPP2 (Chip capacitor) model for ATC [12].
Figure 4- 20 Forward transmission vs frequency characteristics for 1 pF capacitor
dofferent companies such as Kemet, ATC, Philips and Murata.
Figure 4- 21 Forward Transmission vs Frequency characteristic of Kemet capacitor
model with different values.
Figure 4- 22 Forward Transmission vs Frequency for Bypassing Kemet capacitor
model. Thick line for C1 and thin line for C2 to C4
Figure 4- 23 Three types of RF choke [13].
Figure 4- 24 ADS set-up for RF choke using quarter wave stub.
Figure 4- 25 RF choke using radial stub.
Figure 4- 26 RF choke using butterfly stub.
Figure 4- 27 Forward transmission vs frequency characteristics of different types of
RF chokes (Thick line for Butterfly, Thin line for quarter wave line and Das line for
radial).
Figure 4- 28 Forward transmission vs frequency with different terminated values in
port 3 (Das line for 5 ohm, star line for 10 ohm thin line for 20 ohm and thick line for
50 ohm).
Figure 4- 29 Complete Schematic of RF choke with bias arrangement.
Figure 4- 30 Forward transmission vs frequency characteristic for the schematic of
Figure 4- 29.
Figure 4- 31 Schematic of the NE3512S02 S-parameter model before stabilization.
Figure 4- 32 Stability factor vs frequency before stabilization.
Figure 4- 33 Power gain and noise figure before stabilization.

v
Figure 4- 34 Annotation of DC simulation of stabilized FET (Electrical model) fixed
bias (IDS=20 mA and VDS=2V, VGS=-0.17V) circuit without matching network.
Figure 4- 35 Schematic of stabilized FET(S-parameter model) without matching
network.
Figure 4- 36 Stability factor vs frequency characteristic after stabilization with S-
parameter model.
Figure 4- 37 Power gain and noise figure after stabilization with S-parameter model.
Figure 4- 38 Layout component.
Figure 4- 39 Matching for noise figure at 8.5 GHz.
Figure 4- 40 Smith chart of input matching network by lumped elements.
Figure 4- 41 Input matching network where L1=1.54 nH, L2=1.87 nH, L3=1.02 nH,
L4=1.11 nH,C1=1.2 pF, C2=1.5 pF, C3=1.55 and C4=0.42 pF pF.
Figure 4- 42 Matching condition at 8.5 GHz after putting input matching network.
Figure 4- 43 Comparison between Noise figure (star line) and minimum noise (solid
line).
Figure 4- 44 Input matching network with microstrip, L1=2.1 mm, L2=2 mm, L3=2
mm, L4=3.5 mm, L5=3.57 mm, L6=1.25 mm, L7=2.38 mm and W=0.524 mm.
Figure 4- 45 Power gain and noise figure (star line) vs frequency with input matching
network.
Figure 4- 46 Matching condition at 8.5 GHz after putting input microstrip matching
network.
Figure 4- 47 Output matching network with microstrip line, L1=2 mm, L2=7 mm,
L3=2 mm, L4=2.5mm, L5=3mm, L6=2 mm, L7=4mm and W=0.524mm.Figure 4- 1
Minimum noise figure, associated gain vs. frequency characteristics [3].
Figure 4- 48 Power gain and noise figure (star line) vs frequency with input and
output network.
Figure 4- 49 LNA before matching network.
Figure 4- 50 Simulation result of LNA at 8.5 GHz matching point without matching
network.
Figure 4- 51 Smith chart for IMN design at 8.5 GHz.
Figure 4- 52 IMN at 8.5 GHz before optimize.
Figure 4- 53 IMN at 9 GHz after optimize.
Figure 4- 54 Simulation result of LNA with IMN after optimization.
Figure 4- 55 Smith chart for OMN design at 9 GHz.
Figure 4- 56 OMN at 9 GHz before optimize.
Figure 4- 57 Simulation result of LNA with optimized IMN and unutilized OMN.
Figure 4- 58 OMN at 9 GHz after optimization.
Figure 4- 59 LNA with optimize IMN and OMN at 9 GHz.
Figure 4- 60 Simulation result of LNA with IMN and OMN.
Figure 4- 61 complete layout look like LNA with IMN and OMN.
Figure 4- 62 Forward transmission (solid line) and transducer gain (dot line).
Figure 4- 63 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220
pF, C4=100nF and R1=43 Ω.
Figure 5- 1 Schematic for VIA model simulation.
Figure 5- 2 Input reflection coefficient of different via models of Figure 5- 1.
Figure 5- 3 Schematic for SMT capacitor model simulation.

vi
Figure 5- 4 Forward transmission vs frequency characteristics for 10 pF capacitor,
Kemet-solid line star, ATC-circle line, Philips-star line and Murata-triangle line.
Figure 5- 5 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220 pF,
C4=100nF and R1=43 Ω.
Figure 5- 6 Forward transmission vs frequency simulation result of Figure 5- 5.
Figure 5- 7 Forward transmission vs frequency simulation result of Figure 5- 5.
Figure 5- 8 Input reflection coefficient vs frequency simulation result of Figure 5- 5.
Figure 5- 9 Simulation setup of the LNA module-1with input and out put matching
networks.
Figure 5- 10 Power gain vs frequency of LNA module-1.
Figure 5- 11 NF vs frequency (LNA module-1); star line- actual noise and solid line-
minimum noise.
Figure 5- 12 Simulation setup of the LNA module-2 with input and output matching
network at 8.5 GHz
Figure 5- 13 Power gain vs frequency of LNA module-2
Figure 5- 14 NF vs frequency (LNA-modele-2); star line- actual noise and solid line-
minimum noise
Figure 5- 15 Simulation setup of the LNA with input and out put matching networks.
Figure 5- 16 Power gain vs frequency.
Figure 5- 17 Noise figure vs frequency; star line- actual noise and solid line-
minimum noise.
Figure 5- 18 Power gain vs frequency; solid line at 8.5 GHz matching and dot line at
9 GHz matching.
Figure 5- 19 Noise figure vs frequency; dot line-for 9 GHz and solid line-8.5 GHz
Figure 5- 20 Complete layout of LNA module-1; C1, C2, C3, C7=10 pF; C4, C8=100
pF; C5, C9=220 pF; C6, C10=100 nF.
Figure 5- 21Complete layout of LNA module-2; C1, C2,C3, C7=1.5 pF; C4, C8=3
pF; C5, C9=10 pF; C6, C10=100 pF. R1=3.9 ohm, R2=10 ohm, R3=150 ohm and
Q1= NE3512S02
Figure 5- 22 Schematic for data display of measured LNA modele-1.
Figure 5- 23 Power gain of the LNA after implementation.
Figure 5- 24 Schematic for data display of measured LNA modele-2
Figure 5- 25 LNA module-2
Figure 5- 26 Comparison between LNA module -1 and -2. Solid line for LNA
module -1 and star line for module -2.
Figure 5- 27 LNA post manufactured simulation
Figure 5- 28 Power gain vs frequency
Figure 5- 29 Noise figure

vii
Contents
Preface …………………………………………………………………………...……i
Abstract …………………………………………………………………………..…. ii
List of Abbreviations ……………………………………………………………......iii
List of Figures …………………………………………………………………...…. iv
Contents ……………………………………………………………………...…….viii

1. Introduction …………………………………………………………………….1
1.1. Background …………………………………………………………….…….1
1.2. Purpose …………………………………………………………………….....1
1.3. Task ……………………………………………………………………..……2
1.4. Outline ………………………………………………………………….…….2
References

2. Ultra-wideband and General RF Theory ……………………………….…3

2.1. Ultra-wideband ……………………………………………………………….3

2.1.1. History of UWB ………………………………………………...……3
2.1.2. UWB Theory …………………………………………………………4
2.1.3. Regulations …………………………………………………………...6
2.1.4. Applications …………………………………………………………..6
2.2. RF Passive Components ……………………………………………………...7
2.2.1. Wire …………………………………………………………………..7
2.2.2. Resistors …………………………………………………………..….8
2.2.3. Capacitor ……………………………………………………………..9
2.2.4. Inductor ……………………………………………………………..10
2.3. Active Devices ……………………………………………………………...12
2.3.1. JFETs ………………………………………………………………..12
2.3.2. GaAs MESFETs …………………………………………………….13
2.3.3. HEMTs ……………………………………………………………...13
2.3.4. FET Transistor Modeling …………………………………………...14
2.3.4.1. High Frequency Model of FET…………………………..….15
2.4. Transmission Line …………………………………………………………..15
2.4.1. Lossless Transmission Line ……………………………………...….17
2.4.2. Voltage Reflection Coefficient …………………………………...…17
2.4.3. Standing Wave Ratio …………………………………………….….18
2.5. Microstrip Transmission Line ……………………………………………....18
2.6. Transmission Line as Electrical Elements ……………………………….…19
2.6.1. Transmission Line as a Reactance ………………………………….21
2.6.2. Transmission Line as a Transformer …………………………….….21
2.7. Smith Chart ………………………………………………………………....22
2.7.1. Smith Chart Theory ……………………………………………..…..23
2.7.2. Smith Chart Applications ………………………………………..….25
2.8. Networks model …………………………………………………………….26

viii
 2.8.1. Two-port Networks …………………………………………………27
2.8.2. S-parameters ………………………………………………………...28
References

3. Low-Noise Amplifier ……………………………………..…………….…..31

3.1. Receiver Overview ………………………………………………….…...….31
3.2. Stability ……………………………………………………………………..32
3.3. Noise Analysis ……………………………………………………………....32
3.3.1. Internal Noise Sources ………………………………………………32
3.3.2. Noise Figure ………………………………………………………...34
3.4. Power Gain ………………………………………………………………….35
3.5. Matching Network …………………………………………………………..36
3.5.1. Microstrip Matching Network ………………………………………38
References

4. Design of LNA …………………………………………................................39

4.1. LNA Specification ……………………………………………………….….39
4.2. Transistor Selection …………………………………………………………40
4.3. Transistor Characteristics ………………………………………………..….40
4.4. Transistor Models Comparison ……………………………………………..41
4.5. Transistor Biasing Network Design …………………………………….…..43
4.5.1. Fixed-bias Configuration …………………………………………....43
4.5.2. Self-bias Configuration ……………………………………………..43
4.5.3. Active-bias Network …………………………………………….…..44
4.6. Microstrip Footprint ………………………………………………………...44
4.7. VIA Hole Model ………………………………………………………….....45
4.8. Broadband Chip Capacitors Selection ………………………………………46
4.9. ADS Capacitor Model ………………………………………...………...…..48
4.10. DC Blocking and Decoupling ………………………………………………50
4.10.1. DC Blocking Capacitor Selection …………………………………..50
4.10.2. Dcoupling Capacitor Selection ……………………………..……….51
4.11. Microstrip RF Choke ………………………………………………………..52
4.11.1. RF Choke Design and Simulation …………………………………..52
4.11.2. RF Choke with Bias Arrangement ………………………………….54
4.12. LNA Design …………………………………………………………….…..55
4.12.1. Matching Network Design at 8.5 GHz …………………………..….59
4.12.1.1. Matching Network by Lumped Elements ……………….….60
4.12.1.2. Microstrip Matching network ………………………….……61
4.12.2. Matching Network Design at 9 GHz …………………………..……62
4.12.2.1. IMN Design …………………………………………………64
4.12.2.2. OMN Design ………………………………………………..66
4.12.3. Layout of RF Choke …………………………………………….…..70
References

5. LNA Implementation: Simulation Results and Measurements ……...72

ix
5.1. Simulation Results …………………………………………………..………72
5.1.1. VIA Model Simulation ………………………………………...……72
5.1.2. DC Blocking Capacitor Simulation ……………………...………….74
5.1.3. RF Choke …………………………………………………..………..75
5.1.4. LNA with Matching Network at 8.5 GHz …………………………..77
5.1.5. LNA with Matching Network at 9 GHz …………………….………82
5.1.6. Comparison of Two LNA ……………………………………….…..83
5.1.7. LNA Layout ……………………………………………….………..85
5.2. Measurement ………………………………………………………………..87
5.3. LNA Post-manufactured Simulation ……………………………………….89

6. Conclusion and Further Work ……………………………….………….....92

Appendix …………………………………………………………………...……..93

x
1 Introduction
This chapter is intended to give an overall idea of this Master Thesis work.
The report starts with describing the background and is continues by explaining
the purpose, task and outline.

1.1 Background
Most of the today’s radio systems operate within 1 to 40 GHz which is a
part of the microwave spectrum defined by Radio Society of Great Britain [1].
Ultra-wideband radio (UWB) is a wireless communication technology based on
either orthogonal frequency division multiplexing (OFDM) or spread spectrum
technologies [2]. The UWB spectrum in the range 3.1 GHz to 10.6 GHz is defined
by the Federal Communication commission (FCC) in USA [3]. Europe, Japan and
recently China have put restriction on 3.1 to 4.8 GHz frequency band that causes
problems regarding from the coexistence of the UWB system with other
narrowband wireless system [4]. Consequently, here is a great interest in the
higher part of the UWB European Spectrum 6-9 GHz (6-8.5 GHz long term range
and 8.5-9 GHz short term range) applications [5].
Howerever, at high frequency and over a wide frequency band, it is a
challenging task to design radio receiver circuits [4]. A simple receiver front-end
consists of a Low-Noise Amplifier (LNA), filter and mixer. All active and passive
components contribute to process the signal but also they can degrade the original
signal. At each circuit, the signal must be handled carefully over a wide frequency
band to meet the design specifications [6].
For example, as the operation frequency increases above 1 GHz, the
lumped element models as those used in SPICE and SPICE-like simulators are no
longer valid. In order to provide accurate models, new design techniques based on
electromagnetic simulations should be considered. To support the new challenges,
electronic design automation (EDA) and computer aided design (CAD) vendors
have continuously improved their tools so that the entire design from system
simulation to every circuit design can be performed under a single simulation
environment [6]. Despite design difficulties, the UWB technology is considered
to be one of the promising technologies to design indoor data communication for
high data rates [4].

1.2 Purpose
The purpose of this Master thesis is to design and implement a 6-9 GHz
Low-Noise Amplifier (LNA) and to understand the design process of the LNA
module from schematic to the LNA module layout and prototype. Another
purpose is to acquire skills using the Advanced Design System (ADS) tool from
Agilent Technologies, a complex and important software for any engineer
developing circuits and systems operating at high frequencies.

1
1.3 Task
The main task was the design of a broadband 6-9 GHz LNA with the help
of ADS. At first, special theoretical knowledge about designing RF circuits was
needed. The necessary information sources were various books, scientific papers,
internet sources and useful discussions with the supervisor. The advanced ADS
skills were step-by-step learned by working and trying to solve different
problems. This thesis work also involves the passive component selection, layout
design, simulation techniques, and understanding of high frequency effects when
implementing the LNA in a PCB process.

1.4 Outline
The report is organized with six chapters including the introduction. And
the report is ended with appendix.

Chapter two starts with the theoretical concepts of the UWB and radio
frequency (RF) passive components. This chapter also gives same RF
theory that was used in this work.

Chapter three covers the theoretical design consideration for the LNA.

Chapter four gives the overall design process of the LNA. This starts with
design specification then covers the component selection to matching
network design.

Chapter five contains the final LNA simulation and measurement results.
In the same time other necessary simulation results for component
selection are given.

Chapter six is for the conclusion and further work.

1.5 References
[1] Wikipedia, http://en.wikipedia.org/wiki/Ku_band.
[2] Eric Ottosson, Design and Implementation of a Ultra wide-band low noise
amplifier 3.1-4.8 GHz, Thesis LITH-ITN-ED-EX-06/017-SE.
[3] Federal Communication commission (FCC), Revision of part 15 of the
Commission’s Rules Regarding Ultra Wideband Transmission Systems,
First Report and Order ET Docket 98-153, Feb. 2002.
[4] Adriana Serban, Ultra-Wideband Low-Noise Amplifier and Six-Port
Transceiver for High Speed Data Transmission. LiU-Tryck Linkoping,
Sweden, 2010.
[5] Radio Spectrum Committee, RSCOMO7-23 Final CEPT Report on UWB
Mandate, March 2007.
http://circa.europa.eu/Public/irc/infso/Home/main?index.
[6] Adriana Serban Craciunescu, Low-Noise Amplifier Design for Ultra-
Wideband Systems, Thesis LiU-TEK-LIC-2006:62.

2
2 Ultra-wideband and General RF Theory
The main purpose of this chapter is to describe UWB and general RF
theory which are necessary for this diploma work. It is assumed that the reader
has basic knowledge of electrical engineering. The motivated reader, who would
like to get deeper understanding, can see the books and articles listed in the
references.

2.1 Ultra-wideband
Ultra-wideband (UWB) communication technology promises a huge
opportunity to impact the future communication world. Large available
bandwidth, the wide scope of the data rate/range trade-off, and low-cost operation
which will lead to massive usages, all present a unique opportunity for UWB
systems to impact the way people and intelligent machines communicate and
interact with their environment. In particularly, UWB will give huge advantages
for short-range communications. In the past 20 years, UWB has been used for
different areas e.g. radar, sensing, military communications [1]. Even though the
development and advancement of UWB system is not faster as other wireless
system, UWB will be the next best technology for all types of wireless systems
[2].

2.1.1 History of UWB

UWB history is generally perceived to start after 1960 with the
development of Linear Time Invariant System description via impulse stimuli. On
the contrary, UWB transmissions history is much older and goes back to the end
of XIX century. The history of wireless communications can be considered to
start at the end of XIX century with the work carried by Guglielmo Marconi.
From the end of XIX century until nowadays, three eras can be devised in
the history of development of UWB systems development: pioneering era (1886-
1906), subnanosecond era (1939-1994) contemporary standardization and
commercialization era (1998-2007) [3].
Despite its renewed interest during the past decade, UWB has a history as
long as radio. When invented by Guglielmo Marconi more than a century ago,
radio communications utilized enormous bandwidth as information was conveyed
using spark-gap transmitters [4]. Until 1960s communications were dominated by
continuous wave radio transmissions [3]. The next milestone of UWB technology
came in the late 1960s, when the high sensitivity to scatterers and low power
consumption motivated the introduction of UWB radar systems [4]. During the
1980s, UWB technology was referred alternately to as impulse, carrier-free or
baseband. The term ‘‘UltraWideBand’’ was first coined by the U.S. Department
of Defense in 1989. After the great technical developments, related to
subnanosecond pulses in the years from the sixties until the end of the century,
another rush started with the world-wide activities for technology standardization.
Nowadays, Multi Carrier UWB (MC-UWB), Orthogonal Frequency Division
Multiplexing (OFDM) UWB and Frequency Modulation UWB (FM-UWB) are
the strongest candidates for future UWB communication systems [3].

3
2.1.2 Theory
When UWB technology was proposed for civilian applications, there were
no definitions for the signal. According to the FCC definition, the signal is
characterized as UWB if the signal bandwidth (BW) is 500 MHz or more or a
fractional bandwidth Bf of more than 20% [5]. The fractional bandwidth is
defined as
BW f − fL
Bf = =2 H (2.1)
fc fH + fL
Where fL is the lower and fL is the higher -10 dB emission point, respectively. As
for an example, Universal mobile Telecommunication system (UMTS) operates
around 2 GHz with a bandwidth of 5 MHz. This system is often called wideband,
however according to Equation (2.1), the fractional bandwidth of UMTS is
0.0025, which is much smaller than 0.2 (i.e., 80 times smaller)!
Channel capacity of a communication system is defined by the Shannon’s
capacity theorem. The channel capacity (C bit/s) of a system relates to the
following equation.
C = BW ⋅ log 2 (1 + SNR ) (2.2)
S
Where signal to noise ratio, SNR =
N
Where S is the signal power and N is the noise power respectively. It can be seen
that channel capacity increases linearly with the bandwidth (BW) and
logarithmically with SNR. So channel bandwidth is the main route to get the high
data rate.
UWB wireless personal area network (WPAN) physical (PHY) layer
standard divides the whole available ultra wideband spectrum between 3.1- 10.6
GHz into 14 sub-bands belonged to 6 band groups as show in Fig. 1 [1]. Band
group 1 is mandatory, remaining groups are optional.

Figure 2- 1 Diagram of band allocation [7]

FCC Mask
To avoid interference with existing communication systems, various
regions of the spectrum should have different allowed power spectral densities
(PSD). FCC has assigned the effective isotropic radiated power (EIRP) allowed
for each frequency band [6]. EIRP is the equivalent isotropically radiated power

4
which is the power radiated by an omnidirectional antenna with gain 1. The level
of –41.3 dBm/MHz in the frequency range of 3.1–10.6 GHz is set to limit the
interference to existing communication systems, and to protect the existing radio
services [8]. Figure 2- 2 and Figure 2- 3 shows the FCC emission limit for
outdoor and indoor UWB communications respectively. These figures also called
FCC mask.
Table 1 FCC emission limits for indoor and outdoor UWB
Frequency Ranges Indoor EIRP Outdoor EIRP
(dBm/MHz) (dBm/MHz)
960 MHz-1.61 GHz -75.3 -75.3
1.61 GHz-1.99 GHz -53.3 -63.3
1.99 GHz-3.1 GHz -51.3 -61.3
3.1 GHz-10.6 GHz -41.3 -41.3
Above 10.6 GHz -51.3 -51.3

Figure 2- 2 FCC emission limit for outdoor UWB communications [3]

Figure 2- 3 FCC emission limit for indoor UWB communications [3]

5
2.1.3 Regulations
One of the important issues in UWB communication is the frequency of
operation. There are many systems operating under allocated bands in the UWB
signal band. So existing narrowband allocated services to be protected from
possible interference generated in UWB systems. Figure 2- 4 shows the possible
interferes for the UWB system. It can be seen that UWB has huge bandwidth and
less PSD, whereas other narrow-band e.g. GSM, GPS, WiMAX have high PSD
and less data rate.

Figure 2- 4 Spectrum of the Main Interfering Communication Standards for UWB

Communication System [11]

In USA, the FCC committee is responsible for all kind of regulations and
legal requirements of UWB system. FCC has given permission to design and
operation of low power UWB system within 3.1 to 10.6 GHz frequency spectrum
[5].
In Europe there are number of key organizations are recognize by the
European Commission (EC). Currently ETSI, ECC and EC have all
recommended and approved the use of UWB devices within 6-8.5 GHz subject to
mitigate the technical problems arise by the FCC in USA [9].
And the extended range 8.5 to 9 GHz band which is same as US but this
band is considered for UWB impact analysis on surveillance radars. Furthermore,
EC has allowed to operate in EU 4.2 – 4.8 GHz band with -41.3 dBm/MHz and
the maximum peak EIRP of 0 dBm measured in 50 MHz [6].

2.1.4 Applications
UWB technology was first used in the Second World War by US Army
for their communication system. Since the signal at any particular frequency is
incomplete, the enemies could not able to intercept the entire message [6]. Thus
far the UWB technology has been mainly applied to military (especially radar)
appliances [9]. UWB has a number of features which make it attractive for
consumer communications applications. In particular, UWB systems
• have potentially low complexity and low cost;
• have a noise-like signal spectrum;
• are resistant to severe multipath and jamming;

6
 • have very good time-domain resolution allowing for location and tracking
applications
Even with the significant power restrictions, UWB holds enormous potential for
wireless ad-hoc and peer-to-peer networks [1]. Some of the commercial
applications of UWB are given below [3]:
• Adhoc Networking e.g. WPANs
• Wireless sensor networks e.g. smart highway
• Radio Frequency Identification or RFID e.g. tag, barcode
• Consumer Electronics e.g. wireless DVD player
• Asset Location e.g. inventory items
• Medical applications e.g. medical imaging

2.2 RF Passive Components

The RF passive and active components do not behave according to simple
mathematical models; they have size, shape and are manufactured using non ideal
materials [12]. Capacitors at certain frequencies may not be capacitors at all, but
may look inductive, while inductors may look like capacitors, and resistors may
tend to be a little of both. In this chapter we will discuss about RF passive
components. But, first we will look the simplest components of any system and
examine its problem at radio frequency [13].

2.2.1 Wires
Wires used in an RF circuit can take many forms. Wire-wound resistors,
inductors, and axial- and radial-leaded capacitors all use a wire of some size and
length either in their leads, or in the actual body of the component, or both. Wires
are also used in many interconnect applications in the lower RF spectrum. The
behavior of a wire in the RF spectrum depends to a large extent on the wire’s
diameter and length [13].
Wires at low frequencies, utilizes its entire cross-sectional area as a
transport medium for charge carriers. As the frequency is increased, an increased
magnetic field at the center of the conductor presents an impedance to the charge
carriers, thus decreasing the current density at the center of the conductor and
increasing the current density around its perimeter. This increased current density
near the edge of the conductor is known as skin effect. It occurs in all conductors
including resistor leads, capacitor leads, and inductor leads. The depth into the
conductor at which the charge-carrier current density falls to l/e, or 37% of its
value along the surface, is known as the skin depth and is a function of the
frequency and the permeability and conductivity of the medium. The net result of
skin effect is an effective decrease in the cross-sectional area of the conductor
and, therefore, a net increase in the ac resistance of the wire as shown in Figure 2-
5 [13]. For copper, the skin depth is approximately 0.65 µm at 10 GHz [14].
In the medium surrounding any current-carrying conductor, there exists a
magnetic field. If the current in the conductor is an alternating current, this
magnetic field is alternately expanding and contracting and, thus, producing a
voltage on the wire which opposes any change in current flow. This opposition to
change is called self-inductance and we call anything that possesses this quality

7
an inductor. Straight-wire inductance might seem trivial, but the higher the
frequency is the more important this effect becomes. The inductance of a straight
wire depends on both its length and its diameter [13].

Figure 2- 5 Skin depth area of a wire [13].

2.2.2 Resistors
Resistors are used everywhere in circuits, as transistor bias networks, pads
etc. Behaviors of high frequency resistors are different from the world of direct
current (dc). There are different types of resistors such as carbon composite, wire-
wound, metal film and thin-film chip resistors [15]. Of these types, mainly the
thin-film chip resistors are found application in RF and MW circuits as surface
mount devices (SMDs). The electric equivalent circuit of a high frequency
resistor’s R is more complicated and parasitic components have to be considered.
Figure 2- 6 represents the equivalent circuit of a RF resistor. The model includes
two inductances L, modeling the inductor’s leads, the stray capacitance Ca and
inter-lead capacitance Cb [15].

Figure 2- 6 Electric equivalent circuit representation of the resistor [15].

Figure 2- 7 represents the example of 500 ohm thin-film resistor as a

function of frequency. This example underscores the care that is required when
dealing with RF resistors. Not all resistors behave as shown in the figure, often
multiple resonance point occurs when the frequency reaches GHz range [15].

Figure 2- 7 Absolute impedance value of a 500 ohm thin-film resistor as a function of

frequency [15].

8
2.2.3 Capacitor
A capacitor typically consists of two conducting surfaces or plates
separated by dielectric insulation material that permits the storage of energy in the
electric field between the plates. The dielectric is usually ceramic, air, paper,
mica, plastic, film, glass, or oil. Dielectric prevents current flow when applied
voltage is constant, but a time-varying voltage produces a current proportional to
the rate of voltage change [16]. The current in a capacitor is given by
dv
I =C (2.3)
dt
where C is the capacitance measured in farads (F). One farad is the capacitance
that will store one coulomb of electrical charge (6.28×1018 electrons) at an
electrical potential of one volt. Or, in math form:
Qcoulombs
C farads = (2.4)
Vvolts
The capacitance of the parallel plate structure is given by
A A
C =ε = ε oε r (2.5)
d d
Where
ε = absolute permittivity of the dielectric = εoεr
A = area of parallel plates
d = spacing of plates
εo= permittivity of free space
εr = relative permittivity or dielectric constant of dielectric medium
There are widespread applications of chip capacitors in the RF circuits for
the tuning and matching networks as well as for biasing active components such
as transistors. At high frequency dielectric becomes lossy. The impedance of a
capacitor must be written as a parallel combination of conductance Ge and
susceptance ωC:
1
Z= (2.6)
Ge + jωC
Figure 2- 8 represents the equivalent circuit for a high frequency capacitor
with parasitic lead inductance L, series resistor Rs describing losses in the lead
conductors and dielectric loss resistance [15]
1
Re = (2.7)
Ge

Figure 2- 8 Electric equivalent circuit for a high frequency capacitor [15].

9
 In the Figure 2- 9, the capacitor reveals a similar resonance behavior due
to the presence of dielectric losses and finite lead wires [15].

Figure 2- 9 Absolute value of the capacitor impedance as a function of frequency [15].

2.2.4 Inductor
An inductor is nothing more than a wire wound or coiled in such a manner
as to increase the magnetic flux linkage between the turns of the coil. This
increased flux linkage increases the wire’s self-inductance. Inductors are used
extensively in RF design in resonant circuits, filters, radio frequency interference
(RFI)/electromagnetic interference (EMI) suppression, phase shift and delay
networks, and as RF chokes used to prevent, or at least reduce, the flow of RF
energy along a certain path [13]. Figure 2- 10 shows a RF coil [15]. It is known
from the previous discussion that the windings represent an inductance in addition
to the frequency dependent wire resistance Rd and parasitic capacitance Cd [15].

Figure 2- 10 Distributed capacitance and series resistance in the inductor coil [4].

Inductance L is a property of electrical circuits that opposes changes in the

flow of current. An inductor stores energy in a magnetic field. The unit of
inductance is the Henry (H). A Henry is the inductance that creates an
electromotive force (EMF) of one volt when the current in the inductor is
changing at a rate of one ampere per second or in math form:
∆I
V =L (2.8)
∆t
Where
V = created EMF in volts (V)
L = inductance in henrys (H)
I = current in amperes (A)
t = time in seconds (s)

10
 ∆ indicates a small change in.
Several factors affect the inductance of a coil. Perhaps the most obvious
are the length, the diameter and the number of turns in the coil. Also affecting the
inductance is the nature of the core material and its cross-sectional area [17]. Well
known formula for the inductance of an air core solenoid:
πr 2 µo N 2
L= (2.9)
l
Where
N = number of turns
L = length of the coil
r = radius of the coil core
µ o = permeability in vacuum= 4π×107 H/m
The equivalent circuit model of the RF inductor is shown in Figure 2- 11
[15]. The parasitic shunt capacitance Cs and series resistance Rs represent
composite effect of distribution capacitance Cd and resistance Rd respectively.

Figure 2- 11 Equivalent circuit model of the HF inductor [15].

Figure 2- 12 Frequency response of the impedance of an RFC [15].

Figure 2- 12 shows the frequency response of the RFC impedance which

deviates from the expected behavior of an ideal inductance at high frequencies.
Frequency dependency can form complicated resonance conditions with
additional elements in an RF system [15]. The ratio of an inductor’s reactance to
its series resistance is often used as a measure of the quality of the inductor.
X
Q= (2.10)
Rs
The larger the ratio, the better is the inductor. This quality factor is
referred to as the Q of the inductor. If the inductor were wound with a perfect

11
conductor, its Q would be infinite and we would have a lossless inductor. Of
course, there is no perfect conductor and, thus, an inductor always has some finite
Q. At low frequencies, the Q of an inductor is very good because the only
resistance in the windings is the dc resistance of the wire-which is very small. But
as the frequency increases, skin effect and winding capacitance begin to degrade
the quality of the inductor [13].

2.3 Active Devices:

Generally Field Effect Transistors (FETs) are used in the RF and MW
systems due to high gain and low noise figure. There are different types of FETs
family e.g. junction field effect transistors (JFETs), high electron mobility
transistors (HEMTs), metal semiconductor barrier junction transistor (MESFET).
MW transistor amplifiers are always rugged, low-cost, reliable and can be
integrated in both hybrid and monolithic integrated circuits with mixer, oscillator
and related components [18]. Basic structures of FETs for high frequency
applications are discussed in these subsections.

2.3.1 JFETs
It is the most common FET. JFET has high input impedance (on the order
of 107 to 1012 Ω) compare to BJT. Unlike BJT, a JFET has a negative temperature
coefficient so that thermally runway is not a problem. Due to robustness, the
JFET is used as a power transistor [19].
Its operation depends on control of majority carrier in a channel by
applying voltage. This voltage, control the currents by means of an electric field.
Thus JFET is a voltage controlled current source. Figure 2- 13 shows the biasing
effect of n-channel JFET, where electrons flow from the source (S), past the gate
(G), to the drain (D). If a negative voltage is applied at the gate terminal, its
negative electric field will try to pinch the electrons flow and confine it to a
smaller cross-section of the n-channel. This affects the resistance of the n-channel
and limits the current flow. Hence by varying the gate-source voltage it is
possible to control the current flow [21].

Figure 2- 13 Biasing effect of n-channel JFET [21]

12
 Cut-off

Figure 2- 14 IV characteristic of FET [23].

This figure shows the three regions such as triode, saturation and cut-off.
When the gate voltage is zero the maximum carrier flows through the channel
from source to drain. Cut off is the off state of the FET. It needs minimum drain
to source voltage (VDS) to turn on the FET. Once the FET is biased, the drain
current (IDS) increases linearly with VDS up to saturation level at a given value of
gate-source voltage (VGS). The power amplifier is design in the triode region
whereas the LNA is designed at the saturation region.

2.3.2 GaAs MESFET

Metal semiconductor barrier junction transistor (MESFET) is similar to
FET except that junction is a metal semiconductor barrier much as is the case
Schottkey diodes [20]. GaAs MESFET is used in high performance circuits of
communications, computer, and military systems. Specific functions for MESFET
include MW power amp, oscillator, switches, and mixer [19]. Due to higher
electron mobility GaAs is used instead of Si. That, coupled with the use of a
Schottky-barrier gate with a length of only about 1 µm, allows its use as a
microwave amplifier with very good operating characteristics [16].

Figure 2- 15 GaAs MESFET [5]

2.3.3 HEMTs
HEMTs are important recent developments in microwave and millimeter-
wave transistors. These devices make use of heterojunctions for their operation.

13
The heterojunctions are formed between semiconductors of different
compositions and bandgaps, for example, GaAs/AlGaAs and InGaAs/InP. These
relatively new types of devices offer significant improvements for low-noise
amplifiers and microwave power amplifiers [16].

Figure 2- 16 HEMT [16]

Figure 2- 16 shows the cross-section of an HEMT structure using GaAs

and AlGaAs. The conventional HEMT is similar to a GaAs MESFET. As seen in
figure HEMT has two ohmic contacts (source and drain) and a Schottky gate. The
difference between the two types of devices and the key to the HEMT’s improved
performance is in the underlying semiconductor material. The HEMT has superior
electron transport properties and much higher sheet charge density than the
MESFET because of a two-dimension electron gas layer that is formed in a thin
layer between the AlGaAs and the undoped GaAs layers.

HEMPTs have demonstrated unprecedented noise performance at

cryogenic temperatures (within a few degrees of absolute zero) and good
microwave and millimeter-wave noise and power performance at room
temperature at frequencies up to 60 GHz. Typical noise figures at 12 GHz for
commercially available low-noise HEMTs are about 1.0 dB In addition to lower
noise figure, HEMTs also have several characteristics that make them more
attractive for low-noise applications. They are easier to provide impedance
matching, and they have a larger gain-bandwidth product [16].

2.3.4 FET Transistor Modeling

FET Transistor is nonlinear device and for circuits analysis different types
of models are used e.g. small signal, large signal. Moreover these small and large
signal models are divided into low and high frequency applications. Small-signal
modeling is a common analysis technique is used to approximate the behavior of
nonlineaer devices with linear equations. This linearization is formed about the
DC bias point of the device (that is, the voltage/current levels present when no
signal is applied). Nothing changes because the assumption is that the signal is so
small that the operating point (gain, capacitance etc) doesn't change. Large-signal
modeling is a common analysis method used in electrical engineering to describe
nonlinear devices in terms of the underlying nonlinear equations. This model
takes into account the fact that the large signal actually affects the operating point
and takes into account that elements are non-linear and circuits can be limited by
power supply values.

14
2.3.4.1 High Frequency model of FET
It is necessary to take some considerations for the high frequency model
of FET. FET structure acts as a parallel capacitor when viewed from the gate and
source terminals. Frequency dependent components are: Cgs – gate to source
capacitance, Cgd -gate to drain capacitance and Cds -drain to source capacitance.
Drain to source capacitance is small and less effect of high frequency.
Capacitance can be modeled as voltage dependent in the following ways [22]
C gso C gdo
C gs = m
and C gd = m
where
 VGS   VGD 
1 +  1 + 
 ψo   ψo 
Cgso and Cgdo are the zero bias gate-source and gate-drain junction
capacitance; VGS and VDS are the quiescent gate-source and drain-source voltage;
m is the gate p-n grading coefficient (SPICE default is 0.5) and ψo is the gate
junction (barrier) potential typically 0.6 V [22].

Figure 2- 17 High frequency FET model [22]

The maximum operating frequency ωT, is the frequency at which the FET
no longer amplifies the input signal i.e. the dependent current source gmvgs is
equal to the input current [22].
gm
ωT = (2.11)
(Cgs + Cds )
2.4 Transmission Line
In the conventional low frequency circuit analysis the Kirchhoff’s laws
can be applied where voltages and currents are uniform all over the conductor. At
the higher frequencies the Kirchhoff’s laws can not be applied directly due to
spatial behavior of the voltage and current. A new approach is needed to explain
the transmission line which is called distributed circuit theory. The transmission
lines considered here are system of two or more parallel conductors [3]. The line
is subdivided into infinitesimal length ∆z, over which voltage and current can be
assumed to remain constant depicted in Figure 2- 18 [4].

15
Figure 2- 18 Segment of transmission line expressed with distributed parameters R, L, C and
G, where all parameters are given in terms of unit length [4].

Applying Kirchhoff’s voltage laws in the Figure 2- 18

( R + jωL) I ( z ) ∆z + V ( z + ∆z ) = V ( z ) (2.12)
which is re-expressed as a differential equation
dV ( z )
− = ( R + jωL) I ( z ) (2.13)
dz
Applying Kirchhoff’s current laws to the node a in Figure 2- 18 yields
dI ( z )
− = −(G + jωC )V ( z ) (2.14)
dz
From equation (2.13) and (2.14) we can get the standard 2nd order differential
equation
d 2V ( z )
2
− k 2V ( z ) = 0 (2.15)
dz
d 2 I ( z)
2
− k 2 I ( z) = 0 (2.16)
dz
Where k is known as a complex propagation constant
k = k r + jk i = ( R + jωL)(G + jωC ) (2.17)
Solutions of equation (2.15) and (2.16) are two exponential functions for the
voltage and current.
V ( z ) = V + e − kz + V − e + kz (2.18)

I ( z ) = I + e − kz + I − e + kz (2.19)
Equation (2.18) and (2.19) are the general solutions for the transmission lines
aligned along the z-axis. From these two equations, the characteristic line
impedance Z0 can be defined as
( R + jωL) ( R + jωL)
Z0 = = (2.20)
k (G + jωC )
Characteristic impedance can be written as
V+ V−
Z0 = = − (2.21)
I+ I−

16
Z0 is not impedance in the conventional circuit sense. Its definition is based on the
positive and negative travelling voltage and current waves.

2.4.1 Lossless Transmission Line

The characteristic line impedance defined in equation 2.20 is a complex
quantity and therefore there will be losses always in the realistic lines [4]. There
are two regions where Z0 tends to be resistive and constant [9]. The first region
occurs at very low frequencies when R >> jωL and G >> jωC . These results in

R
Z0 = (2.22)
G
The second region occurs at very high frequencies when jωL >> R and
jωC >> G . These result in

L
Z0 = (2.23)
C
which is a constant factor and the transmission line is said to be lossless because
there are no dissipative elements in the line. Equations (2.22) and (2.23) are very
important because under these conditions the line impedance tends to remain
frequency independent and a state known as ‘distortion-less transmission’ [21].

2.4.2 Voltage Reflection Coefficient

High frequency electric circuits can be viewed as a collection of finite
transmission line sections connected to various discrete active and passive
devices. Therefore consider the terminated line of length l shown in Figure 2- 19
[4]. We know the voltage along the line is given by (2.18). The second term in
(2.18) has the meaning of a reflection from the terminating load impedance for
values z < 0. Voltage reflection coefficient Γ0 indicates the amount of reflected
wave with respect to incident wave at the load z = 0 .
V−
Γ0 = (2.24)
V+

Figure 2- 19 Terminated transmission line at location z=0.

Reflection coefficient can be written as

17
 Z L − Z0
Γ0 = (2.25)
Z L + Z0
which involves known circuit quantities and independent of voltage wave. For the
case where load impedance matches the line impedance i.e. Z 0 = Z L , no reflection
occurs and Γ0 = 0 .

2.4.3 Standing Wave Ratio

Standing wave ratio (SWR) is defined as the ratio of the maximum voltage
(current) over the minimum voltage (current). This is the best way to find the
mismatch of a transmission line.
Vmax I
SWR = = max (2.26)
Vmin I min
Another form of SWR is
1 + Γ0
SWR = (2.27)
1 − Γ0
which has a range of l ≤ SWR < ∞ For the matched termination SWR → 1 and for
the worst case of either open or short circuit results in SWR → ∞ .

2.5 Microstrip Transmission Line

Microstrip line is one of the most popular types of planner transmission
lines. It is cheap to manufacture, easily integrated with passive and active devices
[8]. Geometry of microstrip line is shown in the Figure 2- 20 [4] where W is the
width of the line, d is the thickness of the dielectric and εr is the relative
permittivity of dielectric. The phase velocity and propagation constant of a
microstrip line can be expressed as
c
Phase velocity v p = (2.28)
ε eff

Propagation constant β = k0 ε eff (2.29)

where εeff is the effective dielectric constant of the microstrip line which satisfies
the relation, 1 < ε eff < ε r and is independent of on the substrate thickness d and
conductor width W.

Figure 2- 20 (a) Microstrip line; (b) end view of microstrip line [9].

18
 By neglecting the thickness of the conductor, t compare to the substrate
height, d, the characteristic impedance can be represent with the line dimension
(W and d). For narrow strip line, W / d < 1 , the line impedance,
Zf d W
Z 0= ln(8 + ) (2.30)
2π ε eff W 4d

Where Z f = ( µ0 / ε 0 ) = 376.8 Ω, is the wave impedance in free the space and

the effective dielectric constant is given by

ε r + 1 ε r − 1  d  
−1 / 2 2
d  
ε eff = + 1 + 12  + 0.041 −   (2.31)
2 2  W  W  

For the wide line W/d > 1, line impedance is

Zf
Z0 = (2.32)
 d 2 d 
ε eff 1.393 + + ln + 1.444  
 W 3 W 
With
−1 / 2
εr + 1 εr −1 d 
ε eff = + 1 + 12  (2.33)
2 2  W
With the knowledge of the effective dielectric constant we can compute the
expression for the wavelength of
vp c λ
λ= = = 0 (2.34)
f f ε eff ε eff
where c is the speed of light and f is the operating frequency.

2.6 Transmission Line as Electrical Components

It is possible to design transmission line that will behave like electrical
components e.g. capacitor, inductor, resistor, transformer. These components are
made by careful choice of transmission line characteristic impedance (Z0), line
length (l) and termination (ZL). The properties of these components can be
calculated by using well known expressions for calculating the input impedance
of a transmission line. From the transmission line equation the voltage reflection
coefficient can be written as [1]
Z L − Z0
Γv = (2.35)
Z L + Z0

19
 Figure 2- 21 Line voltages reference to the load end [21]

It is more convenient to take voltage and current references from the

terminating or load end of the line. This is shown in Figure 2.6. From the
definition of line attenuation and for a distance l from the load, we have incident
and reflected voltages [21]
vi = ViL e + γl (2.36)
and
vr = VrL e + γl (2.37)
And using the definition for voltage reflection coefficient Γv
V
Γvl = rl = ΓL e − 2γl (2.38)
Vil
where
l = line length
Γv= voltage reflection coefficient at load
Γvl= voltage reflection coefficient at load distance l from load
γ = propagation constant = α+jβ nepers/m
At any point on a transmission line of distance l from the load
vl = vi + vr = vi + vi Γv e −2γl (2.39)
−2 γl
il = ii + ir = ii + ii Γi e (2.40)
Dividing Equation (2.39) by (2.40) and defining Zl at point l and Zo
1 + Γv e −2γl 
Zl = Zo  − 2γl 
(2.41)
1 − Γv e 
If the total length of the line is l, the impedance at point l becomes the input
impedance (Zin) of the line. After doing some calculation, Zin can be written as
 Z sinh γl + Z L cosh γl 
Z in = Z o  o  (2.42)
 Z o cosh γl + Z L sinh γl 
We know propagation constant, γ = α + jβ . When the line is considered as low
loss i.e. α << β, then propagation constant becomes γ = jβ . Since we know
β = 2π / λ where λ is the electrical length at the frequency of operations, so
Equation (2.42) becomes

20
  2πl 2πl 
 jZ o sin λ + Z L cos λ 
Z in = Z o 
2πl 
(2.43)
2πl
 jZ L sin + Z o cos 
 λ λ 
This equation will investigate the property of transmission line.

2.6.1 Transmission Line as a Reactances

A transmission line can be made to behave like a reactance by making the
terminating load a short circuit ( Z L = 0 ). In this case, Equation (2.43) becomes

 2πl   2πl 
 jZ o sin λ + 0   j sin λ  2πl
Z in = Z o  = Zo  = jZ o tan
2πl  2πl 
(2.44)
 0 + Z o cos   cos  λ
 λ   λ 
2πl
When l < λ / 4 , Z in = jZ o tan (2.45a)
λ
is an inductive.
2πl
When λ / 4 < l > λ / 2 , Z in = − jZ o tan (2.45b)
λ
is a capacitive.
Similar reactive effects can be produced by open-circuited load.
2πl
Z in = − jZ o cot (2.46)
λ
At the radio frequency any unterminated transmission has a stray
capacitance with an open circuit. This stray capacitance can be ignored for our
frequencies of operation, its reactance is extremely high [21].

2.6.2 Transmission Line as a Transformer:

When l = λ / 2 , Equation (2.43) becomes
 jZ sin π + Z L cos π 
Z in = Z o  o  = ZL
 jZ L sin π + Z o cos π 
So transmission line acts as a 1:1 transformer. A resistor dissipating a lot
of heat adjacent to a transistor can cause the latter to malfunction. With a 1:1
transformer, the resistor can be physically moved away from the transistor
without upsetting electrical operating conditions.
when l = λ / 4 , Equation (2.43) becomes
Z o2
Z in = (2.47)
ZL
Input impedance becomes higher when length of transmission line
becomes quarter wave. This concept can be used in the bias circuit of active
device.

21
2.7 Smith Chart
Smith chart is a very useful tool for RF circuit design e.g. amplifier,
oscillator. Gain circles, noise circles, matching network design, impedance and
admittance determination, and finding reflection coefficients and voltage standing
wave ratio can be represented using the Smith chart [21]. The Smith chart was
developed by P.H. Smith in the late 1930s. Figure 2- 22 shows a simplified Smith
chart.

Wavelengths
to generator Inductive
domain

Short
circuit Capacitive
domain
Wavelengths
to load Open
circuit

Figure 2- 22 Smith Chart.

The Smith chart is a phasor diagram of the reflection coefficient, Γ, on

which constant-r and constant-x circles are drawn, where r and x are the
normalized values of the series resistive and reactive parts of the load impedance.
The horizontal and vertical axes of the chart are the real and imaginary axes of the
reflection coefficient. Any circle centered on the Smith chart centre is a constant-
|Γ| circle and a constant VSWR circle too.
The Smith chart, described so far as a family of impedance coordinates,
can easily be used to convert any impedance (Z) to an admittance (Y), and vice-
versa. In mathematical terms, an admittance is simply the inverse of an
impedance, or
1
Y= (2.48)
Z
where, the admittance (Y) contains both a real and an imaginary part, similar to
the impedance (Z). Thus
Y = G ± jB (2.49)

G = Conductance in Siemens (S)

B = Susceptance in Siemens (S)

22
2.7.1 Smith Chart Theory
This section deals with the derivation of the resistance (R) and reactance
(X) circles of the Smith chart.
The normalized load impedance is
Z L R + jX
z= = = r + jx (2.50)
Z0 Z0
And the reflection coefficient is
Γ = Γr + jΓi (2.51)
From the Equation (2.25) we can write
1+ Γ
z= (2.52)
1− Γ
Substituting z and Г in Equation (2.50)
1 + Γr + jΓi
r + jx = (2.53)
1 − Γr − jΓi
can be separated into
1 − Γr2 − Γi2
r= (2.54)
(1 − Γr ) 2 + Γi2
2Γi
and x = (2.55)
(1 − Γr ) 2 + Γi
The Equation (2.54) and (2.55) are the transformations rules of finding z if
the reflection coefficient is specified in term of Гr and Гi. We can derive the
parametric equations of circles from (2.54) and (2.55) as
2 2
 r  2  1 
 Γr −  + Γi =   (2.56)
 r +1  r +1
2 2

(Γr − 1)2 +  Γi − 1 1

=  (2.57)
 x  x
Both (2.56) and (2.57) are parametric equations of circles in Г-plane.
Figure 2- 23 represents the parametric circle equations (2.56) for various
normalized resistances. For example, if the normalized resistance r is zero, the
circle is centered at the origin. And in the limit for r → ∞ , the circles radius
approaches r /( r + 1) → 0 . This mapping is for fixed values of r only and does not
involve x. thus for a fixed value of r, an infinite range of reactance values x as
indicated by straight line in z-plane [15].

23
 Figure 2- 23 Parametric representation of the normalized resistance r [15].

Figure 2- 24 represents the parametric circle Equations (2.57) for various

normalized reactance. Here the centers of the circles reside along a line
perpendicular to the Γr = 1 point. For x = ∞ , the circle of radius becomes zero. It
is observed that negative x-values refer to capacitive impedances residing in the
lower half of the Г-plane [15].

Figure 2- 24 Parametric representation of the normalized reactance x [15].

Individually equation (2.56) and (2.57) does not construct unique mapping
from normalized impedance into the reflection coefficient plane. Figure 2- 25
represents the smith chart by combining r and x circles for Γ ≤ 1 . This Smith
chart is a one-to-one mapping between normalized impedance and the reflection
coefficient plane. It is also noticed that resistance circles r have a range 0 ≤ r < ∞
and the reactance circles x can be either negative (capacitive) or positive
(inductive) values in the range, − ∞ < x + ∞ . For the computation of the input
impedance of a terminated transmission line, the motion is always away from the
load impedance or towards the generator. This rotation is indicated by an arrow
on the periphery of the chart [15].

24
 Figure 2- 25 Smith chart by combining r and x circles for Γ ≤ 1 [15].

2.7.2 Smith Chart Applications

The basics of Smith chart and theory have been discussed before. Some of
the applications of Smith chart are given in this section.

a) Reflection Coefficients Evaluation

Smith chart can be used to find the reflection coefficient at any point, in
phasor form. Figure 2- 26 shows a point A (08-j1.6). The line OA is extended to B
and the resulting angle BOC is about -55.50. The modulus of the reflection can be
found from equation (2.27) which states that the voltage standing wave ratio,
1 + Γv
VSWR =
1 − Γv

where Γv is the voltage reflection coefficient. VSWR is obtained by

completing the circle enclosing the point A. It is then read off the intersection
between the circle and the real axis and in this case the value is 5. So
Γv = (5 − 1) / (5 + 1) = 0.667 and hence the reflection coefficient is 0.667∠ − 55.50
[21].

Figure 2- 26 Reflection coefficient: A = (0.8-j1.6), angle BOC=-55.5 degree [21].

25
 b) Impedance Transformation using Smith Chart
ZY Smith chart allows impedance transformation from a given value (ZL)
to a desired value (Zin). This is done using a T-type network shown in Figure 2-
27[15]. Using the Smith chart for computation of the input impedance of this
network we have assumed Z 0 = 50 ohm and f c = 2 GHz.

Figure 2- 27 T network connected to the base-emitter input impedance of a bipolar

transistor. Assuming Z 0 = 50 ohm and f c = 2 GHz [15]

Series-shunt transitions are shown in Figure 2- 28 with the help of ADS

Smith chart tool [15].

ZL Zin
A
E

Figure 2- 28 Computation of the normalized input impedance of the T network

2.8 Networks Model

Up to a few tens of MHz the analog circuits are characterized by
admittances, impedances, voltages, and currents. It is not possible to measure
voltage and current or impedance directly above these frequencies. It is better to
use such as voltage reflection and transmission coefficients that can be easily
measured and are related to power flow. As well, in RF and microwave (MW)
circuit design the power of signal and of noise is always of interest [24]. So for
RF and MW circuits single- and multiport network models give great advantages
for analog circuits and components to input and output port parameters
irrespective of their complicated and often nonlinear behavior. The main

26
advantage of this network model is the experimental determination of input and
output port parameters without knowing the internal structure of the system [15].
At first the basic two-port network input-output parameter relations such
as impedance, admittance, hybrid, ABCD- are discussed and shown how these
quantities can be decomposed into sum of incident and reflected waves. This
leads to the scattering matrix, which gives an alternative characterization of two-
port network in terms of incident and reflected waves. This matrix is called
scattering parameters (S-parameters) and is central to modern RF and MW circuit
design [18].

2.8.1 Two-port Networks

In the maximum circuit analysis methods require that the voltage at each
terminal referenced to a common ground, which is difficult in the RF and MW
circuits. Thus at radio frequencies ports are used, shown in Figure 2- 29. The
network in Figure 2- 29 has four terminals and two-ports. Reciprocity, symmetry,
passivity and linearity are four fundamental propertied of networks. A network is
linear if the response, voltages and currents are linearly dependent on drive level.
So if the two-port shown here is linear, the currents I1 and I2 are linear functions
of V1 and V2. A symmetrical two-port network has the same properties in each of
the ports i.e. transmission line. A reciprocal two-port has a response at port 2 from
an excitation at port 1 and vice-versa. A passive network has no internal sources
of power [24].

Figure 2- 29 Two-port network [15].

At low frequencies design the mostly used parameters are impedance,

admittance, hybrid, and chain or ABCD which relates the input and output
voltages and currents. The relationships of currents and voltages in the input-
output port can determine by combination of either short- or open-circuiting the
ports. The voltage at each port is given by
V1 = Z11I1 + Z 21I 2 (2.58)
V2 = Z 21I1 + Z 22 I 2 (2.59)
Or in a matrix form the impedance parameters are
V1   Z11Z12   I1 
 =   (2.60)
V2   Z 21Z 22   I 2 
Admittance or Y-matrix form:
 I1  Y11Y12  V1 
 =   (2.61)
 I 2  Y21Y22  V 2 

27
Hybrid or h-matrix form:
V1   AB  V2 
  =    (2.62)
 I1  CD   I 2 
Chain or ABCD- matrix form:
V1  h11h12   I1 
 =   (2.63)
 I 2  h21h22  V 2 
ABCD parameters are the best parameters for cascading two ports, when
total voltage and current relationships are required [24]. The hybrid parameters
h21 and h12 define the forward current and reverse voltage gain respectively and
remaining two determine the input impedance (h11) and out put admittance (h22).
So the hybrid parameters are used for low frequency transistor models [15].

2.8.2 S-parameters
Measurements of Z, Y, h and ABCD parameters require the ports be
terminated in either open or short circuits that could result in undesired behavior,
including oscillation or destruction to the device under test (DUT). Moreover in
RF and MW it is difficult to realize a good open and short condition. Since RF
circuits are designed with close attention to maximum power transfer conditions
and resistive load (i.e. 50 Ω), as these are close to the actual operating conditions
and so the effect of measurement errors will have less compare to imperfect opens
and shorts [24]. So in the RF and MW frequency domain S-parameters are used
to characterize the two-port network [15]. S-parameters are related to power flow
and permits to define the input-output relations of a network in terms of incident
and reflected power waves. With reference to Figure 2- 30, a generic two-port
network is driven from a source with impedance usually equal to Z 0 = 50 Ω and
driving a load of impedance ZL [21].

Figure 2- 30 Two port scattering network with source and load [21]

As seen in above figure the incident normalized power wave an and a

reflected normalized power wave bn are defined as follows:
1
an = (Vn + Z 0 I n ) (2.64)
2 Z0

1
bn = (Vn − Z 0 I n ) (2.65)
2 Z0
Where n refers either to port 1or 2 and Z0 is the characteristic impedance of the
connecting lines on the input and output side of the network. The four waves (a1,

28
a2, b1 and b2) are related by the following equations where S11, S12, S21 and S22 are
the S-parameters:
b1 = S11a1 + S12a2 (2.66)
And
b2 = S21a1 + S 22a2 (2.67)
Equations (2.50) and (2.51) can be written in matrix form as
b1   S11S12  a1 
 =   (2.68)
b2   S 21S 22  a2 
where S11 and S22 are the input and output reflection coefficient
respectively and whereas other S21 and S12 are the forward and backward voltage
gain respectively.

References
[1] Maria-Gabriella Di Benedetto, Thomas Kaiser, Andreas F. Molisch, Ian
Oppermann, Christian Politano, and Domenico Porcino, UWB
Communication Systems A Comprehensive Overview. Hindawi, USA,
2006.
[2] Jim Geier, A Technology to Consider: Ultra-wideband, February 25,
2003. www.wi-fiplanet.com/tutorials/article.php/1598581
[3] Homayoun Nikookar and Ramjee Prasad, Introduction to Ultra Wideband
for Wireless Communications. Springer, USA, 2009.
[4] Liuqing Yang and Georgios B. Giannakis, Ultra-wideband
communications - An idea whose time has come. IEEE signal Processing
Magazine, November 2004.
[5] Federal Communication commission (FCC), Revision of part 15 of the
Commission’s Rules Regarding Ultra Wideband Transmission Systems,
First Report and Order ET Docket 98-153, Feb. 2002.
[6] Magnus Karlsson, Ultra-wideband Antenna and Radio Front-end System.
PhD thesis, Linkoping University, Sweden, 2007.
[7] “High Rate Ultra Wideband PHY and MAC Standard,” Standard ECMA
368, 2nd Edition, Dec. 2007
[8] S. Hongson et al., ‘‘On the spectral and power requirements for UWB
transmission,’’ ICC 2003, vol. 1, May 2003, pp. 738–742.
[9] D. Taylor, Ultra Wideband Radar Technology. CRC Press, USA, 2001.
[10] Radio Spectrum Committee, RSCOMO7-23 Final CEPT Report on UWB
Mandate, March 2007.
http://circa.europa.eu/Public/irc/infso/Home/main?index.
[11] Peng Wang, Fredrik jonsson, Hannu Tenhunen, dian Zhou, Li-Rong
Zheng, “Low Noise Amplifier Architecture Analysis for OFDM-UWB
System in 0.18µm CMOS”. 26th Norchip Conference 2008. Page(s):184-
189, IEEE 2008.

[12] Gary Breed, “Fundamentals of Passive Component Behavior at High

Frequencies”, High Frequency Electronics, June 2006, Summit Technical
Media.

29
[13] Chris Bowick, RF Circuit Design. Howard Sams & Co., Indianapolis, IN,
1982.
[14] Wikipedia, http://en.wikipedia.org/wiki/Skin_effect.
[15] Reinhold Ludwig and Pavel Bretchko, RF Circuit Design Theory and
Application. Prentice-Hall Inc, USA, 2000.
[16] Ferril Losee, RF Systems, Components and Circuits Handbook. Artech
House, USA, 1997
[17] Joseph J. Carr, RF Components and Circuits. Radio Society of Great
Britain, UK, 2002.
[18] David M. Pozar, Microwave and RF Design of Wireless System. John
Wiley & Sons, USA, 2001.
[19] Kwok K. NG, Complete guide to Semiconductor Devices. Wiley-
Interscience, Canada, 2002.
[20] Savant, Roden and carpenter, Electronic Design Circuits and Systems. The
Benjamin/Cummings publishing, USA, 1987.
[21] E. da Silva, High Frequency and Microwave Engineering. Butterworth-
Heineman, 2001.
[22] Ernie Kim, Class Lecture EEE 194 Section 4: RF & Microwave
Engineering, University of Sandiego. http://home.sandiego.edu/~ekim
[23] W.Marshall Leach, Class Lecture ECE3050 Analog electronocs. Georgia
Institute of Technology. http://users.ece.gatech.edu/mleach
[24] Michael Steer, Microwave and RF Design A system Approach. Scitech,
USA, 2009

30
3 Low-Noise Amplifier
Low-noise amplifier (LNA) is the first active gain stage of any radio
receiver where amplification is always a critical function. Moreover, for the ultra-
wide band (UWB) systems, the LNA becomes more challenging because of wide
frequency range, low noise figure (NF), high gain and low power consumption
[1]. Virtually all MW and RF amplifiers use three terminal solid state devices
such as junction field effect transistors (JFETs), high electron mobility transistors
(HEMTs) and hetero junction bipolar transistors (HBTs). MW transistor
amplifiers are always rugged, low-cost, reliable and can be integrated in both
hybrid and monolithic integrated circuits with mixer, oscillator and related
components [2]. As details of receiver are beyond the scope of this thesis work
and only a short theory is described in the following subsection, for a better
understanding of the LNA design.

Designing a LNA for UWB applications implies minimizing the NF and

maximizing the power gain and avoiding the undesirable oscillation and
appropriate matching to reduce the voltage standing wave ratio (VSWR). For
these reasons stability is the first step for the LNA design [3].

3.1 Receiver Overview

Receiver is at the heart of all communication systems. The basic function
of the receiver is to distinguish the signal from noise irrespective of how simple
or complex the system is. Here, the signal is some form of modulated
electromagnetic wave and the noise is like to be a random signal either from man-
made or natural [4]. There are different types of receiver architectures that are
used depending on applications e.g. heterodyne, homodyne and super-heterodyne.
Each of this architecture has its own pros and cons.

RF receiver using a heterodyne architecture is shown in Figure 3- 1, where

some of the circuitries are enclosed by dotted line as a frond-end of the receiver.
The main needs of the receiver front-end are amplification, mixing, filtering and
demodulation. It can be observed that the front-end includes three bandpass filters
(BPFs). The BPF1 right after the antenna is used to select the band of interest of
received signal and referred to as a band selection filter. Since the desired signal
at the receiver antenna is very low (some microvolts), so the signal needs
amplification. This amplification must be done with minimum additional noise
injected by the amplifier itself, using low-noise amplifier (LNA) [5].

Figure 3- 1 RF receiver using a heterodyne architecture [5].

31
 The amplification is followed by mixing, and the mixer should be
continued by anti-image filter (BPF2). In this approach a mixer with variable
local oscillator (LO) is followed by a fixed bandpass filter (BPF3). BPF3 operates
at intermediate frequency (IF) and quality factor of this filter is assumed relax.
The BPF3 is also called channel filter. The channel filter is followed by an IF
amplifier to improve the signal. The demodulator takes this output and performs
demodulation [5].

3.2 Stability
Stability is one of the major concerns of an amplifier circuit within the
frequency of interest. An RF circuit tends to oscillate depending on frequency and
terminations of source and load [3]. The stability of LNA could be defined by
Rollett factor k as
2 2 2
1 − S11 − S 22 + ∆
k= >1 (3.1)
2 S12 S 21
where
∆ = S11S22 − S12 S21 (3.2)
If k >1 and ∆<1 then the amplifier remains stable condition throughout the
entire domain of the Smith chart at the selected frequency and bias conditions.
One way is to stabilize an active device is to add a shunt conductance or series
resistance either at input or output port. For a LNA it is good option to avoid
resistive elements at the input port since they cause additional noise to be
amplified. But stabilization through addition of resistors comes at a prize such as
gain, noise and matching [3].

3.3 Noise Analysis

Noise limits the performance of all receivers. There are two types of noise
sources-internal where the noise is generated by the receiver itself and external
where noise is received by the antenna. External noise sources include both
natural and man-made sources. Industrial noise, signals from radar or
communication transmitter that provide interference and jamming sources are
man-made noises. Natural noise sources are lightning storms, solar noise and
atmospheric-loss noise. At VHF and higher frequencies, internally generated
noises are generally greater than external noises received by the antenna and
therefore are the limiting factor in system performance [6].

3.3.1 Internal Noise Sources

As long as the internal noise is the limiting factor at the higher frequency,
we will discuss common noises generated by the electronic devices. Some of the
noise sources are given below:
• Thermal noise
It is also known as a Nyquist or Johnson noise. This is caused by the
random motion of charge carriers. This type of noise generated in any passive

32
elements that contains loss such as resistor, base and emitter resistance of bipolar
transistor, channel resistance of MOSFETs (Figure 3- 2). Due to the noise the root
mean square (RMS) value of voltage fluctuation across a resistor is defined as [7]
Vn = 4kTBR (3.3)
where
k = Boltzmann’s constant
T = Absolute temperature (0K)
B = Bandwidth (Hz)
R = Resistance (Ohm)

Figure 3- 2 Thermal noise [7]

• Shot Noise
Shot noise is associated with the current flow across a potential barrier. It
is due to the fluctuation of current from the random emission of electrons (or
holes). In the semiconductors, the shot noise is due to random diffusion of carriers
through the base of a transistor and the random generation and recombination of
hole electron pairs [7].

I n2 = 2qIB (3.4)
where
q = electron charge
I = average current
B = noise bandwidth

Figure 3- 3 Shot noise [7]

• Flicker Noise
Flicker noise arises from random trapping of charge at the oxide- silicon
interface of MOSFETs. This noise is represented as a voltage source in series
with the gate as [7]
K 1
Vn2 = (3.5)
WLCox f
where

33
 K = Process-dependent constant
W = Width of channel
L = Length of channel
Cox = Oxide capacitance per unit length
f = Frequency
As the noise is inversely proportional to frequency so the effect of this
noise is negligible at higher frequencies. With these noise sources, a two port
system can be modeled by two input noise generators: a series voltage source and
a parallel current source (Figure 3- 4) [7].

Figure 3- 4 Representation of noise by input noise generators [7].

3.3.2 Noise Figure

Most of the front-end receiver is characterized by the noise figure. Noise
figure (NF) is defined as
SNRin
NF = (3.6)
SNRout
where SNRin and SNRout are the signal-to-noise power ratios measured at the input
and output respectively. Noise figure is a measure of how much the SNR
degrades. If a system has no noise then SNRin = SNRout , regardless of the gain.
The noise figure of LNA in a receiver chain can be found form the Friis equation
as
NF2 − 1 NF3 − 1 NFm − 1
NFtot = 1 + ( NF1 − 1) + + + ...... + (3.7)
G1 G1G2 G1G2 ....Gi −1
where Gi and NFm represent the gain and noise of each stage. From this
equation it is clear that the total noise figure is dominated by the first stage, NF1
i.e. the noise of the LNA. At the same time the gain of the first stage, G1 reduces
the noise contribution in the subsequent circuits [8]. Sensitivity of an RF receiver
is defined as the minimum signal level that the system can detect with acceptable
signal-to-noise ratio. Sensitivity of a system can be defined as
Pin. min = −174dBm / Hz + NF + 10 log B + SNRmin (3.8)
where -174 dBm/Hz represents the noise power that source delivers to the
receiver at room temperature considering conjugate matching at the receiver
input. Sum of the first three terms is called “noise floor” [7].

34
3.4 Power Gain
Different power gain definitions are used to understand the RF amplifier
functions. Besides the stability and noise, gain is also a concern for LNA design.
In order to define the power gain, a simplified single stage amplifier is shown in
Figure 3- 5 [3].

Figure 3- 5 Simplified single stage amplifier [3]

Input and output reflection coefficients of the above figure can be expressed as
S 21S12ΓL
Γin = S11 + (3.9)
1 − S 22ΓL
S S Γ
Γout = S 22 + 21 12 S (3.10)
1 − S11ΓS

• Available Power Gain

Power launched towards the amplifier is defined as
2
1 bS
Pinc = 2
(3.11)
2 1 − Γin ΓS
where bs is the source voltage and can write as
Z0
bs = Vs (3.12)
Z s + Z0
Input reflection has to consider for the actual input power Pin of the amplifier.
(
Pin = Pinc 1 − Γin
2
) (3.13)
Maximum power transfer from the source to the amplifier is achieved
when the amplifier is properly conjugated matched or in terms of reflection
coefficients, if Γin = ΓS* . Under this condition the gain is called available gain, PA
as
2
1 bS
PA = 2
(3.14)
2 1 − ΓS

• Transducer Power Gain

Transducer gain, GT is defined as the ratio of the power delivered to the
load to the available power from the source. This is the actual gain of an amplifier

35
stage including the effects of input and output matching and device gain [9].This
gain quantifies the gain of the amplifier placed between source and load [3].
PL
GT = (3.15)
PA
Where PL is the power delivered to the load and
1 2
(
PL = b2 1 − ΓL
2
2
) (3.16)
So after several calculations the transducer gain can be written as

GT =
(1 − Γ )S (1 − Γ )
L
2
21
2
S
2

(3.17)
(1 − S11ΓS )(1 − S 22ΓL ) − S 21S12ΓLΓS 2

• Operating Power Gain

Operating power gain, GP is defined as the ratio of the power delivered to
the load to the power supplied to the amplifier.
PL P
GP = = GT A (3.18)
Pin Pin

• Maximum Available Gain (MAG)

The maximum gain can be found from a transistor under a conjugately
matched condition is called maximum available gain (MAG). This can be
calculated by two steps [9]:

1. Calculate the intermediate quantity called B1 where

2 2 2
B1 = 1 + S11 − S 22 − ∆ (3.20)

∆ is calculated from Equation 3.2.

2. Calculate MAG using the result from Equation 3.1

S 21
MAG = 10 log + 10 log k ± k 2 − 1 (3.21)
S12
Here the value of MAG in dB and k must be greater than 1
(unconditionally stable). Polarity B1 determines which sign (+or -) to use before
the radical Equation (3.21). If the value of MAG for a particular transistor i.e. 15
dB and the design called for a minimum gain greater than 15 dB, a different
transistor would be needed [9].

3.5 Matching Network

After selection of a transistor or gain block for a particular design, there is
not much can be done within the active device other than present efficient ways in
which energy can be coupled in and out of the device. This is called efficient
matching circuits for the intended purposes [9]. In order to achieve maximum

36
power transfer, we need to match the impedance of the load to that of the source
and this is done usually by putting additional passive networks between load and
source [3]. This networks are called matching network. In the RF circuits this
networks is also used for minimizing the noise, linearizing the frequency response
and maximize power handling capabilities. In other way matching network could
be defined as a transformation of given impedance to more suitable value [3].

The cheapest and most reliable matching networks are the two
components networks. Due to the arrangement of components, this is also called
L-sections network. Figure 3- 6 [3] shows the eight possible combinations of
elements connected in series and shunt configuration. This network consists of
one capacitor and one inductor. Using the Smith chart tool, initially we can easily
design this network.

Figure 3- 6 Eight possible two components networks [3].

Figure 3- 7 [3] shows the impedance effect of L and C combinations. The

general thumb rule is that whenever an inductor is involved, we rotate towards the
upper half of the Smith chart and a capacitor results in the movements towards the
lower half.

Figure 3- 7 Impedance effects of series and shunt connections of L and C [3].

37
3.5.1 Microstrip Matching Network
In order to meet the performance of a wideband LNA, it is critical to
design the proper matching networks. Du to the parasitic effect at the higher
frequency, the discrete lumped elements are not suitable and distributed element
is a good alternative. Multi section microstrip matching networks can be used for
the UWB LNA design [10]. Details of the input and output matching network
with microstrip elements are give in Chapter Four.

3.6 References
[1] Peng Wang, Fredrik jonsson, Hannu Tenhunen, dian Zhou, Li-Rong
Zheng, “Low Noise Amplifier Architecture Analysis for OFDM-UWB
System in 0.18µm CMOS”. 26th Norchip Conference 2008. Page(s):184-
189, IEEE 2008.
[2] David M. Pozar, Microwave and RF Design of Wireless System. John
Wiley & Sons, USA, 2001.
[3] Reinhold Ludwig and Pavel Bretchko, RF Circuit Design Theory and
Application. Prentice-Hall, USA, 2000.
[4] Josep J. Carr, RF Components and circuits. Newnes, UK, 2002.
[5] Bosco Leung, VLSI for Wireless Communication. Prentice Hall, USA,
2002.
[6] Ferril Losee, RF Systems Components and Circuits Handbook. Artech
House, USA, 2005.
[7] Behzad Razavi, RF Microelectronics. Prentice Hall, USA, 1998.
[8] Adriana Serban Craciunescu, Low-Noise Amplifier for Ultra-Wideband
System. LiU-TEK-LIC-2006:62
[9] E. da Silva, High Frequency and Microwave Engineering. Butterworth-
Heineman, 2001.
[10] Adriana Serban and Shaofang Gong, Ultra-Wideband Low-Noise
Amplifier Design for 3.1-4.8 GHz. GigaHertz 2005.

38
4 LNA Design
Throughout the LNA design, we have used the ADS design tool from the
Agilent Technologies. We can divide the entire design into two steps i.e. schematic
level design and layout level design. Schematic level design includes schematic
capture, choosing a simulation type (DC, S-parameters, etc.) and choosing the
simulation set-up. Once the schematic is verified through simulation, it can be used
as a component or sub-network in another ADS design.

Once the LNA design was optimized on schematic level, different

components are converted into their layout representation: microstrip input and
output matching networks, bias network including pads for different lumped
components. Finally the RF module layout is designed. Simulations are performed
with Momentum, which is an electromagnetic simulator in ADS. It computes the S-
parameters for any planer topology including microstrip, vias and multi layer
structures. Using Momentum properties and parasitic coupling between components
are included in the of the RF circuit. One powerful possibility of the ADS is the
possibility of producing “layout components” which can be individually optimized
and further used.

4.1 LNA Specification

LNA specifications are taken from the requirements of the radio front-end
receiver in the ultra-wideband applications. There is no certain bandwidth spectrum
for the UWB all over the world. Different regions and countries have their own
bandwidth. In Europe and Asia, 6-9 GHz bandwidth is preferred in order to avoid
radio interference with other system [1]. The designed LNA must satisfy the
following specifications.

Operating frequency range 6-9 GHz

Noise figure below 2 dB

Output gain above 10 dB
Table 2 shows the substrate properties of the designed LNA. One important point of
substrate property is that for the simulation, dielectric constant value is different from
the actual value [2].
Table 2 Rogers RO4350B, substrate property [2]
RO4350B
Substrate property Typical value
Dielectric constant εr 3.48±0.05 mm
3.66 (for Simulation)
Dielectric thickness 0.254 mm
Metal thickness 0.035 mm
Metal conductivity 5.8e7 S/m
Copper roughness 0.001 mm
Dissipation factor 0.0037 mm

39
4.2 Transistor selection
Selection of a proper transistor defines the whole performances of the LNA.
There are different families of FET. We need such a transistor which will meet the
required specifications. NE3512S02 Hetero-Junction Field Effect Transistor is used
for this work which covers the 6-9 GHz bandwidth with reasonable gain and noise.
According to the data sheet of NE3512S02, Figure 4- 1 shows the minimum noise
figure and power gain within the required bandwidth [3].

Figure 4- 1 Minimum noise figure, associated gain vs. frequency characteristics [3].

4.3 Transistor Characteristics

In order to design a LNA we need to choose a proper bias point. Figure 4- 2
shows the ADS simulation setup for the I-V characteristic of the transistor using the
electrical model of NE3512S02. The simulation result is shown in the Figure 4- 3
which coincides with the data sheet result in Figure 4- 4 [2].

I_Probe Drain
V_DC
SRC1 IDS
NEC_FET
Vdc=VDS Gate
Q1
VAR partName=NE3512S02_v118
Var
Eqn
V_DC
VAR1 SRC2
VDS =0 V Vdc=VGS
VGS =0 V Source

PARAMETER SWEEP
ParamSweep TechInclude_NEC_ACTIVELIBRARY
Sweep1 NEC_ACTIVELIBRARY_Lib
SweepVar="VGS" File=Nominal
SimInstanceName[1]="DC1" DC
SimInstanceName[2]= DC
SimInstanceName[3]= DC1 Disp
Temp DisplayTemplate
SimInstanceName[4]= SweepVar="VDS" disptemp3
SimInstanceName[5]= Start=0 "FET_curve_tracer"
SimInstanceName[6]= Stop=2.5
Start=-0.6 Step=0.01
Stop=0
Step=0.1

Figure 4- 2 ADS Simulation setup for the I-V characteristic using electrical model of
NE3512S02.

40
 40
VGS=0.000

Drain Current ID (mA)

VGS=-0.043
30 VGS=-0.086
VGS=-0.129
m1 VGS=-0.171
20 VGS=-0.214
VGS=-0.257
VGS=-0.300
10 VGS=-0.343
VGS=-0.386
VGS=-0.429
VGS=-0.471
VGS=-0.514
0 VGS=-0.557
VGS=-0.600

-10
0.0 0.5 1.0 1.5 2.0 2.5
Drain to Source Voltage VDS (V)

Figure 4- 3 Simulated I-V Characteristic of NE3512S02.

Figure 4- 4 I-V Characteristic of NE3512S02 according to data sheet [3]

For the proper biasing of the designed LNA we have chosen I D = 20mA ,
VGS = −0.17V and VDS = 2V . Marker (m1) in the Figure 4- 3 shows the biasing point
of the LNA.

4.4 Transistor Models Comparison

At high frequency it is necessary to use proper transistor models which will
meet the reliable circuit operation. Two types of models are used for the circuit
design e.g. lumped models (which can be small-signal or large-signal models) and S-
parameter models, either as data sets resulting from simulations or from
measurements.
Lumped elements models are based on the physical properties of the transistor
such as oxide thickness, substrate doping concentration etc. In the low and medium
frequency these models give the accurate information about the circuit. The S-
parameter models of the active devices, i.e. transistor are used to evaluate stability,
power gain, noise-figure and bandwidth both in the conceptual stage of the circuit
design and during the circuit design using CAD-tools.

41
 S-PARAMETERS
S_Param
TechInclude_NEC_ACTIVELIBRARY
I_Probe SP1
V_DC NEC_ACTIVELIBRARY_Lib
SRC1 IDS DC_Feed Start=2 GHz
File=Nominal
Vdc=VDD V DC_Feed2 Stop=18 GHz
Step=0.1 GHz
Var
Eqn
VAR
Disp
T emp
DisplayTemplate VAR3
NEC_FET disptem p1 VDD=2
Q1 "S_Params_Quad_dB_Smith"
Term
partName=NE3512S02_v118 DC_Block "S_21_11_wZoom"
Var
Eqn
VAR
Term2
DC_Block2 VAR4
Num=2
VGG=-0.17
Z=50 Ohm
Term DC_Block S2P
Term 1 DC_Block1 DC_Feed SNP1
Num=1 DC_Feed1 File="NE3512S02v2_2-18_2_20.s2p"
Z=50 Ohm Type=Touchstone

1 2

Term Ref Term

Term3 Term4
V_DC Num=3 Num=4
SRC2 Z=50 Ohm Z=50 Ohm
Vdc=VGG V

Electrical Model S- Parameter Model

Figure 4- 5 Simulation setup for the Electrical and S-Parameter model of NE3512S02.

The S-parameter model is suitable for high frequency applications [4] Figure
4- 5 shows the ADS simulation setup for the simulation of S-parameters of the
transistor using the two models. The simulation results are show in the Figure 4- 6.
From these results, we can conclude that the small-signal model is enough accurate to
be used when necessary. However, we can see that the S-parameters resulting from
these two models do not coincide. We also know that at high frequency, the
measured S-parameters model is better to be used that the lumped model. Along this
project we have mainly used the S-parameter model for the transistor.
S(3,3)
S(1,1)

S(4,4)
S(2,2)

freq (2.000GHz to 18.00GHz) freq (2.000GHz to 18.00GHz)

Input Reflection Coefficient Output Reflection Coefficient

S(4,3)
S(2,1)

S(3,4)
S(1,2)

freq (2.000GHz to 18.00GHz) freq (2.000GHz to 18.00GHz)

Forward Voltage Gain Reverse Voltage Gain

Figure 4- 6 S-Parameters are estimated using Electrical (Thick line) and S-Parameter model
(Thin line) at the Q-point (ID = 20 mA and VDS = 2 V).

42
4.5 Transistor Biasing Network Design
The purpose of a good dc bias design is to select the proper quiescent point
and hold the quiescent constant over the variation of transistor parameters and
temperature [5]. There are at least three ways to bias up a FET amplifier to get the
intended quiescent point. These are

4.5.1 Fixed-bias Configuration

The simplest of biasing arrangement for the FET is fixed-bias configuration
which is shown in Figure 4- 7. It has separate DC power supplies for the Gate and
Drain connections and ground the source. Grounding the source directly will provide
the most gain from the FET and this is a good concept if efficiency is a concern [7].
In order to prevent transient burn-out of the GaAs FET device during turn-on, the
gate voltage must be applied before drain voltage. If the drain is biased positive
before the gate, then transistor will operate momentarily beyond its safe operating
region. This type of configuration is suitable for low noise, high gain, high power and
high efficiency applications [6]. This bias network is used for the LNA design.

Figure 4- 7 Fixed-bias Configuration [7]

4.5.2 Self-bias Configuration

Self-bias network eliminates the need of two dc supplies. Figure 4- 8[7]
shows the self-bias configuration. A resistor of a strategic value is placed between the
source connection and ground. The resistor is bypassed with a capacitor so that the
FET source connection sees a zero Ω connection to ground at the operating
frequency. When drain current flows through the FET and then through the source
resistor, the source voltage rises above ground. The gate voltage is either held at a
fixed voltage or grounded, resulting in a fixed negative gate-source voltage. The
main disadvantages of this scheme are that amplifier efficiency is lost due to the
voltage drop of the source resistor. Also, the FET cannot be RF grounded at all
frequencies as well as if it was DC grounded with via holes, so gain and efficiency
can be degraded as a result. Self-bias networks are often used in LNA, but not power
amplifiers, for these two reasons [7].

43
 VDD
ID
R
R4
R=RD

L
L2

Vo

C
Vi C2
L +
C
C1 L1
VGS NEC_FET
-
Q2

R C
R3 R
R5 C3
R=RG
R=RS

Figure 4- 8 Self-bias Configuration [7]

4.5.3 Active-bias Network

Active bias network (Shown in Figure 4- 9) is another method of biasing a
FET. This type of network is usually preferred for large temperature change. Figure
4- 9 [8] shows the Active current mirror using a negative bias to supply a negative
voltage to the FET. The circuit keeps the drain current constant regardless to the
value of gm in the FET which falls over life and would under fixed bias cause the
drain current to fall [8].
+Vcc

R
R9
R=Rd
R
R10
R=R1
Vds
BJT_PNP
BJT1 Vo

R
R11 Vi
R=R2 NEC_FET
+ Q3
R
VGS
R7 -
R=R3

-Vee

Figure 4- 9 Active-bias Configuration [8].

4.6 Microstrip Foot-print

It is known that each microstrip component plays an important role in the RF
system design especially for the LNA design which is the vital part of the radio front-
end system. In ADS, the library component model use SMT pad for generating the
proper footprint in the layout level. But there are no effects in simulation with SMT
pad in the schematic level. So it is necessary to make layout component of foot-print
for individual component. The layout component of foot-print will add parasitic
effect in the SMT component model simulation and provides accurate result close to
real life component. Different layout components of foot-prints are generated using
ADS tool. At first a layout foot-print is design according to standard foot-print
specification. Then ADS Momentum simulation is performed for each foot-print.
Finally layout component of individual footprint is generated.

44
 TL6

Z0402
Z0402_1
TL4 TL5

Z0603 TL7
Z0603_1
NEC_FET_foot
NEC_FET_foot_1

Z0805
Z0805_1

Figure 4- 10 Layout component of footprint for the transistor (NE3512S02) and three types of
packages such as 0402, 0603 and 0805.

Figure 4- 10 shows the different layout component for the active and passive
components. All dimensions are specified according the given data sheet values.

4.7 Via Hole Model

We can not achieve ideal ground for the real-life circuit. There is always
some impedance in the ground. It is common practice to have RF ground through via.
The VIA must be closed to the component terminal. According to the ADS model
(Figure 4- 11(h)), via hole is considered as a cylindrical conductor that will add
additional inductance in the ground path [9]. Especially for the transistor’s common-
source grounding through via, we need to reduce inductance in the source terminal.
So if we can put multiple vias closely together then overall inductance will be less
than a single via. Layout component model of via could better option for accurate
simulations. Using the same way of foot-print layout generation, different layout
components of via models were designed as shown in Figure 4- 11 .

Z08
Z08_1
K17 Z12
ModelType=MW Z15
K17_1 Z12_2
Z15_1
ModelType=MW ModelType=MW
ModelType=MW
(a) One 0.4 mm via (b) Three 0.4 mm via (c) Six 0.4 mm via (d) One 0.4 mm via with
5 mm microstrip line

VIA2
Z11 V1
Z11_1
D=0.4 mm
Z16 Z14 ModelType=MW
H=0.254 mm
Z16_1 Z14_1 T=0.00375 mm
ModelType=MW ModelType=MW
(e) Two 0.4 mm via with (f) One 0.4 mm via with
5 mm microstrip line 1.6 mm microstrip line (g) One 0.2 mm via (h) ADS via model(0.4 mm)

Figure 4- 11 Different layout components of via hole model and ADS via model.

Simulation results of the layout via models are presented in Figure 4- 13.
These simulation results show that multiple (Figure 4- 13 (c) six 0.4 mm) via model
provides less reflection coefficient i.e. better grounding comparing to other models.

45
 Disp DisplayTemplate Z08 Term
Temp Term Term2
disptemp1 Term1 Z08_2
ModelType=MW Num=2
"S_Params_Quad_dB_Smith" Num=1
Z=50 Ohm
Z=50 Ohm
(a) One 0.4 mm via

S-PARAMETERS
S_Param
SP1
Start=0 GHz Term
Term K17 Term4
Stop=18 GHz Term3 K17_2 Num=4
Step=0.1 GHz Num=3 ModelType=MW Z=50 Ohm
Z=50 Ohm
(b) Three 0.4 mm via

TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
Term Z12 Term
Term5 Z12_1 Term6
Num=5 ModelType=MW Num=6
Z=50 Ohm Z=50 Ohm
(c) Six 0.4 mm via

Figure 4- 12 ADS set-up for via simulation.

m1 m2 m3
freq=9.000GHz freq= 9.000GHz freq= 9.000GHz
S(1,1)=0.971 / 167.769 S(3,3)=0.981 / 171.026 S(5,5)=0.987 / 173.531
impedance = Z0 * (0.015 + j0.107) impedance = Z0 * (0.010 + j0.078) impedance = Z0 * (0.006 + j0.057)

m1
m2
m3
S(1,1)

S(3,3)

S(5,5)

freq (0.0000Hz to 18.00GHz) freq (0.0000Hz to 18.00GHz) freq (0.0000Hz to 18.00GHz)

(a) (b) (c)

Figure 4- 13 Reflection coefficients for different via models.

4.8 Broadband Chip Capacitor Selection

General description of the capacitor is given in the RF passive components
section. Selection criteria of chip capacitors for the RF broadband applications e.g.
bypassing FET source, DC blocking and coupling are discussed in this subsection. In
order to get the proper chip capacitor for the design, it is necessary to consider the
overall performances of the circuit. Typical requirements for selecting a chip
capacitor for the wireless applications are [10]:
• Capacitance (pF)
• Tolerance (%)
• Equivalent series resistance (ESR)
• Series resonant frequency(Fsr)
• Parallel resonant frequency(Fpr)
• Temperature coefficient(TC, PPM/0C)
• Tolerance (%)
• Voltage Rating (WVDDC, VRMS)

46
• Equivalent Series Resistance (ESR)
1
An ideal capacitor stores all of its energy in the dielectric, as CV 2 . It is
2
known from previous discussion that a real capacitor always shows series resistance.
This resistance is called equivalent series resistance (ESR). ESR contributes mainly
dielectric and metal losses of a capacitor. These losses at the higher frequencies
become more significant because of skin effect and increase proportionally as the
square root of frequency. We can calculate the ESR value at the desired frequency
f desired
from the specified frequency by ESRdesired = ESRspecified . The power loss of a
f specified
capacitor is P = I 2 ESR [10].

• Quality Factor (Q)

This is a figure of merit and is a measure of a capacitor’s ability to store
X
energy. Since Q = c , low ESR yields high Q. As with ESR, the Q must be
ESR
specified at the design frequency [10].

• Dissipation Factor (DF)

This is also referred to as the loss tangent is the reciprocal of Q. the tangent of
the loss is equal to the dissipation factor and indicates what portion of the total
reactive power in the capacitor will be lost as heat i.e. dissipation loss.
DF = tan θ loss _ angle .

• Series Resonant Frequency (Fsr)

Capacitor’s series resonance frequency also referred to as self-resonance. At
this frequency the capacitor’s net reactance is zero and the impedance is equal to
ESR. Figure 4- 14 shows the comparison of a 100 pF ATC capacitor model with the
ideal capacitor. Marker indicate the series resonance frequency, Fsr and provide
lowest impedance path making it an ideal coupling element at 1 GHz. Net impedance
below the Fsr is capacitive and above the Fsr is inductive[11].

47
 14

12

10

Impedance (Ohm)
8

2
m1
0
0 1 2 3 4
Frequency (GHz)

Figure 4- 14 Impedance vs Frequency. Solid line represents for ATC100A101 (100pF) and dot
line for ideal 100 pF capacitor [11] .

• Parallel Resonant Frequency (Fpr)

Figure 4- 15 shows the insertion loss of ATC100A101 (100 pF) capacitor.
Parallel resonance frequency is observed as a sharp attenuation in the S21 magnitude
in the Figure 4- 15. It is important to see one or more parallel resonant falling within
the operating passband. If a parallel resonance does fall within the operating band it
will be necessary to evaluate its depth in order to determine whether or not the loss is
acceptable. An insertion loss of several tenths of a dB is generally acceptable
criterion for most coupling applications.
0

-10
Magnitude dB(S(21))

-20

-30

-40

-50

-60
0 2 4 6 8 10 12 14 16 18

Frequency (GHz)

Figure 4- 15 Insertion loss (S21) of ATC100A101 (100 pF) capacitor [11].

4.9 ADS Capacitor Model

Selecting a capacitor is a big issue for broadband applications like in UWB
LNA design. There are several physical models of SMT capacitors in ADS library
component. The SMT capacitor represents an equivalent circuit model embedded
within the netlist of the schematic design and different companies use unique model
for their components. Using different model gives different results. Moreover
component availability was another issue for the LNA implementation. Since
capacitors from the Kemet manufacturer were available, so it is good to use Kemet

48
SMT capacitor model for the LNA design. Some of the capacitors models are given
below.
• Kemet Ceramic SMT Capacitor Model

Figure 4- 16 Kemet COG ceramic capacitor model schematic [12].

Figure 4- 17 Kemet X7R ceramic capacitor model schematic [12].

• Murata Monolithic ceramic SMT Capacitor Model

Figure 4- 18 Murata Monolithic ceramic SMT Capacitor model [12].

• ATC SMT Capacitor Model

Figure 4- 19 CAPP2 (Chip capacitor) model for ATC [12].

• Philips Measurement-Based CMC Capacitor Model

This capacitor model is different from the other model. This capacitor is not
represented by an equivalent circuit like other models. This capacitor is based on
actual frequency dependent S-parameter files [12].

49
 From above SMT capacitor models it is clear that overall frequency responses
will vary from each other. Figure 4- 20 shows an example of 1 pF capacitor’s
property for varies SMT capacitor models. The insertion losses are not same for all
models.
10
Forward Transmission (dB)

ATC
-10

-20
Murata Kemet
-30
Philips
-40
0 2 4 6 8 10 12 14 16 18
Frequency (GHz)
Figure 4- 20 Forward transmission vs frequency characteristics for 1 pF capacitor dofferent
companies such as Kemet, ATC, Philips and Murata.

4.10 DC Blocking and Decoupling

In the microwave amplifier design, RF signal coexist with the DC signal
which gives power to the active device. So it is necessary to separate these two types
of signal for the proper circuit operation. Refereeing to Figure 4- 7, DC blocking
capacitor Ci and Co are simple capacitors that have a low series reactance at the RF
frequency and act like an open circuit for the DC signal. Decoupling capacitor, C will
suppress the power supply noise. RF choke L will allow the DC signal for biasing the
active device. In the same time RF choke will prevent the RF signal to mix with DC
signal. At the higher frequency ideal RF choke will not give the proper bandwidth
and microstrip quarter-wave transmission lines are better solution [13]. Microstrip RF
choke will discuss in later.

4.10.1 DC Blocking Capacitor Selection

Impedance and forward transmission behaviors of Kemet capacitor model for
different values are shown in Figure 4- 21. Solid line shows sharp insertion loss in
the lower band. So Kemet 10 pF capacitor model could be used for the DC blocking
purpose in the RF input and output port.

50
 0

-5
Forward Transmission (dB)

1 pF
-10

2.7 pF
-15

-20
10 pF
-25

-30
0 2 4 6 8 10 12 14 16 18
Frequency (GHz)

Figure 4- 21 Forward Transmission vs Frequency characteristic of Kemet capacitor model with

different values.

4.10.2 Decoupling Capacitor Selection

Broadband bypassing is a critical design matter that needs careful attention.
Multiple capacitor approach gives more efficient solution for wider frequency
spectrum [11]. In this design there are four decoupling capacitors C1 through C4 are
chosen to obtain low impedance path to ground. C1 will suppress in-band 6-9 GHz
carrier frequency from appearing on the DC supply and its Fsr is close to amplifier s
operating frequency. And C2 through C4 capacitor will suppress the RF energy at the
frequency below the operating frequency. Figure 4- 22 shows the forward
transmission behavior for the C1 through C4 decoupling capacitors. Four different
capacitor values are 10 pF, 100 pF, 220 pF and 100 nF respectively.
0
Forward Transmission (dB)

C2
C1
-10 C3

C4
-20

-30

-40
0 2 4 6 8 10 12 14 16 18
Frequency (GHz)

Figure 4- 22 Forward Transmission vs Frequency for Bypassing Kemet capacitor model. Thick
line for C1 and thin line for C2 to C4

51
4.11 Microstrip RF Choke
Figure 4- 23 shows the microstrip RF choke that consists of three parts such
as quarter wavelength transformer (L1), open circuited stub (L2) and an arbitrary
length (L3). Open circuited stub could be made by different microstrip elements.
Third butterfly stub is used to design the RF choke which gives broader bandwidth
compare to microstrip stub.

Figure 4- 23 Three types of RF choke [13].

Theoretically a RF choke provides a low loss RF path from port1 to port2 and
an infinite impedance towards port 3 i.e. DC bias port. At the centre frequency open-
circuited (L2) stub provides RF short at point B. The quarter wavelength transmission
line (L1) transforms the RF short at point B to RF open i.e. infinite impedance at
junction point A [13].

4.11.1 RF Choke Design and Simulation

The simulation setup of the three type’s microstrip RF choke is given below.
The simulation results of forward transmission between port one and two are given in
Figure 4- 27. From these simulation results it is clear that butterfly RF choke gives
wider bandwidth than others chokes. Transmission line width (W) is 0.524 mm is
defined by 50 Ω at 7.5 GHz, quarter wave length (L1) is 5.22 mm at 8.5 GHz and
radial angle is 78 degree is used throughout the design.

52
 S-PARAMETERS Term
MSub Term3
S_Param MLIN Num=3
MSUB Z=50 Ohm
SP1 TL289
MSub1
Start=0 GHz Subst="MSub1"
H=0.254 mm
Stop=12 GHz W=0.524 mm
Er=3.66
Mur=1 Step=0.1 GHz L=5 mm
Cond=5.8e7
Hu=1.0e+033 mm MTEE_ADS
T=0.035 mm Tee34
TanD=0.0037 Subst="MSub1"
Rough=0.001 mm N W1=0.524 mm
MLOC
W2=0.524 mm
Zin TL298
W3=0.524 mm MLIN
Zin Subst="MSub1"
Zin1 TL294 W=0.524 mm
Zin1=zin(S11,PortZ1) Subst="MSub1" L=5.22 mm
W=0.524 mm
TechInclude_NEC_ACTIVELIBRARY
L=5.22 mm
NEC_ACTIVELIBRARY_Lib
File=Nominal

Term MLIN MTEE_ADS MLIN Term

Term1 TL295 Tee33 TL296 Term2
Num=1 Subst="MSub1" Subst="MSub1" Subst="MSub1" Num=2
Z=50 Ohm W=0.524 mm W1=0.524 mm W=0.524 mm Z=50 Ohm
L=1 mm W2=0.524 mm L=1 mm
W3=0.524 mm

Figure 4- 24 ADS set-up for RF choke using quarter wave stub.

S-PARAMETERS Term
MSub MLIN
Term3
TL289
S_Param Num=3
MSUB Subst="MSub1"
SP1 W=0.524 mm Z=50 Ohm
MSub1
H=0.254 mm Start=0 GHz L=5 mm
Er=3.66 Stop=12 GHz
Mur=1 Step=0.1 GHz MTEE_ADS
Cond=5.8e7 Tee34
Subst="MSub1"
Hu=1.0e+033 mm
W1=0.524 mm
T=0.035 mm
N W2=0.524 mm MRSTUB
TanD=0.0037
Rough=0.001 mm W3=0.524 mm Stub3
Zin
MLIN Subst="MSub1"
Zin TL294 Wi=0.524 mm
Zin1 Subst="MSub1" L=4 mm
Zin1=zin(S11,PortZ1) W=0.524 mm Angle=78
L=5.22 mm
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal

MLIN MTEE_ADS MLIN

Term Term
TL295 Tee33 TL296
Term1 Term2
Subst="MSub1" Subst="MSub1" Subst="MSub1"
Num=1 Num=2
W=0.524 mm W1=0.524 mm W=0.524 mm
Z=50 Ohm Z=50 Ohm
L=1 mm W2=0.524 mm L=1 mm
W3=0.524 mm

Figure 4- 25 RF choke using radial stub.

MSub S-PARAMETERS Term

Term3
MSUB S_Param Num=3
MSub1 SP1 MLIN MCROSO Z=50 Ohm
H=0.254 mm Start=0 GHz TL289 Cros1
Er=3.66 Stop=12 GHz Subst="MSub1" Subst="MSub1"
Mur=1 Step=0.1 GHz W=0.524 mm W1=0.524 mm
Cond=5.8e7 L=5 mm W2=0.524 mm
Hu=1.0e+033 mm W3=0.524 mm
T=0.035 mm W4=0.524 mm
TanD=0.0037 N
Rough=0.001 mm Zin

Zin MRSTUB MRSTUB

Zin1 MLIN
Stub4 Stub3
Zin1=zin(S11,PortZ1) TL294
Subst="MSub1" Subst="MSub1"
Subst="MSub1"
Wi=0.524 mm Wi=0.524 mm
L=4 mm W=0.524 mm L=4 mm
L=5.22 mm
TechInclude_NEC_ACTIVELIBRARY Angle=78 Angle=78
NEC_ACTIVELIBRARY_Lib
File=Nominal

MLIN MTEE_ADS MLIN

Term Term
TL295 Tee33 TL296
Term1 Term2
Subst="MSub1" Subst="MSub1" Subst="MSub1"
Num=1 Num=2
W=0.524 mm W1=0.524 mm W=0.524 mm
Z=50 Ohm Z=50 Ohm
L=1 mm W2=0.524 mm L=1 mm
W3=0.524 mm

Figure 4- 26 RF choke using butterfly stub.

But in the practical circuit the DC line (port 3) is not 50 Ω terminated. But for
butterfly RF choke there is less effect on termination at port3. Butterfly choke is
simulated with different values such as 5 Ω, 10 Ω, 20 Ω, and 50 Ω termination at the
port 3 and simulation results are given in Figure 4- 28.

53
 0

Forward Transmission dB(S(2,1))

-5
Stub
-10
Radial stub

Butterfly stub
-15

-20
0 2 4 6 8 10 12

Frequency GHz

Figure 4- 27 Forward transmission vs frequency characteristics of different types of RF chokes

(Thick line for Butterfly, Thin line for quarter wave line and Das line for radial).

0
Forward Transmission dB(S(2,1))

-5

-10

-15

-20
0 2 4 6 8 10 12

Frequency GHz

Figure 4- 28 Forward transmission vs frequency with different terminated values in port 3 (Das
line for 5 ohm, star line for 10 ohm thin line for 20 ohm and thick line for 50 ohm).

4.11.2 RF Choke with Bias Arrangement

After seeing the termination condition at port 3 (DC line), it was necessary to
see the parasitic effects of capacitor in this RF choke. So all bypass capacitors with
their footprint layouts are added and simulated. Figure 4- 29 shows the complete
schematic of RF choke with bypass capacitor arrangement. The impedance at port 3
is more close to RF short than a 50 Ω (Port 1 and 2). Among the three types of RF
choke, the butterfly stub is most robust with any termination at port 3 [13]. Figure 4-
30 shows the optimized simulation results. RF choke gives good forward
transmission between port 1 and 2 and high impedance towards port 3. This RF
choke has designed at the higher band frequency (8.5 GHz) instead of center
frequency (7.5 GHz)

54
 Term
MLIN
TL289 Term3
Num=3
Subst="MSub1"
Z=50 Ohm
W=0.524 mm
L=2 mm

sc_kmt_X7R_08055_M_19960828 MTEE_ADS
C27 Tee32
PART_NUM=C0805C104M5R 100nF Subst="MSub1"
Vtest=1 W1=0.524 mm
Temperature=25 W2=0.524 mm
Z0805 SMT_Pad
SMT_Pad="Pad2" MLIN
W3=0.524 mm
Z0805_1
TL292
ModelType=MW SMT_Pad
Subst="MSub1"
W=0.524 mm Pad1
L=2 mm W=0.8 mm
MTEE_ADS L=0.3 mm
sc_kmt_C0G_06035_J_19960828
Tee31 PadLayer="bond"
C25
Subst="MSub1" SMO=0.12 mm
PART_NUM=C0603C221J5G 220pF
Temperature=25 W1=0.524 mm SM_Layer="solder_mask"
Z0603 W2=0.524 mm PO=-0.15 mm
SMT_Pad="Pad1"
Z0603_2 MLIN
W3=0.524 mm
ModelType=MW TL291
Subst="MSub1"
W=0.524 mm
L=2 mm
MTEE_ADS
Tee30 SMT_Pad
sc_kmt_C0G_06035_J_19960828 Subst="MSub1"
C13
W1=0.524 mm
PART_NUM=C0603C101J5G 100pF Z0603 W2=0.524 mm SMT_Pad
Temperature=25 MLIN Pad2
Z0603_4 W3=0.524 mm
SMT_Pad="Pad1" TL290 W=1.22 mm
ModelType=MW
Subst="MSub1" L=0.457 mm
W=0.524 mm PadLayer="bond"
L=2 mm SMO=0.12 mm
MTEE_ADS SM_Layer="solder_mask"
Tee29 PO=-0.23 mm
Subst="MSub1"
sc_kmt_C0G_06035_D_19960828 W1=0.524 mm
C24 Z0603 W2=0.524 mm
PART_NUM=C0603C100D5G 10pF Z0603_5 W3=0.524 mm
Temperature=25 N
ModelType=MW
SMT_Pad="Pad1" Zin

MLIN Zin
MSub TL288 Zin1
Subst="MSub1" Zin1=zin(S11,PortZ1)
MSUB W=0.524 mm
MSub1 L=2 mm
H=0.254 mm
Er=3.66 sr_ims_RC-I_0603_G_19950814 Z0603
Mur=1
R2 Z0603_3
Cond=5.8e7 PART_NUM=RC-I-0603-43R0-G 43 Ohm ModelType=MW
Hu=1.0e+033 mm
SMT_Pad="Pad1"
T=0.035 mm
TanD=0.0037
Rough=0.001 mm
MCROSO
Cros1
S-PARAMETERS
Subst="MSub1"
W1=0.524 mm
S_Param
W2=0.524 mm
SP1
W3=0.524 mm
Start=1 GHz
W4=0.524 mm
Stop=12 GHz
Step=0.1 GHz

MRSTUB MRSTUB
Stub2 MLIN Stub3
Subst="MSub1" TL294 Subst="MSub1"
Wi=0.524 mm Subst="MSub1" Wi=0.524 mm
L=4 mm W=0.524 mm L=4 mm
TechInclude_NEC_ACTIVELIBRARY Angle=78 L=5.22 mm Angle=78
NEC_ACTIVELIBRARY_Lib
File=Nominal

MLIN MTEE_ADS MLIN

Term Term
TL295 Tee33 TL296
Term1 Term2
Subst="MSub1" Subst="MSub1" Subst="MSub1"
Num=1 Num=2
W=0.524 mm W1=0.524 mm W=0.524 mm
Z=50 Ohm Z=50 Ohm
L=1 mm W2=0.524 mm L=1 mm
W3=0.524 mm

Figure 4- 29 Complete Schematic of RF choke with bias arrangement.

0 -20
F o rw a r d T ra n s m is s io n d B (S ( 2 ,1 ))

F o rw a r d T ra n s m is s io n d B (S ( 3 ,1 ))

-30
-5
-40

-50
-10

-60

-15
-70

-80
-20
-90

-25 -100
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12

Frequency GHz Frequency GHz

(a) (b)

Figure 4- 30 Forward transmission vs frequency characteristic for the schematic of Figure 4- 29.

4.12 LNA design

Primarily S-parameter model of selected transistor (NE3512S02) is going to
use throughout the LNA. After getting the LNA layout with proper input and output
matching network, we will use lumped elements model of the transistor. Using the
fixed-bias network, the transistor’s operating bias point is already adjusted in the
previous section as I D = 20 mA, VGS = −0.17 V and VDS = 2 V. It is needed to see
the Rollett factor or stability factor of the model either stable or unstable within the
operating frequency. From the simulation result it is clear that it is necessary to
increase the stability factor within the operating frequency. So stabilization
techniques are used to get stable operation within the bandwidth (6-9 GHz). Figure 4-

55
33(a) and (b) shows the gain and noise figure (star line) respectively before
stabilization.
S2P
S-PARAMETERS SNP1
File="NE3512S02v2_2-18_2_20.s2p"
S_Param
SP1
Start=4 GHz 1 2

Term Ref Term

Stop=10 GHz
Term1 Term2
Step=0.1 GHz
Num=1 Num=2
CalcNoise=yes
Z=Z0 Z=Z0

OPTIONS
Options
Options1
Temp=16.85
Tnom=25 Meas MeasEqn
N Eqn
meas1
Zin

TechInclude_NEC_ACTIVELIBRARY Zin Var VAR

Eqn
NEC_ACTIVELIBRARY_Lib Zin1 VAR1
File=Nominal Zin1=zin(S11,PortZ1) Z0=50

Figure 4- 31 Schematic of the NE3512S02 S-parameter model before stabilization.

2.0
Stability Factor K

1.5

1.0

0.5

0.0
4 5 6 7 8 9 10
Frequency GHz
Figure 4- 32 Stability factor vs frequency before stabilization.
Actual noise figure
20 1.0
Power Gain dB(S(2,1))

Noise Figure dB

18 0.8
16 Minimum noise figure
0.6
14
0.4
12

10 0.2
4 5 6 7 8 9 10 4 5 6 7 8 9 10
Frequency GHz Frequency GHz
(a) (b)

Figure 4- 33 Power gain and noise figure before stabilization.

The transistor is stabilized by adding a series resistor at the output. Figure 4- 34

shows the DC annotation after stabilize the transistor.

56
 3-20.3
V mA
3V
V_DC 20.3 mA I_Probe
SRC1 IDS MLIN
Vdc =VDS V TL289
Subst="MSub1"
W=0.524 mm
L=2 mm
3.00
20.3 VmA
-20.3 mA
sc _kmt_X7R_08055_M_19960828 MT EE_ADS
C27 Tee32
PART _NUM=C0805C104M5R 100nF Subst="MSub1"
Vtest=1 -30.0 nA 30.0
63.3 nA
aA W1=0.524 mm
Temperature=25 W2=0.524 mm
Z0805
SMT_Pad="Pad2" MLIN
W3=0.524 mm
Z0805_1 -20.3 mA
TL292
ModelType=MW
Subst="MSub1"
W=0.524 mm
20.3 mA
L=2 mm
sc_kmt_C0G_06035_J_19960828 MT EE_ADS
-20.3 mA
C25 Tee31
PART_NUM=C0603C221J5G 220pF Subst="MSub1"
-30.0 nA 30.0
20.0 nA
aA W1=0.524 mm
Temperature=25
Z0603 W2=0.524 mm
SMT _Pad="Pad1"
Z0603_2 MLIN
W3=0.524
-20.3 mA mm
ModelType=MW TL291
Subst="MSub1"
W=0.524 mm
20.3
L=2mAmm
MT EE_ADS
-20.3 mA
Tee30
s c_kmt_C0G_06035_J _19960828
Subst="MSub1"
C13 -30.0 nA 30.0
20.0 nA
aA W1=0.524 mm
PART _NUM=C0603C101J 5G 100pF
Z0603 W2=0.524 mm
T emperature=25 MLIN
Z0603_4 W3=0.524
-20.3 mA mm
SMT_Pad="Pad1" TL290
ModelType=MW
Subst="MSub1"
W=0.524 mm
20.3
L=2mA
mm
MT EE_ADS
-20.3 mA
Tee29
Subst="MSub1"
s c_kmt_C0G_06035_D_19960828 -30.0 nA 30.0
20.0 nA
aA W1=0.524 mm
C24 Z0603 W2=0.524 mm
PART _NUM=C0603C100D5G 10pF Z0603_5 W3=0.524 mm
-20.3 mA
OPTIONS T emperature=25 ModelType=MW 3.00 V
SMT_Pad SMT_Pad="Pad1"
Options 20.3 mA

T echInclude_NEC_ACTIVELIBRARYOptions1 SMT_Pad MLIN

T emp=16.85 Pad1 TL288
NEC_ACT IVELIBRARY_Lib
T nom=25 W=0.8 mm Subst="MSub1"
File=Nominal
L=0.3 mm W=0.524 mm
PadLayer="bond" L=2 mm
VAR SMO=0.12 mm 3.00 V
Var Meas MeasEqn 20.3 aA
20.1 mA
N Eqn
VAR1
Eqn
SM_Layer="solder_mas k"
meas1 sr_ims _RC-I_0603_G_19950814 Z0603
Zin Z0=50 PO=-0.15 mm
R2 Z0603_10
Zin PART _NUM=RC-I-0603-43R0-G 43 Ohm ModelType=MW
MSub
Zin1 SMT_Pad="Pad1"
Zin1=zin(S11,PortZ1) MSUB SMT_Pad
DC
MSub1
H=0.254 mm MCROSO
SMT_Pad DC Cros1
S-PARAMETERS Er=3.66 2.13 V
Pad2 DC1 Subst="MSub1"
Mur=1
S_Param W=1.22 mm SweepVar="VDS" W1=0.524 mm
Cond=5.8e7 L=0.457 mm
SP1 Start=0 W2=0.524 mm
Hu=1.0e+033 mm PadLayer="bond" 20.3 mA
Start=4 GHz Var
Stop=3 W3=0.524 mm
VAR T=0.035 mm SMO=0.12 mm
Stop=10 GHz
Eqn Step=0.1 W4=0.524 mm
VAR4 TanD=0.0037
SM_Layer="solder_mas k"
Step=0.1 GHz VDS=3 Rough=0.001 mm 2.13 V 2.13 V
PO=-0.23 mm
Calc Nois e=yes VGS=-0.17 1890fAA 0 A 189 fA
MRST UB 2.13 V MRSTUB
Stub2 -20.3
MLINmA Stub3
Subs t="MSub1" TL294 Subs t="MSub1"
Wi=0.524 mm Subst="MSub1" Wi=0.524 mm
MT EE_ADS L=4 mm W=0.524 mm L=4 mm
Tee34 Angle=78 L=5.22 mm Angl e=78
sc_kmt_C0G_06035_D_19960828 sc_kmt_C0G_06035_D_19960828
C36 Subst="MSub1" sr_i ms_RC-I_0603_G_19950814 -20.3VmA
2.13 C37
PART_NUM=C0603C100D5G 10pF W1=0.524 mm R1 PART_NUM=C0603C100D5G 10pF
20.3 mA 20.3 mA
Temperature=25 W2=0.524 mm PART_NUM=RC-I-0603-3R90-G 3.9 Ohm Temperature=25
SMT _Pad="Pad1" W3=0.524 mm SMT _Pad="Pad1" SMT _Pad="Pad1"
-85.0 nV -170 mV -170 mV -170 mV -170 mV -170 mV 2.05 V 2.05 V 2.05 V 2.13 V 2.13 V 2.13 V 2.13 V 1.06 uV
1.70 nA 0A 1.70
-1.70nAnA 1.70 nA -25.2pA
25.0 pA -25.2 pA -20.3 mA 11.3mA
-20.3 aA -20.3 mA -20.3 mA -21.3 nA
21.3 nA 14.2 aA 21.3 nA
-21.3 nA
Z25_Mline MLIN Z25_Mline MLIN MTEE_ADS MLIN Z25_Mline
MLIN
-85.0 nV Z25_Mline_2 Z0603 T L297 Z25_Mline_1 Z0402 Tee33 TL296 Z0603 Z25_Mline_3 1.06 uV
TL298 TL295
Model Type=MW Z0603_1 Subst="MSub1" -1.73mV
nA -20.3 mA
NEC_FET ModelType=MW Z0402_1 Subst="MSub1" Subs t="MSub1" Subst="MSub1" Z0603_12 ModelT ype=MW
-170 Subs t="MSub1"
-1.70 nA Model Type=MW W=0.524 mm Q1 ModelType=MW W=0.524 mm W1=0.524 mm W=0.524 mm Model Type=MW
T erm 1.73 nA W=0.524 mm
W2=0.524 mm L=1 mm 21.3 nA
T erm1
L=1 mm
MLIN L=1 mm zzzzzzzzpartName=NE3512S02_v118 L=1 mm
W3=0.524 mm T erm
Num=1 TL304 zzzzzzzz_1
T erm2
Z=Z0 Subst="MSub1" ModelType=MW
Num=2
W=0.524 mm Z=Z0
L=5.22
1.73
-170 nA mm
mV

-170 mV -170 mV
0A
-15.1 fA -114 fA fA
-15.1
MRSTUB MCROSO MRSTUB
Stub4 Cros2nA
-1.73 Stub5
Subst="MSub1" Subst="MSub1" Subst="MSub1"
Wi=0.524 mm W1=0.524 mm Wi =0.524 mm
-170 mV
L=4 mm W2=0.524 mm L=4 mm
Angle=78 W3=0.524 mm Angle=78
W4=0.524 mm
-1.14 aA
sr_ims_RC-I_0603_G_19950814
Z0603 R3
Z0603_11 PART_NUM=RC-I-0603-10R0-G 10 Ohm
Model Type=MW SMT _Pad="Pad1"

-170
-1.73mV
nA
MLIN
TL300
Subst="MSub1"
W=0.524 mm
L=2 mm
-1.73 nA
-170 mV
1.73 nA
MTEE_ADS sc_kmt_C0G_06035_D_19960828
Tee37 C28
Subs t="MSub1" PART_NUM=C0603C100D5G 10pF
1.70 nA -1.70
-1.13 nA
aA W1=0.524 mm Temperature=25
3.43 nA SMT_Pad="Pad1"
Z0603 W2=0.524 mm
Z0603_7 MLIN
W3=0.524
-3.43 nA mm
ModelT ype=MW TL302
Subst="MSub1"
W=0.524 mm
3.43
L=2nAmm
MTEE_ADS s c_kmt_C0G_06035_J _19960828
Tee36 C29
Subs t="MSub1" PART _NUM=C0603C101J 5G 100pF
1.70 nA -1.70
-1.13 nA
aA W1=0.524 mm T emperature=25
5.13 nA SMT_Pad="Pad1"
Z0603 W2=0.524 mm
Z0603_6 MLIN
W3=0.524 mm
-5.13 nA
ModelT ype=MW TL303
Subst="MSub1"
W=0.524 mm
5.13 nA
L=2 mm
MTEE_ADS sc_kmt_C0G_06035_J_19960828
Tee38 C30
Subs t="MSub1" PART_NUM=C0603C221J5G 220pF
1.70 nA -1.70
-1.13 nA
aA W1=0.524 mm
6.83 nA Temperature=25
Z0603 W2=0.524 mm
SMT _Pad="Pad1"
Z0603_8 MLIN
W3=0.524
-6.83 nA mm
ModelT ype=MW TL301
Subst="MSub1"
W=0.524 mm
6.83
L=2nAmm
MTEE_ADS s c_kmt_X7R_08055_M_19960828
Tee35 C31
Subs t="MSub1" PART _NUM=C0805C104M5R 100nF
1.70 nA -1.70
-3.59 nA
aA W1=0.524 mm Vtest=1
W2=0.524 mm T emperature=25
Z0805 -170 mV
8.53 nA
W3=0.524 mm SMT_Pad="Pad2"
Z0805_2 -8.53 nA
ModelT ype=MW MLIN
TL299
Subst="MSub1"
W=0.524 mm
L=2 mm
8.53 mV
-170 nA
V_DC
SRC2
Vdc =VGS V

Figure 4- 34 Annotation of DC simulation of stabilized FET (Electrical model) fixed bias

(IDS=20 mA and VDS=2V, VGS=-0.17V) circuit without matching network.

Figure 4- 35 shows the schematic of stabilized LNA with S-parameter model.

From the stability factor (Figure 4- 36) it is clear that the transistor is unconditionally
stable within the bandwidth. But this condition is achieved with the expense of gain
and noise (Figure 4- 37(a) and (b)). Once the transistor is stabilized, the next step is
to design proper matching network for the LNA.

57
 V_DC I_Probe
SRC1 IDS MLIN
Vdc=VDS V T L289
Subst="MSub1"
W=0.524 mm
L=2 mm

sc_kmt_X7R_08055_M_19960828 MTEE_ADS
C27 T ee32
PART _NUM=C0805C104M5R 100nF Subst="MSub1"
Vtest=1 W1=0.524 mm
Temperature=25 W2=0.524 mm
Z0805
SMT_Pad="Pad2" MLIN
W3=0.524 mm
Z0805_1
T L292
ModelType=MW
Subst="MSub1"
W=0.524 mm
L=2 mm
sc_kmt_C0G_06035_J_19960828 MTEE_ADS
C25 T ee31
PART_NUM=C0603C221J5G 220pF Subst="MSub1"
W1=0.524 mm
T emperature=25
Z0603 W2=0.524 mm
SMT _Pad="Pad1"
Z0603_2 MLIN
W3=0.524 mm
ModelType=MW T L291
Subst="MSub1"
W=0.524 mm
L=2 mm
MTEE_ADS
T ee30
sc_kmt_C0G_06035_J_19960828
Subst="MSub1"
C13
W1=0.524 mm
PART _NUM=C0603C101J5G 100pF
Z0603 W2=0.524 mm
Temperature=25 MLIN
Z0603_4 W3=0.524 mm
SMT_Pad="Pad1" T L290
ModelType=MW
Subst="MSub1"
W=0.524 mm
L=2 mm
MTEE_ADS
T ee29
Subst="MSub1"
sc_kmt_C0G_06035_D_19960828 W1=0.524 mm
C24 Z0603 W2=0.524 mm
PART _NUM=C0603C100D5G 10pF Z0603_5 W3=0.524 mm
OPTIONS Temperature=25 ModelType=MW
SMT_Pad SMT_Pad="Pad1"
Opti ons
TechInclude_NEC_ACT IVELIBRARYOpti ons1 SMT_Pad MLIN
Temp=16.85 Pad1 T L288
NEC_ACTIVELIBRARY_Lib
Tnom=25 W=0.8 mm Subst="MSub1"
File=Nomi nal
L=0.3 mm W=0.524 mm
PadLayer="bond" L=2 mm
Var VAR Meas MeasEqn SMO=0.12 mm
N Eqn
VAR1 Eqn
SM_Layer="solder_mask"
meas1 sr_ims_RC-I_0603_G_19950814 Z0603
Zin Z0=50 PO=-0.15 mm
R2 Z0603_10
Zin PART _NUM=RC-I-0603-43R0-G 43 Ohm Model Type=MW
MSub
Zin1 SMT_Pad="Pad1"
Zin1=zin(S11,PortZ1) MSUB SMT_Pad
MSub1
H=0.254 mm MCROSO
SMT_Pad Cros1
Er=3.66
S-PARAMETERS Pad2 Subst="MSub1"
Mur=1
S_Param W=1.22 mm W1=0.524 mm
Cond=5.8e7 L=0.457 mm
SP1 Hu=1.0e+033 mm W2=0.524 mm
PadLayer="bond"
Start=4 GHz Var VAR T=0.035 mm W3=0.524 mm
Eqn SMO=0.12 mm
Stop=10 GHz VAR4 TanD=0.0037 W4=0.524 mm
SM_Layer="solder_mask"
Step=0.1 GHz VDS=3 Rough=0.001 mm
PO=-0.23 mm
Cal cNoise=yes VGS=-0.17
MRSTUB MRSTUB
Stub2 MLIN Stub3
Subst="MSub1" T L294 Subst="MSub1"
Wi =0.524 mm Subst="MSub1" Wi=0.524 mm
MTEE_ADS L=4 mm W=0.524 mm L=4 mm
T ee34 Angl e=78 L=5.22 mm Angl e=78
sc_kmt_C0G_06035_D_19960828 sc_kmt_C0G_06035_D_19960828
C36 Subst="MSub1" S2P sr_ims_RC-I_0603_G_19950814 C37
PART_NUM=C0603C100D5G 10pF W1=0.524 mm SNP1 R1 PART _NUM=C0603C100D5G 10pF
T emperature=25 W2=0.524 mm Fil e="NE3512S02v2_2-18_2_20.s2p" PART _NUM=RC-I-0603-3R90-G 3.9 Ohm Temperature=25
SMT _Pad="Pad1" W3=0.524 mm SMT_Pad="Pad1" SMT_Pad="Pad1"

1 2

Z25_Ml ine MLIN

Ref
Z25_Mli ne MLIN MT EE_ADS MLIN Z25_Ml ine
MLIN
Z25_Ml ine_2 Z0603 TL297 Z25_Mli ne_1 Z0402 Tee33 TL296 Z0603 Z25_Ml ine_3
T L298 T L295
ModelT ype=MW Z0603_1 Subst="MSub1" Model Type=MW Z0402_1 Subst="MSub1" Subst="MSub1" Subst="MSub1" Z0603_12 Model Type=MW
Subst="MSub1"
ModelType=MW W=0.524 mm Model Type=MW W=0.524 mm W1=0.524 mm W=0.524 mm Model Type=MW
Term W=0.524 mm
L=1 mm L=1 mm W2=0.524 mm L=1 mm
Term1 MLIN L=1 mm zzzzzzzz
W3=0.524 mm T erm
Num=1 TL304 zzzzzzzz_1
T erm2
Z=Z0 Subst="MSub1" ModelT ype=MW
Num=2
W=0.524 mm Z=Z0
L=5.22 mm

MRST UB MCROSO MRST UB

Stub4 Cros2 Stub5
Subst="MSub1" Subst="MSub1" Subst="MSub1"
Wi=0.524 mm W1=0.524 mm Wi=0.524 mm
L=4 mm W2=0.524 mm L=4 mm
Angle=78 W3=0.524 mm Angle=78
W4=0.524 mm

sr_ims_RC-I_0603_G_19950814
Z0603 R3
Z0603_11 PART _NUM=RC-I-0603-10R0-G 10 Ohm
ModelT ype=MW SMT_Pad="Pad1"

MLIN
TL300
Subst="MSub1"
W=0.524 mm
L=2 mm

MT EE_ADS sc_kmt_C0G_06035_D_19960828
Tee37 C28
Subst="MSub1" PART _NUM=C0603C100D5G 10pF
W1=0.524 mm Temperature=25
Z0603 W2=0.524 mm SMT_Pad="Pad1"
Z0603_7 MLIN
W3=0.524 mm
ModelT ype=MW TL302
Subst="MSub1"
W=0.524 mm
L=2 mm
MT EE_ADS sc_kmt_C0G_06035_J_19960828
Tee36 C29
Subst="MSub1" PART _NUM=C0603C101J5G 100pF
W1=0.524 mm Temperature=25
Z0603 W2=0.524 mm SMT_Pad="Pad1"
Z0603_6 MLIN
W3=0.524 mm
ModelT ype=MW TL303
Subst="MSub1"
W=0.524 mm
L=2 mm
MT EE_ADS sc_kmt_C0G_06035_J_19960828
Tee38 C30
Subst="MSub1" PART_NUM=C0603C221J5G 220pF
W1=0.524 mm Temperature=25
Z0603 W2=0.524 mm
SMT _Pad="Pad1"
Z0603_8 MLIN
W3=0.524 mm
ModelT ype=MW TL301
Subst="MSub1"
W=0.524 mm
L=2 mm
MT EE_ADS sc_kmt_X7R_08055_M_19960828
Tee35 C31
Subst="MSub1" PART _NUM=C0805C104M5R 100nF
W1=0.524 mm Vtest=1
W2=0.524 mm Temperature=25
Z0805
W3=0.524 mm SMT_Pad="Pad2"
Z0805_2
ModelT ype=MW MLIN
TL299
Subst="MSub1"
W=0.524 mm
L=2 mm

V_DC
SRC2
Vdc=VGS V

Figure 4- 35 Schematic of stabilized FET(S-parameter model) without matching network.

2.0
Stability Factor K

1.5

1.0

0.5

0.0
4 5 6 7 8 9 10
Frequency GHz

Figure 4- 36 Stability factor vs frequency characteristic after stabilization with S-parameter

model.

18 1.6
Actual noise figure
Power Gain dB(S(2,1))

16 1.4
Noise Figure dB

14 1.2
12 1.0 Minimum noise figure
10 0.8

8 0.6

6 0.4
4 5 6 7 8 9 10 4 5 6 7 8 9 10

Frequency GHz Frequency GHz

(a) (b)

Figure 4- 37 Power gain and noise figure after stabilization with S-parameter model.

58
4.12.1 Matching Network Design at 8.5 GHz
Matching network design is the critical task of an LNA. At first the matching
network is designed with lumped elements then ideal transmission line and microstrip
line are used. Matching network is designed step by step using the amplifier design
guide and Smith chart tool in ADS.
All microstrip lines are transferred into layout components of Figure 4- 35.
Figure 4- 38 shows the modified schematic of LNA with layout component. The
microstrip line before DC blocking or coupling capacitor is ignored for the
simplicity. This modification will help to make the matching network easily. But
once the proper matching network is completed, then removed microstrip line is put
in front of coupling capacitor. And finally the matching network is optimized.
V_DC I_Probe
SRC1 IDS
s c _kmt_X7R_08055_M_19960828
Vdc =VDS V
C30
V ar VAR PART_NUM=C0805C104M5R 100nF
E qn
VAR3 Vtes t=1
VDS=3 T emperature=25
SMT _Pad="Pad2"

sc _kmt_C0G_06035_J _19960828
C29
PART _NUM=C0603C221J5G 220pF
Z24m
Temperature=25
Z24m_1
SMT _Pad="Pad1"
ModelT ype=MW

sc _kmt_C0G_06035_J _19960828
C28
PART _NUM=C0603C101J5G 100pF
Temperature=25
SMT _Pad="Pad1"

sc _kmt_C0G_06035_D_19960828
C31
PART _NUM=C0603C100D5G 10pF
Temperature=25
SMT _Pad="Pad1"

s r_ims _RC-I_0603_G_19950814
R3
PART_NUM=RC-I-0603-43R0-G 43 Ohm
SMT _Pad="Pad1"

N OPTIONS
SMT_Pad
MS R

MS R

SMT_Pad
t S

t S

Zin
u

Opti ons
T
bU

T
bU
2B

3B

SMT _Pad Zin Opti ons1

SMT _Pad Temp=16.85
Pad2 Zin1
Pad1 W=1.22 mm Tnom=25
Zin1=zi n(S11,PortZ1)
W=0.8 mm
L=0.457 mm Meas Meas Eqn
L=0.3 mm E qn
PadLayer="bond" meas1
PadLayer="bond"
SMO=0.15 mm
SMO=0.15 mm SM_Layer="solder_mask" T ec hInclude_NEC_ACT IVELIBRARY
SM_Layer="s older_mas k"
PO=-0.228 mm NEC_ACT IVELIBRARY_Lib
PO=-0.15 mm
File=Nominal

MSub S-PARAMETERS
SMT_Pad
S_Param
MSUB SP1
SMT _Pad MSub1
Pad3 Start=4 GHz Var VAR
Eqn
H=0.254 mm Stop=10 GHz VAR1
W=0.5 mm Er=3.66 Step=0.1 GHz Z0=50
L=0.25 mm
Mur=1 CalcNois e=yes
PadLayer="bond" Cond=5.8e7
SMO=0.15 mm
Hu=1.0e+033 mm
SM_Layer="solder_mask"
T=0.035 mm
PO=-0.125 mm
TanD=0.0037
Rough=0.001 mm

s c_kmt_C0G_06035_D_19960828 S2P s c_kmt_C0G_06035_D_19960828

C36 SNP1 C37
PART _NUM=C0603C100D5G 10pF File="NE3512S02v2_2-18_2_20.s 2p" PART _NUM=C0603C100D5G 10pF
T emperature=25 T emperature=25
SMT _Pad="Pad1" SMT _Pad="Pad1"
Z24m
1

Term Z24m_2 2
Term
Ref

Term1 ModelT ype=MW Z25_Ml ine Term2

Num=1 Z0603 Z25_Ml ine_1 Z0402 Z0603 Num=2
Z=Z0 Z0603_1 ModelT ype=MW Z0402_1 Z0603_2 Z=Z0
ModelT ype=MW ModelT ype=MW Model Type=MW
zzzzzzzz
sr_i ms _RC-I_0603_G_19950814
zzzzzzzz_1
R1
ModelT ype=MW
PART _NUM=RC-I-0603-3R90-G 3.9 Ohm
SMT _Pad="Pad3"
MS R

MS R
t S

t S
uT

uT
bU

bU
2B

3B

sr_ims _RC-I_0603_G_19950814
R4
PART _NUM=RC-I-0603-10R0-G 10 Ohm
SMT _Pad="Pad1"

s c_kmt_C0G_06035_D_19960828
C35
PART _NUM=C0603C100D5G 10pF
T emperature=25
SMT_Pad="Pad1"

s c _kmt_C0G_06035_J_19960828
C34
PART_NUM=C0603C101J5G 100pF
T emperature=25
SMT _Pad="Pad1"

s c _kmt_C0G_06035_J_19960828
C33
PART_NUM=C0603C221J5G 220pF
T emperature=25
SMT _Pad="Pad1"

V ar
E qn VAR
VAR4
s c _kmt_X7R_08055_M_19960828 VGS=-0.17
C32
PART_NUM=C0805C104M5R 100nF
Vtes t=1
T emperature=25
SMT _Pad="Pad2"

V_DC
SRC2
Vdc =VGS V

Figure 4- 38 Layout component.

In order to minimize the noise with available gain, noise figure approach has
been used for the matching network. Figure 4- 39 shows the input and output
termination conditions of Figure 4- 38 at the higher band i.e. 8.5 GHz. It is good to
have matching at the higher band that gives less noise over the entire band [14].
Matching For Noise Figure Conjugate Match Load
Power Gain with these
Impedance if Source
Reflection Coefficient Source and Load
NFmin, dB Zopt for NFmin is Sopt for Minimum NF Reflection Coefficients
0.651 17.8 - j37.6 65.7 + j532.m 13.573

Source Reflection
Coefficient for
Conjugate match
Minimum NF Zload if source
0.639 / -101.550 Zopt impedance is Zopt

DUT* *DUT= Device Under Test

(simulated circuit or device)

Figure 4- 39 Matching for noise figure at 8.5 GHz.

59
4.12.1.1 Matching Network by Lumped Elements
Noise figure does not depend on the output matching network. So referring to
Figure 4- 39, it is necessary to make such an input matching network that will be
complex conjugate of 17.3-j37.6. Once the input matching network is designed, a
output matching network has to design to get flat gain over the bandwidth.
We have 50 ohm termination. So In the smith chart tool, we have chosen
source as a 50 ohm and the load is the complex conjugate of Zopt i.e. ZL=*Zopt =
17.8+j37.6. Using Smith chart tool (Figure 4- 40) we have design multi section input
matching network (Figure 4- 41) by ideal lumped elements. Multi section or Π-
network gives larger bandwidth compare to L-section matching network [15].

Zload=*Zopt

Figure 4- 40 Smith chart of input matching network by lumped elements.

C1 C3 C3 C4

L1 L2 L3 L4

Figure 4- 41 Input matching network where L1=1.54 nH, L2=1.87 nH, L3=1.02 nH, L4=1.11
nH,C1=1.2 pF, C2=1.5 pF, C3=1.55 and C4=0.42 pF pF.

Matching For Noise Figure Conjugate Match Load

Power Gain with these
Impedance if Source
Reflection Coefficient Source and Load
NFmin, dB Zopt for NFmin is Sopt for Minimum NF Reflection Coefficients
0.651 49.3 + j712.m 65.7 + j532.m 13.573

Source Reflection
Coefficient for
Conjugate match
Minimum NF Zload if source
0.010 / 135.898 Zopt impedance is Zopt

DUT* *DUT= Device Under Test

(simulated circuit or device)

Figure 4- 42 Matching condition at 8.5 GHz after putting input matching network.

From the simulation result (Figure 4- 42) it is clear the input is matched with
50 ohm termination at 8.5 GHz. The simulated noise figure is shown in Figure 4- 43,
where noise figure (star line) is same as minimum noise (solid line). As seen in
Figure 4- 42 , the output is close to the 50 ohm so we have ignored the output
matching network for this type of matching network only.

60
 2.0
1.8

Noise Figure dB
1.6
1.4
1.2
1.0
0.8
0.6
0.4
4 5 6 7 8 9 10
Frequency GHz
Figure 4- 43 Comparison between Noise figure (star line) and minimum noise (solid line).

4.12.1.2 Microstrip Matching Network

Using the same procedure as given in previous section, we have designed multi
section input matching network with microstrip line. We have transferred the
microstrip line to layout component. Then we optimize the layout component of input
network. Figure 4- 44 shows the optimized input matching network. We have used
Roger, RO4350B substrate that is already defined in section 4.1. With the help of
Line Calc. tool, we have found the width and length.

ZS=50 Ω ZLoad=*Zopt

Figure 4- 44 Input matching network with microstrip, L1=2.1 mm, L2=2 mm, L3=2 mm, L4=3.5
mm, L5=3.57 mm, L6=1.25 mm, L7=2.38 mm and W=0.524 mm.

18 2.0 Actual noise figure

Power Gain dB(S(2,1))

1.8
Noise Figure dB

16
1.6
14 1.4
12 1.2 Minimum noise figure
1.0
10
0.8
8 0.6
6 0.4
5.0
5.5

6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5

10.0

5 6 7 8 9 10
Frequency GHz
Frequency GHz
(a) (b)

Figure 4- 45 Power gain and noise figure (star line) vs frequency with input matching network.

Matching For Noise Figure Conjugate Match Load

Power Gain with these
Impedance if Source
Reflection Coefficient Source and Load
NFmin, dB Zopt for NFmin is Sopt for Minimum NF Reflection Coefficients
0.852 52.0 - j638.m 38.7 + j35.1 13.332

Source Reflection
Coefficient for
Conjugate match
Minimum NF Zload if source
0.020 / -17.602 Zopt impedance is Zopt

DUT* *DUT= Device Under Test

(simulated circuit or device)

Figure 4- 46 Matching condition at 8.5 GHz after putting input microstrip matching network.

61
 From Figure 4- 45 (b) it is clear that compare to lumped elements matching
network, microstrip matching network gives smaller noise figure over the bandwidth.
We can see from Figure 4- 46 that output is far from matching. So we have to make
output matching network for flat power gain over the bandwidth.
In the same way using the ADS design tool we have designed the output
matching network (Figure 4- 47). Figure 4- 48 shows the LNA with input and output
matching network. After adding the output matching network, the power gain (a)) has
increased and becomes more flat than the power gain without output matching
network.

ZS=*ZLoad=38.7-j35.1

ZLoad=50 Ω

Figure 4- 47 Output matching network with microstrip line, L1=2 mm, L2=7 mm, L3=2 mm,
L4=2.5mm, L5=3mm, L6=2 mm, L7=4mm and W=0.524mm.
Actual noise figure
18 2.0
Power Gain dB(S(2,1))

16 1.8
Noise Figure dB

1.6
14 1.4
12 1.2 Minimum noise figure
1.0
10
0.8
8 0.6
6 0.4
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0

5 6 7 8 9 10
Frequency GHz
Frequency GHz
(a) (b)

Figure 4- 48 Power gain and noise figure (star line) vs frequency with input and output network.

4.12.2 Matching Network Design at 9 GHz

In this design we will use all microstrip components instead of individual
layout component. After getting IMN and OMN we will create complete layout
component of the LNA. In the previous matching network design 8.5 GHz was
chosen. As there was a sharp change in gain and noise after 8.5 GHz so this time we
will design matching network at 9 GHz.
We have already seen that matching network with lumped elements does not
give desired large bandwidth compare to microstrip line. So we will design matching
network with microstrip line only. This time we will slightly deviate from the
traditional way of designing matching network. Using LineCalc tools in the ADS, we
have noticed that there is a negligible difference of transmission line width at 8.5 and
9 GHz. So we will start designing matching network with 8.5 GHz in the Smith chart
utility tool then we will optimize it with 9 GHz.

62
 Figure 4- 49 shows the LNA without matching network and do not have any
layout component of capacitor and resistor footprint. For the FET, we have used
exact size of foot print with microstrip line instead of layout components.

V_DC I_Probe
SRC3 IDS1
Vdc=VDS V MLIN
TL304
Subst="MSub1"
W=0.524 mm
L=2 mm

MTEE_ADS
Tee32
Subst="MSub1"
sc_kmt_X7R_06035_J_19960828 W1=0.524 mm
C44 W2=0.524 mm
PART_NUM=C0603C103J5R 10nF MLIN
W3=0.524 mm
SMT_Pad="Pad1" TL292
Subst="MSub1"
W=0.524 mm
L=1.5 mm
sc_kmt_C0G_06035_J_19960828 MTEE_ADS
C25 Tee31
PART_NUM=C0603C221J5G 220pF Subst="MSub1"
SMT_Pad="Pad1" W1=0.524 mm
W2=0.524 mm
MLIN
W3=0.524 mm
TL291
Subst="MSub1"
W=0.524 mm
L=1.5 mm
MTEE_ADS
Tee30
sc_kmt_C0G_06035_J_19960828 Subst="MSub1"
C13 W1=0.524 mm
PART_NUM=C0603C101J5G 100pF W2=0.524 mm
SMT_Pad="Pad1" MLIN
W3=0.524 mm
TL290
Subst="MSub1"
W=0.524 mm
L=1.5 mm
MTEE_ADS
Tee29
Subst="MSub1"
sc_kmt_C0G_06035_D_19960828 W1=0.524 mm
C24 W2=0.524 mm
PART_NUM=C0603C1R0D5G 1pF W3=0.524 mm
SMT_Pad="Pad1"

MLIN
TL288
Subst="MSub1"
W=0.524 mm
L=2 mm

sr_ims_RC-I_0603_G_19950814 MCROSO
R2 Cros1
PART_NUM=RC-I-0603-43R0-G 43 Ohm Subst="MSub1"
SMT_Pad="Pad1" W1=0.524 mm
W2=0.524 mm
MLIN W3=0.524 mm
TL320 W4=0.524 mm
Subst="MSub1"
W=0.65 mm
L=0.5 mm
S2P MRSTUB MRSTUB
MTEE_ADS MLIN
SNP1 Stub4 Stub3
Tee34 Subst="MSub1" TL294 Subst="MSub1"
Subst="MSub1" File="NE3512S02v2_2-18_2_20.s2p" Subst="MSub1"
Wi=0.524 mm Wi=0.524 mm
W1=0.524 mm L=4 mm W=0.524 mm L=4 mm
W2=0.524 mm Ang le=78 L=5.22 mm Angle=78
W3=0.524 mm

1 2
Term
MLIN
Ref
MLIN MTEE_ADS Term2
Term sc_kmt_C0G_06035_D_19960828
Term1 TL317 TL318 Tee33 sc_kmt_C0G_06035_D_19960828 Num=2
C42 MLIN Subst="MSub1" Subst="MSub1" sr_avx_CR_05_J_19960828 Subst="MSub1" Z=50 Ohm
Num=1 PART_NUM=C0603C100D5G 10pF TL299 R6 C43
W=0.524 mm W=0.524 mm W1=0.524 mm
Z=50 Ohm SMT_Pad="Pad1" Subst="MSub1" PART_NUM=CR05-3R9J 3.9 Ohm W2=0.524 mm PART_NUM=C0603C100D5G 10pF
L=1.5 mm MLIN L=1.5 mm SMT_Pad="Pad1"
W=0.524 mm TL319 SMT_Pad="Pad3" W3=0.524 mm
L=5.22 mm Subst="MSub1"
W=0.65 mm
L=0.5 mm

MCROSO
MRSTUB Cros2 MRSTUB
Stub5 Subst="MSub1" Stub6
Subst="MSub1" W1=0.524 mm Subst="MSub1"
Wi=0.524 mm W2=0.524 mm Wi=0.524 mm
L=4 mm W3=0.524 mm L=4 mm
Angle=78 W4=0.524 mm Angle=78

sr_ims_RC-I_0603_G_19950814
R4
PART_NUM=RC-I-0603-10R0-G 10 Ohm
SMT_Pad="Pad1"

MLIN
TL289
Subst="MSub1"
W=0.524 mm S-PARAMETERS
L=2 mm S_Param
MTEE_ADS SP1
Tee38 Start=5 GHz
Subst="MSub1" Stop=10 GHz V ar
VAR
W1=0.524 mm Step=0.1 GHz E qn
VAR2
W2=0.524 mm sc_kmt_C0G_06035_D_19960828 CalcNoise=yes VDS=3
W3=0.524 mm MLIN C41
VGS=-0.17
PART_NUM=C0603C1R0D5G 1pF
TL307 OPTIONS
Subst="MSub1" SMT_Pad="Pad1"
W=0.524 mm Options SMT_Pad
L=1.5 mm Options1
MTEE_ADS Temp=16.85 SMT_Pad
Tee35 Tnom=25 MSub Pad1
Subst="MSub1" VAR W=0.8 mm
Var
W1=0.524 mm Eqn
VAR1 MSUB L=0.3 mm
sc_kmt_C0G_06035_J_19960828 MSub1 PadLayer="bond"
W2=0.524 mm C40 Z0=50
W3=0.524 mm MLIN H=0.254 mm SMO=0.15 mm
TL305 PART_NUM=C0603C101J5G 100pF Er=3.66 SM_Layer="solder_mask"
Subst="MSub1" SMT_Pad="Pad1" Meas MeasEqn Mur=1 PO=-0.15 mm
Eqn

W=0.524 mm meas1 Cond=5.8e7

MTEE_ADS L=1.5 mm Hu=1.0e+033 mm
SMT_Pad
Tee37 T=0.035 mm
Subst="MSub1" TanD=0.0037 SMT_Pad
W1=0.524 mm Rough=0.001 mm Pad3
W2=0.524 mm sc_kmt_C0G_06035_J_19960828 W=0.5 mm
W3=0.524 mm MLIN C39 TechInclude_NEC_ACTIVELIBRARY L=0.25 mm
PART_NUM=C0603C221J5G 220pF NEC_ACTIVELIBRARY_Lib PadLayer="bond"
TL306
Subst="MSub1" SMT_Pad="Pad1" File=Nominal SMO=0.15 mm
W=0.524 mm SM_Layer="solder_mask"
L=1.5 mm N PO=-0.125 mm
MTEE_ADS
Zin
Tee36
Subst="MSub1" Zin
W1=0.524 mm sc_kmt_X7R_06035_J_19960828 Zin1
W2=0.524 mm C45 Zin1=zin(S11,PortZ1)
W3=0.524 mm PART_NUM=C0603C103J5R 10nF
SMT_Pad="Pad1"

MLIN
TL308
Subst="MSub1"
W=0.524 mm
L=2 mm

V_DC
SRC4
Vdc=VGS V

Figure 4- 49 LNA before matching network.

63
4.12.2.1 Input Matching Network design
Figure 4- 50 shows the template of LNA design simulation result at 8.5 GHz
before matching network. Same procedure is used to design matching network as
before done in the previous section 4.42.1. Here only dsign steps are given in
graphically instead of details description.
Maximum Available Gain, Associated
Power Gain (input matched for NFmin, Minimum Noise Figure, dB,
output then conjugately matched), and dB(S21) and Noise Figure with Z0
Ohm terminations
20 1.4
m7
18 m5 freq=9.000GHz
Pgain_assoc

m5 freq=6.000GHz
1.2 m7 nf(2)=1.119
16
dB(S21)

dB(S21)=15.812
MAG

1.0

NFmin
nf(2)
14 m6
freq=9.000GHz
12 dB(S21)=9.893 0.8
m6
10 0.6

8 0.4
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0

5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
freq, GHz freq, GHz

(a) (b)

Matching For Noise Figure Conjugate Match Load

Impedance if Source Power Gain with these
Reflection Coefficient Source and Load
Zopt for NFmin is Sopt for Minimum NF Reflection Coefficients
NFmin, dB
0.581 17.1 - j21.8 27.2 - j30.4 12.810

Source Reflection
Coefficient for Conjugate match
Minimum NF Zload if source
0.560 / -128.393 Zopt impedance is Zopt

DUT* *DUT= Device Under Test

(simulated circuit or device)

(c)

Figure 4- 50 Simulation result of LNA at 8.5 GHz matching point without matching network.

Figure 4- 51 Smith chart for IMN design at 8.5 GHz.

64
 MTEE_ADS
MTEE_ADS MTEE_ADS Tee62
Tee60 Tee61 Subst="MSub1"
Subst="MSub1" Subst="MSub1"
W1=0.524 mm
W1=0.524 mm W1=0.524 mm
W2=0.524 mm
W2=0.524 mm W2=0.524 mm
W3=0.524 mm
W3=0.524 mm W3=0.524 mm
Zsource= 50 Ohm Zload= *Zopt=17.1+j21.8

Port MLIN MLIN Port

P1 TL354 TL352 P2
Subst="MSub1" Subst="MSub1"
W=0.524 mm W=0.524 mm
L=1.55 mm L=3 mm
MLOC MLOC
TL355 TL353 MLOC
Subst="MSub1" Subst="MSub1" TL351
Subst="MSub1"
W=0.524 mm W=0.524 mm
W=0.524 mm
L=1.37 mm L=0.94 mm
L=3.75 mm

Figure 4- 52 IMN at 8.5 GHz before optimize.

As we need to put signal with SMA contact so we need some margin at the
input side of the matching network. That is why a small length (two mm) microstrip
line is added and IMN is optimized with this line at 9 GHz.
MTEE_ADS
MTEE_ADS MTEE_ADS Tee65
Tee63 Tee64
Subst="MSub1"
Subst="MSub1" Subst="MSub1" W1=0.524 mm
W1=0.524 mm W1=0.524 mm W2=0.524 mm
W2=0.524 mm W2=0.524 mm W3=0.524 mm
W3=0.524 mm W3=0.524 mm

Port MLIN MLIN Port

P1 TL359 TL361 P2
MLIN Subst="MSub1" Subst="MSub1"
TL362 W=0.524 mm W=0.524 mm
Subst="MSub1" L=1.395 mm L=3.3 mm
MLOC MLOC
W=0.524 mm MLOC
L=2 mm TL358 TL357
TL360
Subst="MSub1" Subst="MSub1"
W=0.524 mm W=0.524 mm Subst="MSub1"
L=1.35 mm L=1.07 mm W=0.524 mm
L=3.375 mm

Figure 4- 53 IMN at 9 GHz after optimize.

Maximum Available Gain, Associated

Power Gain (input matched for NFmin, Minimum Noise Figure, dB,
output then conjugately matched), and dB(S21) and Noise Figure with Z0
Ohm terminations
20 1.8
18 m7
m5 1.6 freq=9.000GHz
Pgain_assoc

m5 nf(2)=0.805
16 freq=6.000GHz
dB(S21)

dB(S21)=15.796 1.4
MAG

14
NFmin
nf(2)

m6
12 m6 freq=9.000GHz 1.2
dB(S21)=10.995
10 1.0
m7
8 0.8
6 0.6
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0

5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0

freq, GHz freq, GHz

(a) (b)

Matching For Noise Figure Conjugate Match Load

Impedance if Source Power Gain with these
Reflection Coefficient Source and Load
Zopt for NFmin is Sopt for Minimum NF Reflection Coefficients
NFmin, dB
0.805 50.0 + j7.30m 12.025
28.5 - j32.5

Source Reflection
Coefficient for Conjugate match
Minimum NF Zload if source
Zopt impedance is Zopt
7.411E-5 / 100.043
DUT* *DUT= Device Under Test
(simulated circuit or device)

(c)

Figure 4- 54 Simulation result of LNA with IMN after optimization.

65
4.12.2.2 Output Matching Network Design
Figure 4- 55 shows the Smith chart tool of ADS for designing the matching
network at 9 Ghz. Same procedure is used to design matching network as before done
in the previous section. In the same way only dsign steps are given in graphically
instead of description.

Figure 4- 55 Smith chart for OMN design at 9 GHz.

MTEE_ADS
MTEE_ADS MTEE_ADS Tee66
Tee68 Tee67
Subst="MSub1"
Subst="MSub1" Subst="MSub1"
W1=0.524 mm
W1=0.524 mm W1=0.524 mm W2=0.524 mm
W2=0.524 mm W2=0.524 mm W3=0.524 mm
W3=0.524 mm W3=0.524 mm
Zload= *Zload=28.5+32.5 Zsource= 50 Ohm

Port MLIN MLIN Port

P1 TL365 TL363 P2
Subst="MSub1" Subst="MSub1"
W=0.524 mm W=0.524 mm
L=4.36 mm L=3.42 mm
MLOC
MLOC TL364 MLOC
TL366 TL362
Subst="MSub1"
Subst="MSub1" Subst="MSub1"
W=0.524 mm
W=0.524 mm W=0.524 mm
L=1.66 mm
L=2.67 mm L=1.66 mm

Figure 4- 56 OMN at 9 GHz before optimize.

66
 Maximum Available Gain, Associated
Power Gain (input matched for NFmin, Minimum Noise Figure, dB,
output then conjugately matched), and dB(S21) and Noise Figure with Z0
Ohm terminations
20 1.8
m7
18 freq=9.000GHz
m5 1.6
Pgain_assoc
m5 nf(2)=0.813
16 freq=6.000GHz
dB(S21)

dB(S21)=15.601 1.4
MAG

14

NFmin
nf(2)
m6
m6 1.2
12 freq=9.000GHz
dB(S21)=11.697
10 1.0
m7
8 0.8
6 0.6
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0

5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
freq, GHz freq, GHz

(a) (b)

Matching For Noise Figure Conjugate Match Load

Impedance if Source Power Gain with these
Reflection Coefficient Source and Load
NFmin, dB Zopt for NFmin is Sopt for Minimum NF Reflection Coefficients
0.813 50.1 + j175.m 11.861
51.5 + j19.6

Source Reflection
Coefficient for Conjugate match
Minimum NF Zload if source
Zopt impedance is Zopt
0.002 / 63.927
DUT* *DUT= Device Under Test
(simulated circuit or device)

(c)

Figure 4- 57 Simulation result of LNA with optimized IMN and unutilized OMN.

We need extra margin at the out put of the matching network in order to
receive the signal. So we have added a small length (2 mm) of microstrip line then
we have optimized the matching network
MTEE_ADS
MTEE_ADS MTEE_ADS
Tee69
Tee71 Tee70 MLIN
Subst="MSub1"
Subst="MSub1" Subst="MSub1" TL373
W1=0.524 mm
W1=0.524 mm W1=0.524 mm Subst="MSub1"
W2=0.524 mm
W2=0.524 mm W2=0.524 mm W3=0.524 mm W=0.524 mm
W3=0.524 mm W3=0.524 mm L=2 mm

Port MLIN MLIN Port

P1 TL372 TL368 P2
Subst="MSub1" Subst="MSub1"
W=0.524 mm W=0.524 mm
L=3.91 mm L=2.7 mm
MLOC MLOC
TL370 TL369 MLOC
Subst="MSub1" Subst="MSub1" TL371
W=0.524 mm W=0.524 mm Subst="MSub1"
L=2.41 mm L=1.32 mm W=0.524 mm
L=1.67 mm

Figure 4- 58 OMN at 9 GHz after optimization.

Figure 4- 59 shows the complete schematic of the LNA with input and out put
matching network.

67
 V_DC I_Probe
SRC3 IDS1
Vdc=VD S V MLIN
TL304
Subst="MSub1"
W=0.524 mm
L=2 mm

MTEE_A DS
Tee32
Subst="MSub1"
sc_kmt_X7R _06035_J_19960828 W1=0.524 mm
C44 W2=0.524 mm
PART_NUM=C0603C103J5R 10nF MLIN
W3=0.524 mm
SMT_Pad="Pad1" TL292
Subst="MSub1"
W=0.524 mm
L=1.5 mm
sc_kmt_C0G_06035_J_19960828 MTEE_A DS
C25 Tee31
PART_NUM=C0603C221J5G 220pF Subst="MSub1"
SMT_Pad="Pad1" W1=0.524 mm
W2=0.524 mm
MLIN
W3=0.524 mm
TL291
Subst="MSub1"
W=0.524 mm
L=1.5 mm
MTEE_A DS
Tee30
sc_kmt_C0G_06035_J_19960828 Subst="MSub1"
C13 W1=0.524 mm
PART_NUM=C0603C101J5G 100pF W2=0.524 mm
SMT_Pad="P ad1" MLIN
W3=0.524 mm
TL290
Subst="MSub1"
W=0.524 mm
L=1.5 mm
MTEE_A DS
Tee29
Subst="MSub1"
sc_kmt_C0G_06035_D_19960828 W1=0.524 mm
C24 W2=0.524 mm
PART_NUM=C0603C1R0D5G 1pF W3=0.524 mm
SMT_Pad="P ad1"

MLIN
TL288
Subst="MSub1"
W=0.524 mm
L=2 mm

sr_ims_RC-I_0603_G_19950814 MCROSO
R2 C ros1
PART_NUM=RC-I-0603-43R0-G 43 Ohm S ubst="MSub1"
SMT_Pad="P ad1" W 1=0.524 mm
W 2=0.524 mm
MLIN
W 3=0.524 mm
TL320 W 4=0.524 mm
S ubst="MSub1"
W =0.65 mm
L=0.5 mm
MTEE_ADS S2P MRSTUB MR STUB MTEE _ADS
MTEE_ADS MTEE_AD S MTE E_ADS MLIN MTE E_ADS MTE E_ADS
Tee55 SNP1 Stub4 Stub3 Tee65
MLIN Tee59 Tee56 Subst="MSub1" Tee34 Subst="MSub1" TL294 Subst="MSub1" Tee63 Tee64 Subst="MSub1" MLIN
TL356 Subst="MSub1" Subst="MS ub1" Subst="MSub1" File="NE3512S 02v2_2-18_2_20.s2p" Subst="MSub1" Subst="MSub1" Subst="MSub1" TL367
W1=0.524 mm Wi=0.524 mm Wi =0.524 mm W1=0.524 mm
Subst="MSub1" W1=0.524 mm W1=0.524 mm W2=0.524 mm W1=0.524 mm L=4 mm W=0.524 mm L=4 mm W1=0.524 mm W1=0.524 mm W2=0.524 mm Subst="MSub1"
W=0.524 mm W2=0.524 mm W2=0.524 mm W3=0.524 mm W2=0.524 mm Angle=78 L=5.22 mm Angle=78 W2=0.524 mm W2=0.524 mm W3=0.524 mm W=0.524 mm
L=2 mm W3=0.524 mm W3=0.524 mm W3=0.524 mm W3=0.524 mm W3=0.524 mm L=2 mm

1 2

MLIN MLIN MLIN

Re f

MLIN MTEE_ADS MLIN MLIN

sc_kmt_C0G_06035_D_19960828 Tee33
TL346 TL340 TL317 TL318 sr_avx_CR_05_J_19960828 sc_kmt_C0G_06035_D_19960828 TL359 TL361
Subst="MSub1" Subst="MSub1" C42 MLIN Subst="MSub1" Subst="MSub1" Subst="MSub1" Subst="MSub1" Subst="MSub1"
PAR T_NUM=C0603C 100D5G 10pF TL299 R6 W1=0.524 mm C43
W=0.524 mm W=0.524 mm W=0.524 mm W=0.524 mm PAR T_NUM=CR05-3R9J 3.9 Ohm PART_NUM=C0603C100D5G 10pF W=0.524 mm W=0.524 mm
SMT_Pad="Pad1" Subst="MS ub1" MLIN W2=0.524 mm
Term L=1.395 mm L=3.3 mm L=1.5 mm L=1.5 mm SMT_Pad="P ad1" L=3.91 mm L=2.7 mm
MLOC MLOC W=0.524 mm TL319 SMT_Pad="Pad3" W3=0.524 mm MLOC MLOC Term
Term1 MLOC L=5.22 mm S ubst="MSub1"
Num=1 TL350 TL339 TL358 TL357 MLOC Term2
S ubst="MSub1" S ubst="MSub1" TL344 W =0.65 mm Subst="MSub1" Subst="MS ub1" Num=2
Z=50 Ohm S ubst="MSub1" TL360
W =0.524 mm W =0.524 mm L=0.5 mm W=0.524 mm W=0.524 mm Subst="MSub1" Z=50 Ohm
L=1.35 mm L=1.07 mm W =0.524 mm L=2.41 mm L=1.32 mm
L=3.375 mm W=0.524 mm
MCROSO
L=1.67 mm
MRSTU B Cros2 MRS TUB
Stub5 Subst="MS ub1" Stub6
Subst="MSub1" W1=0.524 mm Subst="MSub1"
Wi=0.524 mm W2=0.524 mm Wi=0.524 mm
L=4 mm W3=0.524 mm L=4 mm
Angle=78 W4=0.524 mm Angle=78

sr_ims_RC-I_0603_G_19950814
R4
PART_NUM=RC-I-0603-10R 0-G 10 Ohm
SMT_Pad="Pad1"

MLIN
TL289
Subst="MS ub1"
W=0.524 mm S-PARAMETERS
L=2 mm S_Param
MTEE_ADS SP1
Tee38 Start=5 GHz
S ubst="MSub1" Stop=10 GHz Var VA R
W 1=0.524 mm Step=0.1 GHz Eqn

W 2=0.524 mm sc_kmt_C0G_06035_D_19960828 CalcN oise=yes VA R2

W 3=0.524 mm C 41 VD S=3
MLIN VGS=-0.17
P ART_NUM=C0603C1R0D5G 1pF
TL307 OPTIONS
S MT_Pad="Pad1"
Subst="MS ub1"
W=0.524 mm Options S MT_Pad
L=1.5 mm Options1
MTEE_ADS Temp=16.85 S MT_Pad
Tee35 Tnom=25 MSub P ad1
S ubst="MSub1" W =0.8 mm
Var VAR
W 1=0.524 mm Eqn
VAR1 MSUB L=0.3 mm
sc_kmt_C0G_06035_J_19960828 MSub1 P adLayer="bond"
W 2=0.524 mm C40 Z0=50
W 3=0.524 mm MLIN H=0.254 mm S MO=0.15 mm
TL305 PAR T_NUM=C0603C 101J5G 100pF Er=3.66 S M_Layer="solder_mask"
Subst="MS ub1" SMT_Pad="Pad1" M eas MeasEqn Mur=1 P O=-0.15 mm
Eqn
W=0.524 mm meas1 Cond=5.8e7
MTEE_ADS L=1.5 mm Hu=1.0e+033 mm
SMT_Pad
Tee37 T=0.035 mm
Subst="MSub1" TanD=0.0037 SMT_Pad
W1=0.524 mm Rough=0.001 mm Pad3
W2=0.524 mm sc_kmt_C0G_06035_J_19960828 W=0.5 mm
W3=0.524 mm C 39 TechInclude_NEC_ACTIVELIBRAR Y L=0.25 mm
MLIN
TL306 P ART_NUM=C0603C221J5G 220pF N EC_ACTIVELIB RARY_Lib PadLayer="bond"
Subst="MS ub1" S MT_Pad="Pad1" Fi le=Nominal SMO=0.15 mm
W=0.524 mm SM_Layer="solder_mask"
L=1.5 mm N PO=-0.125 mm
MTEE_ADS
Zi n
Tee36
Subst="MSub1" Zin
W1=0.524 mm sc_kmt_X7R_06035_J_19960828 Zin1
W2=0.524 mm C 45 Zin1=zin(S11,PortZ1)
W3=0.524 mm P ART_NUM=C0603C103J5R 10nF
S MT_Pad="Pad1"

MLIN
TL308
Subst="MS ub1"
W=0.524 mm
L=2 mm

V_DC
SRC4
Vdc=VGS V

Figure 4- 59 LNA with optimize IMN and OMN at 9 GHz.

Figure 4- 60 shows the template of complete schematic level simulation of the

LNA at 9 GHz matching network. Figure 4- 60 contains power gain (a), noise figure
(b) matching (c) information.
Maximum Available Gain, Associated
Power Gain (input matched for NFmin, Minimum Noise Figure, dB,
output then conjugately matched), and dB(S21) and Noise Figure with Z0
Ohm terminations
20
18 1.8
m7
m5 m5 freq=9.000GHz
Pgain_assoc

16 freq=6.000GHz 1.6 nf(2)=0.813

dB(S21)

dB(S21)=15.696
MAG

14 m6
1.4
NFmin

m6
nf(2)

12 freq=9.000GHz
dB(S21)=11.863
1.2
10 1.0
8 m7
0.8
6
0.6
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0

5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0

freq, GHz freq, GHz

(a) (b)

Matching For Noise Figure Conjugate Match Load

Impedance if Source Power Gain with these
Reflection Coefficient Source and Load
Zopt for NFmin is Sopt for Minimum NF Reflection Coefficients
NFmin, dB
0.813 50.1 + j157.m 11.867
50.0 + j808.m

Source Reflection
Coefficient for Conjugate match
Minimum NF Zload if source
Zopt impedance is Zopt
0.002 / 60.518
DUT* *DUT= Device Under Test
(simulated circuit or device)

(c)

Figure 4- 60 Simulation result of LNA with IMN and OMN.

68
 Figure 4- 60 shows the complete schematic look like simulation of LNA with
IMN and OMN. Figure 4- 61 shows the complete layout of LNA with IMN and
OMN.
V_DC
I_Probe
SRC3
IDS1
Vdc= VDS V

sc_kmt_X7R_06035_J_19960828
C44
PART_NUM= C0603C103J5R 10nF
SMT_Pad= "Pad1"

sc_kmt_C0G_06035_J_19960828
C25
PART_NUM= C0603C221J5G 220pF
SMT_Pad= "Pad1"

sc_kmt_C0G_06035_J_19960828
C13
PART_NUM= C0603C101J5G 100pF
SMT_Pad="Pad1"

sc_kmt_C0G_06035_D_19960828
C24
PART_NUM= C0603C1R0D5G 1pF
SMT_Pad= "Pad1"

sr_ims_RC-I_0603_G_19950814
R2
PART_NUM= RC-I-0603-43R0-G 43 Ohm
SMT_Pad= "Pad1"

S2P sc_kmt_C0G_06035_D_19960828
SNP1 C43
File= "NE3512S02v2_2-18_2_20.s2p" PART_NUM=C0603C100D5G 10pF
SMT_Pad= "Pad1"

1 2

Ref

sc_kmt_C0G_06035_D_19960828
C42 Term
Term PART_NUM= C0603C100D5G 10pF Term2
Term1 SMT_Pad= "Pad1" Num=2
Num= 1 Z= 50 Ohm
Z= 50 Ohm sr_avx_CR_05_J_19960828
R6
PART_NUM= CR05-3R9J 3.9 Ohm
SMT_Pad="Pad3"

S-PARAMET ERS
S_Param
sr_ims_RC-I_0603_G_19950814 SP1
R4 Start= 2 GHz
PART_NUM=RC-I-0603-10R0-G 10 Ohm Stop=10 GHz Va r VAR
SMT_Pad= "Pad1" Step=0.1 GHz Eq n
VAR2
CalcNoise= yes
VDS= 3
VGS= -0.17
OPT IONS
Options SMT_Pad
Options1
Temp= 16.85 SMT_Pad
Tnom= 25 MSub Pad1
VAR W= 0.8 mm
Va r
Eq n
VAR1 MSUB L= 0.3 mm
Z0= 50 MSub1 PadLayer= "bond"
H= 0.254 mm SMO= 0.15 mm
Er= 3.66 SM_Layer= "solder_mask"
M eas
Eq n
MeasEqn Mur= 1 PO= -0.15 mm
meas1 Cond= 5.8e7
sc_kmt_C0G_06035_D_19960828 Hu= 1.0e+ 033 mm SMT_Pad
C41 T= 0.035 mm
PART_NUM=C0603C1R0D5G 1pF TanD= 0.0037
SMT_Pad
SMT_Pad= "Pad1" Rough= 0.001 mm Pad3
W= 0.5 mm
TechInclude_NEC_ACTIVELIBRARY L= 0.25 mm
NEC_ACTIVELIBRARY_Lib PadLayer="bond"
File= Nominal SMO= 0.15 mm
SM_Layer="solder_mask"
sc_kmt_C0G_06035_J_19960828 PO= -0.125 mm
N
C40
PART_NUM=C0603C101J5G 100pF Zin
SMT_Pad= "Pad1" Zin
Zin1
Zin1= zin(S11,PortZ1)

sc_kmt_C0G_06035_J_19960828
C39
PART_NUM=C0603C221J5G 220pF
SMT_Pad= "Pad1"

sc_kmt_X7R_06035_J_19960828
C45
PART_NUM= C0603C103J5R 10nF
SMT_Pad= "Pad1"

J11
J11_1 V_DC
ModelType= MW SRC4
Vdc= VGS V

Figure 4- 61 complete layout look like LNA with IMN and OMN.

Figure 4- 62 shows the template of complete layout simulation of the LNA at 9 GHz
matching network. Figure 4- 62 contains power gain (a), noise figure (b) matching (c)
information.
Maximum Available Gain, Associated Minimum Noise Figure, dB,
Power Gain (input matched for NFmin, and Noise Figure with Z0
output then conjugately matched), and dB(S21) Ohm terminations
20 m8 25
m9 m7
m8 freq=9.000GHz
10 freq=6.000GHz
20 nf(2)=1.013
dB(S21)=14.913
Pgain_assoc
dB(S21)

m9 m10
0 freq=9.000GHz 15 freq=6.000GHz
NFmin
nf(2)

dB(S21)=11.382 nf(2)=0.895
-10 10

-20 5
m10 m7
-30 0
2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10

freq, GHz freq, GHz

(b)
(a)

Matching For Noise Figure Conjugate Match Load

Power Gain with these
Impedance if Source
Reflection Coefficient Source and Load
NFmin, dB Zopt for NFmin is Sopt for Minimum NF Reflection Coefficients
0.947 38.1 + j14.0 11.833
41.4 - j33.9m

Source Reflection
Coefficient for Conjugate match
Minimum NF Zload if source
Zopt impedance is Zopt
0.206 / 121.172
DUT* *DUT= Device Under Test
(simulated circuit or device)

(c)

Figure 4- 62 Forward transmission (solid line) and transducer gain (dot line).

69
4.12.3 Layout of RF choke
Figure 4- 63 shows the complete layout of the RF choke which is the first
section of LNA after stabilization.

Figure 4- 63 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220 pF, C4=100nF
and R1=43 Ω.

4.13 References
[1] Adriana Serban, Ultra-Wideband Low-Noise Amplifier and Six-Port
Transceiver for High Speed Data Transmission. Linköping Studies in
Science and Technology, Dissertation No. 1295.
[2] Roger R04350B data sheet, www.rogerscorp.com
[3] NEC Electronics, www.necel.com
[4] Transistor model,www.wikipedia.org
[5] Guillermo Gonzalaz, Microwave Transistor Amplifiers Analysis and Design.
Prentice Hall, USA 1997.
[6] Robert L. Boylestad, Louis Nashelsky, Electronic Devices and Circuit
Theory. Prentice Hall, India, 2000.
[7] Microwave FET Tutorial, www.microwaves101.com/index.cfm.
[8] RFIC Tutorial,
www.odyseus.nildram.co.uk/RFMicrowave_Theory_Files/Bias_Circuits.pdf
[9] M. Goldfarb and R. Pucel. "Modeling Via Hole Grounds in Microstrip," IEEE
Microwave and Guided Wave Letters , Vol. 1, No. 6, June 1991, pp. 135-137
[10] Richard Fiore, Selecting RF chip Capacitor for Wireless Application.
Technical note, American Technical Ceramics.

70
[11] Richard Fiore, Capacitors in Broadband applications. Technical note,
American Technical Ceramics.
[12] Technical manual, Vendor Component libraries- September 2004. Agilent
Technologies
[13] Adriana Serban, Magnus Karlsson and Shaofang Gong, “Study of Bias
Networks with RF Choke for Ultra-Wideband Systems”. IEEE Microwave
and Wireless Components Letters.
[14] Adriana Serban and Shaofang Gong, “Ultra-Wideband Low-Noise Amplifier
Design for 3.1-4.8 GHz”.
[15] Reinhold Ludwig and Pavel Bretchko, RF Circuit Design Theory and
Application. Prentice-Hall, USA, 2000.

71
5 LNA Implementation: Simulation Results and
Measurements
This chapter is divided into three sections; simulation result, measurement
and post-manufactured simulation. Simulation is done using ADS design tool from
Agilent Technologies and measurements is done using Agilent 8703A vector network
analyzer

5.1 Simulation Results

All necessary simulation results are given in this section.

5.1.1 Via Model Simulation

Z08 Term
Disp
Temp DisplayTemplate Term
Z08_2 Term2
disptemp1 Term1
ModelType=MW Num=2
"S_Params_Quad_dB_Smith" Num=1 Z=50 Ohm
Z=50 Ohm
(a) One 0.4 mm via

S-PARAMETERS
S_Param
SP1
Start=0 GHz Term
Term K17 Term4
Stop=18 GHz Term3 K17_2 Num=4
Step=0.1 GHz Num=3 ModelType=MW Z=50 Ohm
Z=50 Ohm
(b) Three 0.4 mm via

TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
Term Z12 Term
Term5 Z12_1 Term6
Num=5 ModelType=MW Num=6
Z=50 Ohm Z=50 Ohm
(c) Six 0.4 mm via

Term
Term Z15
Term8
Term7 Z15_2
Num=8
Num=7 ModelType=MW
Z=50 Ohm
Z=50 Ohm
(d) One 0.4 mm via with
5 mm microstrip line

Term Term
Term9 Z16 Term10
Num=9 Z16_2 Num=10
Z=50 Ohm ModelType=MW Z=50 Ohm

(e) Two 0.4 mm via with

5 mm microstrip line

Z14 Term
Term Term12
Z14_2
Term11 Num=12
ModelType=MW
Num=11 Z=50 Ohm
Z=50 Ohm
(f) One 0.4 mm via with
1.6 mm microstrip line

Z11 Term
Term Z11_2 Term14
Term13 ModelType=MW Num=14
Num=13 Z=50 Ohm
Z=50 Ohm
(g) One 0.2 mm via

Term VIA2 Term

Term15 V2 Term16
Num=15 D=0.4 mm Num=16
Z=50 Ohm H=0.254 mm Z=50 Ohm
T=0.00375 mm

(h) ADS via model(0.4 mm)

Figure 5- 1 Schematic for VIA model simulation.

72
 m1 m2
freq= 9.000GHz freq= 9.000GHz
S(1,1)=0.971 / 167.769 S(3,3)=0.981 / 171.026
impedance = Z0 * (0.015 + j0.107) impedance = Z0 * (0.010 + j0.078)

m1
m2

S(1,1)

S(3,3)
freq (0.0000Hz to 18.00GHz) freq (0.0000Hz to 18.00GHz)
(a) (b)

m3 m4
freq= 9.000GHz freq= 9.000GHz
S(5,5)=0.987 / 173.531 S(7,7)=0.007 / 117.233
impedance = Z0 * (0.006 + j0.057) impedance = Z0 * (0.993 + j0.013)

m3
m4
S(5,5)

S(7,7)

freq (0.0000Hz to 18.00GHz) freq (0.0000Hz to 18.00GHz)

(c) (d)

m6
m5 freq= 9.000GHz
freq= 9.000GHz S(11,11)=0.708 / 135.755
S(9,9)=0.029 / -102.230 impedance = Z0 * (0.198 + j0.393)
impedance = Z0 * (0.986 - j0.057)

m6
S(11,11)
S(9,9)

m5

freq (0.0000Hz to 18.00GHz) freq (0.0000Hz to 18.00GHz)

(e) (f)

m7 m8
freq= 9.000GHz freq= 9.000GHz
S(13,13)=0.967 / 166.887 S(15,15)=0.999 / 177.816
impedance = Z0 * (0.017 + j0.115) impedance = Z0 * (4.865E-4 + j0.019)

m7

m8
S(13,13)

S(15,15)

freq (0.0000Hz to 18.00GHz) freq (0.0000Hz to 18.00GHz)

(h)
(g)

Figure 5- 2 Input reflection coefficient of different via models of Figure 5- 1.

Figure 5- 2 shows the reflection coefficients of different via models. From

Figure 5- 2(c) tt can be seen that multiple smaller via has small reflection coefficient

73
compare to other models. So this kind of via is more suitable especially for
grounding.

5.1.2 DC Blocking Capacitor Simulation

Simulation setup of 10 pF DC blocking capacitor is given in Figure 5- 3. We
have added the footprint in order to add more parasites in the SMT models. Although
we haven’t use all models except Kemet, simulation result of four capacitors forward
transmission are shown in Figure 5- 4.

sc_kmt_C0G_06035_D_19960828 Term
S-PARAMETERS Term Z0603
SMT_Pad C36 Term2
Term1 Z0603_1 PART_NUM=C0603C100D5G 10pF Num=2
S_Param Num=1
SMT_Pad ModelType=MW Temperature=25 Z=50 Ohm
SP1 Z=50 Ohm
Pad1 SMT_Pad="Pad1"
Start=0 GHz
W=0.8 mm
Stop=18 GHz
L=0.3 mm
Step=0.1 GHz
PadLayer="bond"
SMO=0.12 mm
SM_Layer="solder_mask"
PO=-0.15 mm
Term sc_atc_100_CDR11BG_J_19960828
MSub Z0603
N Term3 C44 Term
Num=3 Z0603_2 Term4
MSUB PART_NUM=ATC100A100JCA150 10pF
Zin Z=50 Ohm ModelType=MW
MSub1 Num=4
H=0.254 mm Zin Z=50 Ohm
Er=3.48 Zin1
Mur=1 Zin1=zin(S11,PortZ1)
Cond=5.8e7 Zin4=zin(S77,PortZ1)
Hu=1.0e+033 mm Zin3=zin(S55,PortZ1)
T=0.035 mm Zin2=zin(S33,PortZ1)
TanD=0.0037 sc_phl_CMC_0603_5_19920918 Term
Rough=0.001 mm Term Z0603 C45
Z0603_3 Term6
Term5 PART_NUM=222257811523 10pF
ModelType=MW Num=6
Num=5 Z=50 Ohm
Z=50 Ohm

TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal

Disp
Temp DisplayTemplate
disptemp1 sc_mrt_MC_GRH110C0G050_D_19960828
"S_Params_Quad_dB_Smith" Term Z0603 C46 Term
Term7 Z0603_4 PART_NUM=GRH110C0G100D050 10pF Term8
Num=7 ModelType=MW Num=8
Z=50 Ohm Z=50 Ohm

Figure 5- 3 Schematic for SMT capacitor model simulation.

10
5
Philips
0
Forward Transmission dB

-5
-10
-15 Kemet ATC
-20
-25
-30
-35
-40
Murata
-45
-50
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency GHz

Figure 5- 4 Forward transmission vs frequency characteristics for 10 pF capacitor, Kemet-solid

line star, ATC-circle line, Philips-star line and Murata-triangle line.

74
5.1.3 RF Choke
RF choke is one of the important parts of the LNA design. This will allow the
biasing the active device and in the same time prevents the RF signal move toward
the DC line. Figure 5- 5 shows the simulation setup for the Layout of RF choke.

T erm
T erm3
MSub Num=3
Z=50 Ohm
MSUB
MSub1
H=0.254 mm
Er=3.66
Mur=1
C4
Cond=5.8e7
Hu=1.0e+033 mm
T =0.035 mm
T anD=0.0037 sc_kmt_X7R_08055_M_19960828
Rough=0.001 mm C32
PART_NUM=C0805C104M5R 100nF
Vtest=1
T emperature=25
SMT_Pad="Pad2"

SMT _Pad

SMT _Pad
C3
Pad2
W=1.22 mm sc_kmt_C0G_06035_J_19960828
L=0.457 mm C33
PadLayer="bond" PART _NUM=C0603C221J5G 220pF
SMO=0.12 mm Temperature=25
SM_Layer="solder_mask" SMT _Pad="Pad1"
PO=-0.23 mm

C2
SMT_Pad
sc_kmt_C0G_06035_J_19960828
SMT _Pad C34
Pad1 PART _NUM=C0603C101J5G 100pF
W=0.8 mm Temperature=25
L=0.3 mm SMT _Pad="Pad1"
PadLayer="bond"
SMO=0.12 mm
SM_Layer="solder_mask"
PO=-0.15 mm
C1

sc_kmt_C0G_06035_D_19960828
S-PARAMETERS C35
PART _NUM=C0603C100D5G 10pF
S_Param Temperature=25
SMT _Pad="Pad1"
SP1
Start=4 GHz
Stop=12 GHz
Step=0.1 GHz

R1 sr_ims_RC-I_0603_G_19950814
R4
PART_NUM=RC-I-0603-10R0-G 10 Ohm
SMT_Pad="Pad1"

TechInclude_NEC_ACTIVELIBRARY
NEC_ACT IVELIBRARY_Lib
File=Nominal

N
Zin

Zi n
Zi n1
Zi n1=zi n(S11,PortZ1)

Term
Term Term2
Term1 Num=2
Num=1 Z24DCpath
Z24DCpath_1 Z=50 Ohm
Z=50 Ohm
Model Type=MW

Figure 5- 5 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220 pF, C4=100nF
and R1=43 Ω.

75
 m1 m2
freq=6.000GHz freq=9.000GHz
dB(S(2,1))=-0.497 dB(S(2,1))=-0.213
0 m2
m1
Forward Transmission dB(S(2,1))

-1

-2

-3

-4

-5
4 5 6 7 8 9 10 11 12

Frequency GHz
Figure 5- 6 Forward transmission vs frequency simulation result of Figure 5- 5.

m1 m2
freq=6.000GHz freq=9.000GHz
dB(S(3,1))=-34.453 dB(S(3,1))=-39.019
-20
Forward Transmission dB(S(3,1))

-30
m1
m2
-40

-50

-60
4 5 6 7 8 9 10 11 12

Frequency, GHz
Figure 5- 7 Forward transmission vs frequency simulation result of Figure 5- 5.

76
 m1 m2
freq=6.000GHz freq=9.000GHz
dB(S(1,1))=-10.983 dB(S(1,1))=-18.933
0

m1
Input Reflection dBS(1,1)

-10

m2
-20

-30

-40

-50
4 5 6 7 8 9 10 11 12

Frequency GHz

Figure 5- 8 Input reflection coefficient vs frequency simulation result of Figure 5- 5.

Figure 5- 6 to Figure 5- 8 shows the simulation result of layout of RF choke.

From these results it is clear that this RF choke gives good RF blocking towards the
DC path (Port 3) and better forward transmission between port-1 and port-2 within
the required bandwidth (6-9 GHz).

5.1.4 LNA with Matching Network at 8.5 GHz

There are two LNA modules are design with slightly modifying the matching
network at 8.5 GHz and. At the same time the DC blocking and decoupling
capacitors value were changed.

LNA module-1
Figure 5- 9 shows the LNA with exact matching network which is described
in the previous chapter in section 4.12.1(Matching Network at 8.5 GHz).

77
 V_DC I_Prob e
SRC1 IDS
Vdc=VDS V

Va r
Eq n VAR
VAR3
VDS=3
Z24m
Z24m_1
ModelType=MW

Z0 8 sc_kmt_X7R_080 55_M_199 60828

Z0 8_11 C30
ModelType=MW PART_N UM=C080 5C104M5 R 100nF
Vtest=1
Temper ature=25
SMT_Pa d="Pad2"

Z0 8 sc_k mt_C0G_0 6035_J_19 960828

Z0 8_10 C29
Mo delType=MW
PART_NUM=C0 603C221J 5G 220pF
Temp erature=25
SMT_ Pad="Pad1 "

Z08
sc_kmt_ C0G_0603 5_J_19960 828
Z08_ 9 C28
Mode lType=MW
PART_N UM=C0603 C101J5G 100pF
Tempera ture=25
SMT_Pad ="Pad1"

N OPTIONS
SMT_Pad Z08
sc_kmt_C0G_060 35_D_199 60828
SMT_Pad Zin Option s Z08_8
Option s1 C31
SMT_Pa d Zin ModelType=MW
SMT_ Pad PART_N UM=C060 3C100D5 G 10pF
Pad2 Zin1 Temp=16.85
Pad1 Tnom=25 Temper ature=25
W=1.22 mm Zin1 =zin(S11,PortZ1) SMT_Pa d="Pad1"
W=0 .8 mm
L=0.457 mm M eas Mea sEqn
L=0.3 mm Eq n
PadLay er="bond" mea s1
PadL ayer="bon d" SMO=0 .15 mm
SMO=0.15 mm
SM_Lay er="solde r_mask" Tec hInclude_N EC_ACTIVELIBRARY
SM_L ayer="solder_mask"
PO=-0.2 28 mm NEC _ACTIVEL IBRARY_L ib
PO=- 0.15 mm File =Nominal
sr_ims _RC-I_060 3_G_1995 0814
MSub S-PARAMETERS R3
SMT_Pad PART_ NUM=RC- I-0603-43R 0-G 43 Oh m
S_Param
MSU B SP1 SMT_Pad="Pad1"
SMT_Pad
MSu b1 Star t=5 GHz Va r VAR
Pad3 H=0 .254 mm Eq n
Stop =10 GHz VAR1
W =0.5 mm
Er=3 .66 Step =0.1 GHz Z0=50
L =0.25 mm Mur =1
PadLayer="bond" CalcNoise=ye s
Con d=5.8e7
SMO=0.15 mm
Hu=1.0e+033 mm
SM_Layer="solder_ma sk" T=0 .035 mm
PO=-0.125 mm Tan D=0.0037
Rou gh=0.001 mm

Z08
Z08 _3
Mod elType=MW
sc_kmt_C 0G_06035 _D_19960 828 S2P sc _kmt_C0G_06035_D _19960828
C36 SNP1 C3 7
PART_NU M=C0603 C100D5G 10pF File="NE351 2S02v2_2 -18_2_20.s 2p" s r_avx_CR _05_J_199 60828 PART_NUM=C0603C10 0D5G 10pF
R5
Temperature=25 Te mperature=25
PART_NUM=CR05-3R 9J 3.9 Ohm
SMT_Pad ="Pad1" SMT_Pad="Pa d1"
Z2 4m SMT_Pad="Pad3"
M TEE_ADSM LOTL2
C M TEE_ADS M LOTL6
C TL6
M LO C M TEE_ADS TL2
M LO C M TEE_ADS
Tee1 TL3 Tee2 TL5 Tee3 TL7 Tee4 1 2 Tee4 Tee3TL7 TL5
Tee2 Tee1
TL3
M LO
M LI N TL4
C M TEE_ ADS M LI N M LOTL8
CM L I NM TEE_ADS Z2 4m_2 M TEE_AD
TL8
S
M LO C M LI N MMTEE_AD
LI N STL4
M LO C M LI N
Ref

Z25_Mlin e ModelType=MW Z25_Mlin e Z25_ Mline

Z25_Mlin e_2 Z0 603 Z25_Mlin e_1 Z0402 Z0603 Z25_ Mline_3 Te rm
ModelTy pe=MW Z0 603_1 ModelTy pe=MW Z0402_1 Z0603_2 Mode lType=MW Te rm2
Term Mo delType=MW ModelTy pe=MW ModelTyp e=MW Nu m=2
Z30 Z3 5
Term1 Z=Z0
Z30_1 zzzz zzzz Z3 5_1 Va r
Eq n VAR
Num=1 Va r
Eq n VAR L1 =Z1 mm
Z=Z0 L1=X1 mm zzzz zzzz_1 VAR8
VAR7 L2 =Z2 mm
L2=X2 mm Mode lType=MW Z1=2
X1=2.1 L3 =Z3 mm Z2=7
L3=X3 mm
X2=2 L4 =Z4 mm
L4=X4 mm Z3=2
X3=2 L5 =Z5 mm
L5=X5 mm Z4=2.5
X4=3.5 L6 =Z6 mm Z5=3
L6=X6 mm
X5=3.57 L7 =Z7 mm
L7=X7 mm Z0 8 Z6=2
X6=1.25 Mo delType=MW
ModelTyp e=MW Z0 8_2 Z7=4
X7=2.38 Mo delType=MW

sr_ims_RC-I_0 603_G_19 950814

R4
PAR T_NUM=R C-I-0603-1 0R0-G 10 Ohm
SMT_Pad="Pad 1"

Z08
sc_ kmt_C0G_ 06035_D_1 9960828
Z08_7
C35
ModelTyp e=MW
PAR T_NUM=C 0603C100 D5G 10pF
Temperature=2 5
SMT_Pad="Pad 1"

Z08
Z08_6 sc _kmt_C0G_06035_J_ 19960828
ModelTyp
C3 4e=MW
PART_NUM=C0603C10 1J5G 100p F
Te mperature=25
SMT_Pad="Pa d1"

Z08
sc _kmt_C0G_06035_J _19960828
Z08_5
C 33
ModelTyp e=MW
PART_NUM=C0603C22 1J5G 220 pF
Te mperature =25
SMT_Pad="Pad1"

Z08
sc_ kmt_X7R_0 8055_M_1 9960828
Z08_ 4
C32
Mode lType=MW
PAR T_NUM=C 0805C104 M5R 100nF
Vtes t=1
Temperature=2 5
SMT_Pad="Pad 2"

Va r
Eq n VAR
V_DC
VAR4
SRC2
VGS=-0.17
Vdc=VGS V

Figure 5- 9 Simulation setup of the LNA module-1with input and out put matching networks.

Figure 5- 10 and Figure 5- 11 shows the simulation resuls of layout look like
LNA which matching networks were at 8.5 GHz. From the power gain curve (Figure
5- 10) it can be seen that the power gain is almost flat from 6 GHz to 8.5 GHz with
12.8 dB value. After 8.5 GHz the gain goes down to 10.2 dB point which is within
the design specification. And the power gain deviation between 6 GHz and 9 GHz is
2.6 dB. On the other hand from noise figure (Figure 5- 11) it can be seen that actual
noise figure is almost flat with less than 1 dB value. Since the matching was done at
8.5 GHz, so the actual noise figure is same as minimum noise figure at that
frequency. After this matching frequency actual noise frequency goes to 1.2 dB at 9
GHz which is within the design specifications.

78
 m11 m13
freq=6.000GHz freq=9.000GHz
dB(S21)=12.883 dB(S21)=10.260
20
Power Gain dB(S(2,1))

15 m11

m13
10

0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Frequency GHz

Figure 5- 10 Power gain vs frequency of LNA module-1.

m14 m15
freq=6.000GHz freq=8.500GHz
nf(2)=0.943 nf(2)=0.875
5

4
Noise Figure dB

2
m14 m15
1

0
5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

Frequency GHz
Figure 5- 11 NF vs frequency (LNA module-1); star line- actual noise and solid line-minimum
noise.

LNA module-2
Figure 5- 12 shows the LNA with changing the structure of matching network
at 8.5 GHz. Same design procedure is used as described in the previous chapter in

79
section 4.12.1 (Matching Network at 8.5 GHz). Due to simplicity all descriptions are
avoided and final layout is shown here.
Var
VA R V_ DC
Eqn s r_ i m s _ RC-I_ 0 6 0 3 _ G_ 1 9 9 5 0 8 1 4
VA R3 SRC3
R4
VDD=5 Vd c =VDD V
PART _ NUM =RC-I-0 6 0 3 - 1 5 0 0 -G 1 5 0 Oh m
SM T_ Pa d ="Pa d 2 "

s c _ a tc _ 1 0 0 _ CDR1 1 BG_ J _ 1 9 9 6 0 8 2 8
C2 5
PART _ NUM =ATC1 0 0 A1 0 1 J CA1 5 0 1 0 0 p F
SM T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 1 BG_ J _ 1 9 9 6 0 8 2 8
C2 6
PA RT_ NUM =ATC1 0 0 A1 0 0 J CA1 5 0 1 0 p F
SM T_ Pa d ="Pa d 1 "
S-P ARAMETERS
OPTIONS S_ Pa ra m
Op ti o n s SP1
Op ti o n s 1 Sta rt=5 .5 GHz
Te m p =1 6 .8 5 Sto p =9 .5 GHz
Tn o m =2 5 Ste p =0 .1 GHz
Ca l c No i s e = y e s
M e as M e a s Eq n
Eqn
m eas 1
Var VAR
Eqn
VAR1
Z0 =5 0

s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C2 4
PART_ NUM =ATC1 0 0 A3 R0 BP 1 5 0 3 p F
SM T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C2 7
Te c h In c l u d e _ NEC_ ACTIVEL IBRARY PART_ NUM =ATC1 0 0 A1 R5 BP1 5 0 1 .5 p F
NEC_ ACTI VEL IBRARY_ L i b SM T_ Pa d ="Pa d 1 "
Fi l e =No m i n a l

SM T_ Pa d

SM T_ Pa d
SM T_ Pa d
Pa d 2
W=0 .5 5 m m
SM T_ Pa d
L =0 .4 m m
Pa d 1
Pa d L a y e r="b o n d "
W=0 .5 5 m m
SM O=0 .1 2 m m
L =0 .6 3 m m
SM _ L a y e r="s o l d e r_ m a s k "
Pa d L a y e r="b o n d "
PO=0 m m
SM O=0 .1 6 m m
M Su b
SM _ L a y e r="s o l d e r_ m a s k "
PO=0 m m
M SUB
M Su b 1
H=0 .2 5 4 m m
Er=3 .4 8
M u r=1
Co n d =5 .8 e 7
Hu =1 .0 e +0 3 3 m m
T=0 .0 3 5 m m
Ta n D=0 .0 0 3 7
Ro u g h =0 .0 0 1 m m

S2 P
SNP 2
Fi l e ="NE3 5 1 2 S0 2 v 2 _ 2 -1 8 _ 2 _ 2 0 .s 2 p "
Ty p e =To u c h s to n e
s r_ i m s _ RC- I_ 0 6 0 3 _ G_ 1 9 9 5 0 8 1 4
R6
s c _ a tc _ 1 0 0 _ CDR1 2 B G_ B_ 1 9 9 6 0 8 2 8 PART_ NUM = RC-I-0 6 0 3 -3 R9 0 -G 3 .9 Oh m s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C3 2 SM T_ Pa d ="Pa d 2 " C3 3
PART_ NUM =ATC1 0 0 A 1 R5 BP1 5 0 1 .5 p F PART_ NUM =A TC1 0 0 A1 R5 BP1 5 0 1 .5 p F
SM T_ Pa d ="Pa d 1 " SM T_ Pa d ="P a d 1 "
Te rm
1 2

Te rm 2
Re f

Nu m =2
Te rm Z=5 0 Oh m
Te rm 1
Nu m =1
Z=5 0 Oh m

s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C3 1
PART_ NUM =ATC1 0 0 A1 R5 B P1 5 0 1 .5 p F
SM T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C2 8
PART_ NUM = ATC1 0 0 A3 R0 BP1 5 0 3 p F
SM T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 1 BG_ J _ 1 9 9 6 0 8 2 8
C2 9
PART_ NUM =ATC1 0 0 A1 0 0 J CA1 5 0 1 0 p F
SM T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 1 BG_ J _ 1 9 9 6 0 8 2 8
C3 0
PART_ NUM =ATC1 0 0 A1 0 1 J CA 1 5 0 1 0 0 p F
SM T_ Pa d = "Pa d 1 "

D1 0 l a y
D1 0 l a y _ 1 s r_ i m s _ RC-I_ 0 6 0 3 _ G_ 1 9 9 5 0 8 1 4
M o d e l Ty p e =M W R3
PART_ NUM =RC-I-0 6 0 3 -1 0 R0 -G 1 0 Oh m
SM T_ Pa d ="Pa d 2 "

V_ DC
VAR
Eqn
SRC2
Var
VAR4
Vd c =VGG V
VGG= -0 .1 7

Figure 5- 12 Simulation setup of the LNA module-2 with input and output matching network at
8.5 GHz

Figure 5- 13 and Figure 5- 14 shows the simulation resuls of layout look like
LNA which matching networks were at 8.5 GHz. From the power gain curve (Figure
5- 13) it can be seen that the power gain is almost flat from 6 GHz to 7.5 GHz with
14.7 dB value. After 7.5 GHz the gain goes down to 12 dB point which is within the
design specification. And the power gain deviation between 6 GHz and 9 GHz is 2.7

80
dB. On the other hand from noise figure (Figure 5- 14) it can be seen that actual noise
figure is almost flat with less than 1.1 dB value and actual noise figure is same as
minimum noise figure at 8 GHz frequency. After this matching frequency actual
noise frequency goes to 0.9 dB at 9 GHz which is within the design specifications.
m11 m13
freq= 6.000GHz freq= 8.200GHz
dB(S21)=14.712 dB(S21)=13.703
20
Power Gain dB(S(2,1))

m11
15 m13

10

0
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5
Frequency GHz
Figure 5- 13 Power gain vs frequency of LNA module-2

m14 m15
freq=6.000GHz freq=9.000GHz
nf(2)=1.066 nf(2)=0.878
1.3
1.2
Noise Figure dB

1.1 m14

1.0
m15
0.9
0.8
0.7
0.6
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5
Frequency GHz
Figure 5- 14 NF vs frequency (LNA-modele-2); star line- actual noise and solid line-minimum
noise

Table 3 LNA module-1 and -2 comparisons

LNA freq Gain NF
Module-1 At 6 GHz 12.9 dB 0.94

81
 At 9 GHz 10.3 dB 0.87
Module-2 At 6 GHz 14.7 dB 1.06
At 9 GHz 13.7 dB 0.88

From this comparison it is clear both LNA module-1 and LNA module-2 meet the
design specifications.

5.1.5 LNA with Matching Network at 9 GHz

V_DC I_Probe
SRC3
IDS1
Vdc=VDS V

sc_kmt_X7R_06035_J_19960828
C44
PART_NUM=C0603C103J5R 10nF
SMT_Pad="Pad1"

sc_kmt_C0G_06035_J_19960828
C25
PART_NUM=C0603C221J5G 220pF
SMT_Pad="Pad1"

sc_kmt_C0G_06035_J_19960828
C13
PART_NUM=C0603C101J5G 100pF
SMT_Pad="Pad1"

sc_kmt_C0G_06035_D_19960828
C24
PART_NUM=C0603C1R0D5G 1pF
SMT_Pad="Pad1"

sr_ims_RC-I_0603_G_19950814
R2
PART_NUM=RC-I-0603-43R0-G 43 Ohm
SMT_Pad="Pad1"

S2P sc_kmt_C0G_06035_D_19960828
SNP1 C43
File="NE3512S02v2_2-18_2_20.s2p" PART_NUM=C0603C100D5G 10pF
SMT_Pad="Pad1"

1 2

Ref

sc_kmt_C0G_06035_D_19960828
C42 Term
Term PART_NUM=C0603C100D5G 10pF Term2
Term1 SMT_Pad="Pad1" Num=2
Num=1 Z=50 Ohm
Z=50 Ohm sr_avx_CR_05_J_19960828
R6
PART_NUM=CR05-3R9J 3.9 Ohm
SMT_Pad="Pad3"

DC
S-PARAMET ERS
DC
S_Param DC1
sr_ims_RC-I_0603_G_19950814 SP1 SweepVar="VDS"
R4 Start=5 GHz Start=0
PART_NUM=RC-I-0603-10R0-G 10 Ohm Stop=10 GHz Va r
VAR Stop=3
Eq n
SMT_Pad="Pad1" Step=0.1 GHz VAR2 Step=0.1
CalcNoise=yes VDS=3
VGS=-0.17
OPT IONS
NEC_FET
Options SMT_Pad Q1
Options1 partName=NE3512S02_v118
Temp=16.85 SMT_Pad
Tnom=25 MSub Pad1
VAR W=0.8 mm
Va r
Eq n
VAR1 MSUB L=0.3 mm
Z0=50 MSub1 PadLayer="bond"
H=0.254 mm SMO=0.15 mm
Er=3.66 SM_Layer="solder_mask"
M eas
Eq n
MeasEqn Mur=1 PO=-0.15 mm
meas1 Cond=5.8e7
sc_kmt_C0G_06035_D_19960828 Hu=1.0e+033 mm SMT_Pad
C41 T=0.035 mm
PART_NUM=C0603C1R0D5G 1pF TanD=0.0037 SMT_Pad
SMT_Pad="Pad1" Rough=0.001 mm Pad3
W=0.5 mm
TechInclude_NEC_ACTIVELIBRARY L=0.25 mm
NEC_ACTIVELIBRARY_Lib PadLayer="bond"
File=Nominal SMO=0.15 mm
SM_Layer="solder_mask"
sc_kmt_C0G_06035_J_19960828 PO=-0.125 mm
N
C40
PART_NUM=C0603C101J5G 100pF Zin
SMT_Pad="Pad1" Zin
Zin1
Zin1=zin(S11,PortZ1)

sc_kmt_C0G_06035_J_19960828
C39
PART_NUM=C0603C221J5G 220pF
SMT_Pad="Pad1"

sc_kmt_X7R_06035_J_19960828
C45
PART_NUM=C0603C103J5R 10nF
SMT_Pad="Pad1"

J11
J11_1 V_DC
ModelType=MW SRC4
Vdc=VGS V

Figure 5- 15 Simulation setup of the LNA with input and out put matching networks.

82
 Figure 5- 16 and Figure 5- 17 shows the simulation resuls of layout look like
LNA which matching networks were at 9 GHz. From the power gain curve (Figure 5-
16) it can be seen that the power gain deviation is 3.5 dB between 6 GHz and 9 GHz
frequency and the average value is 11 dB which is within the design limit. But for
this design the power deviation is more compare to other two designs (Module-1 and
Module-2) On the other hand from noise figure (Figure 5- 17) it can be seen that
actual noise figure is almost flat l dB value which also meet the design specification.

m11 m13
freq=6.000GHz freq=9.000GHz
dB(S21)=14.913 dB(S21)=11.382
20
Power Gain dB(S(2,1))

m11
15
m13

10

0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Frequency GHz
Figure 5- 16 Power gain vs frequency.

m14 m15
freq= 6.000GHz freq= 9.000GHz
nf(2)=0.895 nf(2)=1.013

3.0

2.5
Noise Figure dB

2.0

1.5
m15
1.0 m14

0.5
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Frequency GHz
Figure 5- 17 Noise figure vs frequency; star line- actual noise and solid line-minimum noise.

5.1.6 Comparison of two LNA

Figure 5- 18 and Figure 5- 19 show the comparison of LNA modelue-1
which matching networks were done at 8.5 GHz and LNA with matching network at

83
9 GHz. Compare to LNA module-1, the second design gives more gain in the
sidebands and less noise in the higher band. But the power gain deviation between 6
GHz and 9 GHz is less for LNA module-1 compare to LNA with matching at 9 GHz.
It is also important to have less power gain deviation within the bandwidth. So
compare to power gain deviation, LNA with 8.5 GHz matching gives better result
than LNA with 9 GHz mathing.
16

14
Power Gain dB(S(2,1))

12

10

2
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

Frequency GHz

Figure 5- 18 Power gain vs frequency; solid line at 8.5 GHz matching and dot line at 9 GHz
matching.

4
Noise Figure

0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

Frequency GHz

Figure 5- 19 Noise figure vs frequency; dot line-for 9 GHz and solid line-8.5 GHz

84
5.1.7 LNA layout
After getting the RF choke we have designed the input and output matching
network. We have created two layout modules using the 8.5 GHz matching network.
From Figure 5- 20 and Figure 5- 21, it can be seen that final layout design for the
LNA is ready for manufacture. In the same time all manufacturers’ components and
via are added in the layout.

Figure 5- 20 Complete layout of LNA module-1; C1, C2, C3, C7=10 pF; C4, C8=100 pF; C5,
C9=220 pF; C6, C10=100 nF.

85
Figure 5- 21Complete layout of LNA module-2; C1, C2,C3, C7=1.5 pF; C4, C8=3 pF; C5, C9=10
pF; C6, C10=100 pF. R1=3.9 ohm, R2=10 ohm, R3=150 ohm and Q1= NE3512S02

86
5.2 Measurements

LNA module-1
After doing measurement with using Agilent 8703A vector network analyzer,
we have saved our data as a S-parameter file. Then using ADS we have extracted the
measurement data.
Measurement setup:
Frequency 5-10 GHz
VD=3 V
VG=-0.53 V (Design value was -0.17 V)
IDS=17 mA (Design value was 20 mA)

Meas MeasEqn S2P

S-PARAMETERS Eqn
meas1 SNP1
S_Param File="RESULT.S2P"
SP1
N
Start=4 GHz 1 2

Stop=10 GHz Zin

Ref

Step=0.1 GHz Zin

CalcNoise=yes Zin1
Zin1=zin(S11,PortZ1) Term Term
Term1 Term2
OPTIONS Num=1 Num=2
Z=50 Ohm Z=50 Ohm
Options
Options1 Var VAR
Temp=16.85 Eqn
VAR1
Tnom=25 Z0=50

TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal

Figure 5- 22 Schematic for data display of measured LNA modele-1.

m1 m2
freq= 6.000GHz freq= 8.500GHz
dB(S21)=14.774 dB(S21)=7.314
20
Power Gain dB(S(2,1))

m1
15

10
m2

0
4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

Frequency GHz

Figure 5- 23 Power gain of the LNA after implementation.

LNA module-2

87
 OPTIONS S-PARAMETERS
Options S_Param
Options1 SP1
Temp=16.85 Start=5.5 GHz
Tnom=25 Stop=9.5 GHz
Step=0.1 GHz S2P
SNP1
CalcNoise=yes
File="A.S2P"
Type=Touchstone
Meas
Eqn
MeasEqn VAR
Var
meas1 Eqn N
VAR1
Zin 1 2
Z0=50
Ref

Zin Term
Zin1 Term Term2
Zin1=zin(S11,PortZ1) Term1 Num=2
Num=1 Z=50 Ohm
Z=50 Ohm

TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal

Figure 5- 24 Schematic for data display of measured LNA modele-2

m5 m6
freq=6.000GHz freq=9.000GHz
dB(S(2,1))=9.180 dB(S(2,1))=4.220
10
m5
9

8
Power Gain dB

5
m6
4

3
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5

Frequency GHz

Figure 5- 25 LNA module-2

From the measurement data it is clear that the implemented LNA’s gain is less than
the specifications.

88
 m1 m4
freq= 6.000GHz freq=9.000GHz
dB(S(4,3))=14.774 dB(S(2,1))=4.220
m3 m2
freq= 6.000GHz freq=9.000GHz
dB(S(2,1))=9.180 dB(S(4,3))=1.930
20

m1 Module - 1
15
Power Gain dB

10
m3

5
m4
m2
Module - 2
0

-5
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5

Frequency GHz

Figure 5- 26 Comparison between LNA module -1 and -2. Solid line for LNA module -1 and star
line for module -2.

5.3 LNA Post-manufactured Simulation

LNA Module 2: with parasitic
Figure 5- 27 shows the simulation setup for post-manucactured simulation.
This is used for debugging the measurement result of implemented LNA module-2.
Component layout of via ground, inductance and capacitance are added in the Source
terminal of the FET and keeping other parameters constant The capacitor value is
swept from 1 pF to 100 pF and in the same time the inductor value is swept from 1
nH to 5 nH with small resistance (2 ohm). Figure 5- 28 shows the simulation result
with new arrangemet of parasistic effect in the source(S) terminal of the transistor.
Now there are some resonances at lower band. At 6.5 GHz with C=1pF and L=3nH
the power gain curve is same as LNA measurement gain curve but with higher
magnitude. In the simulation, it is also seen that at the higher value of capacitance the
gain curve is almost flat with higher magnitude. In the LNA measurement it was seen
by putting finger on the circuit. The gain increased and became more flat over the
band.

89
 Var VAR V_ DC
Eqn s r_ i m s _ RC-I_ 0 6 0 3 _ G_ 1 9 9 5 0 8 1 4
VAR3 SRC3
R4
VDD=5 Vd c =V DD V
PART_ NUM =RC-I-0 6 0 3 -1 5 0 0 -G 1 5 0 Oh m
SM T_ P a d ="Pa d 2 "

s c _ a tc _ 1 0 0 _ CDR1 1 BG_ J _ 1 9 9 6 0 8 2 8
C2 5
PART_ NUM =ATC1 0 0 A1 0 1 J CA1 5 0 1 0 0 p F
SM T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 1 BG_ J _ 1 9 9 6 0 8 2 8
C2 6
PART_ NUM = ATC1 0 0 A1 0 0 J CA1 5 0 1 0 p F
SM T_ Pa d ="P a d 1 "
S-PARAMETERS
OP TIONS
S_ Pa ra m
Op ti o n s SP1
Op ti o n s 1 Sta rt=5 .5 GHz
Te m p =1 6 . 8 5
Sto p =9 .5 GHz
Tn o m =2 5
Ste p =0 .1 GHz
Ca l c No i s e = y e s
M eas M e a s Eq n
Eqn
m ea s 1
Var VAR
Eqn
VAR1
Z0 =5 0

s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C2 4
PART_ NUM =ATC1 0 0 A3 R0 BP1 5 0 3 p F
SM T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B _ 1 9 9 6 0 8 2 8
C2 7
Te c h In c l u d e _ NEC_ ACTIVEL IBRARY PART_ NUM =ATC1 0 0 A1 R5 BP1 5 0 1 .5 p F
NE C_ ACTIVEL IBRA RY_ L i b SM T_ Pa d ="Pa d 1 "
Fi l e =No m i n a l

SMT_Pad

SM T_ Pa d
SMT_Pad
Pa d 2
W=0 .5 5 m m
SM T_ Pa d
L =0 .4 m m
Pa d 1
W=0 .5 5 m m Pa d L a y e r="b o n d "
SM O=0 .1 2 m m
L =0 .6 3 m m
SM _ L a y e r="s o l d e r_ m a s k "
Pa d L a y e r="b o n d "
PO=0 m m
SM O=0 .1 6 m m
SM _ L a y e r="s o l d e r_ m a s k "
MSub
PO=0 m m M SUB
M Su b 1
H=0 .2 5 4 m m
Er=3 .4 8
M u r=1
Co n d =5 .8 e 7
Hu =1 .0 e +0 3 3 m m
T=0 .0 3 5 m m
Ta n D=0 .0 0 3 7
Ro u g h =0 .0 0 1 m m

L
L3
L =L a n H
R=Ra Oh m

C
C3 5
C= Ca p F

GNDv i a
GNDv i a _ 2
M o d e l Ty p e =M W
S2 P
SNP2
Fi l e = "NE3 5 1 2 S0 2 v 2 _ 2 -1 8 _ 2 _ 2 0 .s 2 p "
Ty p e =To u c h s to n e
s r_ i m s _ RC-I_ 0 6 0 3 _ G_ 1 9 9 5 0 8 1 4
R6
s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8 PART _ NUM =RC-I-0 6 0 3 -3 R9 0 -G 3 .9 Oh m s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C3 2 SM T _ Pa d ="Pa d 2 " C3 3
PART_ NUM =ATC1 0 0 A1 R5 BP1 5 0 1 .5 p F PART_ NUM =ATC1 0 0 A1 R5 BP1 5 0 1 .5 p F

SM T_ Pa d ="Pa d 1 " SM T_ P a d ="Pa d 1 "

1 2

Te rm Te rm
Re f

Te rm 1 Te rm 2
Nu m =1 Nu m = 2
Z=5 0 Oh m Z=5 0 Oh m

Var
Eqn
VAR PARAME TER SWEEP
VAR5
L a =1 Pa ra m Swe e p
Ca =1 Swe e p 1
Ra =2 Swe e p Va r="L a "
Si m In s ta n c e Na m e [ 1 ]="SP1 "
L Si m In s ta n c e Na m e [ 2 ]=
L1 Si m In s ta n c e Na m e [ 3 ]=
C
L= La nH Si m In s ta n c e Na m e [ 4 ]=
C3 4
R= Ra Oh m Si m In s ta n c e Na m e [ 5 ]=
C= Ca p F Si m In s ta n c e Na m e [ 6 ]=
Sta r t=1
Sto p =5
Ste p =1

GNDv i a P ARAMETER SWEEP

GNDv i a _ 1
M o d e l Ty p e =M W
Pa ra m Swe e p
Swe e p 2
Swe e p Va r ="Ca "
Si m In s ta n c e Na m e [1 ]="Swe e p 1 "
Si m In s ta n c e Na m e [2 ]=
Si m In s ta n c e Na m e [3 ]=
Si m In s ta n c e Na m e [4 ]=
Si m In s ta n c e Na m e [5 ]=
Si m In s ta n c e Na m e [6 ]=
Sta rt=1
Sto p =1 0 0
Ste p =1 0

s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C3 1
P ART_ NUM =ATC1 0 0 A1 R5 BP1 5 0 1 .5 p F
S M T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 2 BG_ B_ 1 9 9 6 0 8 2 8
C2 8
P ART_ NUM =ATC1 0 0 A3 R0 BP1 5 0 3 p F
S M T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 1 BG_ J _ 1 9 9 6 0 8 2 8
C2 9
P ART_ NUM =ATC1 0 0 A1 0 0 J CA1 5 0 1 0 p F
S M T_ Pa d ="Pa d 1 "

s c _ a tc _ 1 0 0 _ CDR1 1 BG_ J _ 1 9 9 6 0 8 2 8
C3 0
PA RT_ NUM =ATC1 0 0 A1 0 1 J CA1 5 0 1 0 0 p F
SM T_ Pa d ="Pa d 1 "

D1 0 l a y
D1 0 l a y _ 1
s r_ i m s _ RC-I_ 0 6 0 3 _ G_ 1 9 9 5 0 8 1 4
M o d e l Ty p e =M W
R3
PART_ NUM =RC-I-0 6 0 3 -1 0 R0 -G 1 0 Oh m
SM T _ Pa d ="Pa d 2 "

V_ DC
VAR
Eqn
Var
SRC2 VAR4
Vd c =VGG V
VGG=-0 .1 7

Figure 5- 27 LNA post manufactured simulation

90
 m17 m16
freq= 6.500GHz freq= 7.000GHz
dB(S(2,1))=38.023 dB(S(2,1))=22.881
Ca=1.000000, La=3.000000 Ca=1.000000, La=1.000000

50

40
m17
Power Gain dB(S(2,1))

30
m16
20

10

-10
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

Frequency GHz

Figure 5- 28 Power gain vs frequency

m19 m18
freq= 6.500GHz freq= 6.500GHz
nf(2)=0.892 nf(2)=1.427
Ca=100.000000, La=5.000000 Ca=1.000000, La=1.000000

5
Noise Figure

2
m18
m19
1

0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

Frequency GHz

Figure 5- 29 Noise figure

91
6 Conclusion and Further work
The designed LNA shows good gain but over a narrower bandwidth than the
desired specifications. This can be explained by grounded-source parasitic effects.
Post-manufactured simulations were done in order to identify the origin of the
problem. The post-manufactured simulations were done by replacing ideal ground of
the FET source terminal with the layout component of grounded-via. Moreover in
order to add more parasitic effects, additionally inductor and capacitor were also
added. The capacitor value is swept from 1 pF to 100 pF and in the same time the
inductance value is swept from 1 nH to 5 nH with small resistance (2 ohm). Some
resonances at lower band were identified. At 6.5 GHz with C=1pF and L=3nH the
gain curve is same as LNA measurement gain curve but with higher magnitude. In
the simulation, it was also seen that at the higher value of capacitance the gain curve
is almost flat with higher magnitude.
In conclusion, from the post-manufactured simulations, it can be assumed that
transistor’s source terminal was not properly grounded. It is also known that at the
RF/MW frequency the lumped elements behavior is quite different from that at low-
frequency and we can conclude now that accurate capacitor and inductor S-
parameters models should also be used, when they are available. A better option is to
implement, whenever it is possible, passive components using transmission lines that
will behave like passive components, e.g. Capacitors, inductors. These components
can be implemented by carefully choosing the transmission line characteristics
impedance (Z0) and line length line length (l) and then, by accurate simulation using
electromagnetic simulations as Momentum in ADS.
Future work for this thesis is at first manufacture the next prototype in a better
process with smaller via holes and better process accuracy.

92
Appendix
1. Lists of S-parameters data of NE3512S02 Hetero-junction FET at different
frequencies are given below. These data are obtained from the manufacturer data file,
NE3512S02v2_2-18_2_20.s2p

2. Lists of minimum noise figure (Fmin) of NE3512S02 Hetero-junction FET at

different frequencies are given below. These data are also obtained from the
manufacturer data file, NE3512S02v2_2-18_2_20.s2p

93
94