library ieee;

use IEEE.std_logic_1164.all;

entity add16b is
port(a,b:in std_logic_vector(15 downto 0);
cin: in std_logic;
cout: out std_logic ;
s:out std_logic_vector(15 downto 0));
end;

component HA is
port (a,b,cin :in std_logic;
s,cout: out std_logic);
end component;

architecture struct of add16b is

signal y: std_logic_vecotr(2 downto 0);
begin
for i 0 to 15 loop
pi: HA port map (a(i), b(i),cin,s(i) ,y(i));
end loop
end;
end ;