library ieee;

use ieee.std_logic_1164.all;
entity addsous is
port(
a,b : in std_logic_vector(15 downto 0);
as: in std_logic;

s : out std_logic_vector(15 downto 0);

carry : out std_logic);
end ;

component add4b is
port(a,b:in std_logic_vector(15 downto 0);
cin: in std_logic;
cout: out std_logic ;
s:out std_logic_vector(15 downto 0));
end component;
component xor4b is
port (a:in std_logic_vector(15 downto 0),
as: in std_logic;
s: out std_logic_vector(15 downto 0));
end component;

architecture struct of addsous is

signal y: std_logic_vector(15 downto 0);

signal p0,p1:std_logic;
begin

p0:xor port map(a,as,y);

p1:add16b port map(y,b, s,carry);

end s;