library ieee;

use IEEE.std_logic_1164.all;

entity main is
port(a,b:in std_logic_vector(3 downto 0);
as: in std_logic;
carry: out std_logic ;
y:out std_logic_vector(6 downto 0));
end;

component addsous is
a,b : in std_logic_vector(3 downto 0);
as: in std_logic;

s : out std_logic_vector(3 downto 0);

carry : out std_logic);
end component;

component aff7seg is
port (
num: in STD_LOGIC_VECTOR (3 downto 0);
seg: out STD_LOGIC_VECTOR (6 downto 0));
end component;

architecture struct of main is

signal p0,p1: std_logic;

begin
p0: addsous port map (a, b,as,s,carry);
p1: aff7seg port map (s, y);

end;