This document describes a logic circuit that performs an XOR operation on each bit of a 4-bit input vector with a single input bit and outputs the result to a 4-bit output vector. It declares an entity called xor with a 4-bit input vector a, a single input bit as, and a 4-bit output vector s. The architecture flot assigns each bit of the output s to be the XOR of the corresponding bit in a and the single input as.
This document describes a logic circuit that performs an XOR operation on each bit of a 4-bit input vector with a single input bit and outputs the result to a 4-bit output vector. It declares an entity called xor with a 4-bit input vector a, a single input bit as, and a 4-bit output vector s. The architecture flot assigns each bit of the output s to be the XOR of the corresponding bit in a and the single input as.
This document describes a logic circuit that performs an XOR operation on each bit of a 4-bit input vector with a single input bit and outputs the result to a 4-bit output vector. It declares an entity called xor with a 4-bit input vector a, a single input bit as, and a 4-bit output vector s. The architecture flot assigns each bit of the output s to be the XOR of the corresponding bit in a and the single input as.