234 CHAPTER 7 / INPUT / OUTPUT Review Questions 7A List three broad classifications of external, or peripheral, devices. 7.2 Whatisihe International Reference Alphabet? 73 What are the major functions ef an LO modute? 74 List and briefly define three techniques for pertorming VO. 7.5 What is the difference between memory-mapped 0 and isolated LO? 746 When a doview interrupt occurs, how does the processor determine, whieh devite issued the interrupt? 2 When a DMA module takes control of a buszand while it retains control of the bis, what does the processor do? Problems IB 73 14 18 16 1 In Section? 3,one advantage and one disadvantage of memory-mapped 10, compart ‘with isolated 1/0. were listed. List two more advantages and b¥o more disadvantagss In virtually-all systems that include DMA modules, DMA access to main memory i) aiven higher priority than CPL access to main memory. WI Consider a disk system with 960 512-byte sectors per track and assiume the disk rola fal 36l10 ipm. A. processor reads one sector trom the disk using interrupt-driven 10), with one interrupt per byte, IL it takes 2.5 (6 to pracess each interrupt, what perceal| fue of the time will the processor spend handling LO (disregard seek time)? Repeat Problem-7.3 using DMA. and assume one interrupt per sector ‘A DMA module iy transferring characters to memory using cyele stealing, frome device transmitting at 9600 bps. The processor is fetching instructions at the rated Lnuillion instructions per second (1 MIPS}. By haw niuch wil (he processor be sowed down due to the DMA activity? |A.32:bit computer has two selector channels aid «ne multiplexor channel. Bach see tor channel supports (wo magnctic disk and two magnetic tape units, The multiplexer channel has two line printers, two card readers, and 1) VDT terminals connected st Assume the following (ranster rates: Disk dive 801) KBytesis. Magnetic tape drive 20 KBytesis Line printer 66 KBytes! Card reader 1.2 KBytesis vbr TKBytesis Estimate the maximum aggregate HO transfer rate in this system ‘A computer consists of a processor and an iO device 2 connected 10 main mem ony M viaa shared bus with a data bus width. of one word. The processor can ee cute a maximum of 10° instructions per second, An average instruction requires fre michine cycles, three of which use the memory bus. A memory read or write opet ation uses one miachine cycle, Suppose that the processor |s continuously exeentieg background” programs that require 95" of its instruction execution rate Put tl any HO insiructions. Assume that one processor cycle equals one bus eycle, Now suppose the L/O device is to be used to transfer very large blocks of data betel M and D. a. If programmed [10 is used and each one-word 1° (ransfer requires the processth to execute two instructions, estigyate the maximum LG data-transfer rate, an wards per second, possible through 1. by, Estimate the same rate if DMA is used.7.9 # KEY-TERMS, REVIEW QUESTIONS, AND PROBLEMS 235. 7.8 A data souice produces 7-bit IRA characters, 10 each of which is appended a parity. bit. Derive an expression for the maximum effective data rate (rate of IRA data bits) over an R-bps line for the following: a Asynchronous transmission, with a 1,S-unit stop bit b: Bit synchronous transmission, with a frame consisting of 48 Control bits and 128 information bits c. Same as (b). with a LO24bit Information field a. Character chronous. with 9 control characters per frame and 16 informal characters e. Same as (d)}, with 128 information characters 7.9 ‘The following problem is based on a Suggested illustration of VO mechanisms in JECKE90] (Figure 7.22); ‘Two boys are playing on either side of a high fence. One of the hoys; named Apple- server, has i beautilul apple tree loaded with delicious apples growing on his side af the fence: he is happy to supply apples to the other boy whenever needed. The other boy, named Apple-earer, loves. to eat apples but hus none. In fact, he must eat his apples at a fixed rate (an apple a day keeps the doctor away), If he eats them taster than that rate, he will get sick. H he eats them slower, he will sulfer malnutrition; Nei ther boy can talk, arid sothe problem is to get apples from Apple-server to Apple: eater at the correct rate. a. Assume that there is an alarm clock sitting on top of the fence and that the clock can have multiple alarm settings. How can the clock be used Lo salve the problem? ‘Draw a timing diagram to illustrate the solution, b, Now assume that there ig no alarm clock. Instead Apple-eater has-a flag that he can wave whenever he needs an apple. Suggest a new solution. Would it be help ful for Apple-server also 10 have a flax? Iso, incorporate this into the sofution, Discuss the drawbacks of this approach. Now lake away the flag and assume the existence of a long piece of siring. Suggest a solution that is superior to that of (b) using the string. Apple-eater Apple-server Figure 722 An Apple Problem236 CHAPTER 7 / INPUT / OUTPUT 7.40. Assuine that one: 16-bit and two B-bit microprocessors are to be intertaced toa tem bus, The following details are given: 1. All microprocessors have the harelware features necessary for any type of d transfer; programmed LQ, interrupt-driven FO, and DMA. 2, All microprocessors have a Lé-bit address bus. 3. Two memory bourils, cach of 64 KBytes capacity. are interfaced with the bus. designer wishes to use a shared memory that is as large as possible, 4 The system bus supports'a maximum of four interrupt Lines and one DMA Tine ‘Make any other assumptions necessary, and a. Give the system bus specifications in termsof number and types of lines b. Describe @ possible protocol for communicating on the busy ie, read intercupt, and DMA sequences, ¢: Explain how the aforementioned des Source: [ALEX93| sare interfaced to the system bus.