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DRS RRR BMH AM KA 4K TD FE Sie WE Fs ES Verification Methodology Manual for Low Power [#] Srikanth Jadcherla [#] Janick Bergeron [8] Yoshio Inoue [3] David Flynn NEkK ATR F ¥ MRM MR KS A Mae we wt ARABAP AIAN TB oe FRIES RE BA BLO TEE A JL AD 9 ET AS} ME EJ AB AS LA wt ot AAR AS 4 SH te MH Be FE, OE I DR HS I AAs AE Aol TE AE DL WR ME ie BH A ET HR EAS HA A 8 ne B (CIP) HE ADU REMEUE DT BRA / (SD im a Ls HAT EMME. ACH : RMA MAAS Hh MAL. 2012. 8 ISBN 978 - 7 - 5124 - 0849-4 L. Offi 1. Dill QM OH Ml. Dewi wt WW. OTM02 rf EB AR AS PBA CIP MH EH (2012) 95 140910 HX, Verification Methodology Manual for Low Power Copyright © 2011 by Synopsys Inc. ,ARM Limited and Renesas Technology Corp. ‘Translation Copyright © 2012 by Bei jing University of Aeronautics and Astronautics Press. ‘All rights reserved. AB PK MHF ALA HE EH Symopsys 22 7 BAT dt AK AR A SE HH ACRE AE oh ae AR 9 EL PY RAMA. BRA. ARTA REL ABS MF: 01 - 2012-5456 S (EW MIED RS Verification Methodology Manual for Low Power (] Srikanth Jadcherla (J Janick Bergeron [8] Yoshio Inoue [38] David Flynn HER AFA Kem HOR Ate AR A AL FR ACH OAL HT AGHA ME EK EBA 37 J CBE 100191) http://www. buaapress. com. cn RATA I .(010) 82317024 fH. (010982328026 PEAAAM -emsbook@gmail. com MBIA) IA . (010) 82316936 ‘RIM rs Be El 4a BR ZS A EA % FRA .TIOX1 000 1/16 GNHK12 FHM +256 FH 201246 8 AME LMR 2012 4F 8 AME 1 AED NEC. 4 000 A ISBN 978-7-5124-0849-4 SEP. 32.00 76 PA BAT ATL JT Bk OF EE Ea) GAH HE AT AI AR. HRA MBIA: (010982317024 Fae Be ARTA EB / BOER AR AE A ILA Pe BR I ABR. EF FARA BEAT DP LF BRA D R iL — FUR. MR REBT / BEAR A HE 1S HF A TASS ws RB EEK HB 5 PL,» Ab Se ie ERS SS ek BAB Tt / MOE TR — FE GE BEDS AEB HY Sos ARERR Hs OE AR TY PR ERA He PEA A BAT BY BD ae I A EA. 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YR, bE OR A AE TS AS TR BS Se yt ABBR F BA DEF AY BRD RE AE A — Dy TY a EE TET BRA HF. Mediatek AH BAA] Mal D> eae TRADEMARKS Synopsys is a registered trademark of Synopsys, Inc. ARM and AMBA are registered trademarks of ARM Limited. “ARM” is used to represent ARM Holdings ples its operating company ARM Limiteds and the regional subsidiaries ARM Inc, 5 ARM KK; ARM Korea Ltd. ; ARM Taiwan Limited; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd. ; ARM Belgium N. V. s AXYS Design Automation Inc. ; AXYS Germany GmbH; ARM Embedded Technologies Pvt. Ltd. ; ARM Norway, SA; and ARM Sweden AB. All other brands or product names are the property of their respective holders. DISCLAIMER, Alll content included in this Verification Methodology Manual for Low Power is the result of the combined efforts of ARM Limited, Renesas Technology Corp. » and Synopsys, Inc. Because of the possibility of human or mechanical error, neither the authors, ARM Limited, Renesas Technology Corp. » Synopsys, Inc. nor any of their affiliates guarantees the accuracy, adequacy or completeness of any information contained herein and are not responsible for any errors or omissions, or for the results obtained from the use of such information. THERE ARE NO EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BIT NOT LIMITED TO, WARRANTIES OF MERCHANT- ABILITY OR FITNESS FOR A PARTICULAR PURPOSE relating to the Verification Methodolo- gy Manual for Low Power. In no event shall the authors, ARM Limited, Renesas Technology Corp. , Synopsys, Inc. , nor any of their affiliates be liable for any indirect, special or consequential damages in connection with the information provided herein. About Synopsys Press ‘Synopsys Press offers leading-edge educational publications written by industry experts for the busi- ness and technical communities associated with electronic product design. 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