DDR saving energy cancellation sequence

No
OFF state?

Yes

SSCG/PLL start

PSEL exchange ① 266MHｚ setting

MSCLK gate Open

MCLK/DDR_PHY_CLK
gate Open MRS: Mode Register Set. Must be writen after
EMRS setting. CS/,RAS/,CAS/ and BA0 is asserted Low
DDR should be in all bank precharge (CKE: High)
Self refresh mode OFF

EMRS: Extended Mode Register Set. Must be writen after

power up to enable or disable DLL.
MSR command release CS/,RAS/,CAS/ are asserted Low. BA0: High
DDR should be in all bank precharge (CKE: High)

EMSR command release

DRAM enable to use

Self refresh mode ON

・Dispo head model: Dose not use ADC when Soft Off
・Perma head model: Use ADC when Soft Off

ADC clock supply