HD44780U # 2ine display (N= 1) (Figure 4) — Case 1: When the number of display characters is less than 40 > 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line stat address are not consecutive, For example, when just the HD44780 is used, 8 characters x 2 lines are displayed. Figure 5, When display shift operation is performed, the DDRAM address shifts. See Figure 5, Dispiay poram [00] ot [02 [os [oa 26] 27 agers [a0 [at [42 [43 | 2a 6 |e7 Figure # 2-Line Display Day onan [00[0%]02]03]04 os [os for acess or [az [aaa as [as a7 coe [or]02] 09] 04] 05 ]05 07] oe Shien || a aaa [a [a7 [a or [27]00]o1]o2]03]08 Jos foo Sn ight 7 aoa faz [oe fs [a Figure § 2-Line by 8-Character Display Example HITACHI "HD44780U Normally, instructions that perform data transfer with intemal RAM are used the most, However, auto incrementation by 1 (or auto-decrementation by 1) of intemal HD44780U RAM addresses after each data ‘waite can lighten the program load of the MPU. Since the display shift instruction (Table 11) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency, When an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed, Because the busy flag is set to 1 while an instruction is being executed, check it to make sure itis 0 before sending another instruction from the MPU. Note: Be sure the HD44780U is not in the busy state (BF = 0) before sending an instruction from the MPU to the H1D44780U. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much Tonger than the instruction time itself. Refer to Table 6 for the list of each instruc-tion execution time. Table6 Instructions odo Execution Time oto (max) (when f.. oF Instruction RS_RIW DBT DBS DS 084 DBI DB? DBT DBO Description fone 9 270 KAS) Ger 00 OOO DOO Coarse danlayand spy Sele Bona scares On Ssrese courier Roum 0 0 0 0 0 0 0 0 1 — SeteDDRAW addess0in 152 m5 rome Accrae county Ase Fetus dipay fom being Shite fo dngha postion DRAM contents remain enanges Ey 00 0 0 0 0 0 1 WS Setscwsor nave dvecion S7u8 mage set nd species display shi These operators af porermed dung data write Sndvese Depay 000 0 G0 1 DB Selseniradspay (Dyonloh, 37 one eureor one (C), ane conor Sinking ot ts postion character (8). Gusoror 00000 1 SG AL — — Moves cursorand shits 97 = spay Sepa without changing sae Sera contents Findon 00004 LON F Sets interface oatalengih S78 a {QU numberof dapiay Ines {Riana' character fot Se 00D 1 AGB AGG ACE AGG AGG ACG Ses CGRAM aderess. a7 us Grane GRAN dota sont and sasese fecowed aftr bis sing Sel 01 ADD ADD ADD ADD ADD ADD ADD Sels DDRAM acess. oT us SoRaM Sant datas sent and eicees receWed ater hi sting Readbusy 01 BF AG AG AG AG AG AG AG Reeds busy fag @F) Ons fag Inaenting tera operation sabres isang perarmed and tendo adores counter HITACHI 24HD44780U Table 6 Instruction RS_RIW DB7 DB6 DBS DB4 DBI DB DAT DBD Description Instructions (cont) Execution Time Code (max) (when fo White dala 10 Wrledata ‘Virites dala iio DRAM or {2.CG or coRaM. DRAM Read dala 11 Read ala Reads data rom DDRAM ar ‘fom CG or coRAM. DDRAM WD = 1 Inerement DRAM Display data RAM Exeouton time WD =0: Decrement CGRAM: Character generator changes when S__=1: Accompanies display shit RAM frequency changes SIC =1: Dispiayshit ACG: CGRAMaddress Example! SIG =0; Cursor move ADD: ODRAMaddrass When fy or fog i8 RIL =1: Shitto tne ight (corresponds to cursor 250 KHZ, RIL =O: Shitto tne lett acdress) 210. DL =1 Bbits, L=0: 4 pts AG: Adaress counter used for 97 #S* 35g" 40 HS No =4) 2iines,N=0: 1 Ine both 09 ang CRAM F 21: Sx 0dols,F=0" 5x8 dots addresses BF =1: Intemally operating BF_=0: Instructions acceptable Nate: indicates no effect, After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter is incremented or decremented by 1. The RAM address counter is updated after the busy flag turns off In Figure 10, iy is the time elapsed after the busy flag turns off until the address counter is updated. Busy signal = — Busy state —+| (087 pin) ‘Address counter (OBO to DBS pins) teop Note: taop depends on the operation frequency taa0 = 1.5lfep ot fosc) Seconds igure 10 Address Counter Update HITACHI 5HD44780U Instruction Description Clear Display (Clear display writes space code 20H (character pattem for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted, In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if2 lines are displayed). It also sets MD to I (inerement mode) in entry mode. $ of entry mode does not change. Return Home Return home sets DRAM address 0 into the address counter, and returns the display to its original status if it was shifted. The DDRAM contents do not change. ‘The cursor or blinking go to the left edge of the display (inthe fist line if 2 lines are displayed), Entry Mode Set UD: Increments (1/D = 1) or decrements (L/D = 0) the DDRAM address by 1 when a character code is ‘written into or read from DDRAM. The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1 The same applies to writing and reading of CGRAM. Shifts the entire display either to the right (WD = 0) or to the left (UD not shift if S is 0 ) when $ is 1. The display does IFS is 1, it will seem as if the cursor does not move but the display does. The display does not shift when reading from DDRAM. Also, writing into or reading out from CGRAM does not shift the display. Display On/Off Control D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM, but ‘can be displayed instantly by setting D to | (C: The cursor is displayed when C is 1 and not displayed when C is 0, Even if the cursor disappears, the function of L/D or other specifications will not change during display data write. The cursor is displayed using 5 dots in the 8th line for 5 x 8 dot character font selection and in the Ith line for the 5 x 10 dot character font selection (Figure 13). B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as switching between all blank dots and displayed characters ata speed of 409,6-ms intervals When f of fose is 250 kH¥z, The cursor and blinking can be set to display simultaneously. (The blinking frequency changes according to fose or the reciprocal off. For example, when f,, is 270 kHz, 409.6 x 250/270 = 379.2 ms.) HITACHI 26HD44780U Cursor or Display Shift ‘Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (Table 7), This function is used to correct or search the display. In a 2-line display, the cursor ‘moves to the second line when it passes the 40th digit of the first line. Note that the first and second line displays will shift atthe same time. ‘When the displayed data is shifted repeatedly each line moves only horizontally. The second line display does not shift into the first line position. ‘The address counter (AC) contents will not change if the only action performed is a display shift. Funetion § 7 DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DBO) when DL is 1, and in 4-bit lengths (DBT to DB4) when DL. is 0,When 4-bit length is selected, data must be sent oF received twice. N: Sets the number of display lines. F: Sets the character font. Note: Perform the function at the head of the program before exccuting any instructions (except for the read busy flag and address instruction). From this point, the function set instruction cannot be executed unless the interface data length is changed, Sot CGRAM Address Sot CGRAM address sets the CGRAM address binary AAAAAA into the address counter, Data is then written to or ead from the MPU for CGRAM. HITACHI arHD44780U ear splay Retum home Enty made set Display nia contr Cursor or splay shit Function set Sot CGRAM adress Code code Code Code Code code Code RS. RW 87 Bs Bs DBs Bs 082 Bt Bo RS. e7 DBs. as pes bes bez bet Bo RS. be? Bs 8s es es 082 et Bo RS ber es es bes es a2 et eo RS Rm ber es: bea bes. bez Bt 60 sic RIL RS Rm pe? es: DB Bs B2 0B 60 DL Rs Rm bev es: ea bes. pa Bt 80 a a Higher ‘order bit Lower order bit Note: *Dont care, Note: “Dont care 28 Figure 11 Instruction (1) HITACHIHD44780U Set DDRAM Address Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter. Data is then writen to or rad from the MPU for DDRAM, However, when N is 0 (I-line display), AAAAAAA ean be OOH to FH. When N is 1 (line display), AAAAAAA can be OOH to 27H forthe first ine, and 40H to 67H forthe second line Read Busy Flag and Address Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction, If BF is 1, the internal operation is in progress, The next instruction ‘will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the same time, the value of the address counter in binary AAAAAAA is read out. This address counter is used by both CG and DDRAM addresses, and its value is determined by the previous instruction, The address ‘contents are the same as for instructions set CGRAM address and set DDRAM address. Table7 Shift Function sic RIL 0 (0 ___ Shifts the cursor position to the lef. (AC Is decremented by one.) o 1 Shifts the cursor position tothe right. (AC is incremented by one.) 1 (0 ___ Shifts the entire display to the left The cursor follows the display shift 1 1 Shifis the entire display tothe right. The cursor follows the display shift. TableS Function Set No. of Display Duty NF Lines Character Font Factor Remarks oo 4 x6 dole 18 ota 3x10 dots wa 12 x8 dots 116 ___ Cannot display two lines for 5 x 10 dot character font Note > Indleates don't care, HITACHI 29HD44780U Table 12. 4-Bit Operation, 8-Digit x I-Line Display Example with Internal Reset step Instruction No. RS_RIW DB7 0B6 DBS DBA Display Operation 1 ower supply on (te HO#A760U sinlzed by he temal [—————]_nalzed. No dsp reset cult) 2 Function set Ba 0 operation i ec ) In this case, operation is hance as 8 bits by inializa- ton, and ony ths instucton| completes with one wrt 3 Function set [Sa Bt operation ana 0 0 0 0 4 selects (ine display and 58 0. 0 0 o + dot character font. bit operation starts from this step and reseting is necessary (Number of dspay nes and character fonts cannat ae changed after stop #3.) 4 Display anit contol To] Berson pay and cursor 2 0 0 0 9 Oo Entire cispay isn space mode oo 1 4 10 because ofintialzation, 5 Entrymode set [Sethe increment ine 0 0 0 0 0 oO address by one an to shit the 0 0 0 + 1 0 cursor to the ight atthe time of te to te ODICGRAM, Displays not shited (Wie data to CGRAMIDDRAM Writes H 1 0 0 1 0 0 ‘The cursor incremented by 1 0 1 0 0 0 one and shits to the ight Note: The conivol is the same as for &bit operation beyond step #6, HITACHI 42