si19i2021 Miccochip MPLAB XCB.C Compiler: 16F15213 Support Information 16F15213 Support Information #pragma config Usage fpragna config = For example: // External Oscillator Mode Selection bits : EC (external clock) 16 MHz and above 7/ Power-up Default Value for COSC bits : EXTOSC operating per FEXTOSC bits 7/ Clock Out Enable bit : CLKOUT function is disabled; I/O function on RAS 71 VoD Range Analog Calibration Selection bit : Internal analog systens are calibrated for operation between VoD = 2.3V - 5.5V #pragna config FEXTOSC = ECH, RSTOSC = EXTOSC, CLKOUTEN = OFF, VDDAR = HI pragma config = For example // External Oscillator Mode Selection bits : EC (external clock) 16 MHz and above 7/ Power-up Default Value for COSC bits : EXTOSC operating per FEXTOSC bits // Clock Out Enable bit : CLKOUT function is disabled; 1/0 function on RA 7/ VoD Range Analog Calibration Selection bit : Internal analog systems are calibrated for operation between VoD = 2.3V - 5.5V pragma config FEXTOSC = Ox3, RSTOSC = @x3, CLKOUTEN = @x1, VDDAR = @x1 tipragna config = For example: // External Oscillator Mode Selection bits : EC (external clock) 16 "Hz and above 7/ Power-up Default Value for COSC bits : EXTOSC operating per FEXTOSC bits 7/ Clock Out Enable bit : CLKOUT function is disabled; I/O function on RAd 7/ NOD Range Analog Calibration Selection bit : Internal analog systems are calibrated for operation between VDD = 2.3V - 5.5V #pragna config CONFIG = Ox3FFF For example // TDLOC @ @x8000 pragma config IDLOCe = 6x16383 #pragma config Settings Register: CONFIGI @ 0x8007 FEXTOSC External Oscillator Mode Selection bits ECH EC (external clock) 16 MHz and above ECL EC (external clock) below 16MHz OFF Oscillator not enabled RsTosc Power-up Default Value for COSC bits ExTOsc EXTOSC operating per FEXTOSC bits HFINTOSC_1MHzZ HFINTOSC (1 MHz) LeInTose LFINTOSC HFINTOSC_32m#2 - HFINTOSC (32 MHz) cuKouTen Clock Out Enable bit on CLKOUT function is enabled; FOSC/4 clock appears on RA4 file:HIC:/Program FlesiMicrochipix8iv2.S2ldocsichips!16/15213.hinl 19sy192021 oFF \ooar Hr Lo Microchip MPLAB XC8 C Compiler: 16F15213 Suppot Information CLKOUT function is disabled; 1/0 funetion on RA4 VDD Range Analog Calibration Selection bit Internal analog systems are calibrated for operation between VDD = 2.3V - 5.5V Internal analog systems are calibrated for operation between VDD = 1.8V - 3.6V Register: CONFIG2 @ 0x8008 MCLRE EXTMCLR, INTMCLR, PURTS PHRT_OFF PuRT_64 PuRT_16 PHRT_A wore on NSLEEP SWOTEN oFF OREN on NSLEEP SBOREN oFF Bory Lo Hr PPSIMAY on OFF STVREN on OFF Master Clear Enable bit IfLVP = 0, MCLR pin is MCLR; If LVP = 1, RA3 pin function is MCLR. If LVP = 0, MCLR pin is port defined function; If LVP = 1, RA3 pin function is MCLR Power-up Timer Selection bits PWRT is disabled PWRT set at 64 ms PWRT set at 16 ms PWRT set at | ms WDT Operating Mode bits WDT enabled regardless of Sleep; SEN bit is ignored WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN is ignored WDT enabledidisabled by SEN bit WDT disabled; SE Brown-out Reset Enable bits Brown-out Reset Enabled, SBOREN bit is ignored Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored Brown-out Reset enabled according to SOREN bit Brown-out Reset disabled Brown-out Reset Voltage Selection bit Brown-out Reset Voltage (VBOR) set to 1.9V Brown-out Reset Voltage (VBOR) is set to 2.85V PPSLOCKED One-Way Set Enable bit The PPSLOCKED bit can be set once after an unlocking sequence is executed; once PPSLOCKED is set, all future changes to PPS registers are prevented The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required) Stack Overflow/Underflow Reset Enable bit Stack Overflow or Underflow will cause a reset is ignored Stack Overflow or Underflow will not cause a reset, Register: CONFIG3 @ 0x8009 Register: CONFIG4 @ 0x800A, Besize e512 BB1K BK BBaK BB8K BB16K Boot Block Size Selection bits 512 words boot block size 1024 words boot block size 2048 words boot block size 4096 words boot block size * half of w! * half of w! +r program memory +r program memory file:HIC:/Program FlesiMicrochipix8iv2.S2ldocsichips!16/15213.hinl 29sy192021 832K BB6aK BBEN oFF o SAFEN oFF o WRTAPP oFF o wavs, oFF o wate oFF o WRTSAF oFF o lve on OFF Microchip MPLAB XC8 C Compiler: 16F15213 Suppot Information * half of user program memory * half of user program memory Boot Block Enable bit Boot Block is disabled Boot Block is enabled SAF Enable bit SAF is disabled SAF is enabled Application Block Write Protection bit Application Block is not write-protected Application Block is write-protected Boot Block Write Protection bit Boot Block is not write-protected Boot Block is write-protected Configuration Registers Write Protection bit Configuration Registers are not write-protected Configuration Registers are write-protected Storage Area Flash (SAF) Write Protection bit SAF is not write-protected SAF is write-protected Low Voltage Programming Enable bit Low Voltage programming enabled. MCLR/Vpp pin funetion is MCLR. MCLRE Configuration bit is ignored. High Voltage on MCLR/Vpp must be used for programming Register: CONFIGS @ 0x800B o OFF on User Program Flash Memory Code Protection bit ‘User Program Flash Memory code protection is disabled User Program Flash Memory code protection is enabled Register: IDLOCO @ 0x8000 Register: IDLOCI @ 0x8001 Register: IDLOC2 @ 0x8002 Register: IDLOC3 @ 0x8003 file:HIC:/Program FlesiMicrochipix8iv2.S2ldocsichips!16/15213.hinl 38