Media Devices

FUJITSU SEMICONDUCTOR
DATA SHEET DS07-13737-2E
16-bit Proprietary Microcontroller

CMOS
F2MC-16LX MB90350 Series

MB90F352/S, MB90352/S
■ DESCRIPTION
The MB90350-series with 1 channel FULL-CAN* interface and FLASH ROM is especially designed for automotive
and industrial applications. Its main feature is the on-board CAN Interface, which conform to V2.0 Part A and Part
B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN
approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory
up to 128 Kbytes. An internal voltage booster removes the necessity for a second programming voltage.
An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features a 4 channel Output Compare Unit and 6 channel Input Capture Unit with 2 separate 16-bit free
running timers. 2 channels UART constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ PACKAGE
64-pin Plastic LQFP
(FPT-64P-M09)
MB90350 Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without
S-suffix only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi-
plied PLL clock).
• Built-in clock modulation circuit
• 16 Mbyte CPU memory space
• 24-bit internal addressing
• External Bus Interface
• 4 MByte external memory space
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported
• Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (a timebase timer mode switched from the main clock mode)
• PLL timer mode (a timebase timer mode switched from the PLL clock mode)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Process
• CMOS technology
• I/O port
• General-purpose input/output port (CMOS output)
- 49 ports (devices without S-suffix)
- 51 ports (devices with S-suffix)
(Continued)
2
MB90350 Series
(Continued)
• Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 10 channels, or 16-bit × 6 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 6 channels
- 16-bit output compare : (OCU) : 4 channels
• Full-CAN interface : 1 channel
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
• UART (LIN/SCI) : 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• I2C interface* : 1 channel
• Up to 400 Kbit/s transfer rate
• DTP/External interrupt : 8 channels, CAN wakeup : 1 channel
• Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt.
• Delay interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter : 15 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Address matching detection for 6 address pointers.
• Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
• Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
• Flash security function
• Protects the content of Flash (Flash device only)
* : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-
ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
3
MB90350 Series
■ PRODUCT LINEUP
Part Number
MB90F352/S, MB90352/S*1 MB90V340A-101/102
Parameter
CPU F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
System clock
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
Boot-block, Flash memory
ROM External
128 Kbytes
RAM 4 Kbytes 30 Kbytes
Emulator-specific
 Yes
power supply*2
0.35 µm CMOS with
0.35 µm CMOS with regulator for internal power supply +
Technology regulator for internal
Flash memory charge pump for programming voltage
power supply
3.5 V - 5.5 V : at normal operating (not using A/D converter)
Operating
4.0 V - 5.5 V : at using A/D converter/Flash programming 5 V ± 10%
voltage range
4.5 V - 5.5 V : at using external bus
Temperature range −40 °C to +105 °C (125 °C up to 16 MHz machine clock) 
Package LQFP-64 PGA-299
2 channels 3 channels
UART Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbit/s) 1 channel 1 channel
15 channels
A/D
Converter 10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
(4 channels) Supports External Event Count function
Signals an interrupt when overflowing
16-bit Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
I/O Timer
(fsys = Machine clock freq.)
(2 channels) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Signals an interrupt when 16-bit I/O Timer match output compare registers.
Compare
A pair of compare registers can be used to generate an output signal.
(4 channels)
16-bit Input Capture Rising edge, falling edge or rising & falling edge sensitive
(6 channels) Signals an interrupt upon external event
(Continued)
4
MB90350 Series
Part Number
MB90F352/S, MB90352/S*1 MB90V340A-101/102
Parameter
Supports 8-bit and 16-bit operation modes
8-bit reload counters × 12
8/16-bit
8-bit reload registers for L pulse width × 12
Programmable Pulse
8-bit reload registers for H pulse width × 12
Generator
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
6 channels (16-bit) /
8-bit prescaler + 8-bit reload counter
10 channels (8-bit)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
1 channel 2 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
CAN Interface Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
External Interrupt Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
(8 channels) extended intelligent I/O services (EI2OS) and DMA
D/A converter  1 channel
Subclock devices with ‘S’-suffix and MB90V340A-102 : without subclock
(up to100 kHz) devices without ‘S’-suffix and MB90V340A-101 : with subclock
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
I/O Ports Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs (default)
TTL input level settable for external bus (30 terminals only for external bus)
Supports automatic programming, Embedded AlgorithmTM*3
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Flash
Data retention time : 10 years 
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
*1 : The devices are under development.
*2 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
MB90350 Series
■ PIN ASSIGNMENTS
• MB90F352/S, MB90352/S
(TOP VIEW)
(LQFP-64P)
P12/AD10/SIN3/INT11R
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P23/A19/PPGF(E)
P20/A16/PPG9(8)
P14/AD12/SCK3
P13/AD11/SOT3
P11/AD09/TOT1
P24/A20/IN0
P17/AD15
P16/AD14
P15/AD13
RST
Vss
X0
X1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vcc 49 32 P10/AD08/TIN1
C 50 31 P07/AD07/INT15
P25/A21/IN1/ADTG 51 30 P06/AD06/INT14
P44/SDA0/FRCK0 52 29 P05/AD05/INT13
P45/SCL0/FRCK1 53 28 P04/AD04/INT12
P30/ALE/IN4 54 27 P03/AD03/INT11
P31/RD/IN5 55 26 P02/AD02/INT10
P32/WRL/WR/INT10R 56 25 P01/AD01/INT9
P33/WRH 57 24 P00/AD00/INT8
P34/HRQ/OUT4 58 23 MD0
P35/HAK/OUT5 59 22 MD1
P36/RDY/OUT6 60 21 MD2
P37/CLK/OUT7 61 20 P41/X1A*
P60/AN0 62 19 P40/X0A*
P61/AN1 63 18 Vss
AVcc 64 17 P43/IN7/TX1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P54/AN12/TOT3
P51/AN9/SOT2
P63/AN3/PPG6(7)
AVRH
P50/AN8/SIN2
P55/AN13
P62/AN2/PPG4(5)
P64/AN4/PPG8(9)
P65/AN5/PPGA(B)
P66/AN6/PPGC(D)
P67/AN7/PPGE(F)
AV ss
P 5 6 /A N 1 4
P 52/A N 10/S C K 2
P 4 2 /IN 6 /R X 1 /IN T 9 R
P 53/A N 11/TIN 3
(FPT-64P-M09)
* : MB90F352/352 : X0A, X1A

MB90F352S/352S : P40, P41
6
MB90350 Series
■ PIN DESCRIPTION
Pin No. Circuit
Pin name Function
LQFP64* type
46 X1 Oscillation output pin.
A
47 X0 Oscillation input pin.
45 RST E Reset input pin.
P62 to P67 General purpose I/O ports.
AN2 to AN7 Analog input pins for A/D converter.
3 to 8 I
PPG4, 6, 8,
Output pins for PPGs.
A, C, E
P50 General purpose I/O port.
9 AN8 O Analog input pin for A/D converter.
SIN2 Serial data input pin for UART2.
10 AN9 I Analog input pin for A/D converter.
SOT2 Serial data output pin for UART2.
SCK2 Serial data output pin for UART2.
TIN3 Event input pin for reload timer3.
TOT3 Output pin for reload timer3.
P55, P56 General purpose I/O ports.
14, 15 I
AN13, AN14 Analog input pins for A/D converter.
IN6 Data sample input pin for input capture ICU6.
16 F
RX1 RX input pin for CAN1.
INT9R External interrupt request input pin for INT9.
17 IN7 F Data sample input pin for input capture ICU7.
TX1 TX output pin for CAN1.
General purpose I/O ports
P40, P41 F
(devices with S-suffix and MB90V340A-101) .
19, 20
Oscillation input pins for sub clock
X0A, X1A B
(devices without S-suffix and MB90V340A-102) .
(Continued)
7
MB90350 Series
Pin No. Circuit

Pin name Function
LQFP64* type
General purpose I/O ports.The register can be set to select whether to use
P00 to P07
a pull-up resistor.This function is enabled in single-chip mode.
24 to 31 G Input/output pins of external address data bus lower 8 bit. This function is
AD00 to AD07
enabled when the external bus is enabled.
INT8 to INT15 External interrupt request input pins for INT8 to INT15.
General purpose I/O port.The register can be set to select whether to use
P10
a pull-up resistor.This function is enabled in single-chip mode.
32 G Input/output pin for external bus address data bus bit 8.
AD08
This function is enabled when external bus is enabled.
TIN1 Event input pin for reload timer1.
General purpose I/O.The register can be set to select whether to use a
P11
pull-up resistor.This function is enabled in single-chip mode.
33 G Input/output pin for external bus address data bus bit 9. This function is en-
AD09
abled when external bus is enabled.
TOT1 Output pin for reload timer1.
General purpose I/O port. The register can be set to select whether to use
P12
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 10. This function is
34 AD10 N enabled when external bus is enabled.
SIN3 Serial data input pin for UART3.
INT11R External interrupt request input pin for INT11
P13
AD11
SOT3 Serial data output pin for UART3.
P14
AD12
SCK3 Clock input/output pin for UART3.
P15
37 N
Input/output pin for external bus address data bus bit 13.
AD13
P16
38 G
AD14
(Continued)
8
MB90350 Series
Pin No. Circuit

Pin name Function
LQFP64* type
P17
39 G
AD15
General purpose I/O ports. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a general-
P20 to P23
purpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
40 to 43 G Output pins for A16 to A19 of the external address bus.
A16 to A19 When the corresponding bit in the external address output control register
(HACR) is 0, the pins are enabled as high address output pins A16 to A19.
PPG9, PPGB,
Output pins for PPGs.
PPGD, PPGF
P24
44 G
Output pins for A20 of the external address bus. When the corresponding
A20 bit in the external address output control register (HACR) is 0, the pin is
enabled as high address output pins A20.
P25
51 G Output pin for A21 of the external address bus. When the corresponding bit
A21 in the external address output control register (HACR) is 0, the pin is en-
abled as high address output pin A21.
ADTG Trigger input pin for A/D converter.
P44 General purpose I/O port
52 SDA0 H Serial data I/O pin for I2C 0
FRCK0 Input pin for the 16-bit I/O Timer 0
53 SCL0 H Serial clock I/O pin for I2C 0
FRCK1 Input for the 16-bit I/O Timer 1
P30
54 G Address latch enable output pin. This function is enabled when external bus
ALE
is enabled.
(Continued)
9
MB90350 Series
Pin No. Circuit

Pin name Function
LQFP64* type
P31
55 G Read strobe output pin for data bus. This function is enabled when external
RD
bus is enabled.
P32 pull-up resistor. This function is enabled either in single-chip mode or with
the WR/WRL pin output disabled.
Write strobe output pin for the data bus. This function is enabled when both
56 G
the external bus and the WR/WRL pin output are enabled. WRL is used to
WR/WRL
write-strobe 8 lower bits of the data bus in 16-bit access. WR is used to
write-strobe 8 bits of the data bus in 8-bit access.
INT10R External interrupt request input pin for INT10.
P33 a pull-up resistor. This function is enabled either in single-chip mode or with
the WRH pin output disabled.
57 G
Write strobe output pin for the 8 higher bits of the data bus. This function is
WRH enabled when the external bus is enabled, when the external bus 16-bit
mode is selected, and when the WRH output pin is enabled.
the hold function disabled.
58 G
Hold request input pin. This function is enabled when both the external bus
HRQ
and the hold function are enabled.
OUT4 Waveform output pin for output compare OCU4.
the hold function disabled.
59 G
Hold acknowledge output pin. This function is enabled when both the
HAK
external bus and the hold function are enabled.
the external ready function disabled.
60 G
Ready input pin. This function is enabled when both the external bus and
RDY
the external ready function are enabled.
the CLK output disabled.
61 G
CLK output pin. This function is enabled when both the external bus and
CLK
CLK output are enabled.
(Continued)
10
MB90350 Series
(Continued)
Pin No. Circuit
Pin name Function
LQFP64* type
P60, P61 General purpose I/O ports.
62, 63 I
AN0, AN1 Analog input pins for A/D converter.
64 AVCC K VCC power input pin for analog circuits.
Reference voltage input for the A/D converter. This power supply must be
2 AVRH L turned on or off while a voltage higher than or equal to AVRH is applied to
AVCC.
1 AVSS K VSS power input pin for analog circuits.
22, 23 MD1, MD0 C Input pins for specifying the operating mode.
21 MD2 D Input pins for specifying the operating mode.
49 VCC  Power (3.5 V to 5.5 V) input pin.
18, 48 VSS  Power (0 V) input pins.
This is the power supply stabilization capacitor pin. It should be connected
50 C K
to a higher than or equal to 0.1 µF ceramic capacitor.
* : FPT-64P-M09
11
MB90350 Series
■ I/O CIRCUIT TYPE

Type Circuit Remarks
Oscillation circuit
X1 • High-speed oscillation feedback
Xout
resistor = approx. 1 MΩ
A X0
Standby control signal
X1A Oscillation circuit

Xout
• Low-speed oscillation feedback
resistor = approx. 10 MΩ
B X0A
Standby control signal
Mask ROM device:

• CMOS Hysteresis input pin
C R
Hysteresis
inputs Flash device:
• CMOS input pin
Mask ROM device:

R
Hysteresis
• CMOS Hysteresis input pin
inputs • Pull-down resistor valule: approx. 50 kΩ
D
Pull-down
Flash device:
Resistor
• CMOS input pin
• No Pull-down
CMOS Hysteresis input pin

• Pull-up resistor valule: approx. 50 kΩ
Pull-up
E Resistor
R
Hysteresis
inputs
(Continued)
12
MB90350 Series

• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
Pout
• CMOS hysteresis inputs (With the stand-
by-time input shutdown function)
Nout • Automotive input (With the standby-time
input shutdown function)
F R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown

pull-up control
pull-up
resistor • CMOS hysteresis inputs (With the stand-
Pout by-time input shutdown function)
• Automotive input (With the standby-time
Nout
• TTL input (With the standby-time input
R shutdown function)
G • Programmalble pullup resistor: 50 kΩ
Hysteresis inputs
approx.
Automotive inputs
TTL input
Standby control for

input shutdown

Pout
H R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
13
MB90350 Series

• CMOS level output(IOL = 4 mA)
Pout
Nout input shutdown function)
• A/D analog input
R
I
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
• Power supply input protection circuit
• A/D converter reference voltage power

ANE
supply input pin, with the protection cir-
cuit
L AVR • Flash devices do not have a protection
circuit against VCC for pin AVRH
ANE
(Continued)
14
MB90350 Series
(Continued)
pull-up control
pull-up (IOL = 4 mA, IOH = −4 mA)
registor • CMOS inputs (With the standby-time
Pout input shutdown function)
Nout
• TTL input (With the standby-time input
R shutdown function)
N
• Programmable pull-up registor:50 kΩ
CMOS inputs
approx
Automotive inputs
TTL input
Standby control for

input shutdown

Pout
• CMOS inputs (With the standby-time
R
• A/D analog input
O
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
15
MB90350 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
• Initialization
• Port0 to port3 output during Power-on (External-bus mode)
• Notes on using CAN Function
• Flash security Function
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90350 Series
X0
Open X1
4. Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
16
MB90350 Series
5. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device
Vcc
Vss
Vcc Vss
Vss
MB90350
Vcc Series Vcc
Vss
Vss Vcc
7. Pull-up/down resistors
The MB90350 Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
8. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after
turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simulta-
neously is acceptable).
10. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
17
MB90350 Series
11. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V)
12. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
14. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.
1/2 VCC
VCC
Port0 to Port3
Port0 to Port3 outputs Port0 to Port3 outputs = Hi-Z

might be unstable
15. Notes on using CAN Function

To use CAN function, please set ’1’ to DIRECT bit of CAN Direct Mode Register (CDMR).
If DIRECT bit is set to ’0’ (initial value), wait states will be performed when accessing CAN registers.
Please refer to Hardware Manual of MB90350 series for detail of CAN Direct Mode Register.
16. Flash security Function
The security byte is located in the area of the flash memory.
If protection code 01H is written in the security bit, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security bit.
Flash memory size Address for security bit
MB90F352 Embedded 1 Mbit Flash Memory FE0001H
18
MB90350 Series
■ BLOCK DIAGRAMS
• MB90V340A-101/102
X0,X1
X0A,X1A * Clock
16LX
RST Controller CPU
IO Timer 0 FRCK0
RAM 30 K
Input
Capture IN7 to IN4,
6 ch IN1 to IN0
Output
Compare OUT7 to OUT4
4 ch
Prescaler
3 ch IO Timer 1
FRCK1
SOT4 to SOT2 CAN

UART RX2 to RX1
SCK4 to SCK2 3 ch Controller
2 ch TX2 to TX1
SIN4 to SIN2
AVCC 16-bit Reload TIN3, TIN1

AVSS Timer 4 ch TOT3, TOT1
AN14 to AN0 10-bit ADC
AVRH 15 ch
AD15 to AD00
ADTG A21 to A16
FMC-16 Bus
ALE
RD
10-bit External
DA00 DAC WRL
Bus
1 ch Interface WRH
HRQ
8/16-bit HAK
PPGF to PPG8, PPG RDY
PPG6, PPG4, 12/8 ch
PPG2, PPG0 CLK
SDA0 I2C
Interface External
SCL0 1 ch INT15 to INT8
Interrupt
(INT11R to INT9R)
DMAC
* : MB90V340A-102
19
MB90350 Series
• MB90F352/S, MB90352/S
X0,X1
X0A,X1A* Clock
16LX
RST Controller CPU
RAM IO Timer 0 FRCK0

4K
Input
Capture IN7 to IN4,
6 ch IN1, IN0
ROM/Flash
128 K Output
Compare OUT7 to OUT4
4 ch
Prescaler
2 ch IO Timer 1
FRCK1
SOT3, SOT2 CAN

UART RX1
SCK3, SCK2 2 ch Controller
1 ch TX1
SIN3, SIN2
AVCC 16-bit Reload TIN3, TIN1

AVSS Timer 4 ch TOT3, TOT1
AN14 to AN0 10-bit ADC
15 ch
AVRH AD15 to AD00
A21 to A16
FMC-16 Bus
ADTG ALE
RD
External
WRL
Bus
Interface WRH
8/16-bit HRQ
PPGF to PPG8 PPG
PPG6, PPG4 10/6 ch HAK
RDY
CLK
SDA0 I2C
Interface
SCL0 1 ch INT15 to INT8
External (INT11R to INT9R)
Interrupt
DMAC
* : Only for devices without ‘S’ Suffix
20
MB90350 Series
■ MEMORY MAP
MB90V340A-101/102 MB90F352/S
MB90352/S
FFFFFFH FFFFFFH
ROM (FF bank) ROM (FF bank)
FF0000H FF0000H
FEFFFFH FEFFFFH
ROM (FE bank) ROM (FE bank)
FE0000H FE0000H
FDFFFFH FDFFFFH
External access
area
C00100H
C000FFH
00FFFFH ROM 00FFFFH ROM

(image of FF bank) (image of FF bank)
008000H 008000H
007FFFH 007FFFH
Peripheral Peripheral
007900H 007900H
0078FFH
RAM 30 K
001100H
0010FFH
RAM 4 K
000100H 000100H
External access area
0000EFH 0000EFH
Peripheral Peripheral
000000H 000000H
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
21
MB90350 Series
■ I/O MAP
Abbrevia-
Address Register Access Resource name Initial value
tion
00H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXX
07H to 0AH Reserved
0BH Analog Input Enable Register 5 ADER5 R/W Port 5, A/D 11111111
0CH Analog Input Enable Register 6 ADER6 R/W Port 6, A/D 11111111
0DH Reserved
0EH Input Level Select Register 0 ILSR0 R/W Ports 00000000
0FH Input Level Select Register 1 ILSR1 R/W Ports 00000000
10H Port 0 Direction Register DDR0 R/W Port 0 00000000
12H Port 2 Direction Register DDR2 R/W Port 2 XX000000
17H to 19H Reserved
1AH SIN input Level Setting Register DDRA W UART2, UART3 X00XXXXX
1BH Reserved
1CH Port 0 Pull-up Control Register PUCR0 R/W Port 0 00000000
1DH Port 1 Pull-up Control Register PUCR1 R/W Port 1 00000000
1EH Port 2 Pull-up Control Register PUCR2 R/W Port 2 00000000
1FH Port 3 Pull-up Control Register PUCR3 R/W Port 3 00000000
20H to 37H Reserved
38H PPG 4 Operation Mode Control Register PPGC4 W, R/W 0X000XX1
16-bit Programable
39H PPG 5 Operation Mode Control Register PPGC5 W, R/W 0X000001
Pulse Generator 4/5
3AH PPG 45 Clock Select Register PPG45 R/W 000000X0
Program Address Detection Control Address Match
3BH PACSR1 R/W 00000000
Status Register 1 Detection 1
(Continued)
22
MB90350 Series
Abbrevia-
tion
3CH PPG 6 Operation Mode Control Register PPGC6 W, R/W 0X000XX1
16-bit Programable
3DH PPG 7 Operation Mode Control Register PPGC7 W, R/W 0X000001
Pulse Generator 6/7
3EH PPG 67 Clock Select Register PPG67 R/W 000000X0
3FH Reserved
40H PPG 8 Operation Mode Control Register PPGC8 W, R/W 0X000XX1
16-bit Programable
41H PPG 9 Operation Mode Control Register PPGC9 W, R/W 0X000001
Pulse Generator 8/9
42H PPG 89 Clock Select Register PPG89 R/W 000000X0
43H Reserved
44H PPG A operation mode control register PPGCA W, R/W 0X000XX1
16-bit Programable
45H PPG B operation mode control register PPGCB W, R/W 0X000001
Pulse Generator A/B
46H PPG AB clock select register PPGAB R/W 000000X0
47H Reserved
48H PPG C Operation Mode Control Register PPGCC W,R/W 0X000XX1
16-bit Programable
49H PPG D Operation Mode Control Register PPGCD W,R/W 0X000001
Pulse Generator C/D
4AH PPG CD Clock Select Register PPGCD R/W 000000X0
4BH Reserved
4CH PPG E Operation Mode Control Register PPGCE W,R/W 0X000XX1
16-bit Programable
4DH PPG F Operation Mode Control Register PPGCF W,R/W 0X000001
Pulse Generator E/F
4EH PPG EF Clock Select Register PPGEF R/W 000000X0
4FH Reserved
Input Capture Control Status
50H ICS01 R/W 00000000
Register 0/1 Input Capture 0/1
51H Input Capture Edge Register 0/1 ICE01 R/W, R XXX0X0XX
52H, 53H Reserved
54H ICS45 R/W 00000000
55H Input Capture Edge Register 4/5 ICE45 R XXXXXXXX
56H ICS67 R/W 00000000
57H Input Capture Edge Register 6/7 ICE67 R/W, R XXX000XX
58H to 5BH Reserved
Output Compare Control Status
5CH OCS4 R/W 0000XX00
Register 4
Output Compare 4/5
5DH OCS5 R/W 0XX00000
Register 5
(Continued)
23
MB90350 Series
Abbrevia-
tion
5EH OCS6 R/W 0000XX00
Register 6
Output Compare 6/7
5FH OCS7 R/W 0XX00000
Register 7
60H Timer Control Status Register 0 TMCSR0 R/W 16-bit Reload Timer 00000000
61H Timer Control Status Register 0 TMCSR0 R/W 0 XXXX0000
68H A/D Control Status Register 0 ADCS0 R/W 000XXXX0
69H A/D Control Status Register 1 ADCS1 R/W 0000000X
6AH Data Register 0 ADCR0 R 00000000
A/D Converter
6BH Data Register 1 ADCR1 R XXXXXX00
6CH A/D Setting Register 0 ADSR0 R/W 00000000
6DH A/D Setting Register 1 ADSR1 R/W 00000000
6EH Reserved
6FH ROM Mirroring Register ROMM W ROM Mirror XXXXXXX1
70H to 7FH Reserved
80H to 8FH Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
90H to 9AH Reserved
DMA Descriptor Channel Specification
9BH DCSR R/W 00000000
Register
DMA
9CH DMA Status Register L DSRL R/W 00000000
9DH DMA Status Register H DSRH R/W 00000000
Program Address Detection Control Address Match
9EH PACSR0 R/W 00000000
Status Register 0 Detection 0
9FH Delayed Interrupt/Release DIRR R/W Delayed Interrupt 00000000
Low Power Control
A0H Low-power Mode Control Register LPMCR W,R/W 00011000
Circuit
Low Power Control
A1H Clock Selection Register CKSCR R,R/W 11111100
Circuit
A2H, A3H Reserved
A4H DMA Stop Status Register DSSR R/W DMA 00000000
(Continued)
24
MB90350 Series
Abbrevia-
tion
Automatic Ready Function Selection
A5H ARSR W 0011XX00
Register
External Memory
A6H External Address Output Control Register HACR W Access 00000000
A7H Bus Control Signal Selection Register ECSR W 0000000X
A8H Watchdog Timer Control Register WDTC R,W Watchdog Timer XXXXX111
A9H Timebase Timer Control Register TBTC W,R/W Time base timer 1XX00100
AAH Watch Timer Control Register WTC R,R/W Watch timer 1X001000
ABH Reserved
ACH DMA Enable Register L DERL R/W 00000000
DMA
ADH DMA Enable Register H DERH R/W 00000000
Flash Control Status Register
AEH (Flash Devices only. Otherwise FMCS R,R/W Flash Memory 000X0000
reserved)
AFH Reserved
B0H Interrupt Control Register 00 ICR00 W,R/W 00000111
Interrupt Control
BAH Interrupt Control Register 10 ICR10 W,R/W 00000111
BBH Interrupt Control Register 11 ICR11 W,R/W 00000111
BCH Interrupt Control Register 12 ICR12 W,R/W 00000111
BDH Interrupt Control Register 13 ICR13 W,R/W 00000111
BEH Interrupt Control Register 14 ICR14 W,R/W 00000111
BFH Interrupt Control Register 15 ICR15 W,R/W 00000111
C0H to C9H Reserved
(Continued)
25
MB90350 Series
Abbrevia-
tion
External Interrupt Request Enable
CAH ENIR1 R/W 00000000
Register 1
CBH External Interrupt Request Register 1 EIRR1 R/W XXXXXXXX
CCH External Interrupt Level Register 1 ELVR1 R/W External Interrupt 1 00000000
CDH External Interrupt Level Register 1 ELVR1 R/W 00000000
External Interrupt Source Select
CEH EISSR R/W 00000000
Register
CFH PLL/Subclock Control register PSCCR W PLL XXXX0000
D0H DMA Buffer Address Pointer L BAPL R/W XXXXXXXX
D1H DMA Buffer Address Pointer M BAPM R/W XXXXXXXX
D2H DMA Buffer Address Pointer H BAPH R/W XXXXXXXX
D3H DMA Control Register DMACS R/W XXXXXXXX
DMA
D4H I/O Register Address Pointer L IOAL R/W XXXXXXXX
D5H I/O Register Address Pointer H IOAH R/W XXXXXXXX
D6H Data Counter L DCTL R/W XXXXXXXX
D7H Data Counter H DCTH R/W XXXXXXXX
D8H Serial Mode Register 2 SMR2 W,R/W 00000000
D9H Serial Control Register 2 SCR2 W,R/W 00000000
Reception/Transmission Data Register RDR2/
DAH R/W 00000000
2 TDR2
DBH Serial Status Register 2 SSR2 R,R/W 00001000
UART2
Extended Communication Control R,W,
DCH ECCR2 000000XX
Register 2 R/W
DDH Extended Status/Control Register 2 ESCR2 R/W 00000100
DEH Baud Rate Reload Register 20 BGR20 R/W 00000000
DFH Baud Rate Reload Register 21 BGR21 R/W 00000000
E0H to EFH Reserved
F0H to FFH External
7900H to
Reserved
7907H
(Continued)
26
MB90350 Series
Abbrevia-
tion
7908H Reload Register L4 PRLL4 R/W XXXXXXXX
7909H Reload Register H4 PRLH4 R/W 16-bit Programable XXXXXXXX
Pulse
790AH Reload Register L5 PRLL5 R/W Generator 4/5 XXXXXXXX
790BH Reload Register H5 PRLH5 R/W XXXXXXXX
790CH Reload Register L6 PRLL6 R/W XXXXXXXX
790DH Reload Register H6 PRLH6 R/W 16-bit Programable XXXXXXXX
Pulse
790EH Reload Register L7 PRLL7 R/W Generator 6/7 XXXXXXXX
790FH Reload Register H7 PRLH7 R/W XXXXXXXX
7910H Reload Register L8 PRLL8 R/W XXXXXXXX
7911H Reload Register H8 PRLH8 R/W 16-bit Programable XXXXXXXX
Pulse
7912H Reload Register L9 PRLL9 R/W Generator 8/9 XXXXXXXX
7913H Reload Register H9 PRLH9 R/W XXXXXXXX
7914H Reload Register LA PRLLA R/W XXXXXXXX
7915H Reload Register HA PRLHA R/W 16-bit Programable XXXXXXXX
Pulse
7916H Reload Register LB PRLLB R/W Generator A/B XXXXXXXX
7917H Reload Register HB PRLHB R/W XXXXXXXX
7918H Reload Register LC PRLLC R/W XXXXXXXX
7919H Reload Register HC PRLHC R/W 16-bit Programable XXXXXXXX
Pulse
791AH Reload Register LD PRLLD R/W Generator C/D XXXXXXXX
791BH Reload Register HD PRLHD R/W XXXXXXXX
791CH Reload Register LE PRLLE R/W XXXXXXXX
791DH Reload Register HE PRLHE R/W 16-bit Programable XXXXXXXX
Pulse
791EH Reload Register LF PRLLF R/W Generator E/F XXXXXXXX
791FH Reload Register HF PRLHF R/W XXXXXXXX
7920H Input Capture Data Register 0 IPCP0 R XXXXXXXX
Input Capture 0/1
7924H to
Reserved
7927H
Input Capture 4/5
792AH Input Capture Data Register 5 IPCP5 R XXXXXXXX
792BH Input Capture Data Register 5 IPCP5 R XXXXXXXX
(Continued)
27
MB90350 Series
Abbrevia-
tion
792CH Input Capture Data Register 6 IPCP6 R XXXXXXXX
792DH Input Capture Data Register 6 IPCP6 R XXXXXXXX
Input Capture 6/7
792EH Input Capture Data Register 7 IPCP7 R XXXXXXXX
792FH Input Capture Data Register 7 IPCP7 R XXXXXXXX
7930H to
Reserved
7937H
7938H Output Compare Register 4 OCCP4 R/W XXXXXXXX
7939H Output Compare Register 4 OCCP4 R/W XXXXXXXX
Output Compare 4/5
793AH Output Compare Register 5 OCCP5 R/W XXXXXXXX
793BH Output Compare Register 5 OCCP5 R/W XXXXXXXX
793CH Output Compare Register 6 OCCP6 R/W XXXXXXXX
793DH Output Compare Register 6 OCCP6 R/W XXXXXXXX
Output Compare 6/7
793EH Output Compare Register 7 OCCP7 R/W XXXXXXXX
793FH Output Compare Register 7 OCCP7 R/W XXXXXXXX
7940H Data Register 0 TCDT0 R/W 00000000
I/O Timer 0
7942H Control status Register 0 TCCSL0 R/W 00000000
7943H Control status Register 0 TCCSH0 R/W 0XXXXXXX
I/O Timer 1
7946H Control status Register 1 TCCSL1 R/W 00000000
7947H Control status Register 1 TCCSH1 R/W 0XXXXXXX
7948H TMR0/ R/W 16-bit Reload XXXXXXXX
Timer Register 0/Reload Register 0
7949H TMRLR0 R/W Timer 0 XXXXXXXX
794AH TMR1/ R/W 16-bit Reload XXXXXXXX
794BH TMRLR1 R/W Timer 1 XXXXXXXX
794CH TMR2/ R/W 16-bit Reload XXXXXXXX
794DH TMRLR2 R/W Timer 2 XXXXXXXX
794EH TMR3/ R/W 16-bit Reload XXXXXXXX
794FH TMRLR3 R/W Timer 3 XXXXXXXX
(Continued)
28
MB90350 Series
Abbrevia-
tion
7950H Serial Mode Register 3 SMR3 W, R/W 00000000
7951H Serial Control Register 3 SCR3 W, R/W 00000000
Reception/Transmission Data Register RDR3/
7952H R/W 00000000
3 TDR3
7953H Serial Status Register 3 SSR3 R,R/W 00001000
UART3
Extended Communication Control Reg- R,W,
7954H ECCR3 000000XX
ister 3 R/W
7955H Extended Status/Control Register 3 ESCR3 R/W 00000100
7956H Baud Rate Reload Register 30 BGR30 R/W 00000000
7957H Baud Rate Reload Register 31 BGR31 R/W 00000000
7958H to
Reserved
796DH
796EH CAN Direct Mode Register CDMR R/W CAN clock sync XXXXXXX0
796FH Reserved
7970H I2C Bus Status Register 0 IBSR0 R 00000000
7971H I2C Bus Control Register 0 IBCR0 W,R/W 00000000
7972H ITBAL0 R/W 00000000
I2C 10 bit Slave Address Register 0
7973H ITBAH0 R/W 00000000
2
7974H I2C 10 bit Slave Address Mask Register ITMKL0 R/W I C Interface 0 11111111
7975H 0 ITMKH0 R/W 00111111
2
7976H I C 7 bit Slave Address Register 0 ISBA0 R/W 00000000
7977H 2
I C 7 bit Slave Address Mask Register 0 ISMK0 R/W 01111111
7978H I2C data register 0 IDAR0 R/W 00000000
7979H,
Reserved
797AH
797BH I2C Clock Control Register 0 ICCR0 R/W I2C Interface 0 00011111
797CH to
Reserved
79C1H
79C2H Clock Modulator Control Register CMCR R,R/W Clock Modulator 0001X000
79C3H to
Reserved
79DFH
(Continued)
29
MB90350 Series
(Continued)
Abbrevia-
tion
79E0H Program Address Detection Register 0 PADR0 R/W XXXXXXXX
Address Match
Detection 0
79E9H to
Reserved
79EFH
79F0H Program Address Detection Register 3 PADR3 R/W XXXXXXXX
Address Match
Detection 1
79F9H to
Reserved
7BFFH
7C00H to
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
7CFFH
7D00H to
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
7DFFH
7E00H to
Reserved
7FFFH
Notes : • Initial value of “X” represents unknown value.
• Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary
functions of the MCU. A read access to these reserved addresses results reading “X” and any write
access should not be performed.
30
MB90350 Series
■ CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz)
List of Control Registers (1)

Address
Register Abbreviation Access Initial Value
CAN1
000080H 00000000
Message buffer enable register BVALR R/W
000081H 00000000
000082H 00000000
Transmit request register TREQR R/W
000083H 00000000
000084H 00000000
Transmit cancel register TCANR W
000085H 00000000
000086H 00000000
Transmission complete register TCR R/W
000087H 00000000
000088H 00000000
Receive complete register RCR R/W
000089H 00000000
00008AH 00000000
Remote request receiving register RRTRR R/W
00008BH 00000000
00008CH 00000000
Receive overrun register ROVRR R/W
00008DH 00000000
00008EH Reception interrupt 00000000
RIER R/W
00008FH enable register 00000000
31
MB90350 Series
List of Control Registers (2)

Address
CAN1
007D00H R/W, W 0XXXX0X1
Control status register CSR
007D01H R/W, R 00XXX000
007D02H 000X0000
Last event indicator register LEIR R/W
007D03H XXXXXXXX
007D04H 00000000
Receive/transmit error counter RTEC R
007D05H 00000000
007D06H 11111111
Bit timing register BTR R/W
007D07H X1111111
007D08H XXXXXXXX
IDE register IDER R/W
007D09H XXXXXXXX
007D0AH 00000000
Transmit RTR register TRTRR R/W
007D0BH 00000000
007D0CH Remote frame receive waiting XXXXXXXX
RFWTR R/W
007D0DH register XXXXXXXX
007D0EH Transmit interrupt 00000000
TIER R/W
007D0FH enable register 00000000
007D10H XXXXXXXX
007D11H XXXXXXXX
Acceptance mask
AMSR R/W
007D12H select register XXXXXXXX
007D13H XXXXXXXX
007D14H XXXXXXXX
007D15H XXXXXXXX
Acceptance mask register 0 AMR0 R/W
007D16H XXXXXXXX
007D17H XXXXXXXX
007D18H XXXXXXXX
007D19H XXXXXXXX
Acceptance mask register 1 AMR1 R/W
007D1AH XXXXXXXX
007D1BH XXXXXXXX
32
MB90350 Series
List of Message Buffers (ID Registers) (1)

Address
CAN1
007C00H XXXXXXXX
to General-purpose RAM  R/W to
007C1FH XXXXXXXX
007C20H XXXXXXXX
007C21H XXXXXXXX
ID register 0 IDR0 R/W
007C22H XXXXXXXX
007C23H XXXXXXXX
007C24H XXXXXXXX
007C25H XXXXXXXX
007C26H XXXXXXXX
007C27H XXXXXXXX
007C28H XXXXXXXX
007C29H XXXXXXXX
007C2AH XXXXXXXX
007C2BH XXXXXXXX
007C2CH XXXXXXXX
007C2DH XXXXXXXX
007C2EH XXXXXXXX
007C2FH XXXXXXXX
007C30H XXXXXXXX
007C31H XXXXXXXX
007C32H XXXXXXXX
007C33H XXXXXXXX
007C34H XXXXXXXX
007C35H XXXXXXXX
007C36H XXXXXXXX
007C37H XXXXXXXX
007C38H XXXXXXXX
007C39H XXXXXXXX
007C3AH XXXXXXXX
007C3BH XXXXXXXX
007C3CH XXXXXXXX
007C3DH XXXXXXXX
007C3EH XXXXXXXX
007C3FH XXXXXXXX
33
MB90350 Series
List of Message Buffers (ID Registers) (2)

Address
CAN1
007C40H XXXXXXXX
007C41H XXXXXXXX
007C42H XXXXXXXX
007C43H XXXXXXXX
007C44H XXXXXXXX
007C45H XXXXXXXX
007C46H XXXXXXXX
007C47H XXXXXXXX
007C48H XXXXXXXX
007C49H XXXXXXXX
007C4AH XXXXXXXX
007C4BH XXXXXXXX
007C4CH XXXXXXXX
007C4DH XXXXXXXX
007C4EH XXXXXXXX
007C4FH XXXXXXXX
007C50H XXXXXXXX
007C51H XXXXXXXX
007C52H XXXXXXXX
007C53H XXXXXXXX
007C54H XXXXXXXX
007C55H XXXXXXXX
007C56H XXXXXXXX
007C57H XXXXXXXX
007C58H XXXXXXXX
007C59H XXXXXXXX
007C5AH XXXXXXXX
007C5BH XXXXXXXX
007C5CH XXXXXXXX
007C5DH XXXXXXXX
007C5EH XXXXXXXX
007C5FH XXXXXXXX
34
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers) (1)

Address
CAN1
007C60H
DLC register 0 DLCR0 R/W XXXXXXXX
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
35
MB90350 Series

Address
CAN1
007C80H XXXXXXXX
Data register 0
to DTR0 R/W to
(8 bytes)
007C87H XXXXXXXX
007C88H XXXXXXXX
Data register 1
to DTR1 R/W to
(8 bytes)
007C8FH XXXXXXXX
007C90H XXXXXXXX
Data register 2
to DTR2 R/W to
(8 bytes)
007C97H XXXXXXXX
007C98H XXXXXXXX
Data register 3
to DTR3 R/W to
(8 bytes)
007C9FH XXXXXXXX
007CA0H XXXXXXXX
Data register 4
to DTR4 R/W to
(8 bytes)
007CA7H XXXXXXXX
007CA8H XXXXXXXX
Data register 5
to DTR5 R/W to
(8 bytes)
007CAFH XXXXXXXX
007CB0H XXXXXXXX
Data register 6
to DTR6 R/W to
(8 bytes)
007CB7H XXXXXXXX
007CB8H XXXXXXXX
Data register 7
to DTR7 R/W to
(8 bytes)
007CBFH XXXXXXXX
007CC0H XXXXXXXX
Data register 8
to DTR8 R/W to
(8 bytes)
007CC7H XXXXXXXX
007CC8H XXXXXXXX
Data register 9
to DTR9 R/W to
(8 bytes)
007CCFH XXXXXXXX
007CD0H XXXXXXXX
Data register 10
to DTR10 R/W to
(8 bytes)
007CD7H XXXXXXXX
007CD8H XXXXXXXX
Data register 11
to DTR11 R/W to
(8 bytes)
007CDFH XXXXXXXX
007CE0H XXXXXXXX
Data register 12
to DTR12 R/W to
(8 bytes)
007CE7H XXXXXXXX
007CE8H XXXXXXXX
Data register 13
to DTR13 R/W to
(8 bytes)
007CEFH XXXXXXXX
36
MB90350 Series

Address
CAN1
007CF0H XXXXXXXX
Data register 14
to DTR14 R/W to
(8 bytes)
007CF7H XXXXXXXX
007CF8H XXXXXXXX
Data register 15
to DTR15 R/W to
(8 bytes)
007CFFH XXXXXXXX
37
MB90350 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control
EI2OS DMA ch Interrupt vector
Interrupt cause register
clear number
Number Address Number Address
Reset N  #08 FFFFDCH  
INT9 instruction N  #09 FFFFD8H  
Exception N  #10 FFFFD4H  
Reserved N  #11 FFFFD0H
ICR00 0000B0H
Reserved N  #12 FFFFCCH
CAN 1 RX / Input Capture 6 Y1  #13 FFFFC8H
ICR01 0000B1H
CAN 1 TX/NS / Input Capture 7 Y1  #14 FFFFC4H
I2C N  #15 FFFFC0H
ICR02 0000B2H
Reserved N  #16 FFFFBCH
16-bit Reload Timer 0 Y1 0 #17 FFFFB8H
ICR03 0000B3H
ICR04 0000B4H
16-bit Reload Timer 3 Y1  #20 FFFFACH
PPG 4/5 N  #21 FFFFA8H
ICR05 0000B5H
PPG 6/7 N  #22 FFFFA4H
PPG 8/9/C/D N  #23 FFFFA0H
ICR06 0000B6H
PPG A/B/E/F N  #24 FFFF9CH
Time Base Timer N  #25 FFFF98H
ICR07 0000B7H
External Interrupt 8 to 11 Y1 3 #26 FFFF94H
Watch Timer N  #27 FFFF90H
ICR08 0000B8H
External Interrupt 12 to 15 Y1 4 #28 FFFF8CH
A/D Converter Y1 5 #29 FFFF88H
ICR09 0000B9H
I/O Timer 0 / I/O Timer 1 N  #30 FFFF84H
Input Capture 4/5 Y1 6 #31 FFFF80H
ICR10 0000BAH
Output Compare 4/5 Y1 7 #32 FFFF7CH
Input Capture 0/1 Y1 8 #33 FFFF78H
ICR11 0000BBH
Output Compare 6/7 Y1 9 #34 FFFF74H
Reserved N 10 #35 FFFF70H
ICR12 0000BCH
Reserved N 11 #36 FFFF6CH
UART 3 RX Y2 12 #37 FFFF68H
ICR13 0000BDH
UART 3 TX Y1 13 #38 FFFF64H
(Continued)
38
MB90350 Series
(Continued)
Interrupt control
EI2OS DMA ch Interrupt vector
Interrupt cause register
clear number
Number Address Number Address
UART 2 RX Y2 14 #39 FFFF60H
ICR14 0000BEH
UART 2 TX Y1 15 #40 FFFF5CH
Flash Memory N  #41 FFFF58H
ICR15 0000BFH
Delayed interrupt N  #42 FFFF54H
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
39
MB90350 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0 V)
Rating
Parameter Symbol Unit Remarks
Min Max
VCC VSS − 0.3 VSS + 6.0 V
Power supply voltage AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC*1
AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH*1
Input voltage VI VSS − 0.3 VSS + 6.0 V *2
Output voltage VO VSS − 0.3 VSS + 6.0 V *2
Maximum Clamp Current ICLAMP −4.0 +4.0 mA *4
Total Maximum Clamp Current Σ|ICLAMP|  40 mA *4
“L” level maximum output current IOL  15 mA *3
“L” level average output current IOLAV  4 mA *3
“L” level maximum overall output current ΣIOL  100 mA *3
“L” level average overall output current ΣIOLAV  50 mA *3
“H” level maximum output current IOH  −15 mA *3
“H” level average output current IOHAV  −4 mA *3
“H” level maximum overall output current ΣIOH  −100 mA *3
“H” level average overall output current ΣIOHAV  −50 mA *3
+105 °C < TA ≤ +125 °C,
 240 mW Normal operation : maximum
frequency 16 MHz
Power consumption PD
−40 °C < TA ≤ +105 °C,
 320 mW Normal operation : maximum
frequency 24 MHz
−40 +105 °C
Operating temperature TA
−40 +125 °C *5
Storage temperature TSTG −55 +150 °C
(Continued)
40
MB90350 Series
(Continued)
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating.
*3: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67
*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,
P50 to P56 (for evaluation : P50 to P55) , P60 to P67
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting P-ch
resistance
+B input (0 V to 16 V)
N-ch
*5 : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
41
MB90350 Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Value
Parameter Symbol Unit Remarks
Min Typ Max
4.0 5.0 5.5 V Under normal operation
Under normal operation, when not using the
VCC, 3.5 5.0 5.5 V
Power supply voltage A/D converter and not Flash programming.
AVCC
4.5 5.0 5.5 V When External bus is used.
3.0  5.5 V Maintains RAM data in stop mode
Use a ceramic capacitor or capacitor of bet-
Smooth capacitor CS 0.1  1.0 µF ter AC characteristics. Capacitor at the VCC
should be greater than this capacitor.
−40  +105 °C
Operating temperature TA
−40  +125 °C *
* : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations.
CS
C Pin Connection Diagram
Operation guaranteed range

24
Internal clock fCP (MHz)
16
− 40 105 125
Operation temperature TA (°C)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
42
MB90350 Series
3. DC Characteristics
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Sym- Value
Parameter Pin Condition Unit Remarks
bol Min Typ Max
Port inputs if CMOS
hysteresis input levels
VIHS   0.8 VCC  VCC + 0.3 V are selected (except
P12, P15, P44, P45,
P50)
Port inputs if
VIHA   0.8 VCC  VCC + 0.3 V AUTOMOTIVE input
levels are selected
Input H Port inputs if TTL input
voltage VIHT   2.0  VCC + 0.3 V
levels are selected
(At VCC =
P12, P15, P50 inputs if
5 V ± 10%)
VIHS   0.7 VCC  VCC + 0.3 V CMOS input levels are
selected
P44, P45 inputs if
VIHI   0.7 VCC  VCC + 0.3 V CMOS hysteresis input
levels are selected
RST input pin (CMOS
VIHR   0.8 VCC  VCC + 0.3 V
hysteresis)
VIHM   VCC − 0.3  VCC + 0.3 V MD input pin
Port inputs if CMOS
hysteresis input levels
VILS   VSS − 0.3  0.2 VCC V are selected (except
P12, P15, P44, P45,
P50)
Port inputs if
VILA   VSS − 0.3  0.5 VCC V AUTOMOTIVE input
levels are selected
Input L Port inputs if TTL
voltage VILT   VSS − 0.3  0.8 V
input levels are selected
(At VCC =
P12, P15, P50 inputs if
5 V ± 10%)
VILS   VSS − 0.3  0.3 VCC V CMOS input levels are
selected
P44, P45 inputs if
VILI   VSS − 0.3  0.3 VCC V CMOS hysteresis input
levels are selected
RST input pin (CMOS
VILR   VSS − 0.3  0.2 VCC V
hysteresis)
VILM   VSS − 0.3  VSS + 0.3 V MD input pin
Output H Normal VCC = 4.5 V,
VOH VCC − 0.5   V
voltage outputs IOH = −4.0 mA
Output H I2C current VCC = 4.5 V,
VOHI VCC − 0.5   V
voltage outputs IOH = −3.0 mA
Output L Normal VCC = 4.5 V,
VOL   0.4 V
voltage outputs IOL = 4.0 mA
Output L I2C current VCC = 4.5 V,
VOLI   0.4 V
voltage outputs IOL = 3.0 mA
(Continued)
43
MB90350 Series
(Continued)
Sym- Value
bol Min Typ Max
Input leak current IIL  VCC = 5.5 V, VSS < VI < VCC −1  1 µA
P00 to P07,
P10 to P17,
Pull-up
RUP P20 to P25,  25 50 100 kΩ
resistance
P30 to P37,
RST
Except
Pull-down
RDOWN MD2  25 50 100 kΩ Flash
resistance
devices
VCC = 5.0 V,
Internal frequency : 24 MHz,  50 65 mA MB90F352
At normal operation.
VCC = 5.0 V,
ICC Internal frequency : 24 MHz,  65 80 mA MB90F352
At writing FLASH memory.
VCC = 5.0 V,
Internal frequency : 24 MHz,  70 85 mA MB90F352
At erasing FLASH memory.
VCC = 5.0 V,
ICCS Internal frequency : 24 MHz,  25 35 mA MB90F352
At Sleep mode.
VCC = 5.0 V,
ICTS Internal frequency : 2 MHz,  0.3 0.8 mA MB90F352
At Main Timer mode
VCC = 5.0 V,
Power supply Internal frequency : 24 MHz,
current* ICTSPLL6 VCC  4 7 mA MB90F352
At PLL Timer mode,
external frequency = 4 MHz
VCC = 5.0 V,
Internal frequency: 8 kHz,
ICCL  170 360 µA MB90F352
At sub operation
TA = +25°C
VCC = 5.0 V,
ICCLS  20 50 µA MB90F352
At sub sleep
TA = +25°C
VCC = 5.0 V,
ICCT  10 35 µA MB90F352
At watch mode
TA = +25°C
VCC = 5.0 V,
ICCH At Stop mode,  7 25 µA MB90F352
TA = +25°C
Other than C, AVCC, AVSS,
Input capacity CIN   5 15 pF
AVRH, VCC, VSS,
* : The power supply current is measured with an external clock.
44
MB90350 Series
4. AC Characteristics
(1) Clock Timing
Value
Parameter Symbol Pin Unit Remarks
Min Typ Max
X0, X1 3  16 MHz When using an oscillation circuit
fC
Clock frequency X0 3  24 MHz When using an external clock*
fCL X0A, X1A — 32.768 100 kHz
X0, X1 62.5  333 ns When using an oscillation circuit
tCYL
Clock cycle time X0 41.67  333 ns When using an external clock
tCYLL X0A, X1A 10 30.5 — µs
PWH, PWL X0 10   ns
Input clock pulse width Duty ratio is about 30% to 70%.
PWHL, PWLL X0A 5 15.2  µs
Input clock rise and fall
tCR, tCF X0   5 ns When using external clock
time
When using main clock at
24
Internal operating TA ≤ +105 °C
fCP  1.5  MHz
clock frequency When using main clock at
16
(machine clock) TA ≤ +125 °C
fCPL  8.192 50 kHz When using sub clock
When using main clock at
41.67
Internal operating TA ≤ +105 °C
tCP   666 ns
clock cycle time When using main clock at
62.5
(machine clock) TA ≤ +125 °C
tCPL  20 122.1  µs When using sub clock
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as
mentioned in “Relation among external clock frequency and machine clock frequency”.
tCYL
0.8 VCC
X0
0.2 VCC
PWH PWL
tCF tCR
tCYLL
0.8 VCC
X0A
0.2 VCC
PWHL PWLL
tCF tCR
Clock Timing
45
MB90350 Series
Guaranteed operation range
5.5
Guaranteed A/D Converter
operation range
4.0
Power supply voltage
3.5
Guaranteed PLL operation range
VCC (V)
1.5 4 24
Machine clock fCP (MHz)
Guaranteed operation range of MB90350 series
Guaranteed oscillation frequency range
x6 x4 x3 x2 x1
24
16
Internal clock
x 1/2
fCP (MHz) 12 (PLL off)
4.0
1.5
3 4 8 12 16 24
External clock fC (MHz) *
* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz
External clock frequency and Machine clock frequency
46
MB90350 Series
(2) Reset Standby Input

Value
Min Max
500  ns Under normal operation
In Stop mode, Sub Clock
Oscillation time of oscillator*
Reset input  µs mode, Sub Sleep mode
tRSTL RST + 100 µs
time and Watch mode
In Main timer mode and
100  µs
PLL timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC 0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC 0.2 VCC
90% of
amplitude
X0
Internal operation
clock 100 µs
Oscillation time
of oscillator Oscillation stabilization
waiting time
Instruction execution
Internal reset
47
MB90350 Series
(3) Power On Reset

Value
Parameter Symbol Pin Condition Unit Remarks
Min Max
Power on rise time tR VCC 0.05 30 ms

Power off time tOFF VCC 1  ms Due to repetitive operation
tR
2.7 V
VCC
0.2 V 0.2 V 0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
VCC
We recommend a rise of
3V 50 mV/ms maximum.
Holds RAM data
VSS
(4) Clock Output Timing

(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Min Max
62.5  ns fCP = 16 MHz
Cycle time tCYC CLK 
41.76  ns fCP = 24 MHz
20  ns fCP = 16 MHz
CLK ↑ → CLK ↓ tCHCL CLK 
tCYC
tCHCL
2.4 V 2.4 V
CLK
0.8 V
48
MB90350 Series
(5) Bus Timing (Read)

(TA = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Sym- Value
bol Min Max
ALE pulse width tLHLL ALE tCP/2 − 10  ns
ALE, A21 to
Valid address ⇒ ALE ↓ time tAVLL A16, AD15 tCP/2 − 20  ns
to AD00
ALE, AD15
ALE ↓ ⇒ Address valid time tLLAX tCP/2 − 15  ns
to AD00
A21 toA16,
Valid address ⇒ RD ↓ time tAVRL AD15 to tCP − 15  ns
AD00, RD
A21 to A16,
Valid address ⇒ Valid data
tAVDV AD15 to  5 tCP/2 − 60 ns
input
AD00
RD pulse width tRLRH RD  3 tCP/2 − 20  ns
RD, AD15 to
RD ↓ ⇒ Valid data input tRLDV  3 tCP/2 − 50 ns
AD00
RD, AD15 to
RD ↑ ⇒ Data hold time tRHDX 0  ns
AD00
RD ↓ ⇒ ALE ↑ time tRHLH RD, ALE tCP/2 − 15  ns
RD, A21 to
RD ↑ ⇒ Address valid time tRHAX tCP/2 − 10  ns
A16
A21 to A16,
Valid address ⇒ CLK ↑ time tAVCH AD15 to tCP/2 − 16  ns
AD00, CLK
RD ↓ ⇒ CLK ↑ time tRLCH RD, CLK tCP/2 − 15  ns
ALE ↓ ⇒ RD ↓ time tLLRL ALE, RD tCP/2 − 15  ns
49
MB90350 Series
tRLCH
tAVCH
2.4 V 2.4 V
CLK
tLLAX
tAVLL tRHLH
2.4 V 2.4 V 2.4 V

ALE
0.8 V
tLHLL
tAVRL tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
2.4 V 2.4 V
A21 to A16
0.8 V 0.8 V
tRLDV
tRHDX
tAVDV
2.4 V 2.4 V VIH VIH
AD15 to AD00 Address Read data
0.8 V 0.8 V VIL VIL
50
MB90350 Series
(6) Bus Timing (Write)

Value
Min Max
A21 to A16,
Valid address ⇒ WR ↓ time tAVWL AD15 to AD00, tCP−15  ns
WR
WR pulse width tWLWH WR 3 tCP/2 − 20  ns
Valid data output ⇒ WR ↑ AD15 to AD00,
tDVWH 3 tCP/2 − 20  ns
time WR

AD15 to AD00,
WR ↑ ⇒ Data hold time tWHDX 15  ns
WR
A21 to A16,
WR ↑ ⇒ Address valid time tWHAX tCP/2 − 10  ns
WR
WR ↑ ⇒ ALE ↑ time tWHLH WR, ALE tCP/2 − 15  ns
WR ↓ ⇒ CLK ↑ time tWLCH WR, CLK tCP/2 − 15  ns
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V 2.4 V
A21 to A16
0.8 V 0.8 V
tDVWH tWHDX
2.4 V 2.4 V 2.4 V

AD15 to AD00 Address Write data
0.8 V 0.8 V 0.8 V
51
MB90350 Series
(7) Ready Input Timing

Sym- Test Rated Value
Parameter Pin Units Remarks
bol Condition Min Max
RDY setup time tRYHS RDY
 32  ns fCP = 24 MHz
RDY hold time tRYHH RDY 0  ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
tRYHS tRYHH
VIH VIH
RDY
When WAIT is not used.
RDY
When WAIT is used. VIL
52
MB90350 Series
(8) Hold Timing

Value
Parameter Symbol Pin Condition Units Remarks
Min Max
Pin floating ⇒ HAK ↓
tXHAL HAK 30 tCP ns
time

HAK ↑ time ⇒ Pin valid
tHAHV HAK tCP 2 tCP ns
time
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4V
HAK
0.8V
tXHAL tHAHV
High-Z
2.4V 2.4V
Each pin
0.8V 0.8V
53
MB90350 Series
(9) UART 2/3

(TA = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)
Value
Min Max
Serial clock cycle time tSCYC SCK2, SCK3 8 tCP*  ns
SCK2, SCK3,
SCK ↓ → SOT delay time tSLOV Internal clock −80 +80 ns
SOT2, SOT3
operation output
SCK2, SCK3,
Valid SIN → SCK ↑ tIVSH pins are 100  ns
SIN0 to SIN4 CL = 80 pF + 1 TTL
SCK2, SCK3,
SCK ↑ → Valid SIN hold time tSHIX 60  ns
SIN2, SIN3
Serial clock “H” pulse width tSHSL SCK2, SCK3 4 tCP*  ns
Serial clock “L” pulse width tSLSH SCK2, SCK3 4 tCP*  ns
SCK2, SCK3, External clock
SCK ↓ → SOT delay time tSLOV  150 ns
SOT2, SOT3 operation output
pins are
SCK2, SCK3,
Valid SIN → SCK ↑ tIVSH CL = 80 pF + 1 TTL 60  ns
SIN2, SIN3
SCK2, SCK3,
SCK ↑ → Valid SIN hold time tSHIX 60  ns
SIN2, SIN3
* : Refer to “ (1) Clock timing” rating for tCP (internal operating clock cycle time).
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine cycle (Unit : ns)
tSCYC
2.4 V
SCK
0.8 V 0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH tSHIX
VIH VIH
SIN
VIL VIL
Internal Shift Clock Mode
54
MB90350 Series
tSLSH tSHSL
VIH VIH
SCK
VIL VIL
tSLOV
2.4 V
SOT
0.8 V
tIVSH tSHIX
VIH VIH
SIN
VIL VIL
External Shift Clock Mode
(10) Trigger Input Timing

Value
Min Max
INT8 to INT15,
tTRGH
Input pulse width INT9R to INT11R,  5 tCP  ns
tTRGL
ADTG
VIH VIH
INT8 to INT15, VIL VIL
INT9R to INT11R,
ADTG tTRGH tTRGL
55
MB90350 Series
(11) Timer Related Resource Input Timing

Value
Min Max
tTIWH TIN1, TIN3,
Input pulse width IN0, IN1,  4 tCP  ns
tTIWL IN4 to IN7
VIH VIH
TIN1, TIN3, VIL VIL
IN0, IN1,
IN4 to IN7 tTIWH tTIWL
(12) Timer Related Resource Output Timing

Value
Min Max
TOT1, TOT3,
CLK ↑ ⇒ TOUT change time tTO PPG4, PPG6,  30  ns
PPG8 to PPGF
2.4 V
CLK
TOT1, TOT3, 2.4 V

PPG4, PPG6 0.8 V
PPG8 to PPGF
tTO
56
MB90350 Series
(13) I2C Timing

(TA = –40°C to +105°C, VCC = AVCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)
(TA = –40°C to +125°C, VCC = AVCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = AVSS = 0.0 V)
Standard-mode Fast-mode*4
Parameter Symbol Condition Unit
Min Max Min Max
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition
tHDSTA 4.0  0.6  µs
SDA↓→SCL↓
“L” width of the SCL clock tLOW 4.7  1.3  µs
“H” width of the SCL clock tHIGH 4.0  0.6  µs
Set-up time for a repeated START condition
tSUSTA 4.7  0.6  µs
SCL↑→SDA↓
R = 1.7 kΩ,
Data hold time C = 50 pF*1
tHDDAT 0 3.45*2 0 0.9*3 µs
SCL↓→SDA↓↑
Data set-up time
tSUDAT 250  100  ns
SDA↓↑→SCL↑
Set-up time for STOP condition
tSUSTO 4.0  0.6  µs
SCL↑→SDA↑
Bus free time between a STOP and START
tBUS 4.7  1.3  µs
condition
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tLOW tSUDAT tHDSTA tBUS
SCL
tHIGH
tHDSTA tHDDAT tSUSTA tSUSTO
57
MB90350 Series
5. A/D Converter
(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)
Value
Min Typ Max
Resolution     10 bit
Total error     ±3.0 LSB
Nonlinearity error     ±2.5 LSB
Differential
    ±1.9 LSB
nonlinearity error
Zero reading
VOT AN0 to AN14 AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB
voltage
Full scale reading
VFST AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB
voltage
1.0 4.5 V ≤ AVCC ≤ 5.5 V
Compare time    16,500 µs
2.0 4.0 V ≤ AVCC < 4.5 V
0.5 4.5 V ≤ AVCC ≤ 5.5 V
Sampling time    ∞ µs
1.2 4.0 V ≤ AVCC < 4.5 V
Analog port input
IAIN AN0 to AN14 −0.3  +0.3 µA
current
Analog input
VAIN AN0 to AN14 AVSS  AVRH V
voltage range
Reference
 AVRH AVSS + 2.7  AVCC V
voltage range
Power supply IA AVCC  3.5 7.5 mA
current IAH AVCC   5 µA *
Reference IR AVRH  600 900 µA
voltage current IRH AVRH   5 µA *
Offset between
 AN0 to AN14   4 LSB
input channels
* : IF A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as |AVRH − AVSS| becomes smaller.
58
MB90350 Series
6. Definition of A/D Converter Terms

Resolution : Analog variation that is recognized by an A/D converter.
Non linearity : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
error and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
Differential : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
linearity error value.
Total error : Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Zero reading : Input voltage which results in the minimum conversion value.
voltage
Full scale : Input voltage which results in the maximum conversion value.
reading voltage
Total error
3FF
1.5 LSB
3FE Actual conversion
characteristics
3FD
{1 LSB × (N − 1) + 0.5 LSB}
Digital output
004 VNT
(Actually-measured value)
003
Actual conversion
002 characteristics
Ideal characteristics
001
0.5 LSB
AVSS AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}

Total error of digital output “N” = [LSB]
1 LSB
AVRH − AVSS
1 LSB = (Ideal value) [V]
1024
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
(Continued)
59
MB90350 Series
(Continued)
Non linearity error Differential linearity error

Ideal
3FF characteristics
Actual conversion
characteristics
3FE
{1 LSB × (N − 1) N+1 Actual conversion
+ VOT } characteristics
3FD VFST (actual
measurement
value)
Digital output
Digital output
N
VNT (actual
004 measurement value)
V (N + 1) T
Actual conversion N−1 (actual measurement
003
characteristics value)
VNT
002 (actual measurement value)
Ideal characteristics Actual conversion
001 N−2
characteristics
VOT (actual measurement value)
AVSS AVRH AVSS AVRH
Analog input Analog input
VNT − {1 LSB × (N − 1) + VOT}

Non linearity error of digital output N = [LSB]
1 LSB
V (N+1) T − VNT
Differential linearity error of digital output N = −1 LSB [LSB]
1 LSB
VFST − VOT
1 LSB = [V]
1022
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
60
MB90350 Series
7. Notes on A/D Converter Section

Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period ≤ 0.5 µs)
If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.
• Analog input circuit model
Analog input R
Comparator
4.5 V ≤ AVCC ≤ 5.5 V : R =: 2.52 kΩ, C =: 10.7 pF

4.0 V ≤ AVCC < 4.5 V : R =: 13.6 kΩ, C =: 10.7 pF
Note : Use the values in the figure only as a guideline.
8. Flash Memory Program/Erase Characteristics

Value
Parameter Conditions Unit Remarks
Min Typ Max
Excludes programming
Sector erase time  1 15 s
prior to erasure
TA = +25 °C Excludes programming
Chip erase time  9  s
VCC = 5.0 V prior to erasure
Word (16 bit width) Except for the overhead
 16 3,600 µs
programming time time of the system
Program/Erase cycle  10,000   cycle
Flash Data Retention Average
20   Years *
Time TA = +85 °C
* : This value comes from the technology qualification.
(Using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C)
61
MB90350 Series
■ ORDERING INFORMATION
Part number Package Remarks
MB90F352PFM 64-pin Plastic LQFP
MB90F352SPFM (FPT-64P-M09)
MB90352PFM 64-pin Plastic LQFP
MB90352SPFM (FPT-64P-M09)
MB90V340A-101 299-pin Ceramic PGA
For evaluation
MB90V340A-102 (PGA-299C-A01)
62
MB90350 Series
■ PACKAGE DIMENSIONS
Note 1) * : These dimensions do not include resin protrusion.
64-pin Plastic LQFP
Note 2) Pins width and pins thickness including plating thickness.
(FPT-64P-M09)
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ 0.145±0.055
(.0057±.0022)
48 33
49 32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8˚
64 17
0.50±0.20 0.10±0.10
"A" (.020±.008) (.004±.004)
1 16 (Stand off)
0.60±0.15
0.65(.026) (.024±.006)
0.32±0.05
0.13(.005) M
(.013±.002)
C 2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
63
MB90350 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0405
 FUJITSU LIMITED Printed in Japan

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FUJITSU SEMICONDUCTOR

DATA SHEET DS07-13737-2E

16-bit Proprietary Microcontroller

F2MC-16LX MB90350 Series

64-pin Plastic LQFP

* : MB90F352/352 : X0A, X1A

Pin No. Circuit

Pin No. Circuit

Pin No. Circuit

■ I/O CIRCUIT TYPE

Standby control signal

X1A Oscillation circuit

Standby control signal

Mask ROM device:

Mask ROM device:

CMOS Hysteresis input pin

Type Circuit Remarks

• CMOS level output

Standby control for

• CMOS level output

Type Circuit Remarks

• Power supply input protection circuit

• A/D converter reference voltage power

Standby control for

• CMOS level output

4. Precautions for when not using a sub clock signal

5. Notes on during operation of PLL clock mode

11. Notes on Energization

Port0 to Port3 outputs Port0 to Port3 outputs = Hi-Z

15. Notes on using CAN Function

SOT4 to SOT2 CAN

AVCC 16-bit Reload TIN3, TIN1

RAM IO Timer 0 FRCK0

SOT3, SOT2 CAN

AVCC 16-bit Reload TIN3, TIN1

* : Only for devices without ‘S’ Suffix

00FFFFH ROM 00FFFFH ROM

List of Control Registers (1)

List of Control Registers (2)

List of Message Buffers (ID Registers) (1)

List of Message Buffers (ID Registers) (2)

List of Message Buffers (DLC Registers and Data Registers) (1)

List of Message Buffers (DLC Registers and Data Registers) (2)

List of Message Buffers (DLC Registers and Data Registers) (3)

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

• Input/output equivalent circuits

C Pin Connection Diagram

Operation guaranteed range

Guaranteed operation range

Guaranteed operation range of MB90350 series

Guaranteed oscillation frequency range

(2) Reset Standby Input

Under normal operation:

0.2 VCC 0.2 VCC

(3) Power On Reset

(4) Clock Output Timing

(5) Bus Timing (Read)

2.4 V 2.4 V 2.4 V

(6) Bus Timing (Write)

2.4 V 2.4 V 2.4 V

(7) Ready Input Timing

(8) Hold Timing

(9) UART 2/3