CHAPTER Flip-Flops and Simple Flip-Flop Applications he logic networks studied thus far are combinational networks. A combina T tional network is defined as a two-valued network in which the outputs at any instant are dependent only upon the inputs present at that instant. As a consequence of this definition, it is possible to describe each output of a combina- tional network by a single algebraic expression whose variables are the inputs to the network. The above behavioral definition established only one class of logic networks. Atthis time, attention is tuned to another class of logic networks. A sequential net- work is defined as a two-valued network in which the outputs at any instant are de- pendent not only upon the inputs present at that instant but also upon the past his- tory (or sequence) of inputs. The past history of inputs must be preserved by the network. For this reason, sequential networks are said to have memory. The mecha- nism which is used to explain and represent the information preserved is referred to 48 the internal state, secondary state, ot simply state, of the network. Physically, the internal state is a collection of signals at a set of points within the network. In this way, the inputs at any time to a sequential network, along with its present inter- tal state, determine the outputs of the network. There are two basic types of sequential networks. They are distinguished by the ‘iming of the signals within the network. A synchronous sequential network is one in “hich its behavior is determined by the values of the signals at only discrete instants oftime. These networks typically have a master-clock generator which produces a Sequence of clock pulses. It is these clock pulses that effectively sample the input inal t determine the network behavior. This type of network is formally studied Chapters 7 and 8. The second type of sequential network is the asynchronous se- ential network. In this case the behavior of the network is immediately affected by e “TRU Signal changes. Asynchronous sequential networks are studied in Chapter 9 Sips basic logic element that provides memory in many sequential networks is op. Actually, the flip-flop itself is a simple sequential network, It can be ~~Y DIGITAL PRINCIPLES AND DESIGN shown that all sequential networks require the ana o secs In See. ¢, 7 is seen that feedback is present In flip-flop circuits. A flip-flop has two stable con, i. tions. To each of these stable conditions is associated a state, or, equivalently, the storage of a binary symbol. This chapter is concerned with the structure and Opera. tion of several types of flip-flops and some simple networks, ©. registers ang counters, that are constructed using them. Mt 6.1. THE BASIC BISTABLE ELEMENT Central to all flip-flop circuits is the basic bistable element which is shown in Fig. 6,1, This circuit has two outputs, Q and @. As seen from the figure, it consists of two cross-coupled not-gates, i.e., the output of the first not-gate serving as the input to the second and the output of the second not-gate serving as the input to the first. Clearly, this structure involves feedback. ‘As its name implies, the basic bistable element is a circuit having two stable conditions (or states). To see this, first assume x = 0 in Fig. 6.1. The output of the upper not-gate is then I, i., @ = ¥ = 1. Since the output of the upper not-gate is the input to the lower not-gate, x = y = 1. Consequently, the output of the lower not- gate, ie. jis 0. However, since the output ofthe lower not-gate is connected to the input of the upper not-gate, = 0. This is precisely what was assumed to be the value of x. Thus, the circuit is stable with @ = x = ¥ = Oand Q = 1 Using a similar argument, it is easy to show that if it is assumed that x = 1, then the basic bistable element is stable with Q=x=y=landQ=x=y=0. This is the second stable condition associated with the basic bistable element. ‘As a result of having two stable conditions, the basic bistable element is used to store binary symbols. In the case of positive logic, when the output line Q is 1, the element is said to be storing a 1; while when the output line Q is 0, the element is said to be storing a 0. It should be noted that the two outputs are complementary That is, when Q = 0, Q = 1; and when Q = 1,0 = 0. The binary symbol that is stored in the basic bistable clement is referred to as the content or state of the element. The state of the basic bistable element is given by the signal value at the Q output terminal. Hence, the Q output term! y Figure 6.1 Basic bistable element.CHAPTER 6 Flip-Flops and Simple Flip-Flop Applications called the normal output; while the Q output is referred to as the comple- ** ousput. When the device is storing a 1, it is said to be in its J-state or We other hand, when the device is storing a 0, itis said to be in its O-state ral yt stl ont o rough the bistable element is normally in one of its two stable conditions, is one more equilibrium condition that can exist. This occurs when the two there signals are about halfway between those associated with logic-O and logic-1. our output is not a valid logic signal. This is known as the metastable state. Tes er, a smal! change in any of the internal signal values of the circuit, say, due Homit noise, quickly causes the basic bistable element to leave the metastable oe and enter one of its two stable states. Unfortunately, the amount of time a de- vive can stay in Its metastable state, if it should occur, is unpredictable. For this rea- fon, the metastable state should be avoided. To avoid the metastable state, certain ressictions are placed on the operation of the basic bistable element. This is further iscussed in Sec. 6.3. The basic bistable element of Fig. 6.1 has no inputs. When power is applied, it becomes stable in one of its two stable states. It remains in this state until power is removed. For the circuit to be useful, provisions must be made to force the device into a particular state. A flip-flop is a bistable device, with inputs, that remains in a given state as long as power is applied and until input signals are applied to cause its output to change. It consists of a basic bistable element in which appropriate logic is added in order to control its state. The process of storing a 1 into a flip-flop is called setting or presetting the flip-flop; while the process of storing a 0 into a flip-flop is called resetting or clearing the flip-flop. The inputs to a flip-flop are of two types. An asynchronous or direct input is one in which a signal change of sufficient magnitude and duration essentially pro- duces an immediate change in the state of the flip-flop. In physical circuits, the re- sponse actually occurs after a very short time delay. This point is elaborated upon in Sec. 6.3 when the timing of signals is discussed in greater detail. On the other hand, a synchronous input does not immediately affect the state of the flip-flop, but rather affects the state of the flip-flop only when some control signal, usually called an enable or clock input, also occurs. In the next several sections, various input schemes to the basic bistable element are introduced that result in different types of flip-flops. 6.2 LATCHES The storage devices called Jatches form one class of flip-flops. This class is charac- lerized by the fact that the timing of the output changes is not controlled. That is, the output essentially responds immediately to changes on the input lines, although special control signal, called the enable or clock, might also need to be present. lus, the input lines are continuously being interrogated. In Secs. 6.4 and 6.5 flip- fops in which the timing of the ‘output changes is controlled are studied. It this case, ‘te inputs are normally sampled and not interrogated continuously.es AND DESION 304 DIGITAL PRING 6.2.1 The SR Latch Figure 6.2a shows the SR (or set-reset) latch that consists Of two cross-coupled ny, gates. It has two inputs, S and R, referred to as the set and reset inputs, and two oy, puts, Q and @. As is immediately evident from the second logic diagram in Fig, 6 then § = R = 0, the logic diagram simplifies to the basic bistable element descrity in the previous section, i.e., the cross-coupling of two not-gates. Thus, the latch isin Cone of its two stable states when these inputs are applied. This condition correspond, to the first row of the function table given in Fig. 6.2b. In the table, Q denotes the present state ofthe latch. That is, Q is the state of the device at the time the input si. nals are applied. The response of the latch at the Q and Q output terminals as acon. sequence of applying the various inputs is denoted by Q* and Q", respectively ‘Thus, Q* is called the next state of the latch. For $ = R = 0, the entries Q and Qin the Q* and Q* columns, respectively, are interpreted to mean that the next state of the device is the same as its present state. That is, the outputs do not change and the present state is retained. Now assume a 1 is applied to the R input of the upper nor-gate in Fig. 6.2a and 0 is applied to the S input of the lower nor-gate. Regardless of the second input to the upper nor-gate, the output Q must become 0 since R = 1. This signal, whichis fed back to the lower nor-gate along with the 0 on the S input, causes the output of the lower nor-gate, Q, to become 1. Thus it is seen that a 1 on the R input and 0 on the S input results in the latch being reset. This is given by the second row of the function table in Fig. 6.2. If the input R is subsequently returned to 0, then the latch retains its present reset state as described by the first row of the function table R R iG 9 = *Unpredictable behavior @ s @ will result if inputs ‘ return to 0 simultaneously ° o 5 @ s al rk @ te Rk ep— © Figure 6.2. Sflatch. (a) Logic diagrams. (b) Function table where Q* denotes the output @in respons? the inputs, (c) Two logic symbols.SHAPTER 6 Flip-Flops and Simple Flip-Flop Applications hed si gnal applied to the lower input of the upper nor-gate maintains the ce ME oand = 1. us similar argument, if a 1 is applied to the S input and a Ois applied to the R B the latch becomes set regardless of its present state. That is, the new out- ge @ = 1 and Q = 0. This corresponds to the third row of the function table. more, the latch remains in the 1-state when the § input returns to 0. For the three situations just discussed, the outputs Q and @ are complementary. iger now the case when S = R= 1. This causes the outputs of both nor-gates to Gone 0 indicated in the function table, and, consequently, they are not comple. tary oupuss. Difficulty is encountered when the inputs return to 0. If one input sod retum t0O before the other, then the final state ofthe latch is determined by oer in which the inputs are changed. In particular, the last input to stay at 1 de- ees the final state. In the event of both inputs Teturning to 0 simultaneously, the device may enter its metastable state. This is a condition that should be avoided as. discussed previously. Eventually, the device becomes stable, but its final state is un- ,ictable since it is based on such things as construction differences and thermal noise. For this reason, along with the fact that the outputs are not complementary, the 5= R= | input is frequently regarded as a forbidden input condition. From the function table of the SR latch it should be noted that a 1 serves as the activation signal of the device. That is, a 1 on either the S or R input terminal causes the device to set or reset, respectively. Furthermore, since changes on the $ and R inputs can immediately affect the outputs of the latch, the S and R inputs are re- garded as asynchronous (or direct) inputs. Two logic symbols for the SR latch are given in Fig. 6.2c. In the second sym- bol, the output bubble indicates the inversion of the normal state of the latch. Thus the output terminal with the bubble corresponds to @. int 0 6.2.2 An Application of the SR Latch: A Switch Debouncer Acommon problem involving switches is the occurrence of contact bounce. This is illustrated in Fig. 6.3a. As indicated by the waveforms, with the center contact of the switch in its lower position, the voltage at terminal B is + V volts, while the volt- age at terminal A is zero. Now if the center contact is moved from its lower position ‘0 its upper position, then it is noted that the voltage at terminal B first becomes 210, followed by the voltage at terminal A becoming +V volts when the center Contact reaches the upper terminal. However, as a result of contact bounce, the cen- ‘er contact of the switch leaves terminal A, causing the output voltage at that termi- ‘0 return to zero, and then upon returning to terminal A, causing the voltage at terminal A to become +V volts again. This opening and closing effect, due to the ‘Pringiness of the contacts, may occur several times before the center contact of the “witch remains in its upper position. It is important to note that during contact Ounce, the center contact does not return all the way to terminal B. Similarly, as in- dicated by the waveforms of Fig. 6.34, contact bounce again occurs when the Switch is moved from its upper position to its lower position. The effect of contact ~~DIGITAL PRINCIPLES AND DESIGN Vs v 0 ——* Tie Ve v ° Ti (a) me Va | iif | 0 Time Vs Vv Q 0 Time ep— 2 ‘Time Q Ti O} Figure 6.3 An application of the SR latch. (a) Effects of contact bounce. (b) A switch debouncer. bounce is normally undesirable. For example, in the case of push-button keys on @ keyboard, contact bounce may cause a system to respond as though a key was de- pressed several times in succession. A very simple, but important, application of the SR latch is to eliminate the ef fect of contact bounce. A switch debouncer circuit and corresponding waveforms© So Aap: are Seow Fro-Fap ADORCaIOrs in fap @ 36 Assume prsmive logic en that +) volts corresponds 80 «ground #6 Jaen 6 By use off the tee uh den reactors, hope 0 values vm w Cand R terminal: of the SR latch whenever the center contact of pee rare ted ie ethos terminars 4 or Bo¢@ a Senever the sartch ts The wer the cent upper poe “ ay if tote b reraains 1 IS Tee! ate unit! the center contact reaches Fermanal bs enim the (output of the SR latch becomes 1 If the va itch now opens, as rewayt nt ceantac! HOUTCE ADEN the O input to the § ami R termmmals of the latch vine. te () a! (7 outputs to remain unchanged Hence, by use ot the SR latch. the tal cemtact bounce 1s eliminated. In a similar manner, the effect of contact ‘ale chiminated when the switch moves from its upper position £0 its. omtact mon este oma ot Be pare ee penance awer postion 6.2.3 The $RLatch Awother type of latch, the SR latch, 1s constructed by cross-coupling two nand- yates Such a latch 15 shown in Fig, 64a and its function table is given in fy 64h From the second logic diagram of Fig. 6.4a. it is immediately seen that K 1 the logic diagram reverts to the basic bistable element of See. 6.1. xs-coupling of two not-gates. Thus, the device has two stable states. This ied by the last row of the function table ‘of the inputs to the SR latch 1s made 0 while the othet ¢ having the Q input becomes 1. This, in turn, is applied as an ate that also has a 1 as its other input, Consequently, the It just oi ‘output of the input to the se nd. nid nand j—4 @ “Unpredictable behavior _ 0 will result if inputs k—4 return to | simultaneously 1a) @) to) Figure 6.4 SA latch. (a) Logic diagrams. (b) Function table where Q* denotes the output Qin response to the inputs. (c) Two logic symbols. ae| DIGITAL PRINCIPLES AND DESIGN Gi if R = Oand S = 1, then the nd-gate becomes 0. Thus, i ' tach a as oo fe = 0, then the latch sets. These conditions are descrit resets: = by the two middle rows of the function table. In either case, when the 0 input re. SR ins its present state. , Seca e input combination causes difficulty , a Similar to the SR latch, the fourth possible i In this case, if 0 is applied to both the S and R inputs, then both outputs become | Now if the inputs subsequently return to 1 simultaneously, then unpredictable be. havior results in a similar way, as was discussed for the SR latch. Thus, the applica. tion of § = R = 0 is normally not recommended. — ; Referring to the function table of Fig. 6.4, it is readily seen that 0 serves to inj. tiate action in the SR latch. That is, a 0 on the S terminal causes the latch to set; while a0 on the terminal causes it to reset. Two symbols for the SR latch are shown in Fig. 6.4c. It should be noted that in. version bubbles appear at the input terminals of the symbols since the latch re- sponds to 0’s on the inputs. 6.2.4 The Gated SR Latch The inputs for both the SR latch and the SR latch just described are asynchronous (or direct). That is, a change in value of these inputs causes an immediate change of the outputs. It is frequently desirable to prevent input activation signals from affect- ing the state of the latch immediately, but rather to have the effect occur at some de- sirable time or, alternatively, to allow the input changes to be effective only during a prescribed period of time. For these situations, a gated SR latch is used. The gated SR latch is also called an SR latch with enable. A gated SR latch is shown in Fig. 6.5a. It consists of the SR latch along with two additional nand-gates and a control input, C, referred to as the enable, gate, ot clock input. The enable input, C, determines when the S and R inputs become effec- tive. As long as the enable input is 0, the outputs of nand-gates A and B are |, which, according to the SR-latch function table of Fig. 6.4b, keeps the SR latch in its current stable state. In this case, any changes on the S and R lines are blocked and the output is said to be latched in its present state, Equivalently, the latch is said to be disabled. This is indicated by the last row of the function table in Fig. 6.50. The crosses in the table under the S and R inputs are interpreted as “regardless of the value” or, simply, “irrelevant.” The remaining four rows of the function table correspond to those situations when the enable signal, C, is 1. In these cases the gated latch is said to be en abled. Here the latch behaves as a regular SR latch. The nand-gates A and B Serve to invert the signals on the S and R input lines when the latch is enabled. ee ay on al one Se R input, in turn, becomes a 0 to the cross-coupled nand-gates and causes the latch to set or reset, res i imulta- neously to both the S and R input terminals when C= B ae in order to avoid the possibility of an unpredictable state if the activation signals are subsequently removed simultaneously or if C is changed to 0 while both the 4