CHAPTER Flip-Flops and Simple Flip-Flop Applications he logic networks studied thus far are combinational networks. A combina T tional network is defined as a two-valued network in which the outputs at any instant are dependent only upon the inputs present at that instant. As a consequence of this definition, it is possible to describe each output of a combina- tional network by a single algebraic expression whose variables are the inputs to the network. The above behavioral definition established only one class of logic networks. Atthis time, attention is tuned to another class of logic networks. A sequential net- work is defined as a two-valued network in which the outputs at any instant are de- pendent not only upon the inputs present at that instant but also upon the past his- tory (or sequence) of inputs. The past history of inputs must be preserved by the network. For this reason, sequential networks are said to have memory. The mecha- nism which is used to explain and represent the information preserved is referred to 48 the internal state, secondary state, ot simply state, of the network. Physically, the internal state is a collection of signals at a set of points within the network. In this way, the inputs at any time to a sequential network, along with its present inter- tal state, determine the outputs of the network. There are two basic types of sequential networks. They are distinguished by the ‘iming of the signals within the network. A synchronous sequential network is one in “hich its behavior is determined by the values of the signals at only discrete instants oftime. These networks typically have a master-clock generator which produces a Sequence of clock pulses. It is these clock pulses that effectively sample the input inal t determine the network behavior. This type of network is formally studied Chapters 7 and 8. The second type of sequential network is the asynchronous se- ential network. In this case the behavior of the network is immediately affected by e “TRU Signal changes. Asynchronous sequential networks are studied in Chapter 9 Sips basic logic element that provides memory in many sequential networks is op. Actually, the flip-flop itself is a simple sequential network, It can be ~~Y DIGITAL PRINCIPLES AND DESIGN shown that all sequential networks require the ana o secs In See. ¢, 7 is seen that feedback is present In flip-flop circuits. A flip-flop has two stable con, i. tions. To each of these stable conditions is associated a state, or, equivalently, the storage of a binary symbol. This chapter is concerned with the structure and Opera. tion of several types of flip-flops and some simple networks, ©. registers ang counters, that are constructed using them. Mt 6.1. THE BASIC BISTABLE ELEMENT Central to all flip-flop circuits is the basic bistable element which is shown in Fig. 6,1, This circuit has two outputs, Q and @. As seen from the figure, it consists of two cross-coupled not-gates, i.e., the output of the first not-gate serving as the input to the second and the output of the second not-gate serving as the input to the first. Clearly, this structure involves feedback. ‘As its name implies, the basic bistable element is a circuit having two stable conditions (or states). To see this, first assume x = 0 in Fig. 6.1. The output of the upper not-gate is then I, i., @ = ¥ = 1. Since the output of the upper not-gate is the input to the lower not-gate, x = y = 1. Consequently, the output of the lower not- gate, ie. jis 0. However, since the output ofthe lower not-gate is connected to the input of the upper not-gate, = 0. This is precisely what was assumed to be the value of x. Thus, the circuit is stable with @ = x = ¥ = Oand Q = 1 Using a similar argument, it is easy to show that if it is assumed that x = 1, then the basic bistable element is stable with Q=x=y=landQ=x=y=0. This is the second stable condition associated with the basic bistable element. ‘As a result of having two stable conditions, the basic bistable element is used to store binary symbols. In the case of positive logic, when the output line Q is 1, the element is said to be storing a 1; while when the output line Q is 0, the element is said to be storing a 0. It should be noted that the two outputs are complementary That is, when Q = 0, Q = 1; and when Q = 1,0 = 0. The binary symbol that is stored in the basic bistable clement is referred to as the content or state of the element. The state of the basic bistable element is given by the signal value at the Q output terminal. Hence, the Q output term! y Figure 6.1 Basic bistable element.CHAPTER 6 Flip-Flops and Simple Flip-Flop Applications called the normal output; while the Q output is referred to as the comple- ** ousput. When the device is storing a 1, it is said to be in its J-state or We other hand, when the device is storing a 0, itis said to be in its O-state ral yt stl ont o rough the bistable element is normally in one of its two stable conditions, is one more equilibrium condition that can exist. This occurs when the two there signals are about halfway between those associated with logic-O and logic-1. our output is not a valid logic signal. This is known as the metastable state. Tes er, a smal! change in any of the internal signal values of the circuit, say, due Homit noise, quickly causes the basic bistable element to leave the metastable oe and enter one of its two stable states. Unfortunately, the amount of time a de- vive can stay in Its metastable state, if it should occur, is unpredictable. For this rea- fon, the metastable state should be avoided. To avoid the metastable state, certain ressictions are placed on the operation of the basic bistable element. This is further iscussed in Sec. 6.3. The basic bistable element of Fig. 6.1 has no inputs. When power is applied, it becomes stable in one of its two stable states. It remains in this state until power is removed. For the circuit to be useful, provisions must be made to force the device into a particular state. A flip-flop is a bistable device, with inputs, that remains in a given state as long as power is applied and until input signals are applied to cause its output to change. It consists of a basic bistable element in which appropriate logic is added in order to control its state. The process of storing a 1 into a flip-flop is called setting or presetting the flip-flop; while the process of storing a 0 into a flip-flop is called resetting or clearing the flip-flop. The inputs to a flip-flop are of two types. An asynchronous or direct input is one in which a signal change of sufficient magnitude and duration essentially pro- duces an immediate change in the state of the flip-flop. In physical circuits, the re- sponse actually occurs after a very short time delay. This point is elaborated upon in Sec. 6.3 when the timing of signals is discussed in greater detail. On the other hand, a synchronous input does not immediately affect the state of the flip-flop, but rather affects the state of the flip-flop only when some control signal, usually called an enable or clock input, also occurs. In the next several sections, various input schemes to the basic bistable element are introduced that result in different types of flip-flops. 6.2 LATCHES The storage devices called Jatches form one class of flip-flops. This class is charac- lerized by the fact that the timing of the output changes is not controlled. That is, the output essentially responds immediately to changes on the input lines, although special control signal, called the enable or clock, might also need to be present. lus, the input lines are continuously being interrogated. In Secs. 6.4 and 6.5 flip- fops in which the timing of the ‘output changes is controlled are studied. It this case, ‘te inputs are normally sampled and not interrogated continuously.es AND DESION 304 DIGITAL PRING 6.2.1 The SR Latch Figure 6.2a shows the SR (or set-reset) latch that consists Of two cross-coupled ny, gates. It has two inputs, S and R, referred to as the set and reset inputs, and two oy, puts, Q and @. As is immediately evident from the second logic diagram in Fig, 6 then § = R = 0, the logic diagram simplifies to the basic bistable element descrity in the previous section, i.e., the cross-coupling of two not-gates. Thus, the latch isin Cone of its two stable states when these inputs are applied. This condition correspond, to the first row of the function table given in Fig. 6.2b. In the table, Q denotes the present state ofthe latch. That is, Q is the state of the device at the time the input si. nals are applied. The response of the latch at the Q and Q output terminals as acon. sequence of applying the various inputs is denoted by Q* and Q", respectively ‘Thus, Q* is called the next state of the latch. For $ = R = 0, the entries Q and Qin the Q* and Q* columns, respectively, are interpreted to mean that the next state of the device is the same as its present state. That is, the outputs do not change and the present state is retained. Now assume a 1 is applied to the R input of the upper nor-gate in Fig. 6.2a and 0 is applied to the S input of the lower nor-gate. Regardless of the second input to the upper nor-gate, the output Q must become 0 since R = 1. This signal, whichis fed back to the lower nor-gate along with the 0 on the S input, causes the output of the lower nor-gate, Q, to become 1. Thus it is seen that a 1 on the R input and 0 on the S input results in the latch being reset. This is given by the second row of the function table in Fig. 6.2. If the input R is subsequently returned to 0, then the latch retains its present reset state as described by the first row of the function table R R iG 9 = *Unpredictable behavior @ s @ will result if inputs ‘ return to 0 simultaneously ° o 5 @ s al rk @ te Rk ep— © Figure 6.2. Sflatch. (a) Logic diagrams. (b) Function table where Q* denotes the output @in respons? the inputs, (c) Two logic symbols.SHAPTER 6 Flip-Flops and Simple Flip-Flop Applications hed si gnal applied to the lower input of the upper nor-gate maintains the ce ME oand = 1. us similar argument, if a 1 is applied to the S input and a Ois applied to the R B the latch becomes set regardless of its present state. That is, the new out- ge @ = 1 and Q = 0. This corresponds to the third row of the function table. more, the latch remains in the 1-state when the § input returns to 0. For the three situations just discussed, the outputs Q and @ are complementary. iger now the case when S = R= 1. This causes the outputs of both nor-gates to Gone 0 indicated in the function table, and, consequently, they are not comple. tary oupuss. Difficulty is encountered when the inputs return to 0. If one input sod retum t0O before the other, then the final state ofthe latch is determined by oer in which the inputs are changed. In particular, the last input to stay at 1 de- ees the final state. In the event of both inputs Teturning to 0 simultaneously, the device may enter its metastable state. This is a condition that should be avoided as. discussed previously. Eventually, the device becomes stable, but its final state is un- ,ictable since it is based on such things as construction differences and thermal noise. For this reason, along with the fact that the outputs are not complementary, the 5= R= | input is frequently regarded as a forbidden input condition. From the function table of the SR latch it should be noted that a 1 serves as the activation signal of the device. That is, a 1 on either the S or R input terminal causes the device to set or reset, respectively. Furthermore, since changes on the $ and R inputs can immediately affect the outputs of the latch, the S and R inputs are re- garded as asynchronous (or direct) inputs. Two logic symbols for the SR latch are given in Fig. 6.2c. In the second sym- bol, the output bubble indicates the inversion of the normal state of the latch. Thus the output terminal with the bubble corresponds to @. int 0 6.2.2 An Application of the SR Latch: A Switch Debouncer Acommon problem involving switches is the occurrence of contact bounce. This is illustrated in Fig. 6.3a. As indicated by the waveforms, with the center contact of the switch in its lower position, the voltage at terminal B is + V volts, while the volt- age at terminal A is zero. Now if the center contact is moved from its lower position ‘0 its upper position, then it is noted that the voltage at terminal B first becomes 210, followed by the voltage at terminal A becoming +V volts when the center Contact reaches the upper terminal. However, as a result of contact bounce, the cen- ‘er contact of the switch leaves terminal A, causing the output voltage at that termi- ‘0 return to zero, and then upon returning to terminal A, causing the voltage at terminal A to become +V volts again. This opening and closing effect, due to the ‘Pringiness of the contacts, may occur several times before the center contact of the “witch remains in its upper position. It is important to note that during contact Ounce, the center contact does not return all the way to terminal B. Similarly, as in- dicated by the waveforms of Fig. 6.34, contact bounce again occurs when the Switch is moved from its upper position to its lower position. The effect of contact ~~DIGITAL PRINCIPLES AND DESIGN Vs v 0 ——* Tie Ve v ° Ti (a) me Va | iif | 0 Time Vs Vv Q 0 Time ep— 2 ‘Time Q Ti O} Figure 6.3 An application of the SR latch. (a) Effects of contact bounce. (b) A switch debouncer. bounce is normally undesirable. For example, in the case of push-button keys on @ keyboard, contact bounce may cause a system to respond as though a key was de- pressed several times in succession. A very simple, but important, application of the SR latch is to eliminate the ef fect of contact bounce. A switch debouncer circuit and corresponding waveforms© So Aap: are Seow Fro-Fap ADORCaIOrs in fap @ 36 Assume prsmive logic en that +) volts corresponds 80 «ground #6 Jaen 6 By use off the tee uh den reactors, hope 0 values vm w Cand R terminal: of the SR latch whenever the center contact of pee rare ted ie ethos terminars 4 or Bo¢@ a Senever the sartch ts The wer the cent upper poe “ ay if tote b reraains 1 IS Tee! ate unit! the center contact reaches Fermanal bs enim the (output of the SR latch becomes 1 If the va itch now opens, as rewayt nt ceantac! HOUTCE ADEN the O input to the § ami R termmmals of the latch vine. te () a! (7 outputs to remain unchanged Hence, by use ot the SR latch. the tal cemtact bounce 1s eliminated. In a similar manner, the effect of contact ‘ale chiminated when the switch moves from its upper position £0 its. omtact mon este oma ot Be pare ee penance awer postion 6.2.3 The $RLatch Awother type of latch, the SR latch, 1s constructed by cross-coupling two nand- yates Such a latch 15 shown in Fig, 64a and its function table is given in fy 64h From the second logic diagram of Fig. 6.4a. it is immediately seen that K 1 the logic diagram reverts to the basic bistable element of See. 6.1. xs-coupling of two not-gates. Thus, the device has two stable states. This ied by the last row of the function table ‘of the inputs to the SR latch 1s made 0 while the othet ¢ having the Q input becomes 1. This, in turn, is applied as an ate that also has a 1 as its other input, Consequently, the It just oi ‘output of the input to the se nd. nid nand j—4 @ “Unpredictable behavior _ 0 will result if inputs k—4 return to | simultaneously 1a) @) to) Figure 6.4 SA latch. (a) Logic diagrams. (b) Function table where Q* denotes the output Qin response to the inputs. (c) Two logic symbols. ae| DIGITAL PRINCIPLES AND DESIGN Gi if R = Oand S = 1, then the nd-gate becomes 0. Thus, i ' tach a as oo fe = 0, then the latch sets. These conditions are descrit resets: = by the two middle rows of the function table. In either case, when the 0 input re. SR ins its present state. , Seca e input combination causes difficulty , a Similar to the SR latch, the fourth possible i In this case, if 0 is applied to both the S and R inputs, then both outputs become | Now if the inputs subsequently return to 1 simultaneously, then unpredictable be. havior results in a similar way, as was discussed for the SR latch. Thus, the applica. tion of § = R = 0 is normally not recommended. — ; Referring to the function table of Fig. 6.4, it is readily seen that 0 serves to inj. tiate action in the SR latch. That is, a 0 on the S terminal causes the latch to set; while a0 on the terminal causes it to reset. Two symbols for the SR latch are shown in Fig. 6.4c. It should be noted that in. version bubbles appear at the input terminals of the symbols since the latch re- sponds to 0’s on the inputs. 6.2.4 The Gated SR Latch The inputs for both the SR latch and the SR latch just described are asynchronous (or direct). That is, a change in value of these inputs causes an immediate change of the outputs. It is frequently desirable to prevent input activation signals from affect- ing the state of the latch immediately, but rather to have the effect occur at some de- sirable time or, alternatively, to allow the input changes to be effective only during a prescribed period of time. For these situations, a gated SR latch is used. The gated SR latch is also called an SR latch with enable. A gated SR latch is shown in Fig. 6.5a. It consists of the SR latch along with two additional nand-gates and a control input, C, referred to as the enable, gate, ot clock input. The enable input, C, determines when the S and R inputs become effec- tive. As long as the enable input is 0, the outputs of nand-gates A and B are |, which, according to the SR-latch function table of Fig. 6.4b, keeps the SR latch in its current stable state. In this case, any changes on the S and R lines are blocked and the output is said to be latched in its present state, Equivalently, the latch is said to be disabled. This is indicated by the last row of the function table in Fig. 6.50. The crosses in the table under the S and R inputs are interpreted as “regardless of the value” or, simply, “irrelevant.” The remaining four rows of the function table correspond to those situations when the enable signal, C, is 1. In these cases the gated latch is said to be en abled. Here the latch behaves as a regular SR latch. The nand-gates A and B Serve to invert the signals on the S and R input lines when the latch is enabled. ee ay on al one Se R input, in turn, becomes a 0 to the cross-coupled nand-gates and causes the latch to set or reset, res i imulta- neously to both the S and R input terminals when C= B ae in order to avoid the possibility of an unpredictable state if the activation signals are subsequently removed simultaneously or if C is changed to 0 while both the 4CHAPTER 6 Flip-Flops and Simple Flip-Flop Applications nei a *Unpredictable behavior will result Da if S and R return to 0 simultaneously +1 z or C returns to 0 while S and R are 1 (@ © —s Q Ss Q c ic 0 p- © = 2 % s figure 6.5. Gated SRiatch. (2) Logic diagram. (b) Function table where Q* denotes the output Qin response to the inputs. (c) Two logic symbols. activation signals are present. Since the effects of the S and R inputs are depen- dent upon the presence of an enable signal, these inputs are classified as syn- chronous inputs. ‘Two symbols for the gated SR latch are given in Fig. 6.5c. Again, the output terminal having the bubble corresponds to Q. 6.2.5 The Gated D Latch The three latches discussed thus far each has an input combination that is not rec- ‘ommended, In particular, the situation in which both of the noncontrol inputs, i.e., Sand R or S and R, are simultaneously active. The gated D (or data) latch, whose logic diagram and function table are shown in Fig. 6.6a-b, does not have this problem, The gated D latch is a gated SR latch in which a not-gate is connected between theS and R terminals. Thus, the latch consists of a single input D that determines its ‘Next state and a control, i.e., enable, input C that determines when the D input is ef- fective. As indicated in the function table, when the latch is enabled, ie., C = 1, the Sulput of the latch follows the values applied to the D input terminal. In particular, ED = 0, then the latch switches to or remains in the O-state; while if D = 1, then the latch switches to or remains in the 1-state. However, when the latch is disabled, ExC = ©. the latch remains in the state prior to the enable signal going to 0. Two 'tic symbols for the gated D latch are given in Fig. 6.6c. ~ Oh sec se o}— ep— ©. Gated Diatch. (a) Logic diagram, (b) Function table where Q* denotes the output Qin response to the inputs. (c) Two logic symbols. 6.3 TIMING CONSIDERATIONS ‘The function tables for the various latches introduced specify the state outputs asa result of applying the input signals. However, the responses to the inputs are not re- ally immediate, but rather occur after some appropriate time delay. This is due to the time delays associated with the gates themselves, as was discussed in Sec. 3.10. Furthermore, to achieve the desired responses, certain timing constraints must nor- mally be satisfied. These timing constraints are presented in this section with refer- ence to latches; however, they also pertain to the additional types of flip-flops that are discussed in the next two sections, A convenient way of showing the terminal behavior of a flip-flop is the timing diagram. A timing diagram is a graph that depicts the input and output transitions of a flip-flop as a function of time, 6.3.1 Propagation Delays The propagation delay is the time it takes a change in an input signal to produce @ change in an output signal. In general, the propagation delay between each pair of input and output terminals is different, as well as whether the change causes the OU put to go ora to high, ie., from 0 to 1 in positive logic, or from high to lov i.e., from 1 to 0 in positive logic. The various propagati f a flip-flop a specified by the manufacturer, eet ieee Propagation delays in an SR latch are illustrated in Fig. 6.7. Finite slopes the rising and falling edges of the signals are shown since their midpoints are vse in the Specitientians of the delay times. This figure shows the effect of first setiné and then resetting an SR latch. It should be noted that the outputs do not change” ad !_ DIGITAL PRINCIPLES AND DI by changes on the information input lines, ie., the S, R, and D lines. This Prope is referred to as transparency. In certain applications this is an undesirable Prope Rather, it is necessary that the output changes occur only coincident with chan ‘on a control input line. This is particularly the case when itis necessary to sense es current state of a flip-flop while simultaneously allowing new state informay be entered as determined by the information lines. The property of having they ing of a flip-flop response being related to a control input signal is achieveg ma master-slave and edge-triggered flip-flops. ; A master-slave flip-flop consists of two cascaded sections, each capable Of sto. ing a binary symbol. The first section is referred to as the master and the secon section asthe slave. Information is entered into the master on one edge or level control signal and is transferred to the slave on the next edge or level ofthe conn signal. In its simplest form, each section is a latch 6.4.1 The Master-Slave SR Flip-Flop Figure 6.12a shows the master-slave SR flip-flop as constructed from two gated sp latches and an inverter. The information input lines $ and R are used to set and reset the flip-flop. A clock signal, C, is applied to the control input line. The timing behay. ior of the master-slave flip-flop is referenced to the control signal. This behavior isi lustrated in Fig. 6.125. The transition of the control signal from its low to high value, i.e., 0 to | in positive logic, is called the rising, leading, or positive edge of the control signal; while the transition of the control signal from its high to low value, ie,, 1 100 in positive logic, is called the falling, trailing, or negative edge of the control signal Referring to Fig. 6.12, as long as C = 0 the master, being a gated SR latch, is dis abled and any changes on the S and R input lines are ignored. At the same time, the slave is enabled due to the presence of the inverter. Hence, the slave is in the same stale as that of the master since the Qj, and Qy outputs of the master are connected to the S and R inputs, respectively, of the slave. As the control signal starts to rise, the slave is disabled, by design, at time 1; while the master remains disabled. Thus, the slave be- comes disconnected from the master but retains the state of the master. The control sig- nal continues to rise, and it is at time 1 that the master is enabled. Wile C = 1, the master, being a gated SR latch, responds to the inputs on the S and R lines, as was discussed in Sec, 6.2. Meanwhile, since the slave is disabled due to the presence of the inverter, any changes to the state of the master are not reflected to the slave. The control signal is subsequently retumed to its low level at time ty. At this time, the mas ter is disabled, causing it to latch onto its new state. However, it is not until time t that the slave is enabled. This results in the slave taking on the state of the master as the connection is made. It is important to note that for very short periods during the rising and falling edges of the control signal both the master and slave latches are disabled. This is critical to the operation of a master-slave flip-flop. It should be observed that although the master can change its state (and, cO™ spondingly, its output) at any time while the control signal is 1, it is only as the CO" trol signal goes from 1 to 0 that the slave changes its state. Thus, the output chane® of the master-slave flip-flop is synchronized to the falling edge of the control sign ‘hi, adCHAPTER 6 Flip-Flops and Simple Flip-Flop Applications aa — s s Q a Q 1 ——¢——C ~ ro cmck Oy G a R & @ Rk ob= o Master Ne Slave @ Master disabled a Master enabled Master disabled \ a ~ Ki a bh Clock: i" (c) ie Save ‘enabled + Slave disabled i Slave enabled a a [ i! CO) ‘| Outputs | ss 70}— | an sr ag s o7@ Undefined Undefined | —Rr =9b— x x @ a © @ Figure 6.12 Master-siave SA flip-flop. (a) Logic diagram using gated SR latches. (b) Flip-flop action during the control signal. (c) Function table where Q* denotes the output Q in response to the inputs. (d) Two logic symbols.OD DIGITAL PRINCIPLES AND DESIGN This controlling of the output change to be coincident with the change on the cop, trol input line is precisely the property being sought by flip-flops not in the lary category. The master-slave principle is one way in which this property is achieved, ‘The behavior of the master-slave SR flip-flop is summarized by the function table in Fig, 6.12c. The pulse symbol in the C column, _[7L, indicates that the master is enabled while the control signal is high and that the state of the master jg transferred to the slave, and, correspondingly, to the output of the flip-flop, at the end of the pulse period. Special attention should be given to the fourth row of the function table. This row corresponds to the situation of both $ and R being | when the control signal goes from high to low. Since the master is a latch, it enters an un. predictable state, including the possibility of the metastable state. This state value is then subsequently transferred to the slave. Hence, the output of the master-slave SR flip-flop itself becomes unpredictable, Such a condition should be avoided. Since the behavior of master-slave flip-flops constructed from latches is dependent upon the rising and falling edges of the control signal as well as the period of time in which the control signal is high, they are also referred to as pulse-triggered flip-flops. Two logic symbols for the master-slave SR flip-flop are given in Fig. 6.124. The 1 symbol, called the postponed-output indicator, at the output terminals is used to imply that the output change is postponed until the end of the pulse period. For the master-slave flip-flop of Fig. 6.12a, this corresponds to the time when the control sig- nal goes from high to low. Also, as in the case of latches, bubble notation is used to in- dicate the complementary output @ of the flip-flop in the second logic symbol shown. Figure 6.13 shows a timing diagram for the input and output terminals of a master-slave SR flip-flop along with a timing diagram for the output terminals of the master section of the flip-flop. For simplicity, the finite slopes of the rising andy CHAPTER 6 Flp-Fips and Simple Flip-Flop Applications ges of the signals are not shown and the Propagation delays are assumed to jal. However, the sequence of events during the rise oH fall meee the occurring, ang 8 I equi 2 i Et C 1 signal as indicated in Fig. 6.12b is still 2 The Master-Slave JK Flip-Flop since the output state of a master-slave SR flip-flop is undefined upon returning the cai input to O when S = R = 1. it is necessary to avoid this condition. The master. sve JK fp-flop, on the other hand, does allow its two information input lines to be simultaneously 1. This results in the toggling of the Output of the flip-flop. That is, if ie resent state is O, then the next state is 1; while if the present state is 1, then the vex state is 0. The logic diagram of a master-slave JK flip-flop is shown in Fig. 6.14a, The J and K inputs have the effect of setting and resetting the flip-flop, respectively, and hence are analogous to the S and R inputs of the master-slave SR flip-flop. In ad. dition, wo and-gates are used to sense and steer the state of the slave. To see how this flip-flop works, assume the master-slave JK flip-flop of Fig. 6.14a isinits 1-state, the control signal, i.e., the clock, is 0, and that J = K = 1. Thus, the master and slave latches are both in the I-state with @ = Q, = 1 and @ = Q, = 0. As areslt ofthe feedback lines, the output of the J-input and-gate is logic-0 and the out- gutof the K-input and-gate is logic-1. The net effect is that § = 0 and R = 1 at the in- puts to the master latch, although these inputs cannot affect the state of the master at this time since C = 0. If the clock is now changed from 0 to 1, then the master resets; while the slave, being disabled, remains in its 1-state. However, upon the clock retum- ing t 0, the content of the master is transferred to the slave, causing the new state of the master-slave JK flip-flop to become the 0-state. Thus, the output of the master- slave JK flip-flop toggled when J = K = 1 as the result of the control signal Now assume the master-slave JK flip-flop is in its O-state, again J = K = 1, and tbe control signal, i.e., the clock, is low. Thus, @ = Qs = 0 and Q = Qs = 1. In this ‘ase the output of the J-input and-gate is logic- 1; while the output of the K-input and- files logic-0. At the master input terminals, S = 1 and R = 0. Hence, when the clock iSchanged from 0 to 1, the master enters its I-state, which is subsequently transferred ‘othe slave when the clock changes from | to 0. Again, the state of the master-slave Jk fip-flop toggled. The toggling behavior of the flip-flop when J = K = 1 is indi- Caled by the fourth row in the function table shown in Fig, 6.14b. Consider now the third row of the function table that indicates that a 1 on just ‘he J input line has the effect of setting the flip-flop. To see this, assume the master- Save JK ip-flop is in its 1-state when the clock is low. Thus, @ = Qs = 1 and = Qs = 0. Since the slave is enabled and in its 1-state, the master must also be in 'S l-state i¢., Qy = 1 and Qy = 0. If J = 1 and K = 0, then the outputs of both id-Bates are logic-O since they each have a 0 on one of their inputs, i.e., the upper ‘td-gate has Q, = 0 and the lower and-gate has K = 0. Consequently, at the input teminals of the master, § = R = 0. When the clock becomes 1, the state of the mas- S not change, i.e., it remains in its 1-state. Upon returning the clock to 0, the » Which in turn iakes on the value of the master, also remains in its 1-state. )_ Ov the other hand, if the master and slave latches are in their O-states when * 1K = 0, and the clock is low, then Q = Qu = Qs = Oand Q = 0, ae Be slave, 317@ > 5 @ | 0 Os 1 . r e 3 Slave — (a) sy ag ae Kk oO —F =1¢;— eter se Aeb- © Figure 6.14 Master-slave JK flip-lop. (a) Logic diagram using gated SR latches. (b) Function table where @” Genotes the output Qin response to the inputs. (c) Two logic symbols, | The output of the J-input and-gate is logic-1 and the output of the K-input and-gle is logic-0. Thus, 5 = 1 and R = 0 at the inputs to the master latch, When the clock goes high, the master is set. The 1-state of the master is then subsequently trans- n the clock returns to 0. In summary, regardless of its present state when J = | and K = 0, the master-slave JK flip-flop enters or remains in its, I-state upon the occurrence of the pulse signal on the control line. This corresponds to the third row of the function table. By a similar argument, if J = 0 and K enters or remains in its 0-state after a clock is described by the second row of the functi = 1, then the master-slave JK flip-flop Pulse has occurred. This resetting effect on table,- Considering the remaining rows of the function table, the first row indicates 1 ine master-slave JK flip-flop retains its current state when J = K = 0 during a clock pulse. Similarly, the last row indicates that whenever the clock is low, i.e., er the state of the flip-flop does not change. C= (Fig, 6.14¢ two symbols are shown for the master-slave JK flip-flop. Again, tponed-output indicator is used to symbolize that the output change occurs tancdent with the falling edge of the control signal, i., when the control signal changes from 1 t0 0. For ease of the above analysis, the logic-I values on the J and K lines were as- «umed to be applied prior to the application of the clock pulse. In actuality, these values can occur anytime while the control signal is 1 since the master, being a latch, is enabled during that time, ‘A timing diagram illustrating the behavior of a master-slave JK flip-flop is shown in Fig. 6.15. Again, for simplicity, propagation delays are assumed to be qual and the finite slopes of the rising and falling edges of the signals are not shown, In addition, manufacturer’s constraints regarding minimum width of the sig- tals, ie., minimum time durations that signals are applied, and setup and hold times of the information signals relative to the control signal must be adhered to for proper operation of master-slave flip-flops. It is assumed these constraints are satis- fied in the timing diagram of Fig. 6.15. CHAPTER 6 Flip-Flops and Simple Flip-Flop Applications a1 6.4.3 O's and 1’s Catching As was indicated above and illustrated in Fig. 6.15, the master of the master-slave JK flip-flop, being a latch, is enabled during the entire period the control signal is 1. Flaure 6.15 Timing diagram for a master-slave JK tlip-tlopSESS SEE Toe DIGITAL PRINCIPLES AND D! ts 1-state, then a logic-1 on the K input line while latch to reset. This subsequently results in the slave becoming reset when the control signal returns to 0. An example of this o, curred during the second clock pulse in Fig. 6.15. This behavior is known as 9°, catching. It should be noted that once the master latch is reset bya logic-1 signal on the K input line, a subsequent logic-1 signal on the J input line during the same pe. riod in which C = 1 does not cause the master to again become set. This is due to the fact that since the slave does not change its state until C retums to 0, the feedback signal from the slave, i.e., Qs = 0, keeps the output of the J-input and-gate at logic.0, Ina similar manner, if the slave is storing a 0, then a logic-1 on the J input ling while the control signal is 1 causes the master latch to be set, which subsequently results in the setting of the slave upon the occurrence of the falling edge of the con. trol signal. This behavior occurred during the third clock pulse in Fig. 6.15 and is known as J's catching. In many applications, the 0's and 1s catching behavior is undesirable. Hence, it is normally recommended that the J and K input values should be held fixed during the entire interval that the master is enabled. To satisfy this constraint, any changes in the J and K inputs must occur while the control signal is 0. This was done during the first and fourth clock pulses in Fig. 6.15. The function table of Fig. 6.146 does not ac- count for 0's and 1’s catching but, rather, assumes the J and K inputs are held fixed during the entire period the control signal is 1. The problem of 0’s and 1's catching is also solved by the use of another class of flip-flops called edge-triggered flip-flops. This class of flip-flops is studied in Sec. 6.5. Alternatively, a variation of the master- slave flip-flop, called the master-slave flip-flop with data lockout, is available that is not subject to 0's and 1's catching. This variation also is discussed in the next section. Thus, if the slave latch is in it control signal is 1 causes the master l 6.4.4 Additional Types of Master-Slave Flip-Flops So far the master-slave SR and JK flip-flops have been discussed. From these, addi- tional types of master-slave flip-flops can be constructed. For example, by placing an inverter between the S and R inputs of a master-slave SR flip-flop, as shown in Fig. 6.16, a master-slave D flip-flop is obtained. Another type of master-slave flip-flop is shown in Fig. 6.17a, where the J and K input terminals are tied together so that T = J = K. In this case the flip-flop a@ aa 70 @ ® Figure 6.16 Master-siave Dilip-flop. (a) Logic diagram using a master-slave SR tli” flop. (b) Two logic symbols. 4—T 70h 17 v9 S| oeeweee | (a) () 0 Figure 6.17 Master-slave Tlip-fop. (a) Lo gic diagram usin where Q° denotes the output 'g @ master-slave JK flip-flop. (b) Function table Qin response to the inputs. (c) Two logic symbols. changes state, or toggles, with each control Pulse if T = | and retains its current state with each control pulse if T = 0, This is called a master-slave T ‘flip-flop. The function table of the master-slave T flip-flop and its logic symbols are given in Fig, 6.17b-c. 6.5 EDGE-TRIGGERED FLIP-FLOPS In basic master-slave flip-flops, the master is Control input is 1. As was mentioned previously, this can result in 0's and 1's catch. ing, To avoid the catching problem, the signals on the information lines are re. Sticted from changing during the time the master is enabled. In this way the state of the master is established during the positive edge of the control signal and then ‘ransferred to the slave on the negative edge of the control signal. As a consequence ofthis process, the effect of the information signals appears delayed at the output of ‘he master-slave flip-flop. Edge-triggered flip-flops use just one of the edges of the control, ie, clock, sig- tal o affect the reading of the information input lines. This is referred to as the trig- fering edge. These flip-flops are designed to use either the positive or negative tran- ation of the control signal for this purpose. The response to the triggering edge at tk outputs of the flip-flop is almost immediate since it is dependent only on the Propagation delay times of its components. Once the triggering edge occurs, the "plop remains unresponsive to information input changes until the next triggering ‘ge of the control signal. enabled during the entire period the 65.1 The Positive-Edge-Triggered D Flip-Flop The logic diagram of a positive-edge-triggered D flip-flop is shown in Fig. 6.18, where D is the information input and C is the control, or clock, input. By Positive- ‘dee-riggered it is meant thatthe setting or resetting of the flip-flop is established the rising, or Positive, edge of the control signal. The behavior of ie re ‘dge-triggered D flip-flop, given-in Fig, 6.18b, is similar to that of the D ch, wi Major difference being that the value of the D input is transferr Ae Bel oor “nly as a consequence of the rising edge of the signal on the control line. Thus, the . Oe | ( |DIGITAL PRINCIPLES AND DESIGN Clock (C) 4 an LAY + () Te @ © Figure 6.18 Positive-edge-triggered Dtlip-tlop. (a) Logic diagram.(b) Function table where Q* denotes the output Qin response to the inputs. (¢) Two logic symbols. positive edge of the control input has the effect of sampling the D input line. Thisis indicated in the function table by the 1 symbol. At all other times, including the time while the clock is at 1, the D input is inhibited and the state of the flip-flop can- not change. To see how the positive-edge-triggered D flip-flop operates, consider the logic diagram in Fig. 6.18a. Nand-gates 5 and 6 serve as an SR latch whose behavior was previously described by the function table in Fig. 6.46. Thus, as long as 5 = R = | the state of the latch cannot change; while whenever either S or R is 0, but not both, the latch sets or resets, respectively. Assume the control input, i.e., clock, C, is 0. Regardless of the input at D, the outputs of nand-gates 2 and 3 are 1. These signals are applied to the SR output latch, causing it to hold its current state. Now assume that D is also 0. This holds the output of gate 4 at 1. In turn, the output of gate | is 0 since the outputs of gates and 4 are 1"s. When the clock goes from 0 to 1, i.e., the positive edge of the cont! Signal, all three inputs to gate 3 become 1, causing the output of the gate to change to 0. Meanwhile, the output of gate 2, 5, remains at | since the output of gate ! still 0. The 0 on the R line and the 1 on the 5 line cause the SR latch to enter or main ivits reset state, ie., Q = 0 and Q = 1. In addition, the output of gate 3, which is currently 0, is also fed back as an input to gate 4. This:now keeps the output gate 4 at J, and any subsequent changes in the D input while C is 1 have no elle upon the output of gate 4 and, correspondingly, gate 1. Thus, after the occurrence ©- (CMAPTER 6 Flip-Flops and Simple Flip-Flop Applications sitive edge of the clock signal when D = 0, the flip-flop is in its 0-state and Manges in the D input are inhibited even though the clock is 1. stain assume C = 0, but now let D = 1, As before, the outputs of gates 2 and 1, causing the SR latch to hold its current state. However, the D = 1 input “oes the output of ate 4 to be 0, and this output, in turn, causes the output of gate ioe 1. Now when the clock changes to 1, both inputs to gate 2 are 1 and, conse- cently, its output, S, becomes 0. Since the output of gate 4 is 0, the output of gate $j & remains at 1. The S = O and R = 1 results in the setting of the SR latch con- sisting of gates 5 and 6. The 0 output from gate 2 serves as an input to both gates 1 and3 that, in turn, guarantees that their outputs remain at 1. Thus, if D should sub- sequently change from 1 to 0 while the clock is 1, causing the output of gate 4 to change, then the outputs of gates 1 and 3 do not change. Therefore, once the posi- five edge of the clock has occurred, changes in the D input while C = 1 have no ef- fect upon the state of the flip-flop. In summary, only upon the occurrence of the positive edge of the clock signal does the flip-flop respond to the value of the D input. Once the new output state is established, changes in the D input while C = 1 are ineffectual. When the clock sig- ra) returns to 0, both S and R become 1, and the SR latch retains the state entered as consequence of sampling the D input by the positive edge of the control signal. Two logic symbols for the positive-edge-triggered D flip-flop are shown in Fig. 6.18c. Since the outputs of the flip-flop respond essentially immediately to the positive edge of the control signal, postponed-output indicators do not appear. To signify that the output change can only occur as a consequence of the transi- tion of the control signal, a triangular symbol, called the dynamic-input indicator, isused at the control input of the logic symbol Figure 6.19 shows a timing diagram for the positive-edge-triggered D flip-flop. For simplicity, the finite slopes of the rising and falling edges of the signals are not shown and all propagation delays are assumed to be equal. Indicated in Fig. 6.19 are the setup, 1,,, and hold, f,, times with respect to the triggering edge of the control signal that need to be satisfied. During these times the D input must not change; otherwise, an unpredictable output, including the metastable state, is possible. Time Figure 6.19 Timing diagram for a positive-edge-triggered D flip-flop 323DIGITAL PRINCIPLES AND DESIGN D Q Clk—OP C Inputs aL D @ ck _- @ () Figure 6.20 Negative-edge-triggered Dtlip-flop. (a) Function table where Q* denotes the output Qin response to the inputs (b) Two logic symbols. 6.5.2 Negative-Edge-Triggered DFlip-Flops A slight variation of the positive-edge-triggered D flip-flop is the negative-edge- triggered D flip-flop. In this case the falling edge, i.e., a high to low transition, of the control signal is used to sample the D input line rather than the rising edge. This can be achieved by simply placing an inverter at the control input of the fip- flop shown in Fig. 6.18a. The function table and logic symbols for this type of flip- flop are given in Fig. 6.20. It should be noted that an inversion bubble appears at the control input of the symbol in addition to the dynamic-input indicator. This in- version bubble and dynamic-input indicator combination denotes negative-edge triggering. 6.5.3 Asynchronous Inputs Earlier in this chapter, the information inputs of flip-flops were categorized into two types: synchronous and asynchronous. These inputs are distinguished by whether or not they require the presence of a control signal to make them effec- tive. All the information inputs of the edge-triggered and master-slave flip-flops that have been presented thus far are synchronous inputs. To provide greater flexibility, many flip-flops have both asynchronous and synchronous inpuls within the same device. The asynchronous inputs, usually called preset (denote by PR) and clear (denoted by CLR), are used to forcibly set and reset the flip- flop, respectively, independently of the control input. These inputs are particl- larly useful for bringing a flip-flop into a desired initial state prior to norm! clocked operation.