Lightweight Network-on-Chip Router on Research and Design

lZhengzhou Institute of Information Science and Technology, Zhengzhou 450000, China

2State Key Lab of ASIC and System, Fudan University, Shanghai 200433, China
* Email: yrdu_ieu@163.com

Abstract interaction application (e.g. crypto-operation), a complex

router design will not bring a significantly performance
In order to solve the repeated design of NoC router, this improvement but a huge hardware source consumption,
paper proposed a lightweight NoC router after a study of even reduce the performance of NoC. To solve the
NoC's characteristics and Operating mode. In the low problem above, this paper proposed a lightweight NoC
frequency data interaction application, the proposed router based on full combinational logic structure with
router has a high cost performance. It can be mapped in a less hardware resource consumption and the routing
variety ofNoC topology by changing the number of each delay. This lightweight NoC router can effectively meet
internal module and that will help to reduce the design the requirements of data interaction in specific domain.
cycle of multi-core NoC system. At the same, the
maximum data throughput is 703.3Gbps, it can 2. Lightweight NoC Router Design
effectively meet the demand of data interaction inNoC.
The lightweight NoC router is designed for low
1. Introduction frequency data interaction application, in this specific
domain, the proposed router can effectively reduce the
The endless pursuit of high performance computing led hardware resource consumption and the manufacturing
to a development of processor technology. It is hard to cost of chip. Considering the low frequency data
improve the processors' performance by shrinking interaction feature, the lightweight NoC router adopt a
feature size when Moore's Law goes to limit, therefore, fixed routing algorithm, virtual 3-D routing algorithm,
multi-core processor design become the mainstream of which based on dimension ordered routing algorithm. In
today. Due to the limited address space and inefficient this way, the data can be transmitted fast inNoC without
core communication, traditional bus-based multi-core the dead-lock or live-lock. The proposed routing
processor structure restricted the multi-core processor algorithm is described as follows:
performance. For this reason, people follow computer
network interconnection structure and then design aNoC Virtual 3-D Routing Algorithm
(Network-on-Chip) structure for multi-core processor, Stepl: Select X dimension coordinate, if the current
this proposed structure provides a wider bandwidth and router coordinate is not equal to the destination
supports multiple communication mode through a router, move the data towards the destination in X
structured network connection. dimension and go back to step], else go to step2.
The most important design in NoC is the design of the Step2: Select Y dimension coordinate, if the current
router, therefore, people did a large number studies router coordinate is not equal to the destination
aimed atNoC router: P Ou proposed a double-layerNoC router, move the data towards the destination in Y
router structure based on packet-controlled and dimension and go back to step2, else go to step3.
circuit-switched[11, Psarras A proposed aNoC router with Step3: Select Z dimension coordinate, if the current
fine-grained pipeline bypassing[21, Morris R W proposed router coordinate is not equal to the destination
a Three-Dimensional Stacked Nanophotonic NoC router, move the data towards the destination in Z
Architecture with Minimal Reconfiguration[31, dimension and go back to step3, else reach the
Noghondar A F proposed a low-cost and latency bypass destination router.
channel-based NoC structure[41. By adopting virtual
channel, wormhole or adaptive routing algorithm will
Adopting virtual 3-D routing algorithm can effectively
effectively reduce the possibility of data congestion in
meet the existing 2-D NoC topology and can easily
NoC, with the attendant consequences of bringing a huge
expand to the 3-DNoC topology.
hardware source consumption. At the same time, the
The main function ofNoC router is to forward the data.
complex routing algorithm will increase the data
The router should achieve the arbitration of input data
transmission delay and cause the loss of multi-core
and determine the output order when multiple input data
processor performance. For low frequency data
go to the same output port. When an input data cannot be

978-1-4673-9719-3/16/$31.00 ©2016 IEEE

immediately forward by router, a data caching structure design is used in the proposed router. Lightweight NoC
is certainly needed, so as to ensure the integrity of the router contains 5 main modules, for respectively, routing
input data. Based on the above, this paper proposed a prediction module (RP), routing selection module (RS),
lightweight NoC router which can achieve the function read-enable generation module (RG), write-enable
of data arbitration, forwarding and caching. generation module (WG) and data caching module (DC).
In order to improve the adaptive of lightweight NoC The structures are shown in figure 1.
router for different topological structure, a modular

Dir_to_N Dir_O

Dir_lo_ S Dir_ 1

Dir_lO_'VI.' Dir_2
Select
Dir_lo_f Dir_J Signal OR-Gate
RDJN
Array Genemte Array
Vir_to_II Dir_4 Circuit

Dir_to_D Dir_5

Dir_to_I, Dir_6

(A) Routi.ng Prediction Module (B) Routing Selection Module (C) Read-enable Generation Module (D) Write-enable Generation Module

Figure l. Internal module of lightweightNoC router

Routing prediction module is the core of lightweight example, mesh structure, star structure, tree structure and
NoC router, it can predict the output direction based on so on. The commonly used NoC topology structure are
the routing algorithm. This paper adopts the virtual 3-D shown in figure 2.
routing algorithm as the basis of routing prediction. At
the same time, routing prediction module contains an
illegal data judgment circuit which can eliminate the
illegal data from NoC in time and reduce the impact on
normal data routing.
Routing selection module achieves the arbitration of
input data, it receives signals from routing prediction
module and selects a direction to output the data based
on the internal arbitration mechanism. routing selection
module can build a routing path from input to the output. (A) 2D·Mesh (B) 3D·Mesh

Lightweight NoC router is designed for low frequency

data interaction application, therefore the routing

*
selection module adopts fixed priority arbitration method
to reduce resource consumption in data arbitration.
Read-enable generation module and write-enable
generation module are used to generate the enable signal
for data cache. At the same time, data caching module
(C) Star (D) Tree
using asynchronous FIFO structure to separate data
processing from data transmission, it will greatly
improve the working clock frequency of the lightweight Figure 2. Commonly usedNoC topology structure
NoC router and the efficiency of the data transmission
between the nearby router. According to the different types of NoC topology
Lightweight NoC router can effectively reduce the structure above, the proposed lightweight NoC router is
hardware resource consumption of NoC. Because of the able to achieve NoC topological mapping. W hen
modular design, the proposed router can meet the variety mapping in NoC, the number of each module in
ofNoC topology with a high cost performance. lightweight NoC router should be calculated, and it is
based on the number of adjacent router and connected
3. Topological Mapping of Lightweight NoC Router processing element (PE).
For different application scenarios, the NoC topology is
There are various types of NoC topology structure, for not as standard as shown in figure 2 and it is often
manifest as the combination of variety of topologies. cache in PE direction, it will reduce the hardware
Considering the essential ofNoC is data forwarding and resource consumption forNoC as a whole.
data caching, our design can make a better support for The proposed lightweightNoC router is designed for low
extensional NoC structures. Because of the proposed frequency data interaction application, the maximum
lightweight NoC router is based on the virtual 3-D data throughput relates to the structure of the router.
routing algorithm, it can provide a routing direction in W hen the proposed router mapping in n direction, the
three dimensions. As for star and its extensional NoC maximum data throughput is:
structure, there are more than one PE are connected to
the router and every two PE could be divided into a pair, 32 x 2 x n x f
which can be defined as a dimension for mapping. Throughput ------ Gbps ( 1)
The modular characteristics of lightweight NoC router 1000

makes it easily to change the structure of router. It can

meet most of the NoC topological mapping without The maximum data throughput is different when n takes
changing the design. In this way, it will shorten the different values. Under the maximum support of the
design cycle for multi-core systems based on NoC lightweightNoC router, the maximum data throughput is
structure in special field. 703.3Gbps when n equals 7.

4. Performance Analysis 5. Summary

In order to evaluate the performance of lightweight NoC In order to reduce the design cycle of multi-core system
router, we completed the logic synthesis based on 55nm based on NoC structure in special field, this paper
CMOS standard-cell library in this section. The results proposed a lightweight NoC router and it realized a
show in table 1 and the router is mapped in 2D-Mesh reconfigurable structure through a modular design. This
NoC topology structure. paper did a logic synthesis based on 55nm CMOS
standard-cell library, the results shows that the critical
Table I. Performance comparison for router structures path delay of the router is 0.637ns and the area is 8.8X
Critical 103flm2. Under the maximum support, the maximum data
Router Technology Area
path delay throughput is 703.3Gbps. Therefore, the lightweight
structure (nm) (flm2)
(ns) NoC router which we proposed can meet the need of
18.8X 106 multi-coreNoC system in special field, and it also has a
Reference[ 1] 65 l.l76
(whole chip) high cost performance.

Reference[2] 45 0.744 105X 103

Acknowledgments
Reference[3] 22 0.200 2X 103
Reference[4] 45 l.000 234X 103
This work was supported by the National Natural
This paper 55 0.637 8.8X 103 Science Foundation of China under Grant 6 1404 175.

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