ICA Complete Manual 2013

Integrated circuits
And applications
(151003)
B.E. 5 SEMESTER
th
LABORATORY MANUAL
2013
Compiled by Guided by
Nitin J. Bathani Dr. K. R. Parmar
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
L. D. COLLEGE OF ENGINEERING, AHMEDABAD.
CERTIFICATE
This is to certify that Mr. /Ms.
_____________________________________________ Roll No.
_______________ and Enrolment no._______________________ Of fifth
semester of B.E____________________ Class has satisfactorily completed
his/her one full semester in “151003 INTEGRATED CIRCUITS AND
APPLICATIONS” satisfactorily in partial fulfilment of Bachelor of
Electronics and communication Engineering degree to be awarded by Gujarat
Technological University.
Nitin J. Bathani Dr. K. R. Parmar

Faculty – A div H.O.D
(E&C Department)
Nirav D. Patel
Faculty – B div
Date: - …. /… /…….
Preface
The purpose of the experiments described here is to acquaint the student with:
(1) Analog & digital devices
(2) Design of circuits by using various ICs
(3) Instruments & procedures for electronic test & measurement.
The aim is to teach a practical skill that the student can use in the course of his or her
own experimental research projects in physics, astronomy, or another science.
At the end of this course, the student should be able to:
(1) Design and build simple circuits of his or her own design.
(2) Use electronic test & measurement instruments such as oscilloscopes, timers,
function generators etc. in experimental research.
Reference
This manual is intended for use with the following textbook.
1. Ramakant Gayakwad,
Op-amp and linear Integrated circuits.
2. Sergio Franco,
Design with Operational Amplifiers and Analog Integrated Circuits
TMH 2009 edition.
3. D. Roy Choudhury and Shail B. Jain,
Linear Integrated circuits,
New age International publishers, 3rd edition.
Data Sheets
Data books, such as the Texas Instruments or National Instruments references for
TTL, CMOS and LINEAR circuits, should be used by the student to check pin
designations, outputs, and other data not given in this lab manual.
Compiled by – Nitin J. Bathani - L. D. College of Engineering, Ahmedabad.
1
CA741, CA741C, CA1458, CA1558,
LM741, LM741C, LM1458
Data Sheet September 1998 File Number 531.4
0.9MHz Single and Dual, High Gain Features

Operational Amplifiers for Military, • Input Bias Current . . . . . . . . . . . . . . . . . . . . 500nA (Max)
Industrial and Commercial Applications
• Input Offset Current . . . . . . . . . . . . . . . . . . . 200nA (Max)
The CA1458, CA1558 (dual types); CA741C, CA741 (single
types); high-gain operational amplifiers for use in military, Applications
industrial, and commercial applications.
• Comparator
These monolithic silicon integrated circuit devices provide
• Multivibrator
output short circuit protection and latch-free operation.
These types also feature wide common mode and • DC Amplifier
differential mode signal ranges and have low offset voltage • Summing Amplifier
nulling capability when used with an appropriately valued
potentiometer. A 10kΩ potentiometer is used for offset • Integrator or Differentiator
nulling types CA741C, CA741 (see Figure 1). Types • Narrow Band or Band Pass Filter
CA1458, CA1558 have no specific terminals for offset
nulling. Each type consists of a differential input amplifier Ordering Information
that effectively drives a gain and level shifting stage having
PART TEMP. RANGE
a complementary emitter follower output. NUMBER (oC) PACKAGE PKG. NO.
The manufacturing process make it possible to produce IC CA0741E -55 to 125 8 Ld PDIP E8.3
operational amplifiers with low burst “popcorn’’ noise CA0741CE 0 to 70 8 Ld PDIP E8.3
characteristics. CA1458E 0 to 70 8 Ld PDIP E8.3
Technical Data on LM Branded types is identical to the CA1558E -55 to 125 8 Ld PDIP E8.3
corresponding CA Branded types. CA0741T -55 to 125 8 Pin Metal Can T8.C
CA0741CT 0 to 70 8 Pin Metal Can T8.C
CA1558T -55 to 125 8 Pin Metal Can T8.C
LM741N -55 to 125 8 Ld PDIP E8.3
LM741CN 0 to 70 8 Ld PDIP E8.3
LM1458N 0 to 70 8 Ld PDIP E8.3
Pinouts
CA741, CA741C (CAN) CA1558 (METAL CAN)
TOP VIEW TOP VIEW
NC V+
8 8
OFFSET OUTPUT OUTPUT
NULL 1 7 V+ (A) 1 7 (B)
A B
INV. 2 - 6 OUT INV. INPUT 2 - + + - 6 INV. INPUT
INPUT + (A) (B)
NON-INV. 3 5 OFFSET NON-INV. 3 5 NON-INV.

INPUT 4 NULL INPUT (A) 4 INPUT (B)
V- V-
CA741, CA741C, LM741, LM741C (PDIP) CA1458, CA1558, LM1458 (PDIP)
TOP VIEW TOP VIEW
OFFSET NULL 1 8 NC OUTPUT (A) 1 8 V+

A
INV. INPUT 2 - 7 V+ INV. INPUT (A) 2 7 OUTPUT (B)
B
NON-INV. INPUT 3 + 6 OUTPUT NON-INV. INPUT (A) 3 6 INV. INPUT (B)
V- 4 5 OFFSET NULL V- 4 5 NON-INV. INPUT (B)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CA741, CA741C, CA1458, CA1558, LM741, LM741C, LM1458
Absolute Maximum Ratings Thermal Information

Supply Voltage Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W)
CA741C, CA1458, LM741C, LM1458 (Note 1) . . . . . . . . . . . 36V PDIP Package . . . . . . . . . . . . . . . . . . . 130 N/A
CA741, CA1558, LM741 (Note 1) . . . . . . . . . . . . . . . . . . . . . 44V Can Package . . . . . . . . . . . . . . . . . . . . 155 67
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Maximum Junction Temperature (Can Package) . . . . . . . . . . 175oC
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Offset Terminal to V- Terminal Voltage (CA741C, CA741) . . . . ±0.5V Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
CA741, CA1558, LM741 . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CA741C, CA1458, LM741C, LM1458 (Note 2) . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Values apply for each section of the dual amplifiers.
2. All types in any package style can be operated over the temperature range of -55oC to 125oC, although the published limits for certain electrical
specification apply only over the temperature range of 0oC to 70oC.
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±15V
TYPICAL VALUE
PARAMETER SYMBOL TEST CONDITIONS (ALL TYPES) UNITS
Input Capacitance CI 1.4 pF
Offset Voltage Adjustment Range ±15 mV
Output Resistance RO 75 Ω
Output Short Circuit Current 25 mA
Transient Response Unity Gain, VI = 20mV, RL = 2kΩ,

Rise Time tr CL ≤ 100pF 0.3 µs
Overshoot O.S. 5.0 %
Slew Rate (Closed Loop) SR RL ≥ 2kΩ 0.5 V/µs
Gain Bandwidth Product GBWP RL = 12kΩ 0.9 MHz
Electrical Specifications For Equipment Design, VSUPPLY = ±15V
(NOTE 4)
(NOTE 4) CA741C, CA1458, LM741C,
CA741, CA1558, LM741 LM1458
TEST TEMP
PARAMETER CONDITIONS (oC) MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage RS ≤ 10kΩ 25 - 1 5 - 2 6 mV
Full - 1 6 - - 7.5 mV
Input Common Mode Voltage Range 25 - - - ±12 ±13 - V
Full ±12 ±13 - - - - V
Common Mode Rejection Ratio RS ≤ 10kΩ 25 - - - 70 90 - dB
Full 70 90 - - - - dB
Power Supply Rejection Ratio RS ≤ 10kΩ 25 - - - - 30 150 µV/V
Full - 30 150 - - - µV/V
Input Resistance 25 0.3 2 - 0.3 2 - MΩ
2
Electrical Specifications For Equipment Design, VSUPPLY = ±15V (Continued)
(NOTE 4)
(NOTE 4) CA741C, CA1458, LM741C,
CA741, CA1558, LM741 LM1458
TEST TEMP
PARAMETER CONDITIONS (oC) MIN TYP MAX MIN TYP MAX UNITS
Input Bias Current 25 - 80 500 - 80 500 nA
Full - - - - - 800 nA
-55 - 300 1500 - - - nA
125 - 30 500 - - - nA
Input Offset Current 25 - 20 200 - 20 200 nA
Full - - - - - 300 nA
-55 - 85 500 - - - nA
125 - 7 200 - - - nA
Large Signal Voltage Gain RL ≥ 2kΩ, VO = ±10V 25 50,000 200,000 - 20,000 200,000 - V/V
Full 25,000 - - 15,000 - - V/V
Output Voltage Swing RL ≥ 10kΩ 25 - - - ±12 ±14 - V
Full ±12 ±14 - - - - V
RL ≥ 2kΩ 25 - - - ±10 ±13 - V
Full ±10 ±13 - ±10 ±13 - V
Supply Current 25 - 1.7 2.8 - 1.7 2.8 mA
-55 - 2 3.3 - - - mA
125 - 1.5 2.5 - - - mA
Device Power Dissipation 25 - 50 85 - 50 85 mW
-55 - 60 100 - - - mW
125 - 45 75 - - - mW
NOTE:
4. Values apply for each section of the dual amplifiers.
Test Circuits
INVERTING -
INPUT 2
6 OUTPUT
NON-INVERTING
3 + -
INPUT
VOUT
+
OFFSET 1 5
NULL 10kΩ
CL RL
VIN
V-
FIGURE 1. OFFSET VOLTAGE NULL CIRCUIT FOR CA741C, FIGURE 2. TRANSIENT RESPONSE TEST CIRCUIT FOR ALL
CA741, LM741C, AND LM741 TYPES
3
Schematic Diagram (Notes 5, 6)

CA741C, CA741, LM741C, LM741 AND FOR EACH AMPLIFIER OF THE CA1458, CA1558, AND LM1458
* V+
D1 D2
Q5 Q10
INVERTING
INPUT *
C1 R7 Q13
30pF 4.5K
Q12
NON-INVERTING R5 R9
INPUT * Q1 Q2 Q11
39K 25
D4
Q3 Q4 R8
* OUTPUT
7.5K
Q8 Q15 R10
50
Q16
Q6 Q7 Q9
* Q14 Q17
OFFSET
NULL
* D3
R1 R3 R2 R4 R12 R11
1K 50K 1K 3K 50K 80K
* V-
NOTES:
5. See Pinouts for Terminal Numbers of Respective Types.
6. All Resistance Values are in Ohms.
Typical Performance Curves

40
TA = 25oC TA = 25oC
15 35 RL ≥ 2kΩ
COMMON MODE INPUT RANGE (V)
30
OUTPUT SWING (VP-P)
25
10
20
15
5 10
0
0
0 5 10 15 20 0 5 10 15 20
DC SUPPLY (V+, V-) DC SUPPLY (V+, V-)
FIGURE 3. COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY FIGURE 4. OUTPUT VOLTAGE vs SUPPLY VOLTAGE FOR ALL
VOLTAGE FOR ALL TYPES TYPES
4
Typical Performance Curves (Continued)
30
DC SUPPLY VOLTS (V+ = 15, V- = -15)
TA = 25oC, CL = 100pF
25
20
OUTPUT (mV)
90%
15
20
5
10%
RISE TIME
0
-0.5 0 -0.5 1.0 1.5 2.0 2.5 3.0
TIME (µs)
FIGURE 5. TRANSIENT RESPONSE FOR CA741C AND CA741
Metallization Mask Layout

CA741CH
0 10 20 30 40 50 60 64
57
50
40
30 54 - 62
(1.372 - 1.575)
20
10
0
4 - 10
(0.102 - 0.254)
61 - 69
(1.549 - 1.753)
CA1458H
104
0 10 20 30 40 50 60 70 80 90 100
55
50
40
30 52 - 60
(1.321 - 1.524)
20
10
0
4 - 10
(0.102 - 0.254)
101 - 109
(2.565 - 2.768)
NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-
3 inch).
5
LM124
 LM224 - LM324
LOW POWER QUAD OPERATIONAL AMPLIFIERS
.. WIDE GAIN BANDWIDTH : 1.3MHz

INPUT COMMON-MODE VOLTAGE RANGE
.. INCLUDES GROUND
LARGE VOLTAGE GAIN : 100dB
.. VERY LOW SUPPLY CURRENT/AMPLI : 375µA

LOW INPUT BIAS CURRENT : 20nA
LOW INPUT OFFSET VOLTAGE : 5mV max. N D
(for more accurate applications, use the equivalent parts DIP14 SO14
.. LM124A-LM224A-LM324A which feature 3mV max)

LOW INPUT OFFSET CURRENT : 2nA
WIDE POWER SUPPLY RANGE :
(Plastic Package) (Plastic Micropackage)
SINGLE SUPPLY : +3V TO +30V

DUAL SUPPLIES : ±1.5V TO ±15V
P
TSSOP14
(Thin Shrink Small Outline Package)
DESCRIPTION ORDER CODES

These circuits consist of four independent, high Part Temperature Package
gain, internally frequency compensated operational Number Range N D P
amplifiers . They operate from a single power supply LM124
o
-55 C, +125 C
o
• • •
over a wide range of voltages. Operation from split
LM224 -40oC, +105oC • • •
power supplies is also possible and the low power
supply current drain is independent of the magni- LM324 o o
0 C, +70 C • • •
tude of the power supply voltage. Example : LM224N
PIN CONNECTIONS (top view)
Output 1 1 14 Output 4
Inve rting Input 1 2 - - 13 Inve rting Input 4
Non-inve rting Input 1 3 + + 12 Non-inve rting Input 4
VCC + 4 11 VCC -
Non-inve rting Input 2 5 + + 10 Non-inve rting Input 3
Inve rting Input 2 6 - - 9 Inve rting Input 3
Output 2 7 8 Output 3
June 1999 1/14

LM124 - LM224 - LM324
SCHEMATIC DIAGRAM (1/4 LM124)
V CC
6 µA
4µA 10 0µA
Q5
Q6
CC
Q2 Q3
Inve rting Q7
inpu t Q1 Q4
R SC
Non-inverting Q11
inpu t Outp ut
Q13
Q10 Q12
Q8 Q9
50µA
GND
ABSOLUTE MAXIMUM RATINGS

Symbol Parameter LM124 LM224 LM324 Unit
Vcc Supply Voltage ±16 or 32 V
Vi Input Voltage -0.3 to +32 V
Vid Differential Input Voltage - (*) +32 +32 +32 V
Ptot Power Dissipation N Suffix 500 500 500 mW
D Suffix - 400 400 mW
- Output Short-circuit Duration - (note 1) Infinite
Iin Input Current – (note 6) 50 50 50 mA
o
Toper Operating Free Air Temperature Range -55 to +125 -40 to +105 0 to +70 C
o
Tstg Storage Temperature Range -65 to +150 -65 to +150 -65 to +150 C
2/14
LM124 - LM224 - LM324
ELECTRICAL CHARACTERISTICS
VCC+ = +5V, VCC– = Ground, VO = 1.4V, Tamb = +25oC (unless otherwise specified)
LM124 - LM224 - LM324
Symbol Parameter Unit
Min. Typ. Max.
Vio Input Offset Voltage (note 3) mV
o
Tamb = +25 C 2 5
LM324 7
Tmin. ≤ Tamb ≤ Tmax. 7
LM324 9
Iio Input Offset Current nA
o
Tamb = +25 C 2 30
Iib Input Bias Current (note 2) nA
o
Tamb = +25 C 20 150
Avd Large Signal Voltage Gain V/mV
(VCC+ = +15V, RL = 2kΩ, VO = 1.4V to 11.4V)
o
Tamb = +25 C 50 100
SVR Supply Voltage Rejection Ratio (RS ≤ 10kΩ) dB
(VCC+ = 5V to 30V)
Tamb = +25oC 65 110
ICC Supply Current, all Amp, no load mA
Tamb = +25oC VCC = +5V 0.7 1.2
VCC = +30V 1.5 3
Tmin. ≤ Tamb ≤ Tmax. VCC = +5V 0.8 1.2
VCC = +30V 1.5 3
Vicm Input Common Mode Voltage Range V
(VCC = +30V) - (note 4)
o
Tamb = +25 C 0 VCC -1.5
Tmin. ≤ Tamb ≤ Tmax. 0 VCC -2
CMR Common-mode Rejection Ratio (RS ≤ 10kΩ) dB
o
Tamb = +25 C 70 80
Tmin. ≤ Tamb ≤ Tmax 60
Isource Output Current Source (Vid = +1V) mA
VCC = +15V, V o = +2V 20 40 70
Isink Output Sink Current (Vid = -1V)
VCC = +15V, V o = +2V 10 20 mA
VCC = +15V, V o = +0.2V 12 50 µA
3/14
LM124 - LM224 - LM324
ELECTRICAL CHARACTERISTICS (continued)

LM124 - LM224 - LM324
Symbol Parameter Unit
Min. Typ. Max.
VOH High Level Output Voltage V
(VCC = +30V)
Tamb = +25oC R L = 2kΩ 26 27
o
Tamb = +25 C R L = 10kΩ 27 28
(VCC = +5V, RL = 2kΩ)
o
Tamb = +25 C 3.5
VOL Low Level Output Voltage (R L = 10kΩ) mV
o
Tamb = +25 C 5 20
SR Slew Rate V/µs
VCC = 15V, VI = 0.5 to 3V, RL = 2kΩ, C L = 100pF,
unity gain) 0.4
GBP Gain Bandwidth Product MHz
VCC = 30V, f = 100kHz, Vin = 10mV
RL = 2kΩ, CL = 100pF 1.3
THD Total Harmonic Distortion %
f = 1kHz, AV = 20dB, RL = 2kΩ, VO = 2Vpp
CL = 100pF, VCC = 30V 0.015
en Equivalent Input Noise Voltage nV
f = 1kHz, Rs = 100Ω, VCC = 30V 40 √
 Hz
DVio Input Offset Voltage Drift 7 30 µV/oC
DIIO Input Offset Current Drift 10 200 pA/oC
VO1/VO2 Channel Separation (note 5) dB
1kHz ≤ f ≤ 20kHz 120
Notes : 1. Shor t -cir cui t s f rom t he out put t o V C C can cause excessi ve heat i ng if V C C > 15V. T he maxi mum out put cur rent
is appr oxi mat el y 40mA i ndependent of the magni t ude of V C C . D estr ucti ve di ssipat i on can r es ult f r om simul ta-
neous short -cir cuit on al l ampli f iers.
2. The di r ect ion of the i nput cur rent is out of t he IC . Thi s cur r ent is essenti al l y constant, i ndependent of the st ate
of the out put so no l oadi ng change exists on the i nput l i nes.
3. Vo = 1. 4V , R s = 0Ω , 5V < V CC + < 30V , 0 < V ic < V C C + - 1.5V
4. The i nput common- mode vol t age of eit her i nput si gnal volt age shoul d not be allow ed to go negat i ve by mor e
than 0.3V . T he upper end of the common- mode vol tage r ange i s V C C + - 1.5V , but eit her or bot h i nput s can go
to +32V w i thout damage.
5. Due t o the proxi mit y of ex ternal component s insure t hat coupl ing i s not ori gi nat ing vi a str ay capaci t ance be-
tw een these ext ernal par t s. T hi s t ypi call y can be detect ed as t his t ype of capaci tance i ncreases at higher f re-
quences.
6. This input cur rent onl y exi sts w hen t he volt age at any of t he i nput leads is dr iven negat ive. It i s due t o t he
coll ect or - base juncti on of t he i nput PN P transistor becomi ng forw ar d biased and ther eby act ing as input di-
odes clamps. I n addit i on to thi s di ode act i on, there i s al so N PN par asit i c act ion on the I C chip. t hi s t ransi st or
acti on can cause t he output vol t ages of the Op- amps t o go t o the V CC volt age l evel (or to ground f or a l arge
over dri ve) f or t he ti me dur at ion t han an input i s dr iven negati ve.
This i s not destr uct i ve and nor mal out put wi l l set up again f or i nput vol tage higher t han - 0.3V.
4/14
LM555 Timer
July 2006
LM555
Timer
General Description Features
The LM555 is a highly stable device for generating accurate n Direct replacement for SE555/NE555
time delays or oscillation. Additional terminals are provided n Timing from microseconds through hours
for triggering or resetting if desired. In the time delay mode of n Operates in both astable and monostable modes
operation, the time is precisely controlled by one external n Adjustable duty cycle
resistor and capacitor. For astable operation as an oscillator, n Output can source or sink 200 mA
the free running frequency and duty cycle are accurately
n Output and supply TTL compatible
controlled with two external resistors and one capacitor. The
n Temperature stability better than 0.005% per ˚C
circuit may be triggered and reset on falling waveforms, and
the output circuit can source or sink up to 200mA or drive n Normally on and normally off output
TTL circuits. n Available in 8-pin MSOP package
Applications
n Precision timing
n Pulse generation
n Sequential timing
n Time delay generation
n Pulse width modulation
n Pulse position modulation
n Linear ramp generator
Schematic Diagram
00785101
© 2006 National Semiconductor Corporation DS007851 www.national.com

LM555
Connection Diagram
Dual-In-Line, Small Outline
and Molded Mini Small Outline Packages
00785103
Top View
Ordering Information
Package Part Number Package Marking Media Transport NSC Drawing
8-Pin SOIC LM555CM LM555CM Rails
M08A
LM555CMX LM555CM 2.5k Units Tape and Reel
8-Pin MSOP LM555CMM Z55 1k Units Tape and Reel
MUA08A
LM555CMMX Z55 3.5k Units Tape and Reel
8-Pin MDIP LM555CN LM555CN Rails N08E
www.national.com 2
LM555
Absolute Maximum Ratings (Note 2) Soldering Information
If Military/Aerospace specified devices are required, Dual-In-Line Package
please contact the National Semiconductor Sales Office/ Soldering (10 Seconds) 260˚C
Distributors for availability and specifications.
Small Outline Packages
Supply Voltage +18V (SOIC and MSOP)
Power Dissipation (Note 3) Vapor Phase (60 Seconds) 215˚C
LM555CM, LM555CN 1180 mW Infrared (15 Seconds) 220˚C
LM555CMM 613 mW See AN-450 “Surface Mounting Methods and Their Effect
Operating Temperature Ranges on Product Reliability” for other methods of soldering
LM555C 0˚C to +70˚C surface mount devices.
Storage Temperature Range −65˚C to +150˚C
Electrical Characteristics (Notes 1, 2)

(TA = 25˚C, VCC = +5V to +15V, unless othewise specified)
Parameter Conditions Limits Units
LM555C
Min Typ Max
Supply Voltage 4.5 16 V
Supply Current VCC = 5V, RL = ∞ 3 6
VCC = 15V, RL = ∞ 10 15 mA
(Low State) (Note 4)
Timing Error, Monostable
Initial Accuracy 1 %
Drift with Temperature RA = 1k to 100kΩ, 50 ppm/˚C
C = 0.1µF, (Note 5)
Accuracy over Temperature 1.5 %
Drift with Supply 0.1 %/V
Timing Error, Astable
Initial Accuracy 2.25 %
Drift with Temperature RA, RB = 1k to 100kΩ, 150 ppm/˚C
C = 0.1µF, (Note 5)
Accuracy over Temperature 3.0 %
Drift with Supply 0.30 %/V
Threshold Voltage 0.667 x VCC
Trigger Voltage VCC = 15V 5 V
VCC = 5V 1.67 V
Trigger Current 0.5 0.9 µA
Reset Voltage 0.4 0.5 1 V
Reset Current 0.1 0.4 mA
Threshold Current (Note 6) 0.1 0.25 µA
Control Voltage Level VCC = 15V 9 10 11
V
VCC = 5V 2.6 3.33 4
Pin 7 Leakage Output High 1 100 nA
Pin 7 Sat (Note 7)
Output Low VCC = 15V, I7 = 15mA 180 mV
Output Low VCC = 4.5V, I7 = 4.5mA 80 200 mV
3 www.national.com
LM555
Electrical Characteristics (Notes 1, 2) (Continued)
(TA = 25˚C, VCC = +5V to +15V, unless othewise specified)
Parameter Conditions Limits Units
LM555C
Min Typ Max
Output Voltage Drop (Low) VCC = 15V
ISINK = 10mA 0.1 0.25 V
ISINK = 50mA 0.4 0.75 V
ISINK = 100mA 2 2.5 V
ISINK = 200mA 2.5 V
VCC = 5V
ISINK = 8mA V
ISINK = 5mA 0.25 0.35 V
Output Voltage Drop (High) ISOURCE = 200mA, VCC = 15V 12.5 V
ISOURCE = 100mA, VCC = 15V 12.75 13.3 V
VCC = 5V 2.75 3.3 V
Rise Time of Output 100 ns
Fall Time of Output 100 ns
Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 3: For operating at elevated temperatures the device must be derated above 25˚C based on a +150˚C maximum junction temperature and a thermal
resistance of 106˚C/W (DIP), 170˚C/W (S0-8), and 204˚C/W (MSOP) junction to ambient.
Note 4: Supply current when output high typically 1 mA less at VCC = 5V.
Note 5: Tested at VCC = 5V and VCC = 15V.
Note 6: This will determine the maximum value of RA + RB for 15V operation. The maximum total (RA + RB) is 20MΩ.
Note 7: No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.
Note 8: Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.
www.national.com 4
Learning Overview
Application of Op-amp
Negative feedback Positive feedback Open loop

Op-amp follows Virtual If Vnoninv > Vinv If Vnoninv > Vinv
ground Vout = +Vsat Vout = +Vsat
Vinv = Vnoninv If Vnoninv < Vinv If Vnoninv < Vinv
Vout = -Vsat Vout = -Vsat
Application : Application : Application :
Linear – Schmitt trigger, Comparator, detector.
Amplifier, adder, multivibrator.
subtractor,
Instrumentation amplifier
etc.
Non linear –
Rectifier, clipper, clamper,
log amplifier, antilog
amplifier, peak detector
etc.
2
LIST OF EXPERIMENTS
Lab Name of Experiments Page Date of Assessment Faculty

performance Signature
1. To configure op-amp in 5
inverting and non inverting
amplifier mode and measure
their gain and bandwidth.
2. To study application of Op- 13
amp as adder and subtractor.
3. To find the CMRR and slew 19
rate of IC 741 and LM 324.
4. To perform the Op-amp as a 25
precision rectifier. (Half wave
and full wave)
5. To design Schmitt trigger 30

circuit using op-amp
(application of positive
feedback)
6. To perform the clipper circuit 36
using Op-amp.
7. To Design Differentiator 41
Circuit Using The Op-Amp
And Verify It.
8. To Design Integrator Circuit 48
Using The Op-Amp And
Verify It.
9. To design All pass filter using 55
Op-amp.
3
Lab Name of Experiments Page Date of Assessment Faculty
performance Signature
10. To Perform astable and 60
monostable multivibrator
using 555 timer IC.
11. Project: 66
4
Experiment
1 Date:
AIM: To configure op-amp in inverting and non inverting amplifier mode and
measure their gain and bandwidth.
Objective:
(a) To measure gain and bandwidth of amplifier and Comment about gain
bandwidth product.
Apparatus:
 Op-amp 741, Resistors.
 Variable Power supply, Function generator, CRO.
 Breadboard, Digital Multimeter, connecting wires and probes.

Circuit Diagram:
V1
XSC1
XFG1 15 V
Ext T rig
+
7 1 5
_
3 U1 A B
+ _ + _
6
R1
2
1kΩ 741
4
Rf
V2
1kΩ
15 V
Figure (a) Inverting amplifier
5
V1
XFG1
XSC1
15 V
Ext T rig
+
7 1 5
_
3 U1 A B
+ _ + _
6
R1
2
1kΩ 741
4
Rf
V2
1kΩ
15 V
Figure (a) Non - Inverting amplifier
Theory:
(a) Inverting amplifier:
Since the input resistance Rin=∞ and because of concept of virtual ground, the
current going to the op-amp will be zero.
Therefore current I that pass through Rin will also pass through Rf.
Here V2=V1=0
Input voltage Vs=IR1
Output voltage Vo= -IRf
So, closed loop gain =Vo/Vs= -Rf/R1
The negative sign indicates that there is a phase shift of 180° between the input and
output voltages.
(a) Non-Inverting amplifier:

As input resistance of opamp is ∞ therefore the current entering into both the input
terminals of opamp will have a zero value .
Voltage across R1 is given by
V2 =
Here V2=V1=Vs
6
Vs =
.·. =
.·. = 1+ =Avf
Procedure:
 Connect function generator and apply sinusoidal voltage in circuit diagram.
 Set the function generator output voltage to say Vs = ______ Volts.
 Increase the function generator output signal frequency from minimum say
10 Hz to a maximum signal frequency of 1MHz in decade steps
(10,20,30…..100,200,…..1000,2000…..10k,20k…….).
 Measure voltage for applied signal frequency.
 Calculate gain for the frequency.
 Plot the graph of frequency v/s gain in semi log paper.
 Find lower cut off freq and higher cut off frequency and determine
bandwidth.
 Now increase gain of overall circuit diagram and measure bandwidth for that
circuit and determine gain bandwidth product for these two cases.
Calculation and Observation Table:
7
Inverting amplifier (Rf = ________ , R1 = _________)
Vin = _________________________
Sr. Frequency Output Gain =
No. (Hz) Voltage, 20log(Vo/Vi)
Vo (V) (dB)
8
Non inverting amplifier
Vin = _________________________
Rf = _______ Rf = _______
R1 = _______ R1 = _______
Sr. Frequency Output Gain = Output Gain =
No. (Hz) Voltage, 20log(Vo/Vi) Voltage, 20log(Vo/Vi)
Vo (V) (dB) Vo (V) (dB)
9
10
11
Question time:
1. Ideal Op-amp is an ideal
(a) VCVS (b) CCCS (c) VCCS (d) CCVS
2. Find current gain Io/Iin for figure shown in the shunt - shunt feedback.
RF
VEE
R1 4 -15V U1
Iin
2
6
3 RL
7 1 5 741 Io
VCC
15V
(a) –RF (b) –R1 (c) –RF/RL (d) –RL/RF
Conclusion:
Faculty Signature
12
Experiment
2 Date:
AIM: To study application of Op-amp as adder and subtractor.

Objective:
To measure output voltage for circuit connected as adder and subtractor.
Apparatus:
 Variable Power supply.

Theory:
1. Adder:
Op-amp may be used to design a circuit whose output is the sum of several input
signal such as circuit is called a summing amplifier or summer. We can obtain either
inverting or non-inverting summer. The circuit diagram shows a two input inverting
summing amplifier.
It has two input voltages V1 and V2, two input resistors R1,R2 and a feedback
resistor Rf. Assuming that op-amp is in ideal conditions and input bias current is
assumed to be zero, the non-inverting terminal is connected with the ground so
ground potential at non inverting terminal.
By taking nodal equations,
V1/R1+V2/R2+Vo/Rf =0
Vo= - [(Rf /R1) V1 + (Rf /R2) V2]
And here R1= R2= Rf= 1kΩ
Vo= - (V1+V2)
Thus output is inverted and sum of input.
13
Circuit Diagram:
2. Subtractor:
Op-amp may be used to design a circuit whose output is subtraction or difference
between two applied voltages. That circuit is called differential or subtractor
amplifier.
It has two input V1 and V2. V1 is applied to inverting terminal using resistor R1 and
V2 is applied to non-inverting terminal using R2. Here Rf is feedback resistor and
R3 is connected to non-inverting terminal. For subtractor application Rf = R3 and R1
= R2.(here R3=Rcomp)
From nodal equation
Vo = (-Rf/R1)V1 + (Rf/R1)V2
Vo = Rf/R1(V2 – V1)
For gain=1, Rf = R1 = 1kΩ
So, Vo = V2 – V1
14
Circuit Diagram:
Procedure:
Task (a) Adder
 Connect the circuit as per the circuit diagram.
 Apply input voltage V1=2V and V2=2V.
 By using multimeter measure the dc output voltage at the output terminal.
Task (b) Subtractor

 Connect the circuit as per the circuit diagram.
 Apply input voltage V1=2V and V2=2V.
 By using multimeter measure the dc output voltage at the output terminal.
15
16
17
Question time:
1. For the circuit given below, the voltage Vo across the Op-amp output is:
50Ω
VEE
4 -15V U1
10Ω 2
6
Vin
3 741 + 10Ω Vo
7 1 5 Vo 10Ω
VCC
-
15V
(a) – 9Vi (b) -3Vi (c) -11Vi (d) 9Vi

2. Considering the op-amp to be ideal, the output voltage Vo is
3kΩ
VEE
4 -15V U1
3kΩ 3kΩ 3kΩ 2

6
2V 3
7 1 5 741
VCC
15V
(a) -2V (b) -4V (c) -6V (d) -18V
Conclusion:
Faculty Signature
18
Experiment
3 Date:
AIM: To find the CMRR and slew rate of IC 741 and LM 324.
Objective:
(a) To find CMRR for 741 and 324 and conclude about betterment of IC.
(b) To measure slew rate of 741 and 324 and deciders maximum operating frequency
for these ICs.
Apparatus:
 Op-amp 741 and 324, Resistors.

Circuit Diagram:
RF
100kΩ
VEE
-15V
4 U1
VEE R1
2
-15V 100Ω 6
4 U1 Vo
R2 3
2 R3 7 1 5 LM741H
6 100Ω 10Ω
3 Vo VCC
15V
7 1 5 LM741H
VCC
15V
(c) To measure slew rate (d) To measure CMRR
Theory:
CMRR:- It is the ratio of differential mode gain to common mode gain. If a signal is
applied common to both, the output of Op-Amp signal will be alternated. CMRR is
19
usually expressed in dB. When an input signal is applied, common to both inputs
common mode voltage gain Ac = Vo/Vi. Differential mode gain Ad = Rf/Ri. Then
CMRR is given by the expression:
CMRR = 20 log (Ad / AC) in dB
Slew rate:- Slew rate is the maximum rate of change of output voltage. It is the
measure of fastness of Op-Amp. It is expressed in V/μs. The internal output
capacitance prevents sudden rate of output voltage for a sing input. If the slope
requirements of the output voltage of the Op-Amp is greater than the slew rate then
distortion occur.
Procedure:
Task (a) Measurement of CMRR:
 For CMRR we have to find Acm(common mode gain) and Ad.
 To find Acm connect the component as shown in figure and give common
input to both the terminal of Op-Amp and measure the output voltage.
 Apply different voltage to find Ad and measure the output voltage and take
ratio of output voltage to difference of input voltage.
 Then find the CMRR by formula.
 Compare CMRR for both ICs.
Task (b) Measurement of Slew rate and find the maximum operating frequency:
 To find slew rate of op-amp connect the component as shown in figure and
give the sine wave to non-inverting terminal of op-amp by function generator
and Op-amp works in buffer mode.
 Then observe output in CRO, it will be square wave.
 Now, increase frequency of input by using function generator until the output
of op-amp is not triangular wave and note down that frequency. It is
maximum frequency which we can apply to get efficient output.
 Find slew rate for both ICs and compare it.
20
21
22
23
Question time:
1. A unit step positive input voltage u(t) is applied to the circuit. After 20 seconds,
the Vo will be (a) +20 V (b) +15 V (c) -15 V (d) -20 V
1uF
VEE 4 -15V
U1
2
1MΩ
6
3
Vin
7 1 5 741
VCC
15V
2. Output of an Op-amp is 1 V peak, and slew rate is 5V/μs. The maximum

frequency of input sinusoidal signal that can be reproduced is:
(a) 398 Hz (b) 796 Hz (c) 796 KHz (d) 398 KHz
Conclusion:
Faculty Signature
24
Experiment
4 Date:
AIM: To perform the Op-amp as a precision rectifier. (Half wave and full wave)
Objective:
To measure dc and rms voltage from output of precision rectifier with op-amp and
compare analysis with ordinary rectifier.
Apparatus:

Theory:
The precision rectifier, which is also known as a super diode, is a configuration
obtained with an operational amplifier in order to have a circuit behaving like an
ideal diode and rectifier. It can be useful for high-precision signal processing. Basic
circuit of a precision rectifier can be given as shown in figure below.
1.) Half-wave Rectifier:
Half wave rectifier is a circuit that passes only positive (or only negative) portion of
AC input wave and blocks the others.
A half wave rectifier using OP amp is also known as a Precision rectifier or super
diode, is a configuration obtained with an operational amplifier in order to have a
circuit behaving like an ideal diode and rectifier. The basic idea behind the super
diode is to use the high-gain of an op-amp to mask the finite turn-on voltage (and
other nonlinearities) of the diode. This is done by placing it in the negative feedback
path.
Circuit Diagram:
25
XFG1 V1 XSC1
15 V
Ext Trig
+
7 1 5 U1 _
A B
3
D1 + _ + _
2 1N914
4 UA741CD R1
V2 2kΩ
15 V
2.) Full-wave Rectifier:
For full wave rectifier, the output voltage is produced in both the half cycles of the
input voltage. The output can either be positive or negative.
This type of full-wave rectifier is superior to the simple diode version because there
is no 700 mV diode drop. The op-amps are used to produce precise full-wave
rectification for frequencies up to and exceeding 100 kHz without waveform
distortion. This configuration has an additional advantage of high input impedance.
It can rectify input signals of very small amplitude (of the order of few mV)
Circuit Diagram:
R2 R4 R5
2kΩ 2kΩ 2kΩ

XSC1
V1 V4
XFG1 15 V D1 15 V Ext T rig
1N914 +
4 4
U1 U2 B
_
A
R1 + _ + _
2 2
2kΩ 6 6
3 3 UA741CD
UA741CD
7 1 5 7 1 5
V2 D2 V3
15 V 1N914 15 V
R3
2kΩ
26
Procedure:
 Connect the circuit as shown in the figure.

 Now apply known sinusoidal AC voltage at the input of the op-amp using
the function generator.
 Observe the output on the CRO and measure the output voltage.
 Repeat this process for different types of input signals and observe the output.
27
Question time:
1. Consider Op-amp and diode ideal, find the transfer characteristics.
28
R
D1
VEE
4 -15V U1
2 D2
R
6
3
Vin Vo
7 1 5 741
VCC
15V
(a) (b)
(d) none
(c)
Conclusion:
Faculty Signature
29
Experiment
5 Date:
AIM: To design Schmitt trigger circuit using op-amp (application of positive

feedback)
Objective:
To measure hysteresis width and define duty cycle according to reference signal
Apparatus:

Circuit Diagram:
Theory:
Figure shows an inverting comparator with positive feedback. This circuit converts an
irregular-shaped waveform to square wave or pulse. The circuit is known as Schmitt
trigger or squaring circuit. The input voltage vin triggers (changes the states of) the
output vo every time it exceeds certain voltage level called the upper voltage Vut and
lower threshold voltage Vlt.
30
The threshold voltages are obtained by using the voltage divider R 1-R2 , where the
voltage across R1 is fed back to the (+) input. The voltage across R 1 is a variable
reference threshold voltage that depends on the value and polarity of the output
voltage vo. when vo =+Vsat, the voltage across R1 is called the upper threshold voltage,
Vut. The input voltage vin must be slightly more positive than Vut in order to cause
the output vo to switch from +Vsat to –Vsat. As long as Vin<Vut, vo is at +Vsat.
Using the voltage divider rule,
Vut = [R1/(R1+R2)](+Vsat)
On the other hand, when Vo= - Vsat, the voltage across R1 is referred to as the
lower threshold voltage, Vlt is given by the following equation:
Vlt = [R1/(R1+R2)](-Vsat)
Thus, if the threshold voltages Vut and Vlt are made larger than the input noise
voltages, the positive feedback will eliminate the false output transitions. Also, the
positive feedback, because of its regenerative action, will make vo switch faster
between + Vsat and - Vsat.
The output the Schmitt trigger is a square wave when the input is sine wave. When
the input is triangular wave, the output of the Schmitt trigger is a square wave,
whereas if the input is a saw-tooth wave, output of the Schmitt trigger is a pulse
waveform.
The comparator with positive feedback is said to be exhibit hysteresis, a dead-band

condition. That is, when the input of the comparator exceeds Vut , its output switch
from +Vsat to –Vsat and reverts back to its original state, +Vsat , when input goes
below Vlt . The hysteresis voltage is, of course, equal to the difference between Vut
and Vlt. Therefore,
Vhy = Vut - Vlt
31
Procedure:
 Connect the circuit as given in Figure .

 Give the input VPP as given in Figure.
 Observe value of +ve and –ve saturation voltage in output waveform and
calculate the value of upper and lower voltages using eqn.
 Find out the value of Hysteresis width using eqn as well as practically.
 Apply the sine wave to this circuit diagram and observe the output.

R1=_______ohm , R2=_______ohm , Vin=_______Vpp
Vsat Vut Vlt Hysteresis Width
32
33
Question time:
1. Given the ideal op-amp circuit shown in the figure with ideal diodes with zero cut
in voltage. Find out Vut and Vlt.
VEE
4 -15V U1
Vin 2
6
3 Vo
741
7 1 5
VCC
15V
2kΩ
500Ω
2kΩ
(a) Vut = -5V and Vlt = -8V (b) Vut = +8V and Vlt = -5V
(c) Vut = +8V and Vlt = +5V (d) Vut = +5V and Vlt = -8V
34
2. Consider the schmit trigger shown below.
VEE
-15V
10kΩ
4 U1
2
Vin 6
3 Vo
741
7 1 5
10kΩ 10kΩ
VCC
15V
A triangle wave which goes from -12V to +12V is applied to the inverting input of
op-amp. Assume that output of op-amp swings from +15V to -15V. The voltage at
non inverting input switch between
(a) -12 V to +12 V (b) -7.5V to +7.5V
(c) -5V to +5V (d) 0V to 5V
Conclusion:
Faculty Signature
35
Experiment
6 Date:
AIM: To perform the clipper circuit using Op-amp.

Objective:
(a) To measure waveform from output of clipper circuit using Op-amp.
Apparatus:
 Op-amp 741, Resistors, diodes.

Circuit Diagram:
XSC1
XFG1 VCC
15V Ext T rig
+
_
7 1 5 U1 A B
+ _ + _
3
D1
6
2
1N914
4 UA741CP R1
10kΩ
R2
VEE
-15V Key = A
10kΩ
93%
Positive clipper
36
XSC1
XFG1 VCC
15V Ext T rig
+
_
7 1 5 U1 A B
+ _ + _
3
D1
6
2 1N914
4 UA741CP R1
10kΩ XMM1
R2
VEE
-15V Key = A
10kΩ
92%
Negative clipper
Theory:
Wave shaping techniques include limiting, clipping and clamping. In op-amp
clipper circuits a rectifier diode may be used to clip off a certain portion of the input
signal to obtain a desired output waveshapes.
Positive and Negative clipper:
A positive clipper, a circuit that removes positive parts of the input signal, can
be formed by using an op-amp with a rectifier diode. In this circuit the op-amp is
basically used as a voltage follower with a diode in the feedback path. The clipping
level is determined by the reference voltage Vref , which should be less than the
input voltage range of the op-amp. Additionally since Vref is derived from the
positive supply voltage(+Vcc) ,the dc supply voltages must be well regulated. As
shown in figure the output voltage has portions of the positive half cycles above Vref
is clipped off.
The positive clipper of figure is converted into a negative clipper by simply

reversing diode D1 and changing the polarity of reference voltage Vre. The resultant
circuit is shown. The negative clipper clips off the negative clipper clips off the
negative parts of the input signal below the reference voltage.
37
Procedure:
For positive clipper:
 Connect the circuit as shown in figure.

 Apply the proper input at the non inverting input of the opamp.
 Set the Vref =1V< Vin by varying resitance pot of the VR.
 Observe the output on the oscilloscope.
For negative clipper:
 Connect the circuit as shown in figure.

 Apply the proper input at the non inverting input of the opamp.
 Set the Vref =-1V< Vin by varying resitance pot of the VR.
 Observe the output on the oscilloscope.
38
39
Question time:
1. Find the type of filter used
(a) LPF (b) HPF (c) BPF (d) BSF
R2
C1
VEE 4 -15V
L1 R1 U1
Vin 2
6
3 Vo
7 1 5 741
VCC
15V
Conclusion:
Faculty Signature
40
Experiment
7 Date:
AIM: To Design Differentiator Circuit Using The Op-Amp And Verify It.
Objective:
To measure frequency response for input of sine wave and observe the output wave
form for different input signals.
Apparatus:
 Op-amp 741, Resistors, Capacitors.

Circuit Diagram:
C1 RF
11
2
V-
Vin -
AC 1
OUT
3 RL
V+
+
ROM
4
Basic differentiator
CF
R1 C1 RF
11
Vin 2
V-
-
AC
1
OUT
3 RL
V+
+
ROM
4
Practical differentiator
41
Theory:
As its name implies, the circuit performs the mathematical operation of
differentiation; that is, the output waveform is the derivative of the the input
waveform. The differentiator may be constructed from a basic inverting amplifier if
an input resistor R1 is replaced by a capacitor C1.
The expression for the output voltage can be obtained from Kirchhoff’s
current equation written at the node V2 as follows:
iC = iV + iF
Since IB 0,
iC =iF
C1d/dt(Vin-V2)=(V2-V1)/RF
But V1=V2= 0 V, because A is very large. Therefore
C1 d(Vin)/dt = -Vo/RF
Or
Vo= - R1C1(dVin/dt)
Thus the input Vo is equal to times the negative instantaneous
rate of change of the input voltage Vin with time .since the differentiator
performs the reverse of the integrator’s function a cosine wave will produce a sine
wave output, or a triangular input will produce square wave output. However, the
differentiator of figure 1 will not do this because it has some practical problems.
The gain of the circuit (RF/XC1) increases with increase in frequency at the rate of
20db/decade. This makes the unstable. Also the input impedance X C1 decrease with
increase in frequency which makes the circuit is susceptible to high frequency noise.
When amplified this noise can completely overwrite the differentiated output signal.
The frequency response of basic differentiator is shown in figure 2. In this figure fa is
the frequency at which the gain is 0dB and is given by
42
fa = 1/2ΠRFC1
Also fc is the unity gain bandwidth of the op-am and f is some relative operating
frequency.
Both the stability and the high frequency noise problem can be
corrected by the addition of two components R1 and CF shown in the figure 1. This
circuit is practical differentiator the frequency response of which is shown in figure:
8.3 by dashed line. From frequency f to fb the gain increase is 20db/decade.
However after fb the gain decrease at 20db/decade. This 40db/decade change in the
gain caused by the R1C1 and RFCF combinations. The gain limiting frequency fb
given by
fb=1/2ΠR1C1
Where R1C1 = RFCF. Thus R1C1 and RFCF has to reduce significantly the
effect of high frequency input amplifier noise and offsets. Above all R1C1 and RFCF
make the more stable by preventing the increase in the gain with frequency.
Generally the value of fb and the in turn R1C1 and RFCF value should be selected
such that
fa <fb <fc
fa=1/2ΠRFC1
fb=1/2π RFCF
fc=unity gain bandwidth
The input signal will be differentiated properly if the time period T of

the input signal is larger than or equal to that is.
T
Procedure:
 Connect the circuit as given in the fig 2.
43
 Give the square, triangular and sinusoidal waveform as an input to the
circuit as given in the fig 2.
 Calculate the value of fa and fb from equation.
 Verify the output waveform for a given input waveform.
 Draw the output waveform with a proper scale in a graph.
 Draw the frequency response characteristics for differentiator circuit.
Vin = _________________________
Vo (V) (dB)
44
45
46
Question time:
1. For the op-amp circuit shown, the output voltage Vo is
20kΩ
VEE 4 -15V
U1
2
Vin = 100mV 10kΩ 6
3 Vo
7 1 5 741
VCC
15V
(a) -100 mV (b) +100 mV (c) +200 mV (d) +300 mV
Conclusion:
Faculty Signature
47
Experiment
8 Date:
AIM: To Design Integrator Circuit Using The Op-Amp And Verify It.
Objective:
To measure frequency response for input of sine wave and observe the output wave
form for different input signals.
Apparatus:

Circuit Diagram:
+Vcc
7
3
+
6
2
-
4
-Vee
R1 CF
RL
Vin
Figure 1. Basic Integrator
48
+Vcc
7
Rom=R1
3
+
6 Vo
1k
2
-
4
-Vee
R1 CF
RL
Vin RF
Figure 2. Practical Integrator
Theory:
A circuit in which the output voltage waveform is the integral of the input
voltage waveform is the integrator or the integrator amplifier. Such a circuit is
obtained by using a basic inverting amplifier configuration if the feedback resister
is replaced by a capacitor .
The expression for the output voltage can be obtained by writing

Kirchhoff’s current equation at node :
Since IB is negligibly small,
Recall that the relationship between current through and voltage across the
capacitor is
Therefore,
However, because A is very large. Therefore,
The output voltage can be obtained by integrating both the sides with respect
to time:
49
t t
∫ =∫
0 0
= (-Vo) + Vo| t = 0
Therefore,
Vo = ∫ +C
Where C is the integration constant and is proportional to the value of the

output voltage Vo at time t= 0 seconds.
fb is the frequency at which the gain is 0 dB and is given by
Both the stability and the low frequency roll off problems can be corrected by
the addition of the resister RF as shown in the practical integrator of fig 2. The term
stability refers to a constant gain as frequency of an input signal is varied over a
certain range. Also, low frequency roll off refers to the rate of decrease in gain at
lower frequencies. In the figure ,f is some relative operating frequency , and for
frequencies f to fa to gain RF/R1 is constant .The gain limiting frequency fa is given
by ,
Generally, the value of fa and in turn and values should be

selected such that < .For example, if = /10, then .In fact, the input
signal will be integrated properly if the time period of the signal is larger than or
equal to . That is,
T≥ (6.4)
Where, =
The integrator is most commonly used in analog computer and analog–to–

digital (ADC) and signal–wave shaping circuits.
50
Procedure:
 Connect the circuit as given in the fig 2.
 Give the square, triangular and sinusoidal wave as input to the circuit as
given in the fig.
 Calculate the value of fa and fb.
 Verify the output waveform for a given input wave.
 Draw the output waveform with a proper scale in a graph.
 Draw the frequency response characteristics for differentiator circuit.

Vin = _________________________
Vo (V) (dB)
51
52
53
Question time:
1. In the circuit shown in figure current Io is (Assume ideal op-amp)
4kΩ
VEE
4 -15V U1
1kΩ 2
6 Io
2V 3 5kΩ
2kΩ 7 1 5 741
VCC
15V
(a) 2 mA (b) 4 mA (c) 0 (d) none
1. The function generator likes pulse or square wave generator, basic building blocks
are
(a) Integrator, Comparator (b) Integrator, Differentiator
(c) Differentiator, Op-amp (d) Comparator, filter
Conclusion:
Faculty Signature
54
Experiment
9 Date:
AIM: To design All pass filter using Op-amp.

Objective:
To measure frequency response and phase response characteristics for all pass active
filter.
Apparatus:

Circuit Diagram:
e
Theory:
The operational amplifier circuit shown in Figure 1 implements an active all-pass

filter with the transfer function
H(s) =
55
Which has one pole at -1/RC and one zero at 1/RC (i.e., they are reflections of each
other across the imaginary axis of the complex plane). The magnitude and phase of
H(iω) for some angular frequency ω are
As expected, the filter has unity-gain magnitude for all ω. The filter introduces a
different delay at each frequency and reaches input-to-output quadrature at ω=1/RC
(i.e., phase shift is 90 degrees).
This implementation uses a high-pass filter at the non-inverting input to generate the
phase shift and negative feedback to compensate for the filter's attenuation .
Circuit diagram of All pass filter is shown in figure.
Procedure:
 Connect function generator and apply sinusoidal voltage in circuit diagram.
 Set the function generator output voltage to say Vs = ______ Volts.
 Increase the function generator output signal frequency from minimum say
10 Hz to a maximum signal frequency of 1MHz in decade steps
(10,20,30…..100,200,…..1000,2000…..10k,20k…….).
 Measure voltage for applied signal frequency.
 Calculate gain for the frequency.
 Plot the graph of frequency v/s gain in semi log paper.
 Measure phase difference between input and output waveform.
56
Vin = _________________________
Frequency Response Phase Response
Sr. Frequency Output Gain = Practical Theoretical
No. (Hz) Voltage, 20log(Vo/Vi) Phase phase
Vo (V) (dB) difference difference
57
58
Question time:
1. Find the type of filter used
(a) LPF (b) HPF (c) BPF (d) BSF
C2
R2
VEE 4 -15V
U1
R1 C1
2
Vin 6
R3
3 Vo
7 1 5 741
VCC
15V
Conclusion:
Faculty Signature
59
Experiment
10 Date:
AIM: To Perform astable and monostable multivibrator using 555 timer IC.
Objective:
(a) To measure duty cycle of output waveform from astable multivibrator .
(b) To measure ON time period from monostable multivibrator.
Apparatus:
 555 timer IC, Resistors, Capacitors.

Circuit Diagram:
Figure1. astable multivibrator
Theory:
Figure 1 shows 555 configured for astable operation. Initially, when output is high,
capacitor C starts charging toward VCC through RA and RB. However, as soon
60
as voltage across the capacitor equals 2/3 VCC, comparator 1 triggers the flip-flop,
and the output switches low. Now capacitor C starts discharging through RB and
transistor Q1.When the voltage across C equals 1/3Vcc, comparator-2’s output
triggers the flip-flop and output goes high. Then cycle repeats.
As shown in this figure, the capacitor is periodically charged and discharged
between 2/3VCC and 1/3VCC respectively. The time during which the capacitor
charges from 1/3VCC to 2/3VCC is equal to the time the output is high and is
given by TC = 0.69(RA + RB) C

Where RA and RB are in ohms and C is in farads. Similarly, the time during
which capacitor charges from 1/3VCC to 2/3VCC is equal to the time the
outputis low and is given by TC = 0.69(RB) C
Where RA and RB are in ohms and C is in farads. Thus the total period of the
output waveform is T = 0.69(RA + 2RB) C This, in turn gives the frequency of
oscillation as
Often the term duty cycle is used in conjunction with the astable multivibrator. The
duty cycle is the ratio of the time TC during which output is high to the total time
period T.It is generally expressed as a percentage. In equation form,
Circuit Diagram:
61
V1 XSC1
5V
Ext T rig
+
8 U1 _
R1 A B
VCC
2kΩ + _ + _
XFG1 4 RST OUT 3
7 DIS
6 THR
2 TRI
5 CON
C1 C2 GND
1µF 1 LM555CM
0.01µF
Figure2. Monostable multivibrator

Theory:
A 555 timer connected for monostable operation is shown in Figure. The circuit has
an external resistor and capacitor. The voltage across the capacitor is used for the
threshold to pin 6. When the trigger arrives at pin 2, the circuit produces output
pulse at pin 3.
Initially, if the output of the timer is low, that is, the circuit is in a stable state,
transistor Q1 is on and the external capacitor C is shorted to ground. Upon
application of a negative trigger pulse to pin 2, transistor Q1 is turned off, which
releases the short circuit across the capacitor and as a result, the output becomes
high.
The capacitor now starts charging up towards through. When the voltage across
the capacitor equals 2/3 Vcc, the output of comparator 1 switches from low to high,
which in turn makes the output low via the output of the flip-flop.
Also, the output of the flip-flop turns transistor Q1 on and hence the capacitor
rapidly discharges through the transistor. The output of the monostable
multivibrator remains low until a trigger pulse is again applied. The cycle then
62
repeats. Figure 8 shows the trigger input, output voltage, and capacitor voltage
waveforms.
The time for which the output remains high is given by
t=1.1(R1*C1)
Where R1 is in ohms, C1 is in farads and t is in seconds.
Once the circuit is triggered, the output will remain high for the time interval tp. It
will not change even if an input trigger is applied during this time interval. In other
words, the circuit is said to be non-retriggerable. However, the timing can be
interrupted by the application of a negative signal at the reset input on pin 4.
A voltage level going from +VCC to ground at the reset input will cause the timer
to immediately switch back to its stable state with the output low.
The trigger input may be driven by the output of astable multivibrator with high
duty cycle. If the desired pulse width is of the order of seconds, the output can be
seen using a LED and the resistance value used will be of the order of MΩ. In this
case the trigger can be supplied manually by grounding the trigger input for a
fraction of a second.
Procedure:
Astable multivibrator:
 Connect the circuit as shown in figure
 Observe the output wave from pin no. 3
 Also observe output waveform from pin no.7
 Draw the waveforms in graph with proper scale.
Monostable multivibrator:
 Connect the circuit as shown in figure
 Give the trigger at pin no. 2
 Observe the output wave from pin no. 3
 Also observe output waveform from pin no.7
63
 Draw the waveforms in graph with proper scale
64
Conclusion:
Faculty Signature
65
Experiment
11 Date:
PROJECT
66
Faculty Signature
“First they ignore you; then they laugh at you; then they fight
you; then you win.”
- Mahatma Gandhi
67

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Integrated circuits

_____________________________________________ Roll No.

_______________ and Enrolment no._______________________ Of fifth

semester of B.E____________________ Class has satisfactorily completed

his/her one full semester in “151003 INTEGRATED CIRCUITS AND

APPLICATIONS” satisfactorily in partial fulfilment of Bachelor of

Electronics and communication Engineering degree to be awarded by Gujarat

Nitin J. Bathani Dr. K. R. Parmar

Compiled by – Nitin J. Bathani - L. D. College of Engineering, Ahmedabad.

0.9MHz Single and Dual, High Gain Features

NON-INV. 3 5 OFFSET NON-INV. 3 5 NON-INV.

OFFSET NULL 1 8 NC OUTPUT (A) 1 8 V+

V- 4 5 OFFSET NULL V- 4 5 NON-INV. INPUT (B)

Absolute Maximum Ratings Thermal Information

Input Capacitance CI 1.4 pF

Offset Voltage Adjustment Range ±15 mV

Output Short Circuit Current 25 mA

Transient Response Unity Gain, VI = 20mV, RL = 2kΩ,

Overshoot O.S. 5.0 %

Slew Rate (Closed Loop) SR RL ≥ 2kΩ 0.5 V/µs

Gain Bandwidth Product GBWP RL = 12kΩ 0.9 MHz

Electrical Specifications For Equipment Design, VSUPPLY = ±15V

Input Offset Voltage RS ≤ 10kΩ 25 - 1 5 - 2 6 mV

Input Common Mode Voltage Range 25 - - - ±12 ±13 - V

Full ±12 ±13 - - - - V

Common Mode Rejection Ratio RS ≤ 10kΩ 25 - - - 70 90 - dB

Power Supply Rejection Ratio RS ≤ 10kΩ 25 - - - - 30 150 µV/V

Full - 30 150 - - - µV/V

Input Resistance 25 0.3 2 - 0.3 2 - MΩ

Electrical Specifications For Equipment Design, VSUPPLY = ±15V (Continued)

Input Bias Current 25 - 80 500 - 80 500 nA

-55 - 300 1500 - - - nA

Input Offset Current 25 - 20 200 - 20 200 nA

Full 25,000 - - 15,000 - - V/V

Output Voltage Swing RL ≥ 10kΩ 25 - - - ±12 ±14 - V

Full ±12 ±14 - - - - V

RL ≥ 2kΩ 25 - - - ±10 ±13 - V

Full ±10 ±13 - ±10 ±13 - V

Supply Current 25 - 1.7 2.8 - 1.7 2.8 mA

125 - 1.5 2.5 - - - mA

Device Power Dissipation 25 - 50 85 - 50 85 mW

Schematic Diagram (Notes 5, 6)

Typical Performance Curves

DC SUPPLY (V+, V-) DC SUPPLY (V+, V-)

Typical Performance Curves (Continued)

FIGURE 5. TRANSIENT RESPONSE FOR CA741C AND CA741

Metallization Mask Layout

.. WIDE GAIN BANDWIDTH : 1.3MHz

.. VERY LOW SUPPLY CURRENT/AMPLI : 375µA

.. LM124A-LM224A-LM324A which feature 3mV max)

SINGLE SUPPLY : +3V TO +30V

DESCRIPTION ORDER CODES

PIN CONNECTIONS (top view)

Inve rting Input 1 2 - - 13 Inve rting Input 4

Non-inve rting Input 1 3 + + 12 Non-inve rting Input 4

Non-inve rting Input 2 5 + + 10 Non-inve rting Input 3

Inve rting Input 2 6 - - 9 Inve rting Input 3

June 1999 1/14

SCHEMATIC DIAGRAM (1/4 LM124)

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS (continued)

© 2006 National Semiconductor Corporation DS007851 www.national.com

Electrical Characteristics (Notes 1, 2)

Negative feedback Positive feedback Open loop

_ and Enrolment no._________ Of fifth