NAME: R.

PREM KUMAR
RRN.: 180051601052

EXPLAIN DYNAMIC EDGE TRIGGERED RIGISTER

DEFINE CLOCK SKEW AND CLOCK JITTER
Dynamic Edge-Triggered Register

The set-up time of this circuit is simply the delay of the transmission gate, and corresponds
to the time it takes node 1 to sample the D input.
The hold time is approximately zero, since the transmission gate is turned off on the clock
edge and further inputs changes are ignored.
The propagation delay (tc-q) is equal to two inverter delays plus the delay of the
transmission gate T2.

Clock Skew
Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital circuit
systems (such as computer systems) in which the same sourced clock signal arrives at
different components at different times. The instantaneous difference between the readings
of any two clocks is called their skew.

Clock Jitter
Clock jitter: By definition, clock jitter is the deviation of a clock edge from its ideal position
in time. ... There are many causes of jitter including PLL loop noise, power supply ripples,
thermal noise, crosstalk between signals etc.