(CS/BCAN/Odd/SEM-1/BCAN-101(New)/2018-19 Tiel MAULANA ABUL KALAM AZAD UNIVERSITY OF TECHNOLOGY, WEST BENGAL Paper Code : BCAN-101 DIGITAL ELECTRONICS Time Allotted: 3 Hours Full Marks: 10 The figures in the margin indicate full marks. Candidates are required to give their answers in their own words as far as practicable. Group -A (Multiple Choice Type Questions) 1. Choose the correct alternative for any ten of the following: 1x10=10 (Ina multiplexer, the output depends on its (a) Data inputs (b) Select inputs (©) Select outputs (d) None of these Gi) Which of the following condition is not allowed in SR flip-flop? (a) S=0.R=0 (b) Set (©) S=1R=0 (d) S= (iii) The logical expression Y=A+AB+AB’C+A’ BC’ D+ 1 is equivalent to @ A+C (b) 1 a’ WA (iy) A flip-flop has (a) one stable state (b) no stable states (©) two stable states (d) None of these 8481 Turn OverCS/BCAN/OdW/SEM-I/BCAN-10I(New)/2018-19 (v) The dual of a Boolean expression is obtained by (a) interchanging all Os and 1s (b) interchanging all Os and 1s, all + and ‘.” signs (©) interchanging all Os and 1s, all + and ‘.’ signs and complementing all the variables (d) interchanging all + and ',’ signs and complementing all the variables (vi) A+’ Bis equal to (a) A+B (b) A ©B (@) A+B (vii) 11101+1100is equal to (a) 10.1101 (b) 100.1101 (©) 1001101 (@) None of these (viii) In general, a sequential logic circuit consists of (a) only flip-flops (b) only gates (©) flip-flops and combinational logic circuits (4) only combinational logic circuits (ix) Race condition arises in (@) S-R Latch () SREF © JKEE @ TRF (0) When two n bit binary numbers are added, the sum will contain at most (a) nbits (b) n+ 1 bits (©) ne2 bits (d) n+ nbits (xi) While performing BCD addition, if the value of each 4-bit group becomes we add 6 with that group. (a) greater than 9 (b) greater or equal to 9 (c) greater than 6 Group - B (Short Answer Type Questions) Answer any three of the following. Sx3E15 2. Difference between Synchronous and Asynchronous counters. AJ 9 TE S 3. Simplify the expressions: A) A= XYZ + XY'Z+XB" A B= PHPQHPORS POURSx12 +xy7'2 + Ka! = 42(4+y')t *2 = K24 xe! [red x(2 +2!) fates) =Kf+ PO+PGR +P BRS : P/gealerels+9)t Pa (Rv) es) + PA are) GRE Bs) + Gar aalerdt = srr Nees fewe gata OT = pars+ F PORS + POR= P4P6+PB (e+5) = p+ P (osm) le) = (P+ Pers) = R+S7 - ‘4 Aubtwract -C> 3) Farum -( sa) wi ap owe Lema ce + (23), = (10000 0, -63),= (0 | 0000 ! 2 54) 10" Q 11102), +EDo07 (1 lool Sigg sow’? [111001 oot L100" Lire! Noowt!! Ps 1 0e® (oo11008) a ase FI \ = @u),Decimah pc® B-4Y-2-1 ) 2-U-2-! code 5 34), a= Sua 0/00 O10! 0O110HO 2u2l = 0100 js11a01t)100 Code __8 ee C0009 Bove 330), ooll Suu Codes (e1eo 1000001121) 0109 2 |o00o0 10017 1 010 | oO) 1 1 106F (w%4,2)= N= 20,5, 6,1%,13,) + d 2,4) oe me DF —_ miei WKYRE WHALE = wi ” —s y “ Paix 2 = wea net? 2 wry * Poix >= wee | 3 ‘ x1 _ _ _ \o re 5 yaa wry 4 4w1Z domign Hin ciscuit si 00 «(Ol vA !o anne ws go4 ” ya its eP)= TT (051,3, 5161 4, 410,11, 12,13, 15) Maxenm Minton Aaanc D 0 OO Oo Mo ° Bok 2 Ls ooo | RCS oe: @ ‘ BECO Eg pee? oor 8 " pee cio t — o1o 2 z ott oO oe rr) ARe® aac too l- racers b tol © ° ae 5? BH! oO | ° cor Pe st Qo ¢ ¢ peer, pBEMZ OK] | | To ? nee? © re AOE rao ] ° wast - rior ( « ae °Tmpluwmk a ful adden wing tum harf adden Ew Adds — Hart Addr Sum = A@P@l Sum = k@O® Com e C CRON) + AP Cammy = A A Awe A@® BOC ale at 077 gan rle gr Mody cine ONE wandCS/BCAN/Odd/SEM-1/BCAN-101(New 2018-19 ‘Subtract (—33) from (-57) using 2°s complement method, Convert (4536), to Vii) 2421 code Si) 5421 code 3H 5 \$Draw the trth table and logic circuit of a full-subtractor. Using K-map find out the expression for H I difference (D) and borrow (B) 5 6. What is flip-flop? What is race condition? NOTES Group -C (Long Answer Type Questions) Answer any three of the following. 15x3=45 1 Using K-map method minimize the following expression: F(w, x,y,2) = mE(1,5,6,12,13,14) + 4£(2,4). Implement the logic circuit using NAND gates only. a (b) Implement Ex-OR gate using NAND Gute and NAND gate using NOR gate, HE4y4¢34)015 8. (a) Define excitation table of flip-flop and propagation delay. (N O+®? 4H () Using the logic diagram convert a J-K flip-flop D flip-flop and 7 flip-flop. % (©) Design a J-K master-stave flip-flop with circuit diagram and give the truth table. 54545215 27 (© Write down the simplified Boolean expression in (sum of product form and, i) product of sum form for Y(A,B,C.D)=T1MO,1,3,5,6,7,9,10,11,12,13,15) VA Implement a full adder us (444)47=15 10. (a) Design a carry look ahead adder, N ol (b) Design a combinational logic cireie implement 4tit odd parity checker. WOME? gen LL, Write short notes on any three of the following Sx3eI15 ( PIPO (ii) Ripple Counter ii). 4-bit parallel adder we? (iv) Gray Code (¥) Master slave J-K flip-flop